1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
4 * Copyright (C) 2020 Western Digital Corporation or its affiliates.
5 */
6#include <dt-bindings/clock/k210-clk.h>
7#include <dt-bindings/pinctrl/k210-fpioa.h>
8#include <dt-bindings/reset/k210-rst.h>
9
10/ {
11	/*
12	 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
13	 * wide, and the upper half of all addresses is ignored.
14	 */
15	#address-cells = <1>;
16	#size-cells = <1>;
17	compatible = "canaan,kendryte-k210";
18
19	aliases {
20		serial0 = &uarths0;
21		serial1 = &uart1;
22		serial2 = &uart2;
23		serial3 = &uart3;
24	};
25
26	/*
27	 * The K210 has an sv39 MMU following the privileged specification v1.9.
28	 * Since this is a non-ratified draft specification, the kernel does not
29	 * support it and the K210 support enabled only for the !MMU case.
30	 * Be consistent with this by setting the CPUs MMU type to "none".
31	 */
32	cpus {
33		#address-cells = <1>;
34		#size-cells = <0>;
35		timebase-frequency = <7800000>;
36		cpu0: cpu@0 {
37			device_type = "cpu";
38			compatible = "canaan,k210", "riscv";
39			reg = <0>;
40			riscv,isa = "rv64imafdc";
41			mmu-type = "riscv,none";
42			i-cache-block-size = <64>;
43			i-cache-size = <0x8000>;
44			d-cache-block-size = <64>;
45			d-cache-size = <0x8000>;
46			cpu0_intc: interrupt-controller {
47				#interrupt-cells = <1>;
48				interrupt-controller;
49				compatible = "riscv,cpu-intc";
50			};
51		};
52		cpu1: cpu@1 {
53			device_type = "cpu";
54			compatible = "canaan,k210", "riscv";
55			reg = <1>;
56			riscv,isa = "rv64imafdc";
57			mmu-type = "riscv,none";
58			i-cache-block-size = <64>;
59			i-cache-size = <0x8000>;
60			d-cache-block-size = <64>;
61			d-cache-size = <0x8000>;
62			cpu1_intc: interrupt-controller {
63				#interrupt-cells = <1>;
64				interrupt-controller;
65				compatible = "riscv,cpu-intc";
66			};
67		};
68
69		cpu-map {
70			cluster0 {
71				core0 {
72					cpu = <&cpu0>;
73				};
74
75				core1 {
76					cpu = <&cpu1>;
77				};
78			};
79		};
80	};
81
82	sram: memory@80000000 {
83		device_type = "memory";
84		reg = <0x80000000 0x400000>, /* sram0 4 MiB */
85		      <0x80400000 0x200000>, /* sram1 2 MiB */
86		      <0x80600000 0x200000>; /* aisram 2 MiB */
87	};
88
89	sram_controller: memory-controller {
90		compatible = "canaan,k210-sram";
91		clocks = <&sysclk K210_CLK_SRAM0>,
92			 <&sysclk K210_CLK_SRAM1>,
93			 <&sysclk K210_CLK_AI>;
94		clock-names = "sram0", "sram1", "aisram";
95	};
96
97	clocks {
98		in0: oscillator {
99			compatible = "fixed-clock";
100			#clock-cells = <0>;
101			clock-frequency = <26000000>;
102		};
103	};
104
105	soc {
106		#address-cells = <1>;
107		#size-cells = <1>;
108		compatible = "simple-bus";
109		ranges;
110		interrupt-parent = <&plic0>;
111
112		rom0: nvmem@1000 {
113			reg = <0x1000 0x1000>;
114			read-only;
115		};
116
117		clint0: timer@2000000 {
118			compatible = "canaan,k210-clint", "sifive,clint0";
119			reg = <0x2000000 0xC000>;
120			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
121					      <&cpu1_intc 3>, <&cpu1_intc 7>;
122		};
123
124		plic0: interrupt-controller@c000000 {
125			#interrupt-cells = <1>;
126			#address-cells = <0>;
127			compatible = "canaan,k210-plic", "sifive,plic-1.0.0";
128			reg = <0xC000000 0x4000000>;
129			interrupt-controller;
130			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
131					      <&cpu1_intc 11>, <&cpu1_intc 9>;
132			riscv,ndev = <65>;
133		};
134
135		uarths0: serial@38000000 {
136			compatible = "canaan,k210-uarths", "sifive,uart0";
137			reg = <0x38000000 0x1000>;
138			interrupts = <33>;
139			clocks = <&sysclk K210_CLK_CPU>;
140		};
141
142		gpio0: gpio-controller@38001000 {
143			#interrupt-cells = <2>;
144			#gpio-cells = <2>;
145			compatible = "canaan,k210-gpiohs", "sifive,gpio0";
146			reg = <0x38001000 0x1000>;
147			interrupt-controller;
148			interrupts = <34>, <35>, <36>, <37>, <38>, <39>, <40>,
149				     <41>, <42>, <43>, <44>, <45>, <46>, <47>,
150				     <48>, <49>, <50>, <51>, <52>, <53>, <54>,
151				     <55>, <56>, <57>, <58>, <59>, <60>, <61>,
152				     <62>, <63>, <64>, <65>;
153			gpio-controller;
154			ngpios = <32>;
155		};
156
157		dmac0: dma-controller@50000000 {
158			compatible = "snps,axi-dma-1.01a";
159			reg = <0x50000000 0x1000>;
160			interrupts = <27>, <28>, <29>, <30>, <31>, <32>;
161			#dma-cells = <1>;
162			clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>;
163			clock-names = "core-clk", "cfgr-clk";
164			resets = <&sysrst K210_RST_DMA>;
165			dma-channels = <6>;
166			snps,dma-masters = <2>;
167			snps,priority = <0 1 2 3 4 5>;
168			snps,data-width = <5>;
169			snps,block-size = <0x200000 0x200000 0x200000
170					   0x200000 0x200000 0x200000>;
171			snps,axi-max-burst-len = <256>;
172		};
173
174		apb0: bus@50200000 {
175			#address-cells = <1>;
176			#size-cells = <1>;
177			compatible = "simple-pm-bus";
178			ranges = <0x50200000 0x50200000 0x200000>;
179			clocks = <&sysclk K210_CLK_APB0>;
180
181			gpio1: gpio@50200000 {
182				#address-cells = <1>;
183				#size-cells = <0>;
184				compatible = "snps,dw-apb-gpio";
185				reg = <0x50200000 0x80>;
186				clocks = <&sysclk K210_CLK_APB0>,
187					 <&sysclk K210_CLK_GPIO>;
188				clock-names = "bus", "db";
189				resets = <&sysrst K210_RST_GPIO>;
190
191				gpio1_0: gpio-port@0 {
192					#gpio-cells = <2>;
193					#interrupt-cells = <2>;
194					compatible = "snps,dw-apb-gpio-port";
195					reg = <0>;
196					interrupt-controller;
197					interrupts = <23>;
198					gpio-controller;
199					ngpios = <8>;
200				};
201			};
202
203			uart1: serial@50210000 {
204				compatible = "snps,dw-apb-uart";
205				reg = <0x50210000 0x100>;
206				interrupts = <11>;
207				clocks = <&sysclk K210_CLK_UART1>,
208					 <&sysclk K210_CLK_APB0>;
209				clock-names = "baudclk", "apb_pclk";
210				resets = <&sysrst K210_RST_UART1>;
211				reg-io-width = <4>;
212				reg-shift = <2>;
213				dcd-override;
214				dsr-override;
215				cts-override;
216				ri-override;
217			};
218
219			uart2: serial@50220000 {
220				compatible = "snps,dw-apb-uart";
221				reg = <0x50220000 0x100>;
222				interrupts = <12>;
223				clocks = <&sysclk K210_CLK_UART2>,
224					 <&sysclk K210_CLK_APB0>;
225				clock-names = "baudclk", "apb_pclk";
226				resets = <&sysrst K210_RST_UART2>;
227				reg-io-width = <4>;
228				reg-shift = <2>;
229				dcd-override;
230				dsr-override;
231				cts-override;
232				ri-override;
233			};
234
235			uart3: serial@50230000 {
236				compatible = "snps,dw-apb-uart";
237				reg = <0x50230000 0x100>;
238				interrupts = <13>;
239				clocks = <&sysclk K210_CLK_UART3>,
240					 <&sysclk K210_CLK_APB0>;
241				clock-names = "baudclk", "apb_pclk";
242				resets = <&sysrst K210_RST_UART3>;
243				reg-io-width = <4>;
244				reg-shift = <2>;
245				dcd-override;
246				dsr-override;
247				cts-override;
248				ri-override;
249			};
250
251			spi2: spi@50240000 {
252				compatible = "canaan,k210-spi";
253				spi-slave;
254				reg = <0x50240000 0x100>;
255				#address-cells = <0>;
256				#size-cells = <0>;
257				interrupts = <3>;
258				clocks = <&sysclk K210_CLK_SPI2>,
259					 <&sysclk K210_CLK_APB0>;
260				clock-names = "ssi_clk", "pclk";
261				resets = <&sysrst K210_RST_SPI2>;
262				spi-max-frequency = <25000000>;
263			};
264
265			i2s0: i2s@50250000 {
266				compatible = "canaan,k210-i2s", "snps,designware-i2s";
267				reg = <0x50250000 0x200>;
268				interrupts = <5>;
269				clocks = <&sysclk K210_CLK_I2S0>;
270				clock-names = "i2sclk";
271				resets = <&sysrst K210_RST_I2S0>;
272			};
273
274			i2s1: i2s@50260000 {
275				compatible = "canaan,k210-i2s", "snps,designware-i2s";
276				reg = <0x50260000 0x200>;
277				interrupts = <6>;
278				clocks = <&sysclk K210_CLK_I2S1>;
279				clock-names = "i2sclk";
280				resets = <&sysrst K210_RST_I2S1>;
281			};
282
283			i2s2: i2s@50270000 {
284				compatible = "canaan,k210-i2s", "snps,designware-i2s";
285				reg = <0x50270000 0x200>;
286				interrupts = <7>;
287				clocks = <&sysclk K210_CLK_I2S2>;
288				clock-names = "i2sclk";
289				resets = <&sysrst K210_RST_I2S2>;
290			};
291
292			i2c0: i2c@50280000 {
293				compatible = "snps,designware-i2c";
294				reg = <0x50280000 0x100>;
295				interrupts = <8>;
296				clocks = <&sysclk K210_CLK_I2C0>,
297					 <&sysclk K210_CLK_APB0>;
298				clock-names = "ref", "pclk";
299				resets = <&sysrst K210_RST_I2C0>;
300			};
301
302			i2c1: i2c@50290000 {
303				compatible = "snps,designware-i2c";
304				reg = <0x50290000 0x100>;
305				interrupts = <9>;
306				clocks = <&sysclk K210_CLK_I2C1>,
307					 <&sysclk K210_CLK_APB0>;
308				clock-names = "ref", "pclk";
309				resets = <&sysrst K210_RST_I2C1>;
310			};
311
312			i2c2: i2c@502a0000 {
313				compatible = "snps,designware-i2c";
314				reg = <0x502A0000 0x100>;
315				interrupts = <10>;
316				clocks = <&sysclk K210_CLK_I2C2>,
317					 <&sysclk K210_CLK_APB0>;
318				clock-names = "ref", "pclk";
319				resets = <&sysrst K210_RST_I2C2>;
320			};
321
322			fpioa: pinmux@502b0000 {
323				compatible = "canaan,k210-fpioa";
324				reg = <0x502B0000 0x100>;
325				clocks = <&sysclk K210_CLK_FPIOA>,
326					 <&sysclk K210_CLK_APB0>;
327				clock-names = "ref", "pclk";
328				resets = <&sysrst K210_RST_FPIOA>;
329				canaan,k210-sysctl-power = <&sysctl 108>;
330			};
331
332			timer0: timer@502d0000 {
333				compatible = "snps,dw-apb-timer";
334				reg = <0x502D0000 0x14>;
335				interrupts = <14>;
336				clocks = <&sysclk K210_CLK_TIMER0>,
337					 <&sysclk K210_CLK_APB0>;
338				clock-names = "timer", "pclk";
339				resets = <&sysrst K210_RST_TIMER0>;
340			};
341
342			timer1: timer@502d0014 {
343				compatible = "snps,dw-apb-timer";
344				reg = <0x502D0014 0x14>;
345				interrupts = <15>;
346				clocks = <&sysclk K210_CLK_TIMER0>,
347					 <&sysclk K210_CLK_APB0>;
348				clock-names = "timer", "pclk";
349				resets = <&sysrst K210_RST_TIMER0>;
350			};
351
352			timer2: timer@502e0000 {
353				compatible = "snps,dw-apb-timer";
354				reg = <0x502E0000 0x14>;
355				interrupts = <16>;
356				clocks = <&sysclk K210_CLK_TIMER1>,
357					 <&sysclk K210_CLK_APB0>;
358				clock-names = "timer", "pclk";
359				resets = <&sysrst K210_RST_TIMER1>;
360			};
361
362			timer3: timer@502e0014 {
363				compatible = "snps,dw-apb-timer";
364				reg = <0x502E0014 0x114>;
365				interrupts = <17>;
366				clocks = <&sysclk K210_CLK_TIMER1>,
367					 <&sysclk K210_CLK_APB0>;
368				clock-names = "timer", "pclk";
369				resets = <&sysrst K210_RST_TIMER1>;
370			};
371
372			timer4: timer@502f0000 {
373				compatible = "snps,dw-apb-timer";
374				reg = <0x502F0000 0x14>;
375				interrupts = <18>;
376				clocks = <&sysclk K210_CLK_TIMER2>,
377					 <&sysclk K210_CLK_APB0>;
378				clock-names = "timer", "pclk";
379				resets = <&sysrst K210_RST_TIMER2>;
380			};
381
382			timer5: timer@502f0014 {
383				compatible = "snps,dw-apb-timer";
384				reg = <0x502F0014 0x14>;
385				interrupts = <19>;
386				clocks = <&sysclk K210_CLK_TIMER2>,
387					 <&sysclk K210_CLK_APB0>;
388				clock-names = "timer", "pclk";
389				resets = <&sysrst K210_RST_TIMER2>;
390			};
391		};
392
393		apb1: bus@50400000 {
394			#address-cells = <1>;
395			#size-cells = <1>;
396			compatible = "simple-pm-bus";
397			ranges = <0x50400000 0x50400000 0x40100>;
398			clocks = <&sysclk K210_CLK_APB1>;
399
400			wdt0: watchdog@50400000 {
401				compatible = "snps,dw-wdt";
402				reg = <0x50400000 0x100>;
403				interrupts = <21>;
404				clocks = <&sysclk K210_CLK_WDT0>,
405					 <&sysclk K210_CLK_APB1>;
406				clock-names = "tclk", "pclk";
407				resets = <&sysrst K210_RST_WDT0>;
408			};
409
410			wdt1: watchdog@50410000 {
411				compatible = "snps,dw-wdt";
412				reg = <0x50410000 0x100>;
413				interrupts = <22>;
414				clocks = <&sysclk K210_CLK_WDT1>,
415					 <&sysclk K210_CLK_APB1>;
416				clock-names = "tclk", "pclk";
417				resets = <&sysrst K210_RST_WDT1>;
418			};
419
420			sysctl: syscon@50440000 {
421				compatible = "canaan,k210-sysctl",
422					     "syscon", "simple-mfd";
423				reg = <0x50440000 0x100>;
424				clocks = <&sysclk K210_CLK_APB1>;
425				clock-names = "pclk";
426
427				sysclk: clock-controller {
428					#clock-cells = <1>;
429					compatible = "canaan,k210-clk";
430					clocks = <&in0>;
431				};
432
433				sysrst: reset-controller {
434					compatible = "canaan,k210-rst";
435					#reset-cells = <1>;
436				};
437
438				reboot: syscon-reboot {
439					compatible = "syscon-reboot";
440					regmap = <&sysctl>;
441					offset = <48>;
442					mask = <1>;
443					value = <1>;
444				};
445			};
446		};
447
448		apb2: bus@52000000 {
449			#address-cells = <1>;
450			#size-cells = <1>;
451			compatible = "simple-pm-bus";
452			ranges = <0x52000000 0x52000000 0x2000200>;
453			clocks = <&sysclk K210_CLK_APB2>;
454
455			spi0: spi@52000000 {
456				#address-cells = <1>;
457				#size-cells = <0>;
458				compatible = "canaan,k210-spi";
459				reg = <0x52000000 0x100>;
460				interrupts = <1>;
461				clocks = <&sysclk K210_CLK_SPI0>,
462					 <&sysclk K210_CLK_APB2>;
463				clock-names = "ssi_clk", "pclk";
464				resets = <&sysrst K210_RST_SPI0>;
465				reset-names = "spi";
466				num-cs = <4>;
467				reg-io-width = <4>;
468			};
469
470			spi1: spi@53000000 {
471				#address-cells = <1>;
472				#size-cells = <0>;
473				compatible = "canaan,k210-spi";
474				reg = <0x53000000 0x100>;
475				interrupts = <2>;
476				clocks = <&sysclk K210_CLK_SPI1>,
477					 <&sysclk K210_CLK_APB2>;
478				clock-names = "ssi_clk", "pclk";
479				resets = <&sysrst K210_RST_SPI1>;
480				reset-names = "spi";
481				num-cs = <4>;
482				reg-io-width = <4>;
483			};
484
485			spi3: spi@54000000 {
486				#address-cells = <1>;
487				#size-cells = <0>;
488				compatible = "snps,dwc-ssi-1.01a";
489				reg = <0x54000000 0x200>;
490				interrupts = <4>;
491				clocks = <&sysclk K210_CLK_SPI3>,
492					 <&sysclk K210_CLK_APB2>;
493				clock-names = "ssi_clk", "pclk";
494				resets = <&sysrst K210_RST_SPI3>;
495				reset-names = "spi";
496
497				num-cs = <4>;
498				reg-io-width = <4>;
499			};
500		};
501	};
502};
503