1 /****************************************************************************** 2 3 � 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc. 4 All rights reserved. 5 6 This is proprietary source code of Freescale Semiconductor Inc., 7 and its use is subject to the NetComm Device Drivers EULA. 8 The copyright notice above does not evidence any actual or intended 9 publication of such source code. 10 11 ALTERNATIVELY, redistribution and use in source and binary forms, with 12 or without modification, are permitted provided that the following 13 conditions are met: 14 * Redistributions of source code must retain the above copyright 15 notice, this list of conditions and the following disclaimer. 16 * Redistributions in binary form must reproduce the above copyright 17 notice, this list of conditions and the following disclaimer in the 18 documentation and/or other materials provided with the distribution. 19 * Neither the name of Freescale Semiconductor nor the 20 names of its contributors may be used to endorse or promote products 21 derived from this software without specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 35 **************************************************************************/ 36 /****************************************************************************** 37 @File bm.h 38 39 @Description BM header 40 *//***************************************************************************/ 41 #ifndef __BM_H 42 #define __BM_H 43 44 #include "xx_common.h" 45 #include "bm_ext.h" 46 #include "mm_ext.h" 47 48 #include "bman_private.h" 49 #include "bm_ipc.h" 50 51 52 #define __ERR_MODULE__ MODULE_BM 53 54 #define BM_NUM_OF_POOLS 64 55 #define BM_NUM_OF_PM 8 56 57 /**************************************************************************//** 58 @Description Exceptions 59 *//***************************************************************************/ 60 #define BM_EX_INVALID_COMMAND 0x00000010 61 #define BM_EX_FBPR_THRESHOLD 0x00000008 62 #define BM_EX_MULTI_ECC 0x00000004 63 #define BM_EX_SINGLE_ECC 0x00000002 64 #define BM_EX_POOLS_AVAIL_STATE 0x00000001 65 66 #define GET_EXCEPTION_FLAG(bitMask, exception) \ 67 switch(exception){ \ 68 case e_BM_EX_INVALID_COMMAND: \ 69 bitMask = BM_EX_INVALID_COMMAND; break; \ 70 case e_BM_EX_FBPR_THRESHOLD: \ 71 bitMask = BM_EX_FBPR_THRESHOLD; break; \ 72 case e_BM_EX_SINGLE_ECC: \ 73 bitMask = BM_EX_SINGLE_ECC; break; \ 74 case e_BM_EX_MULTI_ECC: \ 75 bitMask = BM_EX_MULTI_ECC; break; \ 76 default: bitMask = 0;break; \ 77 } 78 79 /**************************************************************************//** 80 @Description defaults 81 *//***************************************************************************/ 82 /* BM defaults */ 83 #define DEFAULT_exceptions (BM_EX_INVALID_COMMAND |\ 84 BM_EX_FBPR_THRESHOLD |\ 85 BM_EX_MULTI_ECC |\ 86 BM_EX_SINGLE_ECC ) 87 88 #define DEFAULT_fbprThreshold 0 89 /* BM-Portal defaults */ 90 #define DEFAULT_memAttr MEMORY_ATTR_CACHEABLE 91 92 /* BM-Pool defaults */ 93 #define DEFAULT_dynamicBpid TRUE 94 #define DEFAULT_useDepletion FALSE 95 #define DEFAULT_useStockpile FALSE 96 #define DEFAULT_numOfBufsPerCmd 8 97 98 /**************************************************************************//** 99 @Description Memory Mapped Registers 100 *//***************************************************************************/ 101 102 #if defined(__MWERKS__) && !defined(__GNUC__) 103 #pragma pack(push,1) 104 #endif /* defined(__MWERKS__) && ... */ 105 #define MEM_MAP_START 106 107 typedef _Packed struct 108 { 109 /* BMan Buffer Pool Configuration & Status Registers */ 110 volatile uint32_t swdet[BM_NUM_OF_POOLS]; /**< S/W Portal depletion entry threshold */ 111 volatile uint32_t hwdet[BM_NUM_OF_POOLS]; /**< H/W Portal depletion entry threshold */ 112 volatile uint32_t swdxt[BM_NUM_OF_POOLS]; /**< S/W Portal depletion exit threshold */ 113 volatile uint32_t hwdxt[BM_NUM_OF_POOLS]; /**< H/W Portal depletion exit threshold */ 114 volatile uint32_t sdcnt[BM_NUM_OF_POOLS]; /**< S/W Portal depletion count */ 115 volatile uint32_t hdcnt[BM_NUM_OF_POOLS]; /**< H/W Portal depletion count */ 116 volatile uint32_t content[BM_NUM_OF_POOLS]; /**< Snapshot of buffer count in Pool */ 117 volatile uint32_t hdptr[BM_NUM_OF_POOLS]; /**< Head Pointer for Pool's FBPR list. */ 118 119 /* Free Buffer Proxy Record (FBPR) Manager Query Registers */ 120 volatile uint32_t fbpr_fpc; /**< FBPR Free Pool Count */ 121 volatile uint32_t fbpr_fp_lwit; /**< FBPR Free Pool Low Watermark Interrupt Threshold */ 122 volatile uint8_t res1[248]; /**< reserved */ 123 124 /* Performance Monitor (PM) Configuration Register */ 125 volatile uint32_t cmd_pm_cfg[BM_NUM_OF_PM]; /**< BMan Command Performance Monitor configuration registers. */ 126 volatile uint32_t fl_pm_cfg[BM_NUM_OF_PM]; /**< BMan Free List Performance Monitor configuration registers */ 127 volatile uint8_t res2[192]; /**< reserved */ 128 129 /* BMan Error Capture Registers */ 130 volatile uint32_t ecsr; /**< BMan Error Capture Status Register */ 131 volatile uint32_t ecir; /**< BMan Error Capture Information Register */ 132 volatile uint32_t eadr; /**< BMan Error Capture Address Register */ 133 volatile uint8_t res3[4]; /**< reserved */ 134 volatile uint32_t edata[8]; /**< BMan ECC Error Data Register */ 135 volatile uint32_t sbet; /**< BMan Single Bit ECC Error Threshold Register */ 136 volatile uint32_t efcr; /**< BMan Error Fetch Capture Register */ 137 volatile uint32_t efar; /**< BMan Error Fetch Address Register */ 138 volatile uint8_t res4[68]; /**< reserved */ 139 volatile uint32_t sbec0; /**< BMan Single Bit ECC Error Count 0 Register */ 140 volatile uint32_t sbec1; /**< BMan Single Bit ECC Error Count 1 Register */ 141 volatile uint8_t res5[368]; /**< reserved */ 142 143 /* BMan ID/Revision Registers */ 144 volatile uint32_t ip_rev_1; /**< BMan IP Block Revision 1 register */ 145 volatile uint32_t ip_rev_2; /**< BMan IP Block Revision 2 register */ 146 147 /* CoreNet Initiator Interface Memory Window Configuration Registers */ 148 volatile uint32_t fbpr_bare; /**< Data Structure Extended Base Address Register */ 149 volatile uint32_t fbpr_bar; /**< Data Structure Base Address Register */ 150 volatile uint8_t res6[8]; /**< reserved */ 151 volatile uint32_t fbpr_ar; /**< Data Structure Attributes Register */ 152 volatile uint8_t res7[240]; /**< reserved */ 153 volatile uint32_t srcidr; /**< BMan Source ID Register */ 154 volatile uint32_t liodnr; /**< BMan Logical I/O Device Number Register */ 155 volatile uint8_t res8[244]; /**< reserved */ 156 157 /* BMan Interrupt and Error Registers */ 158 volatile uint32_t err_isr; /**< BMan Error Interrupt Status Register */ 159 volatile uint32_t err_ier; /**< BMan Error Interrupt Enable Register */ 160 volatile uint32_t err_isdr; /**< BMan Error Interrupt Status Disable Register */ 161 volatile uint32_t err_iir; /**< BMan Error Interrupt Inhibit Register */ 162 volatile uint32_t err_ifr; /**< BMan Error Interrupt Force Register */ 163 } _PackedType t_BmRegs; 164 165 #define MEM_MAP_END 166 #if defined(__MWERKS__) && !defined(__GNUC__) 167 #pragma pack(pop) 168 #endif /* defined(__MWERKS__) && ... */ 169 170 /**************************************************************************//** 171 @Description General defines 172 *//***************************************************************************/ 173 #define MODULE_NAME_SIZE 30 174 175 #define FBPR_ENTRY_SIZE 64 /* 64 bytes */ 176 177 /* Compilation constants */ 178 #define RCR_THRESH 2 /* reread h/w CI when running out of space */ 179 #define RCR_ITHRESH 4 /* if RCR congests, interrupt threshold */ 180 181 /* Lock/unlock portals, subject to "UNLOCKED" flag */ 182 #define NCSW_PLOCK(p) ((t_BmPortal*)(p))->irq_flags = XX_DisableAllIntr() 183 #define PUNLOCK(p) XX_RestoreAllIntr(((t_BmPortal*)(p))->irq_flags) 184 185 #define BM_RCR_RING 0 186 #define BM_NUM_OF_RINGS 1 187 188 /**************************************************************************//** 189 @Description Register defines 190 *//***************************************************************************/ 191 192 /* masks */ 193 #define REV1_MAJOR_MASK 0x0000FF00 194 #define REV1_MINOR_MASK 0x000000FF 195 196 #define REV2_INTEG_MASK 0x00FF0000 197 #define REV2_ERR_MASK 0x0000FF00 198 #define REV2_CFG_MASK 0x000000FF 199 200 #define AR_PRIORITY 0x40000000 201 #define AR_SIZE_MASK 0x0000003f 202 203 /* shifts */ 204 #define REV1_MAJOR_SHIFT 8 205 #define REV1_MINOR_SHIFT 0 206 207 #define REV2_INTEG_SHIFT 16 208 #define REV2_ERR_SHIFT 8 209 #define REV2_CFG_SHIFT 0 210 211 #define AR_SIZE_SHIFT 0 212 213 typedef uint8_t bmRingType_t; 214 typedef uint8_t (t_BmUpdateCb)(struct bm_portal *p_BmPortalLow); 215 typedef void (t_BmPrefetchCb)(struct bm_portal *p_BmPortalLow); 216 typedef void (t_BmCommitCb)(struct bm_portal *p_BmPortalLow, uint8_t myverb); 217 218 typedef struct { 219 bool useStockpile; /**< */ 220 bool dynamicBpid; /**< boolean indicates use of dynamic Bpid */ 221 bool useDepletion; /**< boolean indicates use of depletion */ 222 uint32_t depletionThresholds[MAX_DEPLETION_THRESHOLDS]; /**< depletion-entry/exit thresholds, if useThresholds is set. NB: 223 this is only allowed if useThresholds is used and 224 when run in the control plane (which controls Bman CCSR) */ 225 } t_BmPoolDriverParams; 226 227 typedef struct BmPool { 228 uint8_t bpid; /**< index of the buffer pool to encapsulate (0-63) */ 229 t_Handle h_Bm; 230 t_Handle h_BmPortal; 231 bool shadowMode; 232 uint32_t numOfBuffers; /**< Number of buffers use by this pool */ 233 t_BufferPoolInfo bufferPoolInfo; /**< Data buffers pool information */ 234 uint32_t flags; /**< bit-mask of BMAN_POOL_FLAG_*** options */ 235 t_Handle h_App; /**< opaque user value passed as a parameter to 'cb' */ 236 t_BmDepletionCallback *f_Depletion; /**< depletion-entry/exit callback, if BMAN_POOL_FLAG_DEPLETION is set */ 237 uint32_t swDepletionCount; 238 uint32_t hwDepletionCount; 239 /* stockpile state - NULL unless BMAN_POOL_FLAG_STOCKPILE is set */ 240 struct bm_buffer *sp; 241 uint16_t spFill; 242 uint8_t spBufsCmd; 243 uint16_t spMaxBufs; 244 uint16_t spMinBufs; 245 bool noBuffCtxt; 246 247 t_BmPoolDriverParams *p_BmPoolDriverParams; 248 } t_BmPool; 249 250 typedef struct { 251 t_BmUpdateCb *f_BmUpdateCb; 252 t_BmPrefetchCb *f_BmPrefetchCb; 253 t_BmCommitCb *f_BmCommitCb; 254 } t_BmPortalCallbacks; 255 256 typedef struct { 257 uint32_t hwExtStructsMemAttr; 258 struct bman_depletion mask; 259 } t_BmPortalDriverParams; 260 261 typedef struct { 262 t_Handle h_Bm; 263 struct bm_portal *p_BmPortalLow; 264 t_BmPortalCallbacks cbs[BM_NUM_OF_RINGS]; 265 uintptr_t irq; 266 int cpu; /* This is used for any "core-affine" portals, ie. default portals 267 * associated to the corresponding cpu. -1 implies that there is no core 268 * affinity configured. */ 269 struct bman_depletion pools[2]; /**< 2-element array. pools[0] is mask, pools[1] is snapshot. */ 270 uint32_t flags; /**< BMAN_PORTAL_FLAG_*** - static, caller-provided */ 271 uint32_t irq_flags; 272 int thresh_set; 273 uint32_t slowpoll; 274 uint32_t rcrProd; /**< The wrap-around rcr_[prod|cons] counters are used to support BMAN_RELEASE_FLAG_WAIT_SYNC. */ 275 uint32_t rcrCons; 276 /**< 64-entry hash-table of pool objects that are tracking depletion 277 * entry/exit (ie. BMAN_POOL_FLAG_DEPLETION). This isn't fast-path, so 278 * we're not fussy about cache-misses and so forth - whereas the above 279 * members should all fit in one cacheline. 280 * BTW, with BM_MAX_NUM_OF_POOLS entries in the hash table and BM_MAX_NUM_OF_POOLS buffer pools to track, 281 * you'll never guess the hash-function ... */ 282 t_BmPool *depletionPoolsTable[BM_MAX_NUM_OF_POOLS]; 283 t_BmPortalDriverParams *p_BmPortalDriverParams; 284 } t_BmPortal; 285 286 typedef struct { 287 uint8_t partBpidBase; 288 uint8_t partNumOfPools; 289 uint32_t totalNumOfBuffers; /**< total number of buffers */ 290 uint32_t fbprMemPartitionId; 291 uint32_t fbprThreshold; 292 uint16_t liodn; 293 } t_BmDriverParams; 294 295 typedef struct { 296 uint8_t guestId; 297 t_Handle h_BpidMm; 298 t_Handle h_SpinLock; 299 t_Handle h_Portals[DPAA_MAX_NUM_OF_SW_PORTALS]; 300 t_Handle h_Session; 301 char moduleName[MODULE_NAME_SIZE]; 302 t_BmRegs *p_BmRegs; 303 void *p_FbprBase; 304 uint32_t exceptions; 305 t_BmExceptionsCallback *f_Exception; 306 t_Handle h_App; 307 uintptr_t errIrq; /**< error interrupt line; NO_IRQ if interrupts not used */ 308 t_BmDriverParams *p_BmDriverParams; 309 } t_Bm; 310 311 static __inline__ void BmSetPortalHandle(t_Handle h_Bm, t_Handle h_Portal, e_DpaaSwPortal portalId) 312 { 313 ASSERT_COND(!((t_Bm*)h_Bm)->h_Portals[portalId] || !h_Portal); 314 ((t_Bm*)h_Bm)->h_Portals[portalId] = h_Portal; 315 } 316 317 static __inline__ t_Handle BmGetPortalHandle(t_Handle h_Bm) 318 { 319 t_Bm *p_Bm = (t_Bm*)h_Bm; 320 ASSERT_COND(p_Bm); 321 return p_Bm->h_Portals[CORE_GetId()]; 322 } 323 324 static __inline__ uint8_t BmUpdate(t_BmPortal *p_BmPortal, bmRingType_t type) 325 { 326 return p_BmPortal->cbs[type].f_BmUpdateCb(p_BmPortal->p_BmPortalLow); 327 } 328 329 static __inline__ void BmPrefetch(t_BmPortal *p_BmPortal, bmRingType_t type) 330 { 331 if (p_BmPortal->cbs[type].f_BmPrefetchCb) 332 p_BmPortal->cbs[type].f_BmPrefetchCb(p_BmPortal->p_BmPortalLow); 333 } 334 335 static __inline__ void BmCommit(t_BmPortal *p_BmPortal, bmRingType_t type, uint8_t myverb) 336 { 337 p_BmPortal->cbs[type].f_BmCommitCb(p_BmPortal->p_BmPortalLow, myverb); 338 } 339 340 static __inline__ uint32_t BmBpidGet(t_Bm *p_Bm, bool force, uint32_t base) 341 { 342 uint64_t ans, size = 1; 343 uint64_t alignment = 1; 344 345 if (force) 346 { 347 if (MM_InRange(p_Bm->h_BpidMm, (uint64_t)base)) 348 { 349 ans = MM_GetForce(p_Bm->h_BpidMm, 350 base, 351 size, 352 "BM BPID MEM"); 353 ans = base; 354 } 355 else if (p_Bm->h_Session) 356 { 357 t_BmIpcMsg msg; 358 t_BmIpcReply reply; 359 uint32_t replyLength; 360 t_BmIpcBpidParams ipcBpid; 361 t_Error errCode = E_OK; 362 363 memset(&msg, 0, sizeof(t_BmIpcMsg)); 364 memset(&reply, 0, sizeof(t_BmIpcReply)); 365 ipcBpid.bpid = (uint8_t)base; 366 msg.msgId = BM_FORCE_BPID; 367 memcpy(msg.msgBody, &ipcBpid, sizeof(t_BmIpcBpidParams)); 368 replyLength = sizeof(uint32_t) + sizeof(uint32_t); 369 if ((errCode = XX_IpcSendMessage(p_Bm->h_Session, 370 (uint8_t*)&msg, 371 sizeof(msg.msgId) + sizeof(t_BmIpcBpidParams), 372 (uint8_t*)&reply, 373 &replyLength, 374 NULL, 375 NULL)) != E_OK) 376 { 377 REPORT_ERROR(MAJOR, errCode, NO_MSG); 378 return (uint32_t)ILLEGAL_BASE; 379 } 380 if (replyLength != (sizeof(uint32_t) + sizeof(uint32_t))) 381 { 382 REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch")); 383 return (uint32_t)ILLEGAL_BASE; 384 } 385 memcpy((uint8_t*)&ans, reply.replyBody, sizeof(uint32_t)); 386 } 387 else 388 { 389 DBG(WARNING, ("No Ipc - can't validate bpid.")); 390 ans = base; 391 } 392 } 393 else 394 ans = MM_Get(p_Bm->h_BpidMm, 395 size, 396 alignment, 397 "BM BPID MEM"); 398 KASSERT(ans < UINT32_MAX, ("Oops, %jx > UINT32_MAX!\n", (uintmax_t)ans)); 399 return (uint32_t)ans; 400 } 401 402 static __inline__ t_Error BmBpidPut(t_Bm *p_Bm, uint32_t base) 403 { 404 if (MM_InRange(p_Bm->h_BpidMm, (uint64_t)base)) 405 { 406 if (MM_Put(p_Bm->h_BpidMm, (uint64_t)base) != base) 407 return E_OK; 408 else 409 return ERROR_CODE(E_NOT_FOUND); 410 } 411 else if (p_Bm->h_Session) 412 { 413 t_BmIpcMsg msg; 414 t_BmIpcBpidParams ipcBpid; 415 t_Error errCode = E_OK; 416 417 memset(&msg, 0, sizeof(t_BmIpcMsg)); 418 ipcBpid.bpid = (uint8_t)base; 419 msg.msgId = BM_PUT_BPID; 420 memcpy(msg.msgBody, &ipcBpid, sizeof(t_BmIpcBpidParams)); 421 if ((errCode = XX_IpcSendMessage(p_Bm->h_Session, 422 (uint8_t*)&msg, 423 sizeof(msg.msgId) + sizeof(t_BmIpcBpidParams), 424 NULL, 425 NULL, 426 NULL, 427 NULL)) != E_OK) 428 RETURN_ERROR(MAJOR, errCode, NO_MSG); 429 } 430 else 431 DBG(WARNING, ("No Ipc - can't validate bpid.")); 432 return E_OK; 433 } 434 435 /****************************************/ 436 /* Inter-Module functions */ 437 /****************************************/ 438 typedef enum e_BmInterModuleCounters { 439 e_BM_IM_COUNTERS_FBPR = 0, 440 e_BM_IM_COUNTERS_POOL_CONTENT, 441 e_BM_IM_COUNTERS_POOL_SW_DEPLETION, 442 e_BM_IM_COUNTERS_POOL_HW_DEPLETION 443 } e_BmInterModuleCounters; 444 445 446 t_Error BmSetPoolThresholds(t_Handle h_Bm, uint8_t bpid, const uint32_t *thresholds); 447 t_Error BmUnSetPoolThresholds(t_Handle h_Bm, uint8_t bpid); 448 uint8_t BmPortalAcquire(t_Handle h_BmPortal, uint8_t bpid, struct bm_buffer *bufs, uint8_t num); 449 t_Error BmPortalRelease(t_Handle h_BmPortal, uint8_t bpid, struct bm_buffer *bufs, uint8_t num, uint32_t flags); 450 t_Error BmPortalQuery(t_Handle h_BmPortal, struct bman_depletion *p_Pools, bool depletion); 451 uint32_t BmGetCounter(t_Handle h_Bm, e_BmInterModuleCounters counter, uint8_t bpid); 452 t_Error BmGetRevision(t_Handle h_Bm, t_BmRevisionInfo *p_BmRevisionInfo); 453 454 455 #endif /* __BM_H */ 456