1852ba100SJustin Hibbits /*
2852ba100SJustin Hibbits * Copyright 2008-2013 Freescale Semiconductor Inc.
3852ba100SJustin Hibbits *
4852ba100SJustin Hibbits * Redistribution and use in source and binary forms, with or without
5852ba100SJustin Hibbits * modification, are permitted provided that the following conditions are met:
6852ba100SJustin Hibbits * * Redistributions of source code must retain the above copyright
7852ba100SJustin Hibbits * notice, this list of conditions and the following disclaimer.
8852ba100SJustin Hibbits * * Redistributions in binary form must reproduce the above copyright
9852ba100SJustin Hibbits * notice, this list of conditions and the following disclaimer in the
10852ba100SJustin Hibbits * documentation and/or other materials provided with the distribution.
11852ba100SJustin Hibbits * * Neither the name of Freescale Semiconductor nor the
12852ba100SJustin Hibbits * names of its contributors may be used to endorse or promote products
13852ba100SJustin Hibbits * derived from this software without specific prior written permission.
14852ba100SJustin Hibbits *
15852ba100SJustin Hibbits *
16852ba100SJustin Hibbits * ALTERNATIVELY, this software may be distributed under the terms of the
17852ba100SJustin Hibbits * GNU General Public License ("GPL") as published by the Free Software
18852ba100SJustin Hibbits * Foundation, either version 2 of that License or (at your option) any
19852ba100SJustin Hibbits * later version.
20852ba100SJustin Hibbits *
21852ba100SJustin Hibbits * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
22852ba100SJustin Hibbits * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23852ba100SJustin Hibbits * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24852ba100SJustin Hibbits * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
25852ba100SJustin Hibbits * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26852ba100SJustin Hibbits * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
27852ba100SJustin Hibbits * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
28852ba100SJustin Hibbits * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29852ba100SJustin Hibbits * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
30852ba100SJustin Hibbits * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31852ba100SJustin Hibbits */
32852ba100SJustin Hibbits
33852ba100SJustin Hibbits #include "fsl_fman_rtc.h"
34852ba100SJustin Hibbits
fman_rtc_defconfig(struct rtc_cfg * cfg)35852ba100SJustin Hibbits void fman_rtc_defconfig(struct rtc_cfg *cfg)
36852ba100SJustin Hibbits {
37852ba100SJustin Hibbits int i;
38852ba100SJustin Hibbits cfg->src_clk = DEFAULT_SRC_CLOCK;
39852ba100SJustin Hibbits cfg->invert_input_clk_phase = DEFAULT_INVERT_INPUT_CLK_PHASE;
40852ba100SJustin Hibbits cfg->invert_output_clk_phase = DEFAULT_INVERT_OUTPUT_CLK_PHASE;
41852ba100SJustin Hibbits cfg->pulse_realign = DEFAULT_PULSE_REALIGN;
42852ba100SJustin Hibbits for (i = 0; i < FMAN_RTC_MAX_NUM_OF_ALARMS; i++)
43852ba100SJustin Hibbits cfg->alarm_polarity[i] = DEFAULT_ALARM_POLARITY;
44852ba100SJustin Hibbits for (i = 0; i < FMAN_RTC_MAX_NUM_OF_EXT_TRIGGERS; i++)
45852ba100SJustin Hibbits cfg->trigger_polarity[i] = DEFAULT_TRIGGER_POLARITY;
46852ba100SJustin Hibbits }
47852ba100SJustin Hibbits
fman_rtc_get_events(struct rtc_regs * regs)48852ba100SJustin Hibbits uint32_t fman_rtc_get_events(struct rtc_regs *regs)
49852ba100SJustin Hibbits {
50852ba100SJustin Hibbits return ioread32be(®s->tmr_tevent);
51852ba100SJustin Hibbits }
52852ba100SJustin Hibbits
fman_rtc_get_event(struct rtc_regs * regs,uint32_t ev_mask)53852ba100SJustin Hibbits uint32_t fman_rtc_get_event(struct rtc_regs *regs, uint32_t ev_mask)
54852ba100SJustin Hibbits {
55852ba100SJustin Hibbits return ioread32be(®s->tmr_tevent) & ev_mask;
56852ba100SJustin Hibbits }
57852ba100SJustin Hibbits
fman_rtc_get_interrupt_mask(struct rtc_regs * regs)58852ba100SJustin Hibbits uint32_t fman_rtc_get_interrupt_mask(struct rtc_regs *regs)
59852ba100SJustin Hibbits {
60852ba100SJustin Hibbits return ioread32be(®s->tmr_temask);
61852ba100SJustin Hibbits }
62852ba100SJustin Hibbits
fman_rtc_set_interrupt_mask(struct rtc_regs * regs,uint32_t mask)63852ba100SJustin Hibbits void fman_rtc_set_interrupt_mask(struct rtc_regs *regs, uint32_t mask)
64852ba100SJustin Hibbits {
65852ba100SJustin Hibbits iowrite32be(mask, ®s->tmr_temask);
66852ba100SJustin Hibbits }
67852ba100SJustin Hibbits
fman_rtc_ack_event(struct rtc_regs * regs,uint32_t events)68852ba100SJustin Hibbits void fman_rtc_ack_event(struct rtc_regs *regs, uint32_t events)
69852ba100SJustin Hibbits {
70852ba100SJustin Hibbits iowrite32be(events, ®s->tmr_tevent);
71852ba100SJustin Hibbits }
72852ba100SJustin Hibbits
fman_rtc_check_and_clear_event(struct rtc_regs * regs)73852ba100SJustin Hibbits uint32_t fman_rtc_check_and_clear_event(struct rtc_regs *regs)
74852ba100SJustin Hibbits {
75852ba100SJustin Hibbits uint32_t event;
76852ba100SJustin Hibbits
77852ba100SJustin Hibbits event = ioread32be(®s->tmr_tevent);
78852ba100SJustin Hibbits event &= ioread32be(®s->tmr_temask);
79852ba100SJustin Hibbits
80852ba100SJustin Hibbits if (event)
81852ba100SJustin Hibbits iowrite32be(event, ®s->tmr_tevent);
82852ba100SJustin Hibbits return event;
83852ba100SJustin Hibbits }
84852ba100SJustin Hibbits
fman_rtc_get_frequency_compensation(struct rtc_regs * regs)85852ba100SJustin Hibbits uint32_t fman_rtc_get_frequency_compensation(struct rtc_regs *regs)
86852ba100SJustin Hibbits {
87852ba100SJustin Hibbits return ioread32be(®s->tmr_add);
88852ba100SJustin Hibbits }
89852ba100SJustin Hibbits
fman_rtc_set_frequency_compensation(struct rtc_regs * regs,uint32_t val)90852ba100SJustin Hibbits void fman_rtc_set_frequency_compensation(struct rtc_regs *regs, uint32_t val)
91852ba100SJustin Hibbits {
92852ba100SJustin Hibbits iowrite32be(val, ®s->tmr_add);
93852ba100SJustin Hibbits }
94852ba100SJustin Hibbits
fman_rtc_enable_interupt(struct rtc_regs * regs,uint32_t events)95852ba100SJustin Hibbits void fman_rtc_enable_interupt(struct rtc_regs *regs, uint32_t events)
96852ba100SJustin Hibbits {
97852ba100SJustin Hibbits fman_rtc_set_interrupt_mask(regs, fman_rtc_get_interrupt_mask(regs) | events);
98852ba100SJustin Hibbits }
99852ba100SJustin Hibbits
fman_rtc_disable_interupt(struct rtc_regs * regs,uint32_t events)100852ba100SJustin Hibbits void fman_rtc_disable_interupt(struct rtc_regs *regs, uint32_t events)
101852ba100SJustin Hibbits {
102852ba100SJustin Hibbits fman_rtc_set_interrupt_mask(regs, fman_rtc_get_interrupt_mask(regs) & ~events);
103852ba100SJustin Hibbits }
104852ba100SJustin Hibbits
fman_rtc_set_timer_alarm_l(struct rtc_regs * regs,int index,uint32_t val)105852ba100SJustin Hibbits void fman_rtc_set_timer_alarm_l(struct rtc_regs *regs, int index, uint32_t val)
106852ba100SJustin Hibbits {
107852ba100SJustin Hibbits iowrite32be(val, ®s->tmr_alarm[index].tmr_alarm_l);
108852ba100SJustin Hibbits }
109852ba100SJustin Hibbits
fman_rtc_set_timer_fiper(struct rtc_regs * regs,int index,uint32_t val)110852ba100SJustin Hibbits void fman_rtc_set_timer_fiper(struct rtc_regs *regs, int index, uint32_t val)
111852ba100SJustin Hibbits {
112852ba100SJustin Hibbits iowrite32be(val, ®s->tmr_fiper[index]);
113852ba100SJustin Hibbits }
114852ba100SJustin Hibbits
fman_rtc_set_timer_alarm(struct rtc_regs * regs,int index,int64_t val)115852ba100SJustin Hibbits void fman_rtc_set_timer_alarm(struct rtc_regs *regs, int index, int64_t val)
116852ba100SJustin Hibbits {
117852ba100SJustin Hibbits iowrite32be((uint32_t)val, ®s->tmr_alarm[index].tmr_alarm_l);
118852ba100SJustin Hibbits iowrite32be((uint32_t)(val >> 32), ®s->tmr_alarm[index].tmr_alarm_h);
119852ba100SJustin Hibbits }
120852ba100SJustin Hibbits
fman_rtc_set_timer_offset(struct rtc_regs * regs,int64_t val)121852ba100SJustin Hibbits void fman_rtc_set_timer_offset(struct rtc_regs *regs, int64_t val)
122852ba100SJustin Hibbits {
123852ba100SJustin Hibbits iowrite32be((uint32_t)val, ®s->tmr_off_l);
124852ba100SJustin Hibbits iowrite32be((uint32_t)(val >> 32), ®s->tmr_off_h);
125852ba100SJustin Hibbits }
126852ba100SJustin Hibbits
fman_rtc_get_trigger_stamp(struct rtc_regs * regs,int id)127852ba100SJustin Hibbits uint64_t fman_rtc_get_trigger_stamp(struct rtc_regs *regs, int id)
128852ba100SJustin Hibbits {
129852ba100SJustin Hibbits uint64_t time;
130852ba100SJustin Hibbits /* TMR_CNT_L must be read first to get an accurate value */
131852ba100SJustin Hibbits time = (uint64_t)ioread32be(®s->tmr_etts[id].tmr_etts_l);
132852ba100SJustin Hibbits time |= ((uint64_t)ioread32be(®s->tmr_etts[id].tmr_etts_h)
133852ba100SJustin Hibbits << 32);
134852ba100SJustin Hibbits
135852ba100SJustin Hibbits return time;
136852ba100SJustin Hibbits }
137852ba100SJustin Hibbits
fman_rtc_get_timer_ctrl(struct rtc_regs * regs)138852ba100SJustin Hibbits uint32_t fman_rtc_get_timer_ctrl(struct rtc_regs *regs)
139852ba100SJustin Hibbits {
140852ba100SJustin Hibbits return ioread32be(®s->tmr_ctrl);
141852ba100SJustin Hibbits }
142852ba100SJustin Hibbits
fman_rtc_set_timer_ctrl(struct rtc_regs * regs,uint32_t val)143852ba100SJustin Hibbits void fman_rtc_set_timer_ctrl(struct rtc_regs *regs, uint32_t val)
144852ba100SJustin Hibbits {
145852ba100SJustin Hibbits iowrite32be(val, ®s->tmr_ctrl);
146852ba100SJustin Hibbits }
147852ba100SJustin Hibbits
fman_rtc_timers_soft_reset(struct rtc_regs * regs)148852ba100SJustin Hibbits void fman_rtc_timers_soft_reset(struct rtc_regs *regs)
149852ba100SJustin Hibbits {
150852ba100SJustin Hibbits fman_rtc_set_timer_ctrl(regs, FMAN_RTC_TMR_CTRL_TMSR);
151852ba100SJustin Hibbits DELAY(10);
152852ba100SJustin Hibbits fman_rtc_set_timer_ctrl(regs, 0);
153852ba100SJustin Hibbits }
154852ba100SJustin Hibbits
fman_rtc_init(struct rtc_cfg * cfg,struct rtc_regs * regs,int num_alarms,int num_fipers,int num_ext_triggers,bool init_freq_comp,uint32_t freq_compensation,uint32_t output_clock_divisor)155852ba100SJustin Hibbits void fman_rtc_init(struct rtc_cfg *cfg, struct rtc_regs *regs, int num_alarms,
156852ba100SJustin Hibbits int num_fipers, int num_ext_triggers, bool init_freq_comp,
157852ba100SJustin Hibbits uint32_t freq_compensation, uint32_t output_clock_divisor)
158852ba100SJustin Hibbits {
159852ba100SJustin Hibbits uint32_t tmr_ctrl;
160852ba100SJustin Hibbits int i;
161852ba100SJustin Hibbits
162852ba100SJustin Hibbits fman_rtc_timers_soft_reset(regs);
163852ba100SJustin Hibbits
164852ba100SJustin Hibbits /* Set the source clock */
165852ba100SJustin Hibbits switch (cfg->src_clk) {
166852ba100SJustin Hibbits case E_FMAN_RTC_SOURCE_CLOCK_SYSTEM:
167852ba100SJustin Hibbits tmr_ctrl = FMAN_RTC_TMR_CTRL_CKSEL_MAC_CLK;
168852ba100SJustin Hibbits break;
169852ba100SJustin Hibbits case E_FMAN_RTC_SOURCE_CLOCK_OSCILATOR:
170852ba100SJustin Hibbits tmr_ctrl = FMAN_RTC_TMR_CTRL_CKSEL_OSC_CLK;
171852ba100SJustin Hibbits break;
172852ba100SJustin Hibbits default:
173852ba100SJustin Hibbits /* Use a clock from the External TMR reference clock.*/
174852ba100SJustin Hibbits tmr_ctrl = FMAN_RTC_TMR_CTRL_CKSEL_EXT_CLK;
175852ba100SJustin Hibbits break;
176852ba100SJustin Hibbits }
177852ba100SJustin Hibbits
178852ba100SJustin Hibbits /* whatever period the user picked, the timestamp will advance in '1'
179852ba100SJustin Hibbits * every time the period passed. */
180852ba100SJustin Hibbits tmr_ctrl |= ((1 << FMAN_RTC_TMR_CTRL_TCLK_PERIOD_SHIFT) &
181852ba100SJustin Hibbits FMAN_RTC_TMR_CTRL_TCLK_PERIOD_MASK);
182852ba100SJustin Hibbits
183852ba100SJustin Hibbits if (cfg->invert_input_clk_phase)
184852ba100SJustin Hibbits tmr_ctrl |= FMAN_RTC_TMR_CTRL_CIPH;
185852ba100SJustin Hibbits if (cfg->invert_output_clk_phase)
186852ba100SJustin Hibbits tmr_ctrl |= FMAN_RTC_TMR_CTRL_COPH;
187852ba100SJustin Hibbits
188852ba100SJustin Hibbits for (i = 0; i < num_alarms; i++) {
189852ba100SJustin Hibbits if (cfg->alarm_polarity[i] ==
190852ba100SJustin Hibbits E_FMAN_RTC_ALARM_POLARITY_ACTIVE_LOW)
191852ba100SJustin Hibbits tmr_ctrl |= (FMAN_RTC_TMR_CTRL_ALMP1 >> i);
192852ba100SJustin Hibbits }
193852ba100SJustin Hibbits
194852ba100SJustin Hibbits for (i = 0; i < num_ext_triggers; i++)
195852ba100SJustin Hibbits if (cfg->trigger_polarity[i] ==
196852ba100SJustin Hibbits E_FMAN_RTC_TRIGGER_ON_FALLING_EDGE)
197852ba100SJustin Hibbits tmr_ctrl |= (FMAN_RTC_TMR_CTRL_ETEP1 << i);
198852ba100SJustin Hibbits
199852ba100SJustin Hibbits if (!cfg->timer_slave_mode && cfg->bypass)
200852ba100SJustin Hibbits tmr_ctrl |= FMAN_RTC_TMR_CTRL_BYP;
201852ba100SJustin Hibbits
202852ba100SJustin Hibbits fman_rtc_set_timer_ctrl(regs, tmr_ctrl);
203852ba100SJustin Hibbits if (init_freq_comp)
204852ba100SJustin Hibbits fman_rtc_set_frequency_compensation(regs, freq_compensation);
205852ba100SJustin Hibbits
206852ba100SJustin Hibbits /* Clear TMR_ALARM registers */
207852ba100SJustin Hibbits for (i = 0; i < num_alarms; i++)
208852ba100SJustin Hibbits fman_rtc_set_timer_alarm(regs, i, 0xFFFFFFFFFFFFFFFFLL);
209852ba100SJustin Hibbits
210852ba100SJustin Hibbits /* Clear TMR_TEVENT */
211852ba100SJustin Hibbits fman_rtc_ack_event(regs, FMAN_RTC_TMR_TEVENT_ALL);
212852ba100SJustin Hibbits
213852ba100SJustin Hibbits /* Initialize TMR_TEMASK */
214852ba100SJustin Hibbits fman_rtc_set_interrupt_mask(regs, 0);
215852ba100SJustin Hibbits
216852ba100SJustin Hibbits /* Clear TMR_FIPER registers */
217852ba100SJustin Hibbits for (i = 0; i < num_fipers; i++)
218852ba100SJustin Hibbits fman_rtc_set_timer_fiper(regs, i, 0xFFFFFFFF);
219852ba100SJustin Hibbits
220852ba100SJustin Hibbits /* Initialize TMR_PRSC */
221852ba100SJustin Hibbits iowrite32be(output_clock_divisor, ®s->tmr_prsc);
222852ba100SJustin Hibbits
223852ba100SJustin Hibbits /* Clear TMR_OFF */
224852ba100SJustin Hibbits fman_rtc_set_timer_offset(regs, 0);
225852ba100SJustin Hibbits }
226852ba100SJustin Hibbits
fman_rtc_is_enabled(struct rtc_regs * regs)227852ba100SJustin Hibbits bool fman_rtc_is_enabled(struct rtc_regs *regs)
228852ba100SJustin Hibbits {
229852ba100SJustin Hibbits return (bool)(fman_rtc_get_timer_ctrl(regs) & FMAN_RTC_TMR_CTRL_TE);
230852ba100SJustin Hibbits }
231852ba100SJustin Hibbits
fman_rtc_enable(struct rtc_regs * regs,bool reset_clock)232852ba100SJustin Hibbits void fman_rtc_enable(struct rtc_regs *regs, bool reset_clock)
233852ba100SJustin Hibbits {
234852ba100SJustin Hibbits uint32_t tmr_ctrl = fman_rtc_get_timer_ctrl(regs);
235852ba100SJustin Hibbits
236852ba100SJustin Hibbits /* TODO check that no timestamping MACs are working in this stage. */
237852ba100SJustin Hibbits if (reset_clock) {
238852ba100SJustin Hibbits fman_rtc_set_timer_ctrl(regs, (tmr_ctrl | FMAN_RTC_TMR_CTRL_TMSR));
239852ba100SJustin Hibbits
240852ba100SJustin Hibbits DELAY(10);
241852ba100SJustin Hibbits /* Clear TMR_OFF */
242852ba100SJustin Hibbits fman_rtc_set_timer_offset(regs, 0);
243852ba100SJustin Hibbits }
244852ba100SJustin Hibbits
245852ba100SJustin Hibbits fman_rtc_set_timer_ctrl(regs, (tmr_ctrl | FMAN_RTC_TMR_CTRL_TE));
246852ba100SJustin Hibbits }
247852ba100SJustin Hibbits
fman_rtc_disable(struct rtc_regs * regs)248852ba100SJustin Hibbits void fman_rtc_disable(struct rtc_regs *regs)
249852ba100SJustin Hibbits {
250852ba100SJustin Hibbits fman_rtc_set_timer_ctrl(regs, (fman_rtc_get_timer_ctrl(regs)
251852ba100SJustin Hibbits & ~(FMAN_RTC_TMR_CTRL_TE)));
252852ba100SJustin Hibbits }
253852ba100SJustin Hibbits
fman_rtc_clear_periodic_pulse(struct rtc_regs * regs,int id)254852ba100SJustin Hibbits void fman_rtc_clear_periodic_pulse(struct rtc_regs *regs, int id)
255852ba100SJustin Hibbits {
256852ba100SJustin Hibbits uint32_t tmp_reg;
257852ba100SJustin Hibbits if (id == 0)
258852ba100SJustin Hibbits tmp_reg = FMAN_RTC_TMR_TEVENT_PP1;
259852ba100SJustin Hibbits else
260852ba100SJustin Hibbits tmp_reg = FMAN_RTC_TMR_TEVENT_PP2;
261852ba100SJustin Hibbits fman_rtc_disable_interupt(regs, tmp_reg);
262852ba100SJustin Hibbits
263852ba100SJustin Hibbits tmp_reg = fman_rtc_get_timer_ctrl(regs);
264852ba100SJustin Hibbits if (tmp_reg & FMAN_RTC_TMR_CTRL_FS)
265852ba100SJustin Hibbits fman_rtc_set_timer_ctrl(regs, tmp_reg & ~FMAN_RTC_TMR_CTRL_FS);
266852ba100SJustin Hibbits
267852ba100SJustin Hibbits fman_rtc_set_timer_fiper(regs, id, 0xFFFFFFFF);
268852ba100SJustin Hibbits }
269852ba100SJustin Hibbits
fman_rtc_clear_external_trigger(struct rtc_regs * regs,int id)270852ba100SJustin Hibbits void fman_rtc_clear_external_trigger(struct rtc_regs *regs, int id)
271852ba100SJustin Hibbits {
272852ba100SJustin Hibbits uint32_t tmpReg, tmp_ctrl;
273852ba100SJustin Hibbits
274852ba100SJustin Hibbits if (id == 0)
275852ba100SJustin Hibbits tmpReg = FMAN_RTC_TMR_TEVENT_ETS1;
276852ba100SJustin Hibbits else
277852ba100SJustin Hibbits tmpReg = FMAN_RTC_TMR_TEVENT_ETS2;
278852ba100SJustin Hibbits fman_rtc_disable_interupt(regs, tmpReg);
279852ba100SJustin Hibbits
280852ba100SJustin Hibbits if (id == 0)
281852ba100SJustin Hibbits tmpReg = FMAN_RTC_TMR_CTRL_PP1L;
282852ba100SJustin Hibbits else
283852ba100SJustin Hibbits tmpReg = FMAN_RTC_TMR_CTRL_PP2L;
284852ba100SJustin Hibbits tmp_ctrl = fman_rtc_get_timer_ctrl(regs);
285852ba100SJustin Hibbits if (tmp_ctrl & tmpReg)
286852ba100SJustin Hibbits fman_rtc_set_timer_ctrl(regs, tmp_ctrl & ~tmpReg);
287852ba100SJustin Hibbits }
288852ba100SJustin Hibbits
fman_rtc_set_alarm(struct rtc_regs * regs,int id,uint32_t val,bool enable)289852ba100SJustin Hibbits void fman_rtc_set_alarm(struct rtc_regs *regs, int id, uint32_t val, bool enable)
290852ba100SJustin Hibbits {
291852ba100SJustin Hibbits uint32_t tmpReg;
292852ba100SJustin Hibbits fman_rtc_set_timer_alarm(regs, id, val);
293852ba100SJustin Hibbits if (enable) {
294852ba100SJustin Hibbits if (id == 0)
295852ba100SJustin Hibbits tmpReg = FMAN_RTC_TMR_TEVENT_ALM1;
296852ba100SJustin Hibbits else
297852ba100SJustin Hibbits tmpReg = FMAN_RTC_TMR_TEVENT_ALM2;
298852ba100SJustin Hibbits fman_rtc_enable_interupt(regs, tmpReg);
299852ba100SJustin Hibbits }
300852ba100SJustin Hibbits }
301852ba100SJustin Hibbits
fman_rtc_set_periodic_pulse(struct rtc_regs * regs,int id,uint32_t val,bool enable)302852ba100SJustin Hibbits void fman_rtc_set_periodic_pulse(struct rtc_regs *regs, int id, uint32_t val,
303852ba100SJustin Hibbits bool enable)
304852ba100SJustin Hibbits {
305852ba100SJustin Hibbits uint32_t tmpReg;
306852ba100SJustin Hibbits fman_rtc_set_timer_fiper(regs, id, val);
307852ba100SJustin Hibbits if (enable) {
308852ba100SJustin Hibbits if (id == 0)
309852ba100SJustin Hibbits tmpReg = FMAN_RTC_TMR_TEVENT_PP1;
310852ba100SJustin Hibbits else
311852ba100SJustin Hibbits tmpReg = FMAN_RTC_TMR_TEVENT_PP2;
312852ba100SJustin Hibbits fman_rtc_enable_interupt(regs, tmpReg);
313852ba100SJustin Hibbits }
314852ba100SJustin Hibbits }
315852ba100SJustin Hibbits
fman_rtc_set_ext_trigger(struct rtc_regs * regs,int id,bool enable,bool use_pulse_as_input)316852ba100SJustin Hibbits void fman_rtc_set_ext_trigger(struct rtc_regs *regs, int id, bool enable,
317852ba100SJustin Hibbits bool use_pulse_as_input)
318852ba100SJustin Hibbits {
319852ba100SJustin Hibbits uint32_t tmpReg;
320852ba100SJustin Hibbits if (enable) {
321852ba100SJustin Hibbits if (id == 0)
322852ba100SJustin Hibbits tmpReg = FMAN_RTC_TMR_TEVENT_ETS1;
323852ba100SJustin Hibbits else
324852ba100SJustin Hibbits tmpReg = FMAN_RTC_TMR_TEVENT_ETS2;
325852ba100SJustin Hibbits fman_rtc_enable_interupt(regs, tmpReg);
326852ba100SJustin Hibbits }
327852ba100SJustin Hibbits if (use_pulse_as_input) {
328852ba100SJustin Hibbits if (id == 0)
329852ba100SJustin Hibbits tmpReg = FMAN_RTC_TMR_CTRL_PP1L;
330852ba100SJustin Hibbits else
331852ba100SJustin Hibbits tmpReg = FMAN_RTC_TMR_CTRL_PP2L;
332852ba100SJustin Hibbits fman_rtc_set_timer_ctrl(regs, fman_rtc_get_timer_ctrl(regs) | tmpReg);
333852ba100SJustin Hibbits }
334852ba100SJustin Hibbits }
335