1 /* 2 * Copyright 2008-2013 Freescale Semiconductor Inc. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * * Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 8 * * Redistributions in binary form must reproduce the above copyright 9 * notice, this list of conditions and the following disclaimer in the 10 * documentation and/or other materials provided with the distribution. 11 * * Neither the name of Freescale Semiconductor nor the 12 * names of its contributors may be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * 16 * ALTERNATIVELY, this software may be distributed under the terms of the 17 * GNU General Public License ("GPL") as published by the Free Software 18 * Foundation, either version 2 of that License or (at your option) any 19 * later version. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef __FSL_FMAN_MEMAC_MII_ACC_H 34 #define __FSL_FMAN_MEMAC_MII_ACC_H 35 36 #include "common/general.h" 37 #include "fsl_enet.h" 38 /* MII Management Registers */ 39 #define MDIO_CFG_CLK_DIV_MASK 0x0080ff80 40 #define MDIO_CFG_CLK_DIV_SHIFT 7 41 #define MDIO_CFG_HOLD_MASK 0x0000001c 42 #define MDIO_CFG_ENC45 0x00000040 43 #define MDIO_CFG_READ_ERR 0x00000002 44 #define MDIO_CFG_BSY 0x00000001 45 46 #define MDIO_CTL_PHY_ADDR_SHIFT 5 47 #define MDIO_CTL_READ 0x00008000 48 49 #define MDIO_DATA_BSY 0x80000000 50 51 /*MEMAC Internal PHY Registers - SGMII */ 52 #define PHY_SGMII_CR_PHY_RESET 0x8000 53 #define PHY_SGMII_CR_RESET_AN 0x0200 54 #define PHY_SGMII_CR_DEF_VAL 0x1140 55 #define PHY_SGMII_DEV_ABILITY_SGMII 0x4001 56 #define PHY_SGMII_DEV_ABILITY_1000X 0x01A0 57 #define PHY_SGMII_IF_MODE_AN 0x0002 58 #define PHY_SGMII_IF_MODE_SGMII 0x0001 59 #define PHY_SGMII_IF_MODE_1000X 0x0000 60 61 /*----------------------------------------------------*/ 62 /* MII Configuration Control Memory Map Registers */ 63 /*----------------------------------------------------*/ 64 struct memac_mii_access_mem_map { 65 uint32_t mdio_cfg; /* 0x030 */ 66 uint32_t mdio_ctrl; /* 0x034 */ 67 uint32_t mdio_data; /* 0x038 */ 68 uint32_t mdio_addr; /* 0x03c */ 69 }; 70 71 int fman_memac_mii_read_phy_reg(struct memac_mii_access_mem_map *mii_regs, 72 uint8_t phy_addr, uint8_t reg, uint16_t *data, 73 enum enet_speed enet_speed); 74 int fman_memac_mii_write_phy_reg(struct memac_mii_access_mem_map *mii_regs, 75 uint8_t phy_addr, uint8_t reg, uint16_t data, 76 enum enet_speed enet_speed); 77 78 #endif /* __MAC_API_MEMAC_MII_ACC_H */ 79