1 /* 2 * Implement fast Fletcher4 with NEON instructions. (aarch64) 3 * 4 * Use the 128-bit NEON SIMD instructions and registers to compute 5 * Fletcher4 in two incremental 64-bit parallel accumulator streams, 6 * and then combine the streams to form the final four checksum words. 7 * This implementation is a derivative of the AVX SIMD implementation by 8 * James Guilford and Jinshan Xiong from Intel (see zfs_fletcher_intel.c). 9 * 10 * Copyright (C) 2016 Romain Dolbeau. 11 * 12 * Authors: 13 * Romain Dolbeau <romain.dolbeau@atos.net> 14 * 15 * This software is available to you under a choice of one of two 16 * licenses. You may choose to be licensed under the terms of the GNU 17 * General Public License (GPL) Version 2, available from the file 18 * COPYING in the main directory of this source tree, or the 19 * OpenIB.org BSD license below: 20 * 21 * Redistribution and use in source and binary forms, with or 22 * without modification, are permitted provided that the following 23 * conditions are met: 24 * 25 * - Redistributions of source code must retain the above 26 * copyright notice, this list of conditions and the following 27 * disclaimer. 28 * 29 * - Redistributions in binary form must reproduce the above 30 * copyright notice, this list of conditions and the following 31 * disclaimer in the documentation and/or other materials 32 * provided with the distribution. 33 * 34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 36 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 38 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 39 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 40 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 41 * SOFTWARE. 42 */ 43 44 #if defined(__aarch64__) 45 46 #include <sys/simd.h> 47 #include <sys/spa_checksum.h> 48 #include <sys/string.h> 49 #include <zfs_fletcher.h> 50 51 ZFS_NO_SANITIZE_UNDEFINED 52 static void 53 fletcher_4_aarch64_neon_init(fletcher_4_ctx_t *ctx) 54 { 55 kfpu_begin(); 56 memset(ctx->aarch64_neon, 0, 4 * sizeof (zfs_fletcher_aarch64_neon_t)); 57 } 58 59 ZFS_NO_SANITIZE_UNDEFINED 60 static void 61 fletcher_4_aarch64_neon_fini(fletcher_4_ctx_t *ctx, zio_cksum_t *zcp) 62 { 63 uint64_t A, B, C, D; 64 A = ctx->aarch64_neon[0].v[0] + ctx->aarch64_neon[0].v[1]; 65 B = 2 * ctx->aarch64_neon[1].v[0] + 2 * ctx->aarch64_neon[1].v[1] - 66 ctx->aarch64_neon[0].v[1]; 67 C = 4 * ctx->aarch64_neon[2].v[0] - ctx->aarch64_neon[1].v[0] + 68 4 * ctx->aarch64_neon[2].v[1] - 3 * ctx->aarch64_neon[1].v[1]; 69 D = 8 * ctx->aarch64_neon[3].v[0] - 4 * ctx->aarch64_neon[2].v[0] + 70 8 * ctx->aarch64_neon[3].v[1] - 8 * ctx->aarch64_neon[2].v[1] + 71 ctx->aarch64_neon[1].v[1]; 72 ZIO_SET_CHECKSUM(zcp, A, B, C, D); 73 kfpu_end(); 74 } 75 76 #define NEON_INIT_LOOP() \ 77 asm("eor %[ZERO].16b,%[ZERO].16b,%[ZERO].16b\n" \ 78 "ld1 { %[ACC0].4s }, %[CTX0]\n" \ 79 "ld1 { %[ACC1].4s }, %[CTX1]\n" \ 80 "ld1 { %[ACC2].4s }, %[CTX2]\n" \ 81 "ld1 { %[ACC3].4s }, %[CTX3]\n" \ 82 : [ZERO] "=w" (ZERO), \ 83 [ACC0] "=w" (ACC0), [ACC1] "=w" (ACC1), \ 84 [ACC2] "=w" (ACC2), [ACC3] "=w" (ACC3) \ 85 : [CTX0] "Q" (ctx->aarch64_neon[0]), \ 86 [CTX1] "Q" (ctx->aarch64_neon[1]), \ 87 [CTX2] "Q" (ctx->aarch64_neon[2]), \ 88 [CTX3] "Q" (ctx->aarch64_neon[3])) 89 90 #define NEON_DO_REVERSE "rev32 %[SRC].16b, %[SRC].16b\n" 91 92 #define NEON_DONT_REVERSE "" 93 94 #define NEON_MAIN_LOOP(REVERSE) \ 95 asm("ld1 { %[SRC].4s }, %[IP]\n" \ 96 REVERSE \ 97 "zip1 %[TMP1].4s, %[SRC].4s, %[ZERO].4s\n" \ 98 "zip2 %[TMP2].4s, %[SRC].4s, %[ZERO].4s\n" \ 99 "add %[ACC0].2d, %[ACC0].2d, %[TMP1].2d\n" \ 100 "add %[ACC1].2d, %[ACC1].2d, %[ACC0].2d\n" \ 101 "add %[ACC2].2d, %[ACC2].2d, %[ACC1].2d\n" \ 102 "add %[ACC3].2d, %[ACC3].2d, %[ACC2].2d\n" \ 103 "add %[ACC0].2d, %[ACC0].2d, %[TMP2].2d\n" \ 104 "add %[ACC1].2d, %[ACC1].2d, %[ACC0].2d\n" \ 105 "add %[ACC2].2d, %[ACC2].2d, %[ACC1].2d\n" \ 106 "add %[ACC3].2d, %[ACC3].2d, %[ACC2].2d\n" \ 107 : [SRC] "=&w" (SRC), \ 108 [TMP1] "=&w" (TMP1), [TMP2] "=&w" (TMP2), \ 109 [ACC0] "+w" (ACC0), [ACC1] "+w" (ACC1), \ 110 [ACC2] "+w" (ACC2), [ACC3] "+w" (ACC3) \ 111 : [ZERO] "w" (ZERO), [IP] "Q" (*ip)) 112 113 #define NEON_FINI_LOOP() \ 114 asm("st1 { %[ACC0].4s },%[DST0]\n" \ 115 "st1 { %[ACC1].4s },%[DST1]\n" \ 116 "st1 { %[ACC2].4s },%[DST2]\n" \ 117 "st1 { %[ACC3].4s },%[DST3]\n" \ 118 : [DST0] "=Q" (ctx->aarch64_neon[0]), \ 119 [DST1] "=Q" (ctx->aarch64_neon[1]), \ 120 [DST2] "=Q" (ctx->aarch64_neon[2]), \ 121 [DST3] "=Q" (ctx->aarch64_neon[3]) \ 122 : [ACC0] "w" (ACC0), [ACC1] "w" (ACC1), \ 123 [ACC2] "w" (ACC2), [ACC3] "w" (ACC3)) 124 125 static void 126 fletcher_4_aarch64_neon_native(fletcher_4_ctx_t *ctx, 127 const void *buf, uint64_t size) 128 { 129 const uint64_t *ip = buf; 130 const uint64_t *ipend = (uint64_t *)((uint8_t *)ip + size); 131 #if defined(_KERNEL) 132 register unsigned char ZERO asm("v0") __attribute__((vector_size(16))); 133 register unsigned char ACC0 asm("v1") __attribute__((vector_size(16))); 134 register unsigned char ACC1 asm("v2") __attribute__((vector_size(16))); 135 register unsigned char ACC2 asm("v3") __attribute__((vector_size(16))); 136 register unsigned char ACC3 asm("v4") __attribute__((vector_size(16))); 137 register unsigned char TMP1 asm("v5") __attribute__((vector_size(16))); 138 register unsigned char TMP2 asm("v6") __attribute__((vector_size(16))); 139 register unsigned char SRC asm("v7") __attribute__((vector_size(16))); 140 #else 141 unsigned char ZERO __attribute__((vector_size(16))); 142 unsigned char ACC0 __attribute__((vector_size(16))); 143 unsigned char ACC1 __attribute__((vector_size(16))); 144 unsigned char ACC2 __attribute__((vector_size(16))); 145 unsigned char ACC3 __attribute__((vector_size(16))); 146 unsigned char TMP1 __attribute__((vector_size(16))); 147 unsigned char TMP2 __attribute__((vector_size(16))); 148 unsigned char SRC __attribute__((vector_size(16))); 149 #endif 150 151 NEON_INIT_LOOP(); 152 153 do { 154 NEON_MAIN_LOOP(NEON_DONT_REVERSE); 155 } while ((ip += 2) < ipend); 156 157 NEON_FINI_LOOP(); 158 } 159 160 static void 161 fletcher_4_aarch64_neon_byteswap(fletcher_4_ctx_t *ctx, 162 const void *buf, uint64_t size) 163 { 164 const uint64_t *ip = buf; 165 const uint64_t *ipend = (uint64_t *)((uint8_t *)ip + size); 166 #if defined(_KERNEL) 167 register unsigned char ZERO asm("v0") __attribute__((vector_size(16))); 168 register unsigned char ACC0 asm("v1") __attribute__((vector_size(16))); 169 register unsigned char ACC1 asm("v2") __attribute__((vector_size(16))); 170 register unsigned char ACC2 asm("v3") __attribute__((vector_size(16))); 171 register unsigned char ACC3 asm("v4") __attribute__((vector_size(16))); 172 register unsigned char TMP1 asm("v5") __attribute__((vector_size(16))); 173 register unsigned char TMP2 asm("v6") __attribute__((vector_size(16))); 174 register unsigned char SRC asm("v7") __attribute__((vector_size(16))); 175 #else 176 unsigned char ZERO __attribute__((vector_size(16))); 177 unsigned char ACC0 __attribute__((vector_size(16))); 178 unsigned char ACC1 __attribute__((vector_size(16))); 179 unsigned char ACC2 __attribute__((vector_size(16))); 180 unsigned char ACC3 __attribute__((vector_size(16))); 181 unsigned char TMP1 __attribute__((vector_size(16))); 182 unsigned char TMP2 __attribute__((vector_size(16))); 183 unsigned char SRC __attribute__((vector_size(16))); 184 #endif 185 186 NEON_INIT_LOOP(); 187 188 do { 189 NEON_MAIN_LOOP(NEON_DO_REVERSE); 190 } while ((ip += 2) < ipend); 191 192 NEON_FINI_LOOP(); 193 } 194 195 static boolean_t fletcher_4_aarch64_neon_valid(void) 196 { 197 return (kfpu_allowed()); 198 } 199 200 const fletcher_4_ops_t fletcher_4_aarch64_neon_ops = { 201 .init_native = fletcher_4_aarch64_neon_init, 202 .compute_native = fletcher_4_aarch64_neon_native, 203 .fini_native = fletcher_4_aarch64_neon_fini, 204 .init_byteswap = fletcher_4_aarch64_neon_init, 205 .compute_byteswap = fletcher_4_aarch64_neon_byteswap, 206 .fini_byteswap = fletcher_4_aarch64_neon_fini, 207 .valid = fletcher_4_aarch64_neon_valid, 208 .name = "aarch64_neon" 209 }; 210 211 #endif /* defined(__aarch64__) */ 212