1 /* 2 * Implement fast Fletcher4 with SSE2,SSSE3 instructions. (x86) 3 * 4 * Use the 128-bit SSE2/SSSE3 SIMD instructions and registers to compute 5 * Fletcher4 in two incremental 64-bit parallel accumulator streams, 6 * and then combine the streams to form the final four checksum words. 7 * This implementation is a derivative of the AVX SIMD implementation by 8 * James Guilford and Jinshan Xiong from Intel (see zfs_fletcher_intel.c). 9 * 10 * Copyright (C) 2016 Tyler J. Stachecki. 11 * 12 * Authors: 13 * Tyler J. Stachecki <stachecki.tyler@gmail.com> 14 * 15 * This software is available to you under a choice of one of two 16 * licenses. You may choose to be licensed under the terms of the GNU 17 * General Public License (GPL) Version 2, available from the file 18 * COPYING in the main directory of this source tree, or the 19 * OpenIB.org BSD license below: 20 * 21 * Redistribution and use in source and binary forms, with or 22 * without modification, are permitted provided that the following 23 * conditions are met: 24 * 25 * - Redistributions of source code must retain the above 26 * copyright notice, this list of conditions and the following 27 * disclaimer. 28 * 29 * - Redistributions in binary form must reproduce the above 30 * copyright notice, this list of conditions and the following 31 * disclaimer in the documentation and/or other materials 32 * provided with the distribution. 33 * 34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 36 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 38 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 39 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 40 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 41 * SOFTWARE. 42 */ 43 44 #if defined(HAVE_SSE2) 45 46 #include <sys/simd.h> 47 #include <sys/spa_checksum.h> 48 #include <sys/byteorder.h> 49 #include <sys/strings.h> 50 #include <zfs_fletcher.h> 51 52 ZFS_NO_SANITIZE_UNDEFINED 53 static void 54 fletcher_4_sse2_init(fletcher_4_ctx_t *ctx) 55 { 56 bzero(ctx->sse, 4 * sizeof (zfs_fletcher_sse_t)); 57 } 58 59 ZFS_NO_SANITIZE_UNDEFINED 60 static void 61 fletcher_4_sse2_fini(fletcher_4_ctx_t *ctx, zio_cksum_t *zcp) 62 { 63 uint64_t A, B, C, D; 64 65 /* 66 * The mixing matrix for checksum calculation is: 67 * a = a0 + a1 68 * b = 2b0 + 2b1 - a1 69 * c = 4c0 - b0 + 4c1 -3b1 70 * d = 8d0 - 4c0 + 8d1 - 8c1 + b1; 71 * 72 * c and d are multiplied by 4 and 8, respectively, 73 * before spilling the vectors out to memory. 74 */ 75 A = ctx->sse[0].v[0] + ctx->sse[0].v[1]; 76 B = 2 * ctx->sse[1].v[0] + 2 * ctx->sse[1].v[1] - ctx->sse[0].v[1]; 77 C = 4 * ctx->sse[2].v[0] - ctx->sse[1].v[0] + 4 * ctx->sse[2].v[1] - 78 3 * ctx->sse[1].v[1]; 79 D = 8 * ctx->sse[3].v[0] - 4 * ctx->sse[2].v[0] + 8 * ctx->sse[3].v[1] - 80 8 * ctx->sse[2].v[1] + ctx->sse[1].v[1]; 81 82 ZIO_SET_CHECKSUM(zcp, A, B, C, D); 83 } 84 85 #define FLETCHER_4_SSE_RESTORE_CTX(ctx) \ 86 { \ 87 asm volatile("movdqu %0, %%xmm0" :: "m" ((ctx)->sse[0])); \ 88 asm volatile("movdqu %0, %%xmm1" :: "m" ((ctx)->sse[1])); \ 89 asm volatile("movdqu %0, %%xmm2" :: "m" ((ctx)->sse[2])); \ 90 asm volatile("movdqu %0, %%xmm3" :: "m" ((ctx)->sse[3])); \ 91 } 92 93 #define FLETCHER_4_SSE_SAVE_CTX(ctx) \ 94 { \ 95 asm volatile("movdqu %%xmm0, %0" : "=m" ((ctx)->sse[0])); \ 96 asm volatile("movdqu %%xmm1, %0" : "=m" ((ctx)->sse[1])); \ 97 asm volatile("movdqu %%xmm2, %0" : "=m" ((ctx)->sse[2])); \ 98 asm volatile("movdqu %%xmm3, %0" : "=m" ((ctx)->sse[3])); \ 99 } 100 101 static void 102 fletcher_4_sse2_native(fletcher_4_ctx_t *ctx, const void *buf, uint64_t size) 103 { 104 const uint64_t *ip = buf; 105 const uint64_t *ipend = (uint64_t *)((uint8_t *)ip + size); 106 107 kfpu_begin(); 108 109 FLETCHER_4_SSE_RESTORE_CTX(ctx); 110 111 asm volatile("pxor %xmm4, %xmm4"); 112 113 for (; ip < ipend; ip += 2) { 114 asm volatile("movdqu %0, %%xmm5" :: "m"(*ip)); 115 asm volatile("movdqa %xmm5, %xmm6"); 116 asm volatile("punpckldq %xmm4, %xmm5"); 117 asm volatile("punpckhdq %xmm4, %xmm6"); 118 asm volatile("paddq %xmm5, %xmm0"); 119 asm volatile("paddq %xmm0, %xmm1"); 120 asm volatile("paddq %xmm1, %xmm2"); 121 asm volatile("paddq %xmm2, %xmm3"); 122 asm volatile("paddq %xmm6, %xmm0"); 123 asm volatile("paddq %xmm0, %xmm1"); 124 asm volatile("paddq %xmm1, %xmm2"); 125 asm volatile("paddq %xmm2, %xmm3"); 126 } 127 128 FLETCHER_4_SSE_SAVE_CTX(ctx); 129 130 kfpu_end(); 131 } 132 133 static void 134 fletcher_4_sse2_byteswap(fletcher_4_ctx_t *ctx, const void *buf, uint64_t size) 135 { 136 const uint32_t *ip = buf; 137 const uint32_t *ipend = (uint32_t *)((uint8_t *)ip + size); 138 139 kfpu_begin(); 140 141 FLETCHER_4_SSE_RESTORE_CTX(ctx); 142 143 for (; ip < ipend; ip += 2) { 144 uint32_t scratch1 = BSWAP_32(ip[0]); 145 uint32_t scratch2 = BSWAP_32(ip[1]); 146 asm volatile("movd %0, %%xmm5" :: "r"(scratch1)); 147 asm volatile("movd %0, %%xmm6" :: "r"(scratch2)); 148 asm volatile("punpcklqdq %xmm6, %xmm5"); 149 asm volatile("paddq %xmm5, %xmm0"); 150 asm volatile("paddq %xmm0, %xmm1"); 151 asm volatile("paddq %xmm1, %xmm2"); 152 asm volatile("paddq %xmm2, %xmm3"); 153 } 154 155 FLETCHER_4_SSE_SAVE_CTX(ctx); 156 157 kfpu_end(); 158 } 159 160 static boolean_t fletcher_4_sse2_valid(void) 161 { 162 return (kfpu_allowed() && zfs_sse2_available()); 163 } 164 165 const fletcher_4_ops_t fletcher_4_sse2_ops = { 166 .init_native = fletcher_4_sse2_init, 167 .fini_native = fletcher_4_sse2_fini, 168 .compute_native = fletcher_4_sse2_native, 169 .init_byteswap = fletcher_4_sse2_init, 170 .fini_byteswap = fletcher_4_sse2_fini, 171 .compute_byteswap = fletcher_4_sse2_byteswap, 172 .valid = fletcher_4_sse2_valid, 173 .name = "sse2" 174 }; 175 176 #endif /* defined(HAVE_SSE2) */ 177 178 #if defined(HAVE_SSE2) && defined(HAVE_SSSE3) 179 static void 180 fletcher_4_ssse3_byteswap(fletcher_4_ctx_t *ctx, const void *buf, uint64_t size) 181 { 182 static const zfs_fletcher_sse_t mask = { 183 .v = { 0x0405060700010203, 0x0C0D0E0F08090A0B } 184 }; 185 186 const uint64_t *ip = buf; 187 const uint64_t *ipend = (uint64_t *)((uint8_t *)ip + size); 188 189 kfpu_begin(); 190 191 FLETCHER_4_SSE_RESTORE_CTX(ctx); 192 193 asm volatile("movdqu %0, %%xmm7"::"m" (mask)); 194 asm volatile("pxor %xmm4, %xmm4"); 195 196 for (; ip < ipend; ip += 2) { 197 asm volatile("movdqu %0, %%xmm5"::"m" (*ip)); 198 asm volatile("pshufb %xmm7, %xmm5"); 199 asm volatile("movdqa %xmm5, %xmm6"); 200 asm volatile("punpckldq %xmm4, %xmm5"); 201 asm volatile("punpckhdq %xmm4, %xmm6"); 202 asm volatile("paddq %xmm5, %xmm0"); 203 asm volatile("paddq %xmm0, %xmm1"); 204 asm volatile("paddq %xmm1, %xmm2"); 205 asm volatile("paddq %xmm2, %xmm3"); 206 asm volatile("paddq %xmm6, %xmm0"); 207 asm volatile("paddq %xmm0, %xmm1"); 208 asm volatile("paddq %xmm1, %xmm2"); 209 asm volatile("paddq %xmm2, %xmm3"); 210 } 211 212 FLETCHER_4_SSE_SAVE_CTX(ctx); 213 214 kfpu_end(); 215 } 216 217 static boolean_t fletcher_4_ssse3_valid(void) 218 { 219 return (kfpu_allowed() && zfs_sse2_available() && 220 zfs_ssse3_available()); 221 } 222 223 const fletcher_4_ops_t fletcher_4_ssse3_ops = { 224 .init_native = fletcher_4_sse2_init, 225 .fini_native = fletcher_4_sse2_fini, 226 .compute_native = fletcher_4_sse2_native, 227 .init_byteswap = fletcher_4_sse2_init, 228 .fini_byteswap = fletcher_4_sse2_fini, 229 .compute_byteswap = fletcher_4_ssse3_byteswap, 230 .valid = fletcher_4_ssse3_valid, 231 .name = "ssse3" 232 }; 233 234 #endif /* defined(HAVE_SSE2) && defined(HAVE_SSSE3) */ 235