1eda14cbcSMatt Macy /* 2eda14cbcSMatt Macy * CDDL HEADER START 3eda14cbcSMatt Macy * 4eda14cbcSMatt Macy * The contents of this file are subject to the terms of the 5eda14cbcSMatt Macy * Common Development and Distribution License (the "License"). 6eda14cbcSMatt Macy * You may not use this file except in compliance with the License. 7eda14cbcSMatt Macy * 8eda14cbcSMatt Macy * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9271171e0SMartin Matuska * or https://opensource.org/licenses/CDDL-1.0. 10eda14cbcSMatt Macy * See the License for the specific language governing permissions 11eda14cbcSMatt Macy * and limitations under the License. 12eda14cbcSMatt Macy * 13eda14cbcSMatt Macy * When distributing Covered Code, include this CDDL HEADER in each 14eda14cbcSMatt Macy * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15eda14cbcSMatt Macy * If applicable, add the following below this CDDL HEADER, with the 16eda14cbcSMatt Macy * fields enclosed by brackets "[]" replaced with your own identifying 17eda14cbcSMatt Macy * information: Portions Copyright [yyyy] [name of copyright owner] 18eda14cbcSMatt Macy * 19eda14cbcSMatt Macy * CDDL HEADER END 20eda14cbcSMatt Macy */ 21eda14cbcSMatt Macy /* 22eda14cbcSMatt Macy * Copyright (C) 2019 Romain Dolbeau. All rights reserved. 23eda14cbcSMatt Macy * <romain.dolbeau@european-processor-initiative.eu> 24eda14cbcSMatt Macy */ 25eda14cbcSMatt Macy 26eda14cbcSMatt Macy #include <sys/types.h> 27eda14cbcSMatt Macy #include <sys/simd.h> 28eda14cbcSMatt Macy 29eda14cbcSMatt Macy #define _REG_CNT(_0, _1, _2, _3, _4, _5, _6, _7, N, ...) N 30eda14cbcSMatt Macy #define REG_CNT(r...) _REG_CNT(r, 8, 7, 6, 5, 4, 3, 2, 1) 31eda14cbcSMatt Macy 32eda14cbcSMatt Macy #define VR0_(REG, ...) "%[w"#REG"]" 33eda14cbcSMatt Macy #define VR1_(_1, REG, ...) "%[w"#REG"]" 34eda14cbcSMatt Macy #define VR2_(_1, _2, REG, ...) "%[w"#REG"]" 35eda14cbcSMatt Macy #define VR3_(_1, _2, _3, REG, ...) "%[w"#REG"]" 36eda14cbcSMatt Macy #define VR4_(_1, _2, _3, _4, REG, ...) "%[w"#REG"]" 37eda14cbcSMatt Macy #define VR5_(_1, _2, _3, _4, _5, REG, ...) "%[w"#REG"]" 38eda14cbcSMatt Macy #define VR6_(_1, _2, _3, _4, _5, _6, REG, ...) "%[w"#REG"]" 39eda14cbcSMatt Macy #define VR7_(_1, _2, _3, _4, _5, _6, _7, REG, ...) "%[w"#REG"]" 40eda14cbcSMatt Macy 41eda14cbcSMatt Macy /* 42eda14cbcSMatt Macy * Here we need registers not used otherwise. 43eda14cbcSMatt Macy * They will be used in unused ASM for the case 44eda14cbcSMatt Macy * with more registers than required... but GCC 45eda14cbcSMatt Macy * will still need to make sure the constraints 46eda14cbcSMatt Macy * are correct, and duplicate constraints are illegal 47eda14cbcSMatt Macy * ... and we use the "register" number as a name 48eda14cbcSMatt Macy */ 49eda14cbcSMatt Macy 50eda14cbcSMatt Macy #define VR0(r...) VR0_(r) 51eda14cbcSMatt Macy #define VR1(r...) VR1_(r) 52eda14cbcSMatt Macy #define VR2(r...) VR2_(r, 36) 53eda14cbcSMatt Macy #define VR3(r...) VR3_(r, 36, 35) 54eda14cbcSMatt Macy #define VR4(r...) VR4_(r, 36, 35, 34, 33) 55eda14cbcSMatt Macy #define VR5(r...) VR5_(r, 36, 35, 34, 33, 32) 56eda14cbcSMatt Macy #define VR6(r...) VR6_(r, 36, 35, 34, 33, 32, 31) 57eda14cbcSMatt Macy #define VR7(r...) VR7_(r, 36, 35, 34, 33, 32, 31, 30) 58eda14cbcSMatt Macy 59eda14cbcSMatt Macy #define VR(X) "%[w"#X"]" 60eda14cbcSMatt Macy 61eda14cbcSMatt Macy #define RVR0_(REG, ...) [w##REG] "v" (w##REG) 62eda14cbcSMatt Macy #define RVR1_(_1, REG, ...) [w##REG] "v" (w##REG) 63eda14cbcSMatt Macy #define RVR2_(_1, _2, REG, ...) [w##REG] "v" (w##REG) 64eda14cbcSMatt Macy #define RVR3_(_1, _2, _3, REG, ...) [w##REG] "v" (w##REG) 65eda14cbcSMatt Macy #define RVR4_(_1, _2, _3, _4, REG, ...) [w##REG] "v" (w##REG) 66eda14cbcSMatt Macy #define RVR5_(_1, _2, _3, _4, _5, REG, ...) [w##REG] "v" (w##REG) 67eda14cbcSMatt Macy #define RVR6_(_1, _2, _3, _4, _5, _6, REG, ...) [w##REG] "v" (w##REG) 68eda14cbcSMatt Macy #define RVR7_(_1, _2, _3, _4, _5, _6, _7, REG, ...) [w##REG] "v" (w##REG) 69eda14cbcSMatt Macy 70eda14cbcSMatt Macy #define RVR0(r...) RVR0_(r) 71eda14cbcSMatt Macy #define RVR1(r...) RVR1_(r) 72eda14cbcSMatt Macy #define RVR2(r...) RVR2_(r, 36) 73eda14cbcSMatt Macy #define RVR3(r...) RVR3_(r, 36, 35) 74eda14cbcSMatt Macy #define RVR4(r...) RVR4_(r, 36, 35, 34, 33) 75eda14cbcSMatt Macy #define RVR5(r...) RVR5_(r, 36, 35, 34, 33, 32) 76eda14cbcSMatt Macy #define RVR6(r...) RVR6_(r, 36, 35, 34, 33, 32, 31) 77eda14cbcSMatt Macy #define RVR7(r...) RVR7_(r, 36, 35, 34, 33, 32, 31, 30) 78eda14cbcSMatt Macy 79eda14cbcSMatt Macy #define RVR(X) [w##X] "v" (w##X) 80eda14cbcSMatt Macy 81eda14cbcSMatt Macy #define WVR0_(REG, ...) [w##REG] "=v" (w##REG) 82eda14cbcSMatt Macy #define WVR1_(_1, REG, ...) [w##REG] "=v" (w##REG) 83eda14cbcSMatt Macy #define WVR2_(_1, _2, REG, ...) [w##REG] "=v" (w##REG) 84eda14cbcSMatt Macy #define WVR3_(_1, _2, _3, REG, ...) [w##REG] "=v" (w##REG) 85eda14cbcSMatt Macy #define WVR4_(_1, _2, _3, _4, REG, ...) [w##REG] "=v" (w##REG) 86eda14cbcSMatt Macy #define WVR5_(_1, _2, _3, _4, _5, REG, ...) [w##REG] "=v" (w##REG) 87eda14cbcSMatt Macy #define WVR6_(_1, _2, _3, _4, _5, _6, REG, ...) [w##REG] "=v" (w##REG) 88eda14cbcSMatt Macy #define WVR7_(_1, _2, _3, _4, _5, _6, _7, REG, ...) [w##REG] "=v" (w##REG) 89eda14cbcSMatt Macy 90eda14cbcSMatt Macy #define WVR0(r...) WVR0_(r) 91eda14cbcSMatt Macy #define WVR1(r...) WVR1_(r) 92eda14cbcSMatt Macy #define WVR2(r...) WVR2_(r, 36) 93eda14cbcSMatt Macy #define WVR3(r...) WVR3_(r, 36, 35) 94eda14cbcSMatt Macy #define WVR4(r...) WVR4_(r, 36, 35, 34, 33) 95eda14cbcSMatt Macy #define WVR5(r...) WVR5_(r, 36, 35, 34, 33, 32) 96eda14cbcSMatt Macy #define WVR6(r...) WVR6_(r, 36, 35, 34, 33, 32, 31) 97eda14cbcSMatt Macy #define WVR7(r...) WVR7_(r, 36, 35, 34, 33, 32, 31, 30) 98eda14cbcSMatt Macy 99eda14cbcSMatt Macy #define WVR(X) [w##X] "=v" (w##X) 100eda14cbcSMatt Macy 101eda14cbcSMatt Macy #define UVR0_(REG, ...) [w##REG] "+&v" (w##REG) 102eda14cbcSMatt Macy #define UVR1_(_1, REG, ...) [w##REG] "+&v" (w##REG) 103eda14cbcSMatt Macy #define UVR2_(_1, _2, REG, ...) [w##REG] "+&v" (w##REG) 104eda14cbcSMatt Macy #define UVR3_(_1, _2, _3, REG, ...) [w##REG] "+&v" (w##REG) 105eda14cbcSMatt Macy #define UVR4_(_1, _2, _3, _4, REG, ...) [w##REG] "+&v" (w##REG) 106eda14cbcSMatt Macy #define UVR5_(_1, _2, _3, _4, _5, REG, ...) [w##REG] "+&v" (w##REG) 107eda14cbcSMatt Macy #define UVR6_(_1, _2, _3, _4, _5, _6, REG, ...) [w##REG] "+&v" (w##REG) 108eda14cbcSMatt Macy #define UVR7_(_1, _2, _3, _4, _5, _6, _7, REG, ...) [w##REG] "+&v" (w##REG) 109eda14cbcSMatt Macy 110eda14cbcSMatt Macy #define UVR0(r...) UVR0_(r) 111eda14cbcSMatt Macy #define UVR1(r...) UVR1_(r) 112eda14cbcSMatt Macy #define UVR2(r...) UVR2_(r, 36) 113eda14cbcSMatt Macy #define UVR3(r...) UVR3_(r, 36, 35) 114eda14cbcSMatt Macy #define UVR4(r...) UVR4_(r, 36, 35, 34, 33) 115eda14cbcSMatt Macy #define UVR5(r...) UVR5_(r, 36, 35, 34, 33, 32) 116eda14cbcSMatt Macy #define UVR6(r...) UVR6_(r, 36, 35, 34, 33, 32, 31) 117eda14cbcSMatt Macy #define UVR7(r...) UVR7_(r, 36, 35, 34, 33, 32, 31, 30) 118eda14cbcSMatt Macy 119eda14cbcSMatt Macy #define UVR(X) [w##X] "+&v" (w##X) 120eda14cbcSMatt Macy 121eda14cbcSMatt Macy #define R_01(REG1, REG2, ...) REG1, REG2 122eda14cbcSMatt Macy #define _R_23(_0, _1, REG2, REG3, ...) REG2, REG3 123eda14cbcSMatt Macy #define R_23(REG...) _R_23(REG, 1, 2, 3) 124eda14cbcSMatt Macy 125eda14cbcSMatt Macy #define ZFS_ASM_BUG() ASSERT(0) 126eda14cbcSMatt Macy 127eda14cbcSMatt Macy #define OFFSET(ptr, val) (((unsigned char *)(ptr))+val) 128eda14cbcSMatt Macy 129eda14cbcSMatt Macy extern const uint8_t gf_clmul_mod_lt[4*256][16]; 130eda14cbcSMatt Macy 131eda14cbcSMatt Macy #define ELEM_SIZE 16 132eda14cbcSMatt Macy 133eda14cbcSMatt Macy typedef struct v { 134eda14cbcSMatt Macy uint8_t b[ELEM_SIZE] __attribute__((aligned(ELEM_SIZE))); 135eda14cbcSMatt Macy } v_t; 136eda14cbcSMatt Macy 137eda14cbcSMatt Macy #define XOR_ACC(src, r...) \ 138eda14cbcSMatt Macy { \ 139eda14cbcSMatt Macy switch (REG_CNT(r)) { \ 140eda14cbcSMatt Macy case 8: \ 141*15f0b8c3SMartin Matuska __asm__ __volatile__( \ 142eda14cbcSMatt Macy "lvx 21,0,%[SRC0]\n" \ 143eda14cbcSMatt Macy "lvx 20,0,%[SRC1]\n" \ 144eda14cbcSMatt Macy "lvx 19,0,%[SRC2]\n" \ 145eda14cbcSMatt Macy "lvx 18,0,%[SRC3]\n" \ 146eda14cbcSMatt Macy "vxor " VR0(r) "," VR0(r) ",21\n" \ 147eda14cbcSMatt Macy "vxor " VR1(r) "," VR1(r) ",20\n" \ 148eda14cbcSMatt Macy "vxor " VR2(r) "," VR2(r) ",19\n" \ 149eda14cbcSMatt Macy "vxor " VR3(r) "," VR3(r) ",18\n" \ 150eda14cbcSMatt Macy "lvx 21,0,%[SRC4]\n" \ 151eda14cbcSMatt Macy "lvx 20,0,%[SRC5]\n" \ 152eda14cbcSMatt Macy "lvx 19,0,%[SRC6]\n" \ 153eda14cbcSMatt Macy "lvx 18,0,%[SRC7]\n" \ 154eda14cbcSMatt Macy "vxor " VR4(r) "," VR4(r) ",21\n" \ 155eda14cbcSMatt Macy "vxor " VR5(r) "," VR5(r) ",20\n" \ 156eda14cbcSMatt Macy "vxor " VR6(r) "," VR6(r) ",19\n" \ 157eda14cbcSMatt Macy "vxor " VR7(r) "," VR7(r) ",18\n" \ 158eda14cbcSMatt Macy : UVR0(r), UVR1(r), UVR2(r), UVR3(r), \ 159eda14cbcSMatt Macy UVR4(r), UVR5(r), UVR6(r), UVR7(r) \ 160eda14cbcSMatt Macy : [SRC0] "r" ((OFFSET(src, 0))), \ 161eda14cbcSMatt Macy [SRC1] "r" ((OFFSET(src, 16))), \ 162eda14cbcSMatt Macy [SRC2] "r" ((OFFSET(src, 32))), \ 163eda14cbcSMatt Macy [SRC3] "r" ((OFFSET(src, 48))), \ 164eda14cbcSMatt Macy [SRC4] "r" ((OFFSET(src, 64))), \ 165eda14cbcSMatt Macy [SRC5] "r" ((OFFSET(src, 80))), \ 166eda14cbcSMatt Macy [SRC6] "r" ((OFFSET(src, 96))), \ 167eda14cbcSMatt Macy [SRC7] "r" ((OFFSET(src, 112))) \ 168eda14cbcSMatt Macy : "v18", "v19", "v20", "v21"); \ 169eda14cbcSMatt Macy break; \ 170eda14cbcSMatt Macy case 4: \ 171*15f0b8c3SMartin Matuska __asm__ __volatile__( \ 172eda14cbcSMatt Macy "lvx 21,0,%[SRC0]\n" \ 173eda14cbcSMatt Macy "lvx 20,0,%[SRC1]\n" \ 174eda14cbcSMatt Macy "lvx 19,0,%[SRC2]\n" \ 175eda14cbcSMatt Macy "lvx 18,0,%[SRC3]\n" \ 176eda14cbcSMatt Macy "vxor " VR0(r) "," VR0(r) ",21\n" \ 177eda14cbcSMatt Macy "vxor " VR1(r) "," VR1(r) ",20\n" \ 178eda14cbcSMatt Macy "vxor " VR2(r) "," VR2(r) ",19\n" \ 179eda14cbcSMatt Macy "vxor " VR3(r) "," VR3(r) ",18\n" \ 180eda14cbcSMatt Macy : UVR0(r), UVR1(r), UVR2(r), UVR3(r) \ 181eda14cbcSMatt Macy : [SRC0] "r" ((OFFSET(src, 0))), \ 182eda14cbcSMatt Macy [SRC1] "r" ((OFFSET(src, 16))), \ 183eda14cbcSMatt Macy [SRC2] "r" ((OFFSET(src, 32))), \ 184eda14cbcSMatt Macy [SRC3] "r" ((OFFSET(src, 48))) \ 185eda14cbcSMatt Macy : "v18", "v19", "v20", "v21"); \ 186eda14cbcSMatt Macy break; \ 187eda14cbcSMatt Macy case 2: \ 188*15f0b8c3SMartin Matuska __asm__ __volatile__( \ 189eda14cbcSMatt Macy "lvx 21,0,%[SRC0]\n" \ 190eda14cbcSMatt Macy "lvx 20,0,%[SRC1]\n" \ 191eda14cbcSMatt Macy "vxor " VR0(r) "," VR0(r) ",21\n" \ 192eda14cbcSMatt Macy "vxor " VR1(r) "," VR1(r) ",20\n" \ 193eda14cbcSMatt Macy : UVR0(r), UVR1(r) \ 194eda14cbcSMatt Macy : [SRC0] "r" ((OFFSET(src, 0))), \ 195eda14cbcSMatt Macy [SRC1] "r" ((OFFSET(src, 16))) \ 196eda14cbcSMatt Macy : "v20", "v21"); \ 197eda14cbcSMatt Macy break; \ 198eda14cbcSMatt Macy default: \ 199eda14cbcSMatt Macy ZFS_ASM_BUG(); \ 200eda14cbcSMatt Macy } \ 201eda14cbcSMatt Macy } 202eda14cbcSMatt Macy 203eda14cbcSMatt Macy #define XOR(r...) \ 204eda14cbcSMatt Macy { \ 205eda14cbcSMatt Macy switch (REG_CNT(r)) { \ 206eda14cbcSMatt Macy case 8: \ 207*15f0b8c3SMartin Matuska __asm__ __volatile__( \ 208eda14cbcSMatt Macy "vxor " VR4(r) "," VR4(r) "," VR0(r) "\n" \ 209eda14cbcSMatt Macy "vxor " VR5(r) "," VR5(r) "," VR1(r) "\n" \ 210eda14cbcSMatt Macy "vxor " VR6(r) "," VR6(r) "," VR2(r) "\n" \ 211eda14cbcSMatt Macy "vxor " VR7(r) "," VR7(r) "," VR3(r) "\n" \ 212eda14cbcSMatt Macy : UVR4(r), UVR5(r), UVR6(r), UVR7(r) \ 213eda14cbcSMatt Macy : RVR0(r), RVR1(r), RVR2(r), RVR3(r)); \ 214eda14cbcSMatt Macy break; \ 215eda14cbcSMatt Macy case 4: \ 216*15f0b8c3SMartin Matuska __asm__ __volatile__( \ 217eda14cbcSMatt Macy "vxor " VR2(r) "," VR2(r) "," VR0(r) "\n" \ 218eda14cbcSMatt Macy "vxor " VR3(r) "," VR3(r) "," VR1(r) "\n" \ 219eda14cbcSMatt Macy : UVR2(r), UVR3(r) \ 220eda14cbcSMatt Macy : RVR0(r), RVR1(r)); \ 221eda14cbcSMatt Macy break; \ 222eda14cbcSMatt Macy default: \ 223eda14cbcSMatt Macy ZFS_ASM_BUG(); \ 224eda14cbcSMatt Macy } \ 225eda14cbcSMatt Macy } 226eda14cbcSMatt Macy 227eda14cbcSMatt Macy #define ZERO(r...) \ 228eda14cbcSMatt Macy { \ 229eda14cbcSMatt Macy switch (REG_CNT(r)) { \ 230eda14cbcSMatt Macy case 8: \ 231*15f0b8c3SMartin Matuska __asm__ __volatile__( \ 232eda14cbcSMatt Macy "vxor " VR0(r) "," VR0(r) "," VR0(r) "\n" \ 233eda14cbcSMatt Macy "vxor " VR1(r) "," VR1(r) "," VR1(r) "\n" \ 234eda14cbcSMatt Macy "vxor " VR2(r) "," VR2(r) "," VR2(r) "\n" \ 235eda14cbcSMatt Macy "vxor " VR3(r) "," VR3(r) "," VR3(r) "\n" \ 236eda14cbcSMatt Macy "vxor " VR4(r) "," VR4(r) "," VR4(r) "\n" \ 237eda14cbcSMatt Macy "vxor " VR5(r) "," VR5(r) "," VR5(r) "\n" \ 238eda14cbcSMatt Macy "vxor " VR6(r) "," VR6(r) "," VR6(r) "\n" \ 239eda14cbcSMatt Macy "vxor " VR7(r) "," VR7(r) "," VR7(r) "\n" \ 240eda14cbcSMatt Macy : WVR0(r), WVR1(r), WVR2(r), WVR3(r), \ 241eda14cbcSMatt Macy WVR4(r), WVR5(r), WVR6(r), WVR7(r)); \ 242eda14cbcSMatt Macy break; \ 243eda14cbcSMatt Macy case 4: \ 244*15f0b8c3SMartin Matuska __asm__ __volatile__( \ 245eda14cbcSMatt Macy "vxor " VR0(r) "," VR0(r) "," VR0(r) "\n" \ 246eda14cbcSMatt Macy "vxor " VR1(r) "," VR1(r) "," VR1(r) "\n" \ 247eda14cbcSMatt Macy "vxor " VR2(r) "," VR2(r) "," VR2(r) "\n" \ 248eda14cbcSMatt Macy "vxor " VR3(r) "," VR3(r) "," VR3(r) "\n" \ 249eda14cbcSMatt Macy : WVR0(r), WVR1(r), WVR2(r), WVR3(r)); \ 250eda14cbcSMatt Macy break; \ 251eda14cbcSMatt Macy case 2: \ 252*15f0b8c3SMartin Matuska __asm__ __volatile__( \ 253eda14cbcSMatt Macy "vxor " VR0(r) "," VR0(r) "," VR0(r) "\n" \ 254eda14cbcSMatt Macy "vxor " VR1(r) "," VR1(r) "," VR1(r) "\n" \ 255eda14cbcSMatt Macy : WVR0(r), WVR1(r)); \ 256eda14cbcSMatt Macy break; \ 257eda14cbcSMatt Macy default: \ 258eda14cbcSMatt Macy ZFS_ASM_BUG(); \ 259eda14cbcSMatt Macy } \ 260eda14cbcSMatt Macy } 261eda14cbcSMatt Macy 262eda14cbcSMatt Macy #define COPY(r...) \ 263eda14cbcSMatt Macy { \ 264eda14cbcSMatt Macy switch (REG_CNT(r)) { \ 265eda14cbcSMatt Macy case 8: \ 266*15f0b8c3SMartin Matuska __asm__ __volatile__( \ 267eda14cbcSMatt Macy "vor " VR4(r) "," VR0(r) "," VR0(r) "\n" \ 268eda14cbcSMatt Macy "vor " VR5(r) "," VR1(r) "," VR1(r) "\n" \ 269eda14cbcSMatt Macy "vor " VR6(r) "," VR2(r) "," VR2(r) "\n" \ 270eda14cbcSMatt Macy "vor " VR7(r) "," VR3(r) "," VR3(r) "\n" \ 271eda14cbcSMatt Macy : WVR4(r), WVR5(r), WVR6(r), WVR7(r) \ 272eda14cbcSMatt Macy : RVR0(r), RVR1(r), RVR2(r), RVR3(r)); \ 273eda14cbcSMatt Macy break; \ 274eda14cbcSMatt Macy case 4: \ 275*15f0b8c3SMartin Matuska __asm__ __volatile__( \ 276eda14cbcSMatt Macy "vor " VR2(r) "," VR0(r) "," VR0(r) "\n" \ 277eda14cbcSMatt Macy "vor " VR3(r) "," VR1(r) "," VR1(r) "\n" \ 278eda14cbcSMatt Macy : WVR2(r), WVR3(r) \ 279eda14cbcSMatt Macy : RVR0(r), RVR1(r)); \ 280eda14cbcSMatt Macy break; \ 281eda14cbcSMatt Macy default: \ 282eda14cbcSMatt Macy ZFS_ASM_BUG(); \ 283eda14cbcSMatt Macy } \ 284eda14cbcSMatt Macy } 285eda14cbcSMatt Macy 286eda14cbcSMatt Macy #define LOAD(src, r...) \ 287eda14cbcSMatt Macy { \ 288eda14cbcSMatt Macy switch (REG_CNT(r)) { \ 289eda14cbcSMatt Macy case 8: \ 290*15f0b8c3SMartin Matuska __asm__ __volatile__( \ 291eda14cbcSMatt Macy "lvx " VR0(r) " ,0,%[SRC0]\n" \ 292eda14cbcSMatt Macy "lvx " VR1(r) " ,0,%[SRC1]\n" \ 293eda14cbcSMatt Macy "lvx " VR2(r) " ,0,%[SRC2]\n" \ 294eda14cbcSMatt Macy "lvx " VR3(r) " ,0,%[SRC3]\n" \ 295eda14cbcSMatt Macy "lvx " VR4(r) " ,0,%[SRC4]\n" \ 296eda14cbcSMatt Macy "lvx " VR5(r) " ,0,%[SRC5]\n" \ 297eda14cbcSMatt Macy "lvx " VR6(r) " ,0,%[SRC6]\n" \ 298eda14cbcSMatt Macy "lvx " VR7(r) " ,0,%[SRC7]\n" \ 299eda14cbcSMatt Macy : WVR0(r), WVR1(r), WVR2(r), WVR3(r), \ 300eda14cbcSMatt Macy WVR4(r), WVR5(r), WVR6(r), WVR7(r) \ 301eda14cbcSMatt Macy : [SRC0] "r" ((OFFSET(src, 0))), \ 302eda14cbcSMatt Macy [SRC1] "r" ((OFFSET(src, 16))), \ 303eda14cbcSMatt Macy [SRC2] "r" ((OFFSET(src, 32))), \ 304eda14cbcSMatt Macy [SRC3] "r" ((OFFSET(src, 48))), \ 305eda14cbcSMatt Macy [SRC4] "r" ((OFFSET(src, 64))), \ 306eda14cbcSMatt Macy [SRC5] "r" ((OFFSET(src, 80))), \ 307eda14cbcSMatt Macy [SRC6] "r" ((OFFSET(src, 96))), \ 308eda14cbcSMatt Macy [SRC7] "r" ((OFFSET(src, 112)))); \ 309eda14cbcSMatt Macy break; \ 310eda14cbcSMatt Macy case 4: \ 311*15f0b8c3SMartin Matuska __asm__ __volatile__( \ 312eda14cbcSMatt Macy "lvx " VR0(r) " ,0,%[SRC0]\n" \ 313eda14cbcSMatt Macy "lvx " VR1(r) " ,0,%[SRC1]\n" \ 314eda14cbcSMatt Macy "lvx " VR2(r) " ,0,%[SRC2]\n" \ 315eda14cbcSMatt Macy "lvx " VR3(r) " ,0,%[SRC3]\n" \ 316eda14cbcSMatt Macy : WVR0(r), WVR1(r), WVR2(r), WVR3(r) \ 317eda14cbcSMatt Macy : [SRC0] "r" ((OFFSET(src, 0))), \ 318eda14cbcSMatt Macy [SRC1] "r" ((OFFSET(src, 16))), \ 319eda14cbcSMatt Macy [SRC2] "r" ((OFFSET(src, 32))), \ 320eda14cbcSMatt Macy [SRC3] "r" ((OFFSET(src, 48)))); \ 321eda14cbcSMatt Macy break; \ 322eda14cbcSMatt Macy case 2: \ 323*15f0b8c3SMartin Matuska __asm__ __volatile__( \ 324eda14cbcSMatt Macy "lvx " VR0(r) " ,0,%[SRC0]\n" \ 325eda14cbcSMatt Macy "lvx " VR1(r) " ,0,%[SRC1]\n" \ 326eda14cbcSMatt Macy : WVR0(r), WVR1(r) \ 327eda14cbcSMatt Macy : [SRC0] "r" ((OFFSET(src, 0))), \ 328eda14cbcSMatt Macy [SRC1] "r" ((OFFSET(src, 16)))); \ 329eda14cbcSMatt Macy break; \ 330eda14cbcSMatt Macy default: \ 331eda14cbcSMatt Macy ZFS_ASM_BUG(); \ 332eda14cbcSMatt Macy } \ 333eda14cbcSMatt Macy } 334eda14cbcSMatt Macy 335eda14cbcSMatt Macy #define STORE(dst, r...) \ 336eda14cbcSMatt Macy { \ 337eda14cbcSMatt Macy switch (REG_CNT(r)) { \ 338eda14cbcSMatt Macy case 8: \ 339*15f0b8c3SMartin Matuska __asm__ __volatile__( \ 340eda14cbcSMatt Macy "stvx " VR0(r) " ,0,%[DST0]\n" \ 341eda14cbcSMatt Macy "stvx " VR1(r) " ,0,%[DST1]\n" \ 342eda14cbcSMatt Macy "stvx " VR2(r) " ,0,%[DST2]\n" \ 343eda14cbcSMatt Macy "stvx " VR3(r) " ,0,%[DST3]\n" \ 344eda14cbcSMatt Macy "stvx " VR4(r) " ,0,%[DST4]\n" \ 345eda14cbcSMatt Macy "stvx " VR5(r) " ,0,%[DST5]\n" \ 346eda14cbcSMatt Macy "stvx " VR6(r) " ,0,%[DST6]\n" \ 347eda14cbcSMatt Macy "stvx " VR7(r) " ,0,%[DST7]\n" \ 348eda14cbcSMatt Macy : : [DST0] "r" ((OFFSET(dst, 0))), \ 349eda14cbcSMatt Macy [DST1] "r" ((OFFSET(dst, 16))), \ 350eda14cbcSMatt Macy [DST2] "r" ((OFFSET(dst, 32))), \ 351eda14cbcSMatt Macy [DST3] "r" ((OFFSET(dst, 48))), \ 352eda14cbcSMatt Macy [DST4] "r" ((OFFSET(dst, 64))), \ 353eda14cbcSMatt Macy [DST5] "r" ((OFFSET(dst, 80))), \ 354eda14cbcSMatt Macy [DST6] "r" ((OFFSET(dst, 96))), \ 355eda14cbcSMatt Macy [DST7] "r" ((OFFSET(dst, 112))), \ 356eda14cbcSMatt Macy RVR0(r), RVR1(r), RVR2(r), RVR3(r), \ 357eda14cbcSMatt Macy RVR4(r), RVR5(r), RVR6(r), RVR7(r) \ 358eda14cbcSMatt Macy : "memory"); \ 359eda14cbcSMatt Macy break; \ 360eda14cbcSMatt Macy case 4: \ 361*15f0b8c3SMartin Matuska __asm__ __volatile__( \ 362eda14cbcSMatt Macy "stvx " VR0(r) " ,0,%[DST0]\n" \ 363eda14cbcSMatt Macy "stvx " VR1(r) " ,0,%[DST1]\n" \ 364eda14cbcSMatt Macy "stvx " VR2(r) " ,0,%[DST2]\n" \ 365eda14cbcSMatt Macy "stvx " VR3(r) " ,0,%[DST3]\n" \ 366eda14cbcSMatt Macy : : [DST0] "r" ((OFFSET(dst, 0))), \ 367eda14cbcSMatt Macy [DST1] "r" ((OFFSET(dst, 16))), \ 368eda14cbcSMatt Macy [DST2] "r" ((OFFSET(dst, 32))), \ 369eda14cbcSMatt Macy [DST3] "r" ((OFFSET(dst, 48))), \ 370eda14cbcSMatt Macy RVR0(r), RVR1(r), RVR2(r), RVR3(r) \ 371eda14cbcSMatt Macy : "memory"); \ 372eda14cbcSMatt Macy break; \ 373eda14cbcSMatt Macy case 2: \ 374*15f0b8c3SMartin Matuska __asm__ __volatile__( \ 375eda14cbcSMatt Macy "stvx " VR0(r) " ,0,%[DST0]\n" \ 376eda14cbcSMatt Macy "stvx " VR1(r) " ,0,%[DST1]\n" \ 377eda14cbcSMatt Macy : : [DST0] "r" ((OFFSET(dst, 0))), \ 378eda14cbcSMatt Macy [DST1] "r" ((OFFSET(dst, 16))), \ 379eda14cbcSMatt Macy RVR0(r), RVR1(r) : "memory"); \ 380eda14cbcSMatt Macy break; \ 381eda14cbcSMatt Macy default: \ 382eda14cbcSMatt Macy ZFS_ASM_BUG(); \ 383eda14cbcSMatt Macy } \ 384eda14cbcSMatt Macy } 385eda14cbcSMatt Macy 386eda14cbcSMatt Macy /* 387eda14cbcSMatt Macy * Unfortunately cannot use the macro, because GCC 388eda14cbcSMatt Macy * will try to use the macro name and not value 389eda14cbcSMatt Macy * later on... 390eda14cbcSMatt Macy * Kept as a reference to what a numbered variable is 391eda14cbcSMatt Macy */ 392eda14cbcSMatt Macy #define _00 "17" 393eda14cbcSMatt Macy #define _1d "16" 394eda14cbcSMatt Macy #define _temp0 "19" 395eda14cbcSMatt Macy #define _temp1 "18" 396eda14cbcSMatt Macy 397eda14cbcSMatt Macy #define MUL2_SETUP() \ 398eda14cbcSMatt Macy { \ 399*15f0b8c3SMartin Matuska __asm__ __volatile__( \ 400eda14cbcSMatt Macy "vspltisb " VR(16) ",14\n" \ 401eda14cbcSMatt Macy "vspltisb " VR(17) ",15\n" \ 402eda14cbcSMatt Macy "vaddubm " VR(16) "," VR(17) "," VR(16) "\n" \ 403eda14cbcSMatt Macy "vxor " VR(17) "," VR(17) "," VR(17) "\n" \ 404eda14cbcSMatt Macy : WVR(16), WVR(17)); \ 405eda14cbcSMatt Macy } 406eda14cbcSMatt Macy 407eda14cbcSMatt Macy #define MUL2(r...) \ 408eda14cbcSMatt Macy { \ 409eda14cbcSMatt Macy switch (REG_CNT(r)) { \ 410eda14cbcSMatt Macy case 4: \ 411*15f0b8c3SMartin Matuska __asm__ __volatile__( \ 412eda14cbcSMatt Macy "vcmpgtsb 19," VR(17) "," VR0(r) "\n" \ 413eda14cbcSMatt Macy "vcmpgtsb 18," VR(17) "," VR1(r) "\n" \ 414eda14cbcSMatt Macy "vcmpgtsb 21," VR(17) "," VR2(r) "\n" \ 415eda14cbcSMatt Macy "vcmpgtsb 20," VR(17) "," VR3(r) "\n" \ 416eda14cbcSMatt Macy "vand 19,19," VR(16) "\n" \ 417eda14cbcSMatt Macy "vand 18,18," VR(16) "\n" \ 418eda14cbcSMatt Macy "vand 21,21," VR(16) "\n" \ 419eda14cbcSMatt Macy "vand 20,20," VR(16) "\n" \ 420eda14cbcSMatt Macy "vaddubm " VR0(r) "," VR0(r) "," VR0(r) "\n" \ 421eda14cbcSMatt Macy "vaddubm " VR1(r) "," VR1(r) "," VR1(r) "\n" \ 422eda14cbcSMatt Macy "vaddubm " VR2(r) "," VR2(r) "," VR2(r) "\n" \ 423eda14cbcSMatt Macy "vaddubm " VR3(r) "," VR3(r) "," VR3(r) "\n" \ 424eda14cbcSMatt Macy "vxor " VR0(r) ",19," VR0(r) "\n" \ 425eda14cbcSMatt Macy "vxor " VR1(r) ",18," VR1(r) "\n" \ 426eda14cbcSMatt Macy "vxor " VR2(r) ",21," VR2(r) "\n" \ 427eda14cbcSMatt Macy "vxor " VR3(r) ",20," VR3(r) "\n" \ 428eda14cbcSMatt Macy : UVR0(r), UVR1(r), UVR2(r), UVR3(r) \ 429eda14cbcSMatt Macy : RVR(17), RVR(16) \ 430eda14cbcSMatt Macy : "v18", "v19", "v20", "v21"); \ 431eda14cbcSMatt Macy break; \ 432eda14cbcSMatt Macy case 2: \ 433*15f0b8c3SMartin Matuska __asm__ __volatile__( \ 434eda14cbcSMatt Macy "vcmpgtsb 19," VR(17) "," VR0(r) "\n" \ 435eda14cbcSMatt Macy "vcmpgtsb 18," VR(17) "," VR1(r) "\n" \ 436eda14cbcSMatt Macy "vand 19,19," VR(16) "\n" \ 437eda14cbcSMatt Macy "vand 18,18," VR(16) "\n" \ 438eda14cbcSMatt Macy "vaddubm " VR0(r) "," VR0(r) "," VR0(r) "\n" \ 439eda14cbcSMatt Macy "vaddubm " VR1(r) "," VR1(r) "," VR1(r) "\n" \ 440eda14cbcSMatt Macy "vxor " VR0(r) ",19," VR0(r) "\n" \ 441eda14cbcSMatt Macy "vxor " VR1(r) ",18," VR1(r) "\n" \ 442eda14cbcSMatt Macy : UVR0(r), UVR1(r) \ 443eda14cbcSMatt Macy : RVR(17), RVR(16) \ 444eda14cbcSMatt Macy : "v18", "v19"); \ 445eda14cbcSMatt Macy break; \ 446eda14cbcSMatt Macy default: \ 447eda14cbcSMatt Macy ZFS_ASM_BUG(); \ 448eda14cbcSMatt Macy } \ 449eda14cbcSMatt Macy } 450eda14cbcSMatt Macy 451eda14cbcSMatt Macy #define MUL4(r...) \ 452eda14cbcSMatt Macy { \ 453eda14cbcSMatt Macy MUL2(r); \ 454eda14cbcSMatt Macy MUL2(r); \ 455eda14cbcSMatt Macy } 456eda14cbcSMatt Macy 457eda14cbcSMatt Macy /* 458eda14cbcSMatt Macy * Unfortunately cannot use the macro, because GCC 459eda14cbcSMatt Macy * will try to use the macro name and not value 460eda14cbcSMatt Macy * later on... 461eda14cbcSMatt Macy * Kept as a reference to what a register is 462eda14cbcSMatt Macy * (here we're using actual registers for the 463eda14cbcSMatt Macy * clobbered ones) 464eda14cbcSMatt Macy */ 465eda14cbcSMatt Macy #define _0f "15" 466eda14cbcSMatt Macy #define _a_save "14" 467eda14cbcSMatt Macy #define _b_save "13" 468eda14cbcSMatt Macy #define _lt_mod_a "12" 469eda14cbcSMatt Macy #define _lt_clmul_a "11" 470eda14cbcSMatt Macy #define _lt_mod_b "10" 471eda14cbcSMatt Macy #define _lt_clmul_b "15" 472eda14cbcSMatt Macy 473eda14cbcSMatt Macy #define _MULx2(c, r...) \ 474eda14cbcSMatt Macy { \ 475eda14cbcSMatt Macy switch (REG_CNT(r)) { \ 476eda14cbcSMatt Macy case 2: \ 477*15f0b8c3SMartin Matuska __asm__ __volatile__( \ 478eda14cbcSMatt Macy /* lts for upper part */ \ 479eda14cbcSMatt Macy "vspltisb 15,15\n" \ 480eda14cbcSMatt Macy "lvx 10,0,%[lt0]\n" \ 481eda14cbcSMatt Macy "lvx 11,0,%[lt1]\n" \ 482eda14cbcSMatt Macy /* upper part */ \ 483eda14cbcSMatt Macy "vand 14," VR0(r) ",15\n" \ 484eda14cbcSMatt Macy "vand 13," VR1(r) ",15\n" \ 485eda14cbcSMatt Macy "vspltisb 15,4\n" \ 486eda14cbcSMatt Macy "vsrab " VR0(r) "," VR0(r) ",15\n" \ 487eda14cbcSMatt Macy "vsrab " VR1(r) "," VR1(r) ",15\n" \ 488eda14cbcSMatt Macy \ 489eda14cbcSMatt Macy "vperm 12,10,10," VR0(r) "\n" \ 490eda14cbcSMatt Macy "vperm 10,10,10," VR1(r) "\n" \ 491eda14cbcSMatt Macy "vperm 15,11,11," VR0(r) "\n" \ 492eda14cbcSMatt Macy "vperm 11,11,11," VR1(r) "\n" \ 493eda14cbcSMatt Macy \ 494eda14cbcSMatt Macy "vxor " VR0(r) ",15,12\n" \ 495eda14cbcSMatt Macy "vxor " VR1(r) ",11,10\n" \ 496eda14cbcSMatt Macy /* lts for lower part */ \ 497eda14cbcSMatt Macy "lvx 10,0,%[lt2]\n" \ 498eda14cbcSMatt Macy "lvx 15,0,%[lt3]\n" \ 499eda14cbcSMatt Macy /* lower part */ \ 500eda14cbcSMatt Macy "vperm 12,10,10,14\n" \ 501eda14cbcSMatt Macy "vperm 10,10,10,13\n" \ 502eda14cbcSMatt Macy "vperm 11,15,15,14\n" \ 503eda14cbcSMatt Macy "vperm 15,15,15,13\n" \ 504eda14cbcSMatt Macy \ 505eda14cbcSMatt Macy "vxor " VR0(r) "," VR0(r) ",12\n" \ 506eda14cbcSMatt Macy "vxor " VR1(r) "," VR1(r) ",10\n" \ 507eda14cbcSMatt Macy "vxor " VR0(r) "," VR0(r) ",11\n" \ 508eda14cbcSMatt Macy "vxor " VR1(r) "," VR1(r) ",15\n" \ 509eda14cbcSMatt Macy : UVR0(r), UVR1(r) \ 510eda14cbcSMatt Macy : [lt0] "r" (&(gf_clmul_mod_lt[4*(c)+0][0])), \ 511eda14cbcSMatt Macy [lt1] "r" (&(gf_clmul_mod_lt[4*(c)+1][0])), \ 512eda14cbcSMatt Macy [lt2] "r" (&(gf_clmul_mod_lt[4*(c)+2][0])), \ 513eda14cbcSMatt Macy [lt3] "r" (&(gf_clmul_mod_lt[4*(c)+3][0])) \ 514eda14cbcSMatt Macy : "v10", "v11", "v12", "v13", "v14", "v15"); \ 515eda14cbcSMatt Macy break; \ 516eda14cbcSMatt Macy default: \ 517eda14cbcSMatt Macy ZFS_ASM_BUG(); \ 518eda14cbcSMatt Macy } \ 519eda14cbcSMatt Macy } 520eda14cbcSMatt Macy 521eda14cbcSMatt Macy #define MUL(c, r...) \ 522eda14cbcSMatt Macy { \ 523eda14cbcSMatt Macy switch (REG_CNT(r)) { \ 524eda14cbcSMatt Macy case 4: \ 525eda14cbcSMatt Macy _MULx2(c, R_23(r)); \ 526eda14cbcSMatt Macy _MULx2(c, R_01(r)); \ 527eda14cbcSMatt Macy break; \ 528eda14cbcSMatt Macy case 2: \ 529eda14cbcSMatt Macy _MULx2(c, R_01(r)); \ 530eda14cbcSMatt Macy break; \ 531eda14cbcSMatt Macy default: \ 532eda14cbcSMatt Macy ZFS_ASM_BUG(); \ 533eda14cbcSMatt Macy } \ 534eda14cbcSMatt Macy } 535eda14cbcSMatt Macy 536eda14cbcSMatt Macy #define raidz_math_begin() kfpu_begin() 537eda14cbcSMatt Macy #define raidz_math_end() kfpu_end() 538eda14cbcSMatt Macy 539eda14cbcSMatt Macy /* Overkill... */ 540eda14cbcSMatt Macy #if 0 // defined(_KERNEL) 541eda14cbcSMatt Macy #define GEN_X_DEFINE_0_3() \ 542eda14cbcSMatt Macy register unsigned char w0 asm("0") __attribute__((vector_size(16))); \ 543eda14cbcSMatt Macy register unsigned char w1 asm("1") __attribute__((vector_size(16))); \ 544eda14cbcSMatt Macy register unsigned char w2 asm("2") __attribute__((vector_size(16))); \ 545eda14cbcSMatt Macy register unsigned char w3 asm("3") __attribute__((vector_size(16))); 546eda14cbcSMatt Macy #define GEN_X_DEFINE_4_5() \ 547eda14cbcSMatt Macy register unsigned char w4 asm("4") __attribute__((vector_size(16))); \ 548eda14cbcSMatt Macy register unsigned char w5 asm("5") __attribute__((vector_size(16))); 549eda14cbcSMatt Macy #define GEN_X_DEFINE_6_7() \ 550eda14cbcSMatt Macy register unsigned char w6 asm("6") __attribute__((vector_size(16))); \ 551eda14cbcSMatt Macy register unsigned char w7 asm("7") __attribute__((vector_size(16))); 552eda14cbcSMatt Macy #define GEN_X_DEFINE_8_9() \ 553eda14cbcSMatt Macy register unsigned char w8 asm("8") __attribute__((vector_size(16))); \ 554eda14cbcSMatt Macy register unsigned char w9 asm("9") __attribute__((vector_size(16))); 555eda14cbcSMatt Macy #define GEN_X_DEFINE_10_11() \ 556eda14cbcSMatt Macy register unsigned char w10 asm("10") __attribute__((vector_size(16))); \ 557eda14cbcSMatt Macy register unsigned char w11 asm("11") __attribute__((vector_size(16))); 558eda14cbcSMatt Macy #define GEN_X_DEFINE_12_15() \ 559eda14cbcSMatt Macy register unsigned char w12 asm("12") __attribute__((vector_size(16))); \ 560eda14cbcSMatt Macy register unsigned char w13 asm("13") __attribute__((vector_size(16))); \ 561eda14cbcSMatt Macy register unsigned char w14 asm("14") __attribute__((vector_size(16))); \ 562eda14cbcSMatt Macy register unsigned char w15 asm("15") __attribute__((vector_size(16))); 563eda14cbcSMatt Macy #define GEN_X_DEFINE_16() \ 564eda14cbcSMatt Macy register unsigned char w16 asm("16") __attribute__((vector_size(16))); 565eda14cbcSMatt Macy #define GEN_X_DEFINE_17() \ 566eda14cbcSMatt Macy register unsigned char w17 asm("17") __attribute__((vector_size(16))); 567eda14cbcSMatt Macy #define GEN_X_DEFINE_18_21() \ 568eda14cbcSMatt Macy register unsigned char w18 asm("18") __attribute__((vector_size(16))); \ 569eda14cbcSMatt Macy register unsigned char w19 asm("19") __attribute__((vector_size(16))); \ 570eda14cbcSMatt Macy register unsigned char w20 asm("20") __attribute__((vector_size(16))); \ 571eda14cbcSMatt Macy register unsigned char w21 asm("21") __attribute__((vector_size(16))); 572eda14cbcSMatt Macy #define GEN_X_DEFINE_22_23() \ 573eda14cbcSMatt Macy register unsigned char w22 asm("22") __attribute__((vector_size(16))); \ 574eda14cbcSMatt Macy register unsigned char w23 asm("23") __attribute__((vector_size(16))); 575eda14cbcSMatt Macy #define GEN_X_DEFINE_24_27() \ 576eda14cbcSMatt Macy register unsigned char w24 asm("24") __attribute__((vector_size(16))); \ 577eda14cbcSMatt Macy register unsigned char w25 asm("25") __attribute__((vector_size(16))); \ 578eda14cbcSMatt Macy register unsigned char w26 asm("26") __attribute__((vector_size(16))); \ 579eda14cbcSMatt Macy register unsigned char w27 asm("27") __attribute__((vector_size(16))); 580eda14cbcSMatt Macy #define GEN_X_DEFINE_28_30() \ 581eda14cbcSMatt Macy register unsigned char w28 asm("28") __attribute__((vector_size(16))); \ 582eda14cbcSMatt Macy register unsigned char w29 asm("29") __attribute__((vector_size(16))); \ 583eda14cbcSMatt Macy register unsigned char w30 asm("30") __attribute__((vector_size(16))); 584eda14cbcSMatt Macy #define GEN_X_DEFINE_31() \ 585eda14cbcSMatt Macy register unsigned char w31 asm("31") __attribute__((vector_size(16))); 586eda14cbcSMatt Macy #define GEN_X_DEFINE_32() \ 587eda14cbcSMatt Macy register unsigned char w32 asm("31") __attribute__((vector_size(16))); 588eda14cbcSMatt Macy #define GEN_X_DEFINE_33_36() \ 589eda14cbcSMatt Macy register unsigned char w33 asm("31") __attribute__((vector_size(16))); \ 590eda14cbcSMatt Macy register unsigned char w34 asm("31") __attribute__((vector_size(16))); \ 591eda14cbcSMatt Macy register unsigned char w35 asm("31") __attribute__((vector_size(16))); \ 592eda14cbcSMatt Macy register unsigned char w36 asm("31") __attribute__((vector_size(16))); 593eda14cbcSMatt Macy #define GEN_X_DEFINE_37_38() \ 594eda14cbcSMatt Macy register unsigned char w37 asm("31") __attribute__((vector_size(16))); \ 595eda14cbcSMatt Macy register unsigned char w38 asm("31") __attribute__((vector_size(16))); 596eda14cbcSMatt Macy #define GEN_X_DEFINE_ALL() \ 597eda14cbcSMatt Macy GEN_X_DEFINE_0_3() \ 598eda14cbcSMatt Macy GEN_X_DEFINE_4_5() \ 599eda14cbcSMatt Macy GEN_X_DEFINE_6_7() \ 600eda14cbcSMatt Macy GEN_X_DEFINE_8_9() \ 601eda14cbcSMatt Macy GEN_X_DEFINE_10_11() \ 602eda14cbcSMatt Macy GEN_X_DEFINE_12_15() \ 603eda14cbcSMatt Macy GEN_X_DEFINE_16() \ 604eda14cbcSMatt Macy GEN_X_DEFINE_17() \ 605eda14cbcSMatt Macy GEN_X_DEFINE_18_21() \ 606eda14cbcSMatt Macy GEN_X_DEFINE_22_23() \ 607eda14cbcSMatt Macy GEN_X_DEFINE_24_27() \ 608eda14cbcSMatt Macy GEN_X_DEFINE_28_30() \ 609eda14cbcSMatt Macy GEN_X_DEFINE_31() \ 610eda14cbcSMatt Macy GEN_X_DEFINE_32() \ 611eda14cbcSMatt Macy GEN_X_DEFINE_33_36() \ 612eda14cbcSMatt Macy GEN_X_DEFINE_37_38() 613eda14cbcSMatt Macy #else 614eda14cbcSMatt Macy #define GEN_X_DEFINE_0_3() \ 615eda14cbcSMatt Macy unsigned char w0 __attribute__((vector_size(16))); \ 616eda14cbcSMatt Macy unsigned char w1 __attribute__((vector_size(16))); \ 617eda14cbcSMatt Macy unsigned char w2 __attribute__((vector_size(16))); \ 618eda14cbcSMatt Macy unsigned char w3 __attribute__((vector_size(16))); 619eda14cbcSMatt Macy #define GEN_X_DEFINE_4_5() \ 620eda14cbcSMatt Macy unsigned char w4 __attribute__((vector_size(16))); \ 621eda14cbcSMatt Macy unsigned char w5 __attribute__((vector_size(16))); 622eda14cbcSMatt Macy #define GEN_X_DEFINE_6_7() \ 623eda14cbcSMatt Macy unsigned char w6 __attribute__((vector_size(16))); \ 624eda14cbcSMatt Macy unsigned char w7 __attribute__((vector_size(16))); 625eda14cbcSMatt Macy #define GEN_X_DEFINE_8_9() \ 626eda14cbcSMatt Macy unsigned char w8 __attribute__((vector_size(16))); \ 627eda14cbcSMatt Macy unsigned char w9 __attribute__((vector_size(16))); 628eda14cbcSMatt Macy #define GEN_X_DEFINE_10_11() \ 629eda14cbcSMatt Macy unsigned char w10 __attribute__((vector_size(16))); \ 630eda14cbcSMatt Macy unsigned char w11 __attribute__((vector_size(16))); 631eda14cbcSMatt Macy #define GEN_X_DEFINE_12_15() \ 632eda14cbcSMatt Macy unsigned char w12 __attribute__((vector_size(16))); \ 633eda14cbcSMatt Macy unsigned char w13 __attribute__((vector_size(16))); \ 634eda14cbcSMatt Macy unsigned char w14 __attribute__((vector_size(16))); \ 635eda14cbcSMatt Macy unsigned char w15 __attribute__((vector_size(16))); 636eda14cbcSMatt Macy #define GEN_X_DEFINE_16() \ 637eda14cbcSMatt Macy unsigned char w16 __attribute__((vector_size(16))); 638eda14cbcSMatt Macy #define GEN_X_DEFINE_17() \ 639eda14cbcSMatt Macy unsigned char w17 __attribute__((vector_size(16))); 640eda14cbcSMatt Macy #define GEN_X_DEFINE_18_21() \ 641eda14cbcSMatt Macy unsigned char w18 __attribute__((vector_size(16))); \ 642eda14cbcSMatt Macy unsigned char w19 __attribute__((vector_size(16))); \ 643eda14cbcSMatt Macy unsigned char w20 __attribute__((vector_size(16))); \ 644eda14cbcSMatt Macy unsigned char w21 __attribute__((vector_size(16))); 645eda14cbcSMatt Macy #define GEN_X_DEFINE_22_23() \ 646eda14cbcSMatt Macy unsigned char w22 __attribute__((vector_size(16))); \ 647eda14cbcSMatt Macy unsigned char w23 __attribute__((vector_size(16))); 648eda14cbcSMatt Macy #define GEN_X_DEFINE_24_27() \ 649eda14cbcSMatt Macy unsigned char w24 __attribute__((vector_size(16))); \ 650eda14cbcSMatt Macy unsigned char w25 __attribute__((vector_size(16))); \ 651eda14cbcSMatt Macy unsigned char w26 __attribute__((vector_size(16))); \ 652eda14cbcSMatt Macy unsigned char w27 __attribute__((vector_size(16))); 653eda14cbcSMatt Macy #define GEN_X_DEFINE_28_30() \ 654eda14cbcSMatt Macy unsigned char w28 __attribute__((vector_size(16))); \ 655eda14cbcSMatt Macy unsigned char w29 __attribute__((vector_size(16))); \ 656eda14cbcSMatt Macy unsigned char w30 __attribute__((vector_size(16))); 657eda14cbcSMatt Macy #define GEN_X_DEFINE_31() \ 658eda14cbcSMatt Macy unsigned char w31 __attribute__((vector_size(16))); 659eda14cbcSMatt Macy #define GEN_X_DEFINE_32() \ 660eda14cbcSMatt Macy unsigned char w32 __attribute__((vector_size(16))); 661eda14cbcSMatt Macy #define GEN_X_DEFINE_33_36() \ 662eda14cbcSMatt Macy unsigned char w33 __attribute__((vector_size(16))); \ 663eda14cbcSMatt Macy unsigned char w34 __attribute__((vector_size(16))); \ 664eda14cbcSMatt Macy unsigned char w35 __attribute__((vector_size(16))); \ 665eda14cbcSMatt Macy unsigned char w36 __attribute__((vector_size(16))); 666eda14cbcSMatt Macy #define GEN_X_DEFINE_37_38() \ 667eda14cbcSMatt Macy unsigned char w37 __attribute__((vector_size(16))); \ 668eda14cbcSMatt Macy unsigned char w38 __attribute__((vector_size(16))); 669eda14cbcSMatt Macy #define GEN_X_DEFINE_ALL() \ 670eda14cbcSMatt Macy GEN_X_DEFINE_0_3() \ 671eda14cbcSMatt Macy GEN_X_DEFINE_4_5() \ 672eda14cbcSMatt Macy GEN_X_DEFINE_6_7() \ 673eda14cbcSMatt Macy GEN_X_DEFINE_8_9() \ 674eda14cbcSMatt Macy GEN_X_DEFINE_10_11() \ 675eda14cbcSMatt Macy GEN_X_DEFINE_12_15() \ 676eda14cbcSMatt Macy GEN_X_DEFINE_16() \ 677eda14cbcSMatt Macy GEN_X_DEFINE_17() \ 678eda14cbcSMatt Macy GEN_X_DEFINE_18_21() \ 679eda14cbcSMatt Macy GEN_X_DEFINE_22_23() \ 680eda14cbcSMatt Macy GEN_X_DEFINE_24_27() \ 681eda14cbcSMatt Macy GEN_X_DEFINE_28_30() \ 682eda14cbcSMatt Macy GEN_X_DEFINE_31() \ 683eda14cbcSMatt Macy GEN_X_DEFINE_32() \ 684eda14cbcSMatt Macy GEN_X_DEFINE_33_36() \ 685eda14cbcSMatt Macy GEN_X_DEFINE_37_38() 686eda14cbcSMatt Macy #endif 687