13a9fd824SRoger Pau Monné /* 23a9fd824SRoger Pau Monné * Permission is hereby granted, free of charge, to any person obtaining a copy 33a9fd824SRoger Pau Monné * of this software and associated documentation files (the "Software"), to 43a9fd824SRoger Pau Monné * deal in the Software without restriction, including without limitation the 53a9fd824SRoger Pau Monné * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 63a9fd824SRoger Pau Monné * sell copies of the Software, and to permit persons to whom the Software is 73a9fd824SRoger Pau Monné * furnished to do so, subject to the following conditions: 83a9fd824SRoger Pau Monné * 93a9fd824SRoger Pau Monné * The above copyright notice and this permission notice shall be included in 103a9fd824SRoger Pau Monné * all copies or substantial portions of the Software. 113a9fd824SRoger Pau Monné * 123a9fd824SRoger Pau Monné * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 133a9fd824SRoger Pau Monné * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 143a9fd824SRoger Pau Monné * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 153a9fd824SRoger Pau Monné * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 163a9fd824SRoger Pau Monné * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 173a9fd824SRoger Pau Monné * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 183a9fd824SRoger Pau Monné * DEALINGS IN THE SOFTWARE. 193a9fd824SRoger Pau Monné * 203a9fd824SRoger Pau Monné * Copyright (c) 2015, Roger Pau Monne <roger.pau@citrix.com> 213a9fd824SRoger Pau Monné */ 223a9fd824SRoger Pau Monné 233a9fd824SRoger Pau Monné #ifndef __XEN_PUBLIC_HVM_HVM_VCPU_H__ 243a9fd824SRoger Pau Monné #define __XEN_PUBLIC_HVM_HVM_VCPU_H__ 253a9fd824SRoger Pau Monné 263a9fd824SRoger Pau Monné #include "../xen.h" 273a9fd824SRoger Pau Monné 283a9fd824SRoger Pau Monné struct vcpu_hvm_x86_32 { 293a9fd824SRoger Pau Monné uint32_t eax; 303a9fd824SRoger Pau Monné uint32_t ecx; 313a9fd824SRoger Pau Monné uint32_t edx; 323a9fd824SRoger Pau Monné uint32_t ebx; 333a9fd824SRoger Pau Monné uint32_t esp; 343a9fd824SRoger Pau Monné uint32_t ebp; 353a9fd824SRoger Pau Monné uint32_t esi; 363a9fd824SRoger Pau Monné uint32_t edi; 373a9fd824SRoger Pau Monné uint32_t eip; 383a9fd824SRoger Pau Monné uint32_t eflags; 393a9fd824SRoger Pau Monné 403a9fd824SRoger Pau Monné uint32_t cr0; 413a9fd824SRoger Pau Monné uint32_t cr3; 423a9fd824SRoger Pau Monné uint32_t cr4; 433a9fd824SRoger Pau Monné 443a9fd824SRoger Pau Monné uint32_t pad1; 453a9fd824SRoger Pau Monné 463a9fd824SRoger Pau Monné /* 473a9fd824SRoger Pau Monné * EFER should only be used to set the NXE bit (if required) 483a9fd824SRoger Pau Monné * when starting a vCPU in 32bit mode with paging enabled or 493a9fd824SRoger Pau Monné * to set the LME/LMA bits in order to start the vCPU in 503a9fd824SRoger Pau Monné * compatibility mode. 513a9fd824SRoger Pau Monné */ 523a9fd824SRoger Pau Monné uint64_t efer; 533a9fd824SRoger Pau Monné 543a9fd824SRoger Pau Monné uint32_t cs_base; 553a9fd824SRoger Pau Monné uint32_t ds_base; 563a9fd824SRoger Pau Monné uint32_t ss_base; 573a9fd824SRoger Pau Monné uint32_t es_base; 583a9fd824SRoger Pau Monné uint32_t tr_base; 593a9fd824SRoger Pau Monné uint32_t cs_limit; 603a9fd824SRoger Pau Monné uint32_t ds_limit; 613a9fd824SRoger Pau Monné uint32_t ss_limit; 623a9fd824SRoger Pau Monné uint32_t es_limit; 633a9fd824SRoger Pau Monné uint32_t tr_limit; 643a9fd824SRoger Pau Monné uint16_t cs_ar; 653a9fd824SRoger Pau Monné uint16_t ds_ar; 663a9fd824SRoger Pau Monné uint16_t ss_ar; 673a9fd824SRoger Pau Monné uint16_t es_ar; 683a9fd824SRoger Pau Monné uint16_t tr_ar; 693a9fd824SRoger Pau Monné 703a9fd824SRoger Pau Monné uint16_t pad2[3]; 713a9fd824SRoger Pau Monné }; 723a9fd824SRoger Pau Monné typedef struct vcpu_hvm_x86_32 xen_vcpu_hvm_x86_32_t; 733a9fd824SRoger Pau Monné 743a9fd824SRoger Pau Monné /* 753a9fd824SRoger Pau Monné * The layout of the _ar fields of the segment registers is the 763a9fd824SRoger Pau Monné * following: 773a9fd824SRoger Pau Monné * 783a9fd824SRoger Pau Monné * Bits [0,3]: type (bits 40-43). 793a9fd824SRoger Pau Monné * Bit 4: s (descriptor type, bit 44). 803a9fd824SRoger Pau Monné * Bit [5,6]: dpl (descriptor privilege level, bits 45-46). 813a9fd824SRoger Pau Monné * Bit 7: p (segment-present, bit 47). 823a9fd824SRoger Pau Monné * Bit 8: avl (available for system software, bit 52). 833a9fd824SRoger Pau Monné * Bit 9: l (64-bit code segment, bit 53). 843a9fd824SRoger Pau Monné * Bit 10: db (meaning depends on the segment, bit 54). 853a9fd824SRoger Pau Monné * Bit 11: g (granularity, bit 55) 863a9fd824SRoger Pau Monné * Bits [12,15]: unused, must be blank. 873a9fd824SRoger Pau Monné * 883a9fd824SRoger Pau Monné * A more complete description of the meaning of this fields can be 893a9fd824SRoger Pau Monné * obtained from the Intel SDM, Volume 3, section 3.4.5. 903a9fd824SRoger Pau Monné */ 913a9fd824SRoger Pau Monné 923a9fd824SRoger Pau Monné struct vcpu_hvm_x86_64 { 933a9fd824SRoger Pau Monné uint64_t rax; 943a9fd824SRoger Pau Monné uint64_t rcx; 953a9fd824SRoger Pau Monné uint64_t rdx; 963a9fd824SRoger Pau Monné uint64_t rbx; 973a9fd824SRoger Pau Monné uint64_t rsp; 983a9fd824SRoger Pau Monné uint64_t rbp; 993a9fd824SRoger Pau Monné uint64_t rsi; 1003a9fd824SRoger Pau Monné uint64_t rdi; 1013a9fd824SRoger Pau Monné uint64_t rip; 1023a9fd824SRoger Pau Monné uint64_t rflags; 1033a9fd824SRoger Pau Monné 1043a9fd824SRoger Pau Monné uint64_t cr0; 1053a9fd824SRoger Pau Monné uint64_t cr3; 1063a9fd824SRoger Pau Monné uint64_t cr4; 1073a9fd824SRoger Pau Monné uint64_t efer; 1083a9fd824SRoger Pau Monné 1093a9fd824SRoger Pau Monné /* 1103a9fd824SRoger Pau Monné * Using VCPU_HVM_MODE_64B implies that the vCPU is launched 1113a9fd824SRoger Pau Monné * directly in long mode, so the cached parts of the segment 1123a9fd824SRoger Pau Monné * registers get set to match that environment. 1133a9fd824SRoger Pau Monné * 1143a9fd824SRoger Pau Monné * If the user wants to launch the vCPU in compatibility mode 1153a9fd824SRoger Pau Monné * the 32-bit structure should be used instead. 1163a9fd824SRoger Pau Monné */ 1173a9fd824SRoger Pau Monné }; 1183a9fd824SRoger Pau Monné typedef struct vcpu_hvm_x86_64 xen_vcpu_hvm_x86_64_t; 1193a9fd824SRoger Pau Monné 1203a9fd824SRoger Pau Monné struct vcpu_hvm_context { 1213a9fd824SRoger Pau Monné #define VCPU_HVM_MODE_32B 0 /* 32bit fields of the structure will be used. */ 1223a9fd824SRoger Pau Monné #define VCPU_HVM_MODE_64B 1 /* 64bit fields of the structure will be used. */ 1233a9fd824SRoger Pau Monné uint32_t mode; 1243a9fd824SRoger Pau Monné 1253a9fd824SRoger Pau Monné uint32_t pad; 1263a9fd824SRoger Pau Monné 1273a9fd824SRoger Pau Monné /* CPU registers. */ 1283a9fd824SRoger Pau Monné union { 1293a9fd824SRoger Pau Monné xen_vcpu_hvm_x86_32_t x86_32; 1303a9fd824SRoger Pau Monné xen_vcpu_hvm_x86_64_t x86_64; 1313a9fd824SRoger Pau Monné } cpu_regs; 1323a9fd824SRoger Pau Monné }; 1333a9fd824SRoger Pau Monné typedef struct vcpu_hvm_context vcpu_hvm_context_t; 1343a9fd824SRoger Pau Monné DEFINE_XEN_GUEST_HANDLE(vcpu_hvm_context_t); 1353a9fd824SRoger Pau Monné 1363a9fd824SRoger Pau Monné #endif /* __XEN_PUBLIC_HVM_HVM_VCPU_H__ */ 1373a9fd824SRoger Pau Monné 1383a9fd824SRoger Pau Monné /* 1393a9fd824SRoger Pau Monné * Local variables: 1403a9fd824SRoger Pau Monné * mode: C 1413a9fd824SRoger Pau Monné * c-file-style: "BSD" 1423a9fd824SRoger Pau Monné * c-basic-offset: 4 1433a9fd824SRoger Pau Monné * tab-width: 4 1443a9fd824SRoger Pau Monné * indent-tabs-mode: nil 1453a9fd824SRoger Pau Monné * End: 1463a9fd824SRoger Pau Monné */ 147