13a9fd824SRoger Pau Monné /* 23a9fd824SRoger Pau Monné * Permission is hereby granted, free of charge, to any person obtaining a copy 33a9fd824SRoger Pau Monné * of this software and associated documentation files (the "Software"), to 43a9fd824SRoger Pau Monné * deal in the Software without restriction, including without limitation the 53a9fd824SRoger Pau Monné * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 63a9fd824SRoger Pau Monné * sell copies of the Software, and to permit persons to whom the Software is 73a9fd824SRoger Pau Monné * furnished to do so, subject to the following conditions: 83a9fd824SRoger Pau Monné * 93a9fd824SRoger Pau Monné * The above copyright notice and this permission notice shall be included in 103a9fd824SRoger Pau Monné * all copies or substantial portions of the Software. 113a9fd824SRoger Pau Monné * 123a9fd824SRoger Pau Monné * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 133a9fd824SRoger Pau Monné * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 143a9fd824SRoger Pau Monné * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 153a9fd824SRoger Pau Monné * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 163a9fd824SRoger Pau Monné * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 173a9fd824SRoger Pau Monné * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 183a9fd824SRoger Pau Monné * DEALINGS IN THE SOFTWARE. 193a9fd824SRoger Pau Monné * 203a9fd824SRoger Pau Monné * Copyright (c) 2007, Keir Fraser 213a9fd824SRoger Pau Monné */ 223a9fd824SRoger Pau Monné 233a9fd824SRoger Pau Monné #ifndef __XEN_PUBLIC_HVM_PARAMS_H__ 243a9fd824SRoger Pau Monné #define __XEN_PUBLIC_HVM_PARAMS_H__ 253a9fd824SRoger Pau Monné 263a9fd824SRoger Pau Monné #include "hvm_op.h" 273a9fd824SRoger Pau Monné 283a9fd824SRoger Pau Monné /* These parameters are deprecated and their meaning is undefined. */ 293a9fd824SRoger Pau Monné #if defined(__XEN__) || defined(__XEN_TOOLS__) 303a9fd824SRoger Pau Monné 313a9fd824SRoger Pau Monné #define HVM_PARAM_PAE_ENABLED 4 323a9fd824SRoger Pau Monné #define HVM_PARAM_DM_DOMAIN 13 333a9fd824SRoger Pau Monné #define HVM_PARAM_MEMORY_EVENT_CR0 20 343a9fd824SRoger Pau Monné #define HVM_PARAM_MEMORY_EVENT_CR3 21 353a9fd824SRoger Pau Monné #define HVM_PARAM_MEMORY_EVENT_CR4 22 363a9fd824SRoger Pau Monné #define HVM_PARAM_MEMORY_EVENT_INT3 23 373a9fd824SRoger Pau Monné #define HVM_PARAM_NESTEDHVM 24 383a9fd824SRoger Pau Monné #define HVM_PARAM_MEMORY_EVENT_SINGLE_STEP 25 393a9fd824SRoger Pau Monné #define HVM_PARAM_BUFIOREQ_EVTCHN 26 403a9fd824SRoger Pau Monné #define HVM_PARAM_MEMORY_EVENT_MSR 30 413a9fd824SRoger Pau Monné 423a9fd824SRoger Pau Monné #endif /* defined(__XEN__) || defined(__XEN_TOOLS__) */ 433a9fd824SRoger Pau Monné 443a9fd824SRoger Pau Monné /* 453a9fd824SRoger Pau Monné * Parameter space for HVMOP_{set,get}_param. 463a9fd824SRoger Pau Monné */ 473a9fd824SRoger Pau Monné 483a9fd824SRoger Pau Monné #define HVM_PARAM_CALLBACK_IRQ 0 493a9fd824SRoger Pau Monné #define HVM_PARAM_CALLBACK_IRQ_TYPE_MASK xen_mk_ullong(0xFF00000000000000) 503a9fd824SRoger Pau Monné /* 513a9fd824SRoger Pau Monné * How should CPU0 event-channel notifications be delivered? 523a9fd824SRoger Pau Monné * 533a9fd824SRoger Pau Monné * If val == 0 then CPU0 event-channel notifications are not delivered. 543a9fd824SRoger Pau Monné * If val != 0, val[63:56] encodes the type, as follows: 553a9fd824SRoger Pau Monné */ 563a9fd824SRoger Pau Monné 573a9fd824SRoger Pau Monné #define HVM_PARAM_CALLBACK_TYPE_GSI 0 583a9fd824SRoger Pau Monné /* 593a9fd824SRoger Pau Monné * val[55:0] is a delivery GSI. GSI 0 cannot be used, as it aliases val == 0, 603a9fd824SRoger Pau Monné * and disables all notifications. 613a9fd824SRoger Pau Monné */ 623a9fd824SRoger Pau Monné 633a9fd824SRoger Pau Monné #define HVM_PARAM_CALLBACK_TYPE_PCI_INTX 1 643a9fd824SRoger Pau Monné /* 653a9fd824SRoger Pau Monné * val[55:0] is a delivery PCI INTx line: 663a9fd824SRoger Pau Monné * Domain = val[47:32], Bus = val[31:16] DevFn = val[15:8], IntX = val[1:0] 673a9fd824SRoger Pau Monné */ 683a9fd824SRoger Pau Monné 693a9fd824SRoger Pau Monné #if defined(__i386__) || defined(__x86_64__) 703a9fd824SRoger Pau Monné #define HVM_PARAM_CALLBACK_TYPE_VECTOR 2 713a9fd824SRoger Pau Monné /* 723a9fd824SRoger Pau Monné * val[7:0] is a vector number. Check for XENFEAT_hvm_callback_vector to know 733a9fd824SRoger Pau Monné * if this delivery method is available. 743a9fd824SRoger Pau Monné */ 753a9fd824SRoger Pau Monné #elif defined(__arm__) || defined(__aarch64__) 763a9fd824SRoger Pau Monné #define HVM_PARAM_CALLBACK_TYPE_PPI 2 773a9fd824SRoger Pau Monné /* 783a9fd824SRoger Pau Monné * val[55:16] needs to be zero. 793a9fd824SRoger Pau Monné * val[15:8] is interrupt flag of the PPI used by event-channel: 803a9fd824SRoger Pau Monné * bit 8: the PPI is edge(1) or level(0) triggered 813a9fd824SRoger Pau Monné * bit 9: the PPI is active low(1) or high(0) 823a9fd824SRoger Pau Monné * val[7:0] is a PPI number used by event-channel. 833a9fd824SRoger Pau Monné * This is only used by ARM/ARM64 and masking/eoi the interrupt associated to 843a9fd824SRoger Pau Monné * the notification is handled by the interrupt controller. 853a9fd824SRoger Pau Monné */ 863a9fd824SRoger Pau Monné #define HVM_PARAM_CALLBACK_TYPE_PPI_FLAG_MASK 0xFF00 873a9fd824SRoger Pau Monné #define HVM_PARAM_CALLBACK_TYPE_PPI_FLAG_LOW_LEVEL 2 883a9fd824SRoger Pau Monné #endif 893a9fd824SRoger Pau Monné 903a9fd824SRoger Pau Monné /* 913a9fd824SRoger Pau Monné * These are not used by Xen. They are here for convenience of HVM-guest 923a9fd824SRoger Pau Monné * xenbus implementations. 933a9fd824SRoger Pau Monné */ 943a9fd824SRoger Pau Monné #define HVM_PARAM_STORE_PFN 1 953a9fd824SRoger Pau Monné #define HVM_PARAM_STORE_EVTCHN 2 963a9fd824SRoger Pau Monné 973a9fd824SRoger Pau Monné #define HVM_PARAM_IOREQ_PFN 5 983a9fd824SRoger Pau Monné 993a9fd824SRoger Pau Monné #define HVM_PARAM_BUFIOREQ_PFN 6 1003a9fd824SRoger Pau Monné 1013a9fd824SRoger Pau Monné #if defined(__i386__) || defined(__x86_64__) 1023a9fd824SRoger Pau Monné 1033a9fd824SRoger Pau Monné /* 1043a9fd824SRoger Pau Monné * Viridian enlightenments 1053a9fd824SRoger Pau Monné * 1063a9fd824SRoger Pau Monné * (See http://download.microsoft.com/download/A/B/4/AB43A34E-BDD0-4FA6-BDEF-79EEF16E880B/Hypervisor%20Top%20Level%20Functional%20Specification%20v4.0.docx) 1073a9fd824SRoger Pau Monné * 1083a9fd824SRoger Pau Monné * To expose viridian enlightenments to the guest set this parameter 1093a9fd824SRoger Pau Monné * to the desired feature mask. The base feature set must be present 1103a9fd824SRoger Pau Monné * in any valid feature mask. 1113a9fd824SRoger Pau Monné */ 1123a9fd824SRoger Pau Monné #define HVM_PARAM_VIRIDIAN 9 1133a9fd824SRoger Pau Monné 1143a9fd824SRoger Pau Monné /* Base+Freq viridian feature sets: 1153a9fd824SRoger Pau Monné * 1163a9fd824SRoger Pau Monné * - Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) 1173a9fd824SRoger Pau Monné * - APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR) 1183a9fd824SRoger Pau Monné * - Virtual Processor index MSR (HV_X64_MSR_VP_INDEX) 1193a9fd824SRoger Pau Monné * - Timer frequency MSRs (HV_X64_MSR_TSC_FREQUENCY and 1203a9fd824SRoger Pau Monné * HV_X64_MSR_APIC_FREQUENCY) 1213a9fd824SRoger Pau Monné */ 1223a9fd824SRoger Pau Monné #define _HVMPV_base_freq 0 1233a9fd824SRoger Pau Monné #define HVMPV_base_freq (1 << _HVMPV_base_freq) 1243a9fd824SRoger Pau Monné 1253a9fd824SRoger Pau Monné /* Feature set modifications */ 1263a9fd824SRoger Pau Monné 1273a9fd824SRoger Pau Monné /* Disable timer frequency MSRs (HV_X64_MSR_TSC_FREQUENCY and 1283a9fd824SRoger Pau Monné * HV_X64_MSR_APIC_FREQUENCY). 1293a9fd824SRoger Pau Monné * This modification restores the viridian feature set to the 1303a9fd824SRoger Pau Monné * original 'base' set exposed in releases prior to Xen 4.4. 1313a9fd824SRoger Pau Monné */ 1323a9fd824SRoger Pau Monné #define _HVMPV_no_freq 1 1333a9fd824SRoger Pau Monné #define HVMPV_no_freq (1 << _HVMPV_no_freq) 1343a9fd824SRoger Pau Monné 1353a9fd824SRoger Pau Monné /* Enable Partition Time Reference Counter (HV_X64_MSR_TIME_REF_COUNT) */ 1363a9fd824SRoger Pau Monné #define _HVMPV_time_ref_count 2 1373a9fd824SRoger Pau Monné #define HVMPV_time_ref_count (1 << _HVMPV_time_ref_count) 1383a9fd824SRoger Pau Monné 1393a9fd824SRoger Pau Monné /* Enable Reference TSC Page (HV_X64_MSR_REFERENCE_TSC) */ 1403a9fd824SRoger Pau Monné #define _HVMPV_reference_tsc 3 1413a9fd824SRoger Pau Monné #define HVMPV_reference_tsc (1 << _HVMPV_reference_tsc) 1423a9fd824SRoger Pau Monné 1433a9fd824SRoger Pau Monné /* Use Hypercall for remote TLB flush */ 1443a9fd824SRoger Pau Monné #define _HVMPV_hcall_remote_tlb_flush 4 1453a9fd824SRoger Pau Monné #define HVMPV_hcall_remote_tlb_flush (1 << _HVMPV_hcall_remote_tlb_flush) 1463a9fd824SRoger Pau Monné 1473a9fd824SRoger Pau Monné /* Use APIC assist */ 1483a9fd824SRoger Pau Monné #define _HVMPV_apic_assist 5 1493a9fd824SRoger Pau Monné #define HVMPV_apic_assist (1 << _HVMPV_apic_assist) 1503a9fd824SRoger Pau Monné 1513a9fd824SRoger Pau Monné /* Enable crash MSRs */ 1523a9fd824SRoger Pau Monné #define _HVMPV_crash_ctl 6 1533a9fd824SRoger Pau Monné #define HVMPV_crash_ctl (1 << _HVMPV_crash_ctl) 1543a9fd824SRoger Pau Monné 1553a9fd824SRoger Pau Monné /* Enable SYNIC MSRs */ 1563a9fd824SRoger Pau Monné #define _HVMPV_synic 7 1573a9fd824SRoger Pau Monné #define HVMPV_synic (1 << _HVMPV_synic) 1583a9fd824SRoger Pau Monné 1593a9fd824SRoger Pau Monné /* Enable STIMER MSRs */ 1603a9fd824SRoger Pau Monné #define _HVMPV_stimer 8 1613a9fd824SRoger Pau Monné #define HVMPV_stimer (1 << _HVMPV_stimer) 1623a9fd824SRoger Pau Monné 1633a9fd824SRoger Pau Monné /* Use Synthetic Cluster IPI Hypercall */ 1643a9fd824SRoger Pau Monné #define _HVMPV_hcall_ipi 9 1653a9fd824SRoger Pau Monné #define HVMPV_hcall_ipi (1 << _HVMPV_hcall_ipi) 1663a9fd824SRoger Pau Monné 1673a9fd824SRoger Pau Monné /* Enable ExProcessorMasks */ 1683a9fd824SRoger Pau Monné #define _HVMPV_ex_processor_masks 10 1693a9fd824SRoger Pau Monné #define HVMPV_ex_processor_masks (1 << _HVMPV_ex_processor_masks) 1703a9fd824SRoger Pau Monné 1713a9fd824SRoger Pau Monné /* Allow more than 64 VPs */ 1723a9fd824SRoger Pau Monné #define _HVMPV_no_vp_limit 11 1733a9fd824SRoger Pau Monné #define HVMPV_no_vp_limit (1 << _HVMPV_no_vp_limit) 1743a9fd824SRoger Pau Monné 1753a9fd824SRoger Pau Monné /* Enable vCPU hotplug */ 1763a9fd824SRoger Pau Monné #define _HVMPV_cpu_hotplug 12 1773a9fd824SRoger Pau Monné #define HVMPV_cpu_hotplug (1 << _HVMPV_cpu_hotplug) 1783a9fd824SRoger Pau Monné 1793a9fd824SRoger Pau Monné #define HVMPV_feature_mask \ 1803a9fd824SRoger Pau Monné (HVMPV_base_freq | \ 1813a9fd824SRoger Pau Monné HVMPV_no_freq | \ 1823a9fd824SRoger Pau Monné HVMPV_time_ref_count | \ 1833a9fd824SRoger Pau Monné HVMPV_reference_tsc | \ 1843a9fd824SRoger Pau Monné HVMPV_hcall_remote_tlb_flush | \ 1853a9fd824SRoger Pau Monné HVMPV_apic_assist | \ 1863a9fd824SRoger Pau Monné HVMPV_crash_ctl | \ 1873a9fd824SRoger Pau Monné HVMPV_synic | \ 1883a9fd824SRoger Pau Monné HVMPV_stimer | \ 1893a9fd824SRoger Pau Monné HVMPV_hcall_ipi | \ 1903a9fd824SRoger Pau Monné HVMPV_ex_processor_masks | \ 1913a9fd824SRoger Pau Monné HVMPV_no_vp_limit | \ 1923a9fd824SRoger Pau Monné HVMPV_cpu_hotplug) 1933a9fd824SRoger Pau Monné 1943a9fd824SRoger Pau Monné #endif 1953a9fd824SRoger Pau Monné 1963a9fd824SRoger Pau Monné /* 1973a9fd824SRoger Pau Monné * Set mode for virtual timers (currently x86 only): 1983a9fd824SRoger Pau Monné * delay_for_missed_ticks (default): 1993a9fd824SRoger Pau Monné * Do not advance a vcpu's time beyond the correct delivery time for 2003a9fd824SRoger Pau Monné * interrupts that have been missed due to preemption. Deliver missed 2013a9fd824SRoger Pau Monné * interrupts when the vcpu is rescheduled and advance the vcpu's virtual 2023a9fd824SRoger Pau Monné * time stepwise for each one. 2033a9fd824SRoger Pau Monné * no_delay_for_missed_ticks: 2043a9fd824SRoger Pau Monné * As above, missed interrupts are delivered, but guest time always tracks 2053a9fd824SRoger Pau Monné * wallclock (i.e., real) time while doing so. 2063a9fd824SRoger Pau Monné * no_missed_ticks_pending: 2073a9fd824SRoger Pau Monné * No missed interrupts are held pending. Instead, to ensure ticks are 2083a9fd824SRoger Pau Monné * delivered at some non-zero rate, if we detect missed ticks then the 2093a9fd824SRoger Pau Monné * internal tick alarm is not disabled if the VCPU is preempted during the 2103a9fd824SRoger Pau Monné * next tick period. 2113a9fd824SRoger Pau Monné * one_missed_tick_pending: 2123a9fd824SRoger Pau Monné * Missed interrupts are collapsed together and delivered as one 'late tick'. 2133a9fd824SRoger Pau Monné * Guest time always tracks wallclock (i.e., real) time. 2143a9fd824SRoger Pau Monné */ 2153a9fd824SRoger Pau Monné #define HVM_PARAM_TIMER_MODE 10 2163a9fd824SRoger Pau Monné #define HVMPTM_delay_for_missed_ticks 0 2173a9fd824SRoger Pau Monné #define HVMPTM_no_delay_for_missed_ticks 1 2183a9fd824SRoger Pau Monné #define HVMPTM_no_missed_ticks_pending 2 2193a9fd824SRoger Pau Monné #define HVMPTM_one_missed_tick_pending 3 2203a9fd824SRoger Pau Monné 2213a9fd824SRoger Pau Monné /* Boolean: Enable virtual HPET (high-precision event timer)? (x86-only) */ 2223a9fd824SRoger Pau Monné #define HVM_PARAM_HPET_ENABLED 11 2233a9fd824SRoger Pau Monné 2243a9fd824SRoger Pau Monné /* Identity-map page directory used by Intel EPT when CR0.PG=0. */ 2253a9fd824SRoger Pau Monné #define HVM_PARAM_IDENT_PT 12 2263a9fd824SRoger Pau Monné 2273a9fd824SRoger Pau Monné /* ACPI S state: currently support S0 and S3 on x86. */ 2283a9fd824SRoger Pau Monné #define HVM_PARAM_ACPI_S_STATE 14 2293a9fd824SRoger Pau Monné 2303a9fd824SRoger Pau Monné /* TSS used on Intel when CR0.PE=0. */ 2313a9fd824SRoger Pau Monné #define HVM_PARAM_VM86_TSS 15 2323a9fd824SRoger Pau Monné 2333a9fd824SRoger Pau Monné /* Boolean: Enable aligning all periodic vpts to reduce interrupts */ 2343a9fd824SRoger Pau Monné #define HVM_PARAM_VPT_ALIGN 16 2353a9fd824SRoger Pau Monné 2363a9fd824SRoger Pau Monné /* Console debug shared memory ring and event channel */ 2373a9fd824SRoger Pau Monné #define HVM_PARAM_CONSOLE_PFN 17 2383a9fd824SRoger Pau Monné #define HVM_PARAM_CONSOLE_EVTCHN 18 2393a9fd824SRoger Pau Monné 2403a9fd824SRoger Pau Monné /* 2413a9fd824SRoger Pau Monné * Select location of ACPI PM1a and TMR control blocks. Currently two locations 2423a9fd824SRoger Pau Monné * are supported, specified by version 0 or 1 in this parameter: 2433a9fd824SRoger Pau Monné * - 0: default, use the old addresses 2443a9fd824SRoger Pau Monné * PM1A_EVT == 0x1f40; PM1A_CNT == 0x1f44; PM_TMR == 0x1f48 2453a9fd824SRoger Pau Monné * - 1: use the new default qemu addresses 2463a9fd824SRoger Pau Monné * PM1A_EVT == 0xb000; PM1A_CNT == 0xb004; PM_TMR == 0xb008 2473a9fd824SRoger Pau Monné * You can find these address definitions in <hvm/ioreq.h> 2483a9fd824SRoger Pau Monné */ 2493a9fd824SRoger Pau Monné #define HVM_PARAM_ACPI_IOPORTS_LOCATION 19 2503a9fd824SRoger Pau Monné 2513a9fd824SRoger Pau Monné /* Params for the mem event rings */ 2523a9fd824SRoger Pau Monné #define HVM_PARAM_PAGING_RING_PFN 27 2533a9fd824SRoger Pau Monné #define HVM_PARAM_MONITOR_RING_PFN 28 2543a9fd824SRoger Pau Monné #define HVM_PARAM_SHARING_RING_PFN 29 2553a9fd824SRoger Pau Monné 2563a9fd824SRoger Pau Monné /* SHUTDOWN_* action in case of a triple fault */ 2573a9fd824SRoger Pau Monné #define HVM_PARAM_TRIPLE_FAULT_REASON 31 2583a9fd824SRoger Pau Monné 2593a9fd824SRoger Pau Monné #define HVM_PARAM_IOREQ_SERVER_PFN 32 2603a9fd824SRoger Pau Monné #define HVM_PARAM_NR_IOREQ_SERVER_PAGES 33 2613a9fd824SRoger Pau Monné 2623a9fd824SRoger Pau Monné /* Location of the VM Generation ID in guest physical address space. */ 2633a9fd824SRoger Pau Monné #define HVM_PARAM_VM_GENERATION_ID_ADDR 34 2643a9fd824SRoger Pau Monné 2653a9fd824SRoger Pau Monné /* 2663a9fd824SRoger Pau Monné * Set mode for altp2m: 2673a9fd824SRoger Pau Monné * disabled: don't activate altp2m (default) 2683a9fd824SRoger Pau Monné * mixed: allow access to all altp2m ops for both in-guest and external tools 2693a9fd824SRoger Pau Monné * external: allow access to external privileged tools only 2703a9fd824SRoger Pau Monné * limited: guest only has limited access (ie. control VMFUNC and #VE) 2713a9fd824SRoger Pau Monné * 2723a9fd824SRoger Pau Monné * Note that 'mixed' mode has not been evaluated for safety from a 2733a9fd824SRoger Pau Monné * security perspective. Before using this mode in a 2743a9fd824SRoger Pau Monné * security-critical environment, each subop should be evaluated for 2753a9fd824SRoger Pau Monné * safety, with unsafe subops blacklisted in XSM. 2763a9fd824SRoger Pau Monné */ 2773a9fd824SRoger Pau Monné #define HVM_PARAM_ALTP2M 35 2783a9fd824SRoger Pau Monné #define XEN_ALTP2M_disabled 0 2793a9fd824SRoger Pau Monné #define XEN_ALTP2M_mixed 1 2803a9fd824SRoger Pau Monné #define XEN_ALTP2M_external 2 2813a9fd824SRoger Pau Monné #define XEN_ALTP2M_limited 3 2823a9fd824SRoger Pau Monné 2833a9fd824SRoger Pau Monné /* 2843a9fd824SRoger Pau Monné * Size of the x87 FPU FIP/FDP registers that the hypervisor needs to 2853a9fd824SRoger Pau Monné * save/restore. This is a workaround for a hardware limitation that 2863a9fd824SRoger Pau Monné * does not allow the full FIP/FDP and FCS/FDS to be restored. 2873a9fd824SRoger Pau Monné * 2883a9fd824SRoger Pau Monné * Valid values are: 2893a9fd824SRoger Pau Monné * 2903a9fd824SRoger Pau Monné * 8: save/restore 64-bit FIP/FDP and clear FCS/FDS (default if CPU 2913a9fd824SRoger Pau Monné * has FPCSDS feature). 2923a9fd824SRoger Pau Monné * 2933a9fd824SRoger Pau Monné * 4: save/restore 32-bit FIP/FDP, FCS/FDS, and clear upper 32-bits of 2943a9fd824SRoger Pau Monné * FIP/FDP. 2953a9fd824SRoger Pau Monné * 2963a9fd824SRoger Pau Monné * 0: allow hypervisor to choose based on the value of FIP/FDP 2973a9fd824SRoger Pau Monné * (default if CPU does not have FPCSDS). 2983a9fd824SRoger Pau Monné * 2993a9fd824SRoger Pau Monné * If FPCSDS (bit 13 in CPUID leaf 0x7, subleaf 0x0) is set, the CPU 3003a9fd824SRoger Pau Monné * never saves FCS/FDS and this parameter should be left at the 3013a9fd824SRoger Pau Monné * default of 8. 3023a9fd824SRoger Pau Monné */ 3033a9fd824SRoger Pau Monné #define HVM_PARAM_X87_FIP_WIDTH 36 3043a9fd824SRoger Pau Monné 3053a9fd824SRoger Pau Monné /* 3063a9fd824SRoger Pau Monné * TSS (and its size) used on Intel when CR0.PE=0. The address occupies 3073a9fd824SRoger Pau Monné * the low 32 bits, while the size is in the high 32 ones. 3083a9fd824SRoger Pau Monné */ 3093a9fd824SRoger Pau Monné #define HVM_PARAM_VM86_TSS_SIZED 37 3103a9fd824SRoger Pau Monné 3113a9fd824SRoger Pau Monné /* Enable MCA capabilities. */ 3123a9fd824SRoger Pau Monné #define HVM_PARAM_MCA_CAP 38 3133a9fd824SRoger Pau Monné #define XEN_HVM_MCA_CAP_LMCE (xen_mk_ullong(1) << 0) 3143a9fd824SRoger Pau Monné #define XEN_HVM_MCA_CAP_MASK XEN_HVM_MCA_CAP_LMCE 3153a9fd824SRoger Pau Monné 3163a9fd824SRoger Pau Monné #define HVM_NR_PARAMS 39 3173a9fd824SRoger Pau Monné 3183a9fd824SRoger Pau Monné #endif /* __XEN_PUBLIC_HVM_PARAMS_H__ */ 319