1 /*- 2 * Copyright (c) 2003-2005 Nate Lawson (SDG) 3 * Copyright (c) 2001 Michael Smith 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_acpi.h" 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/cpu.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/pcpu.h> 39 #include <sys/power.h> 40 #include <sys/proc.h> 41 #include <sys/sched.h> 42 #include <sys/sbuf.h> 43 #include <sys/smp.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <machine/atomic.h> 47 #include <machine/bus.h> 48 #if defined(__amd64__) || defined(__i386__) 49 #include <machine/clock.h> 50 #include <machine/specialreg.h> 51 #include <machine/md_var.h> 52 #endif 53 #include <sys/rman.h> 54 55 #include <contrib/dev/acpica/include/acpi.h> 56 #include <contrib/dev/acpica/include/accommon.h> 57 58 #include <dev/acpica/acpivar.h> 59 60 /* 61 * Support for ACPI Processor devices, including C[1-3] sleep states. 62 */ 63 64 /* Hooks for the ACPI CA debugging infrastructure */ 65 #define _COMPONENT ACPI_PROCESSOR 66 ACPI_MODULE_NAME("PROCESSOR") 67 68 struct acpi_cx { 69 struct resource *p_lvlx; /* Register to read to enter state. */ 70 uint32_t type; /* C1-3 (C4 and up treated as C3). */ 71 uint32_t trans_lat; /* Transition latency (usec). */ 72 uint32_t power; /* Power consumed (mW). */ 73 int res_type; /* Resource type for p_lvlx. */ 74 int res_rid; /* Resource ID for p_lvlx. */ 75 bool do_mwait; 76 uint32_t mwait_hint; 77 bool mwait_hw_coord; 78 bool mwait_bm_avoidance; 79 }; 80 #define MAX_CX_STATES 8 81 82 struct acpi_cpu_softc { 83 device_t cpu_dev; 84 ACPI_HANDLE cpu_handle; 85 struct pcpu *cpu_pcpu; 86 uint32_t cpu_acpi_id; /* ACPI processor id */ 87 uint32_t cpu_p_blk; /* ACPI P_BLK location */ 88 uint32_t cpu_p_blk_len; /* P_BLK length (must be 6). */ 89 struct acpi_cx cpu_cx_states[MAX_CX_STATES]; 90 int cpu_cx_count; /* Number of valid Cx states. */ 91 int cpu_prev_sleep;/* Last idle sleep duration. */ 92 int cpu_features; /* Child driver supported features. */ 93 /* Runtime state. */ 94 int cpu_non_c2; /* Index of lowest non-C2 state. */ 95 int cpu_non_c3; /* Index of lowest non-C3 state. */ 96 u_int cpu_cx_stats[MAX_CX_STATES];/* Cx usage history. */ 97 /* Values for sysctl. */ 98 struct sysctl_ctx_list cpu_sysctl_ctx; 99 struct sysctl_oid *cpu_sysctl_tree; 100 int cpu_cx_lowest; 101 int cpu_cx_lowest_lim; 102 int cpu_disable_idle; /* Disable entry to idle function */ 103 char cpu_cx_supported[64]; 104 }; 105 106 struct acpi_cpu_device { 107 struct resource_list ad_rl; 108 }; 109 110 #define CPU_GET_REG(reg, width) \ 111 (bus_space_read_ ## width(rman_get_bustag((reg)), \ 112 rman_get_bushandle((reg)), 0)) 113 #define CPU_SET_REG(reg, width, val) \ 114 (bus_space_write_ ## width(rman_get_bustag((reg)), \ 115 rman_get_bushandle((reg)), 0, (val))) 116 117 #define PM_USEC(x) ((x) >> 2) /* ~4 clocks per usec (3.57955 Mhz) */ 118 119 #define ACPI_NOTIFY_CX_STATES 0x81 /* _CST changed. */ 120 121 #define CPU_QUIRK_NO_C3 (1<<0) /* C3-type states are not usable. */ 122 #define CPU_QUIRK_NO_BM_CTRL (1<<2) /* No bus mastering control. */ 123 124 #define PCI_VENDOR_INTEL 0x8086 125 #define PCI_DEVICE_82371AB_3 0x7113 /* PIIX4 chipset for quirks. */ 126 #define PCI_REVISION_A_STEP 0 127 #define PCI_REVISION_B_STEP 1 128 #define PCI_REVISION_4E 2 129 #define PCI_REVISION_4M 3 130 #define PIIX4_DEVACTB_REG 0x58 131 #define PIIX4_BRLD_EN_IRQ0 (1<<0) 132 #define PIIX4_BRLD_EN_IRQ (1<<1) 133 #define PIIX4_BRLD_EN_IRQ8 (1<<5) 134 #define PIIX4_STOP_BREAK_MASK (PIIX4_BRLD_EN_IRQ0 | PIIX4_BRLD_EN_IRQ | PIIX4_BRLD_EN_IRQ8) 135 #define PIIX4_PCNTRL_BST_EN (1<<10) 136 137 #define CST_FFH_VENDOR_INTEL 1 138 #define CST_FFH_INTEL_CL_C1IO 1 139 #define CST_FFH_INTEL_CL_MWAIT 2 140 #define CST_FFH_MWAIT_HW_COORD 0x0001 141 #define CST_FFH_MWAIT_BM_AVOID 0x0002 142 143 /* Allow users to ignore processor orders in MADT. */ 144 static int cpu_unordered; 145 SYSCTL_INT(_debug_acpi, OID_AUTO, cpu_unordered, CTLFLAG_RDTUN, 146 &cpu_unordered, 0, 147 "Do not use the MADT to match ACPI Processor objects to CPUs."); 148 149 /* Knob to disable acpi_cpu devices */ 150 bool acpi_cpu_disabled = false; 151 152 /* Platform hardware resource information. */ 153 static uint32_t cpu_smi_cmd; /* Value to write to SMI_CMD. */ 154 static uint8_t cpu_cst_cnt; /* Indicate we are _CST aware. */ 155 static int cpu_quirks; /* Indicate any hardware bugs. */ 156 157 /* Values for sysctl. */ 158 static struct sysctl_ctx_list cpu_sysctl_ctx; 159 static struct sysctl_oid *cpu_sysctl_tree; 160 static int cpu_cx_generic; 161 static int cpu_cx_lowest_lim; 162 163 static device_t *cpu_devices; 164 static int cpu_ndevices; 165 static struct acpi_cpu_softc **cpu_softc; 166 ACPI_SERIAL_DECL(cpu, "ACPI CPU"); 167 168 static int acpi_cpu_probe(device_t dev); 169 static int acpi_cpu_attach(device_t dev); 170 static int acpi_cpu_suspend(device_t dev); 171 static int acpi_cpu_resume(device_t dev); 172 static int acpi_pcpu_get_id(device_t dev, uint32_t *acpi_id, 173 uint32_t *cpu_id); 174 static struct resource_list *acpi_cpu_get_rlist(device_t dev, device_t child); 175 static device_t acpi_cpu_add_child(device_t dev, u_int order, const char *name, 176 int unit); 177 static int acpi_cpu_read_ivar(device_t dev, device_t child, int index, 178 uintptr_t *result); 179 static int acpi_cpu_shutdown(device_t dev); 180 static void acpi_cpu_cx_probe(struct acpi_cpu_softc *sc); 181 static void acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc); 182 static int acpi_cpu_cx_cst(struct acpi_cpu_softc *sc); 183 static void acpi_cpu_startup(void *arg); 184 static void acpi_cpu_startup_cx(struct acpi_cpu_softc *sc); 185 static void acpi_cpu_cx_list(struct acpi_cpu_softc *sc); 186 #if defined(__i386__) || defined(__amd64__) 187 static void acpi_cpu_idle(sbintime_t sbt); 188 #endif 189 static void acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context); 190 static void acpi_cpu_quirks(void); 191 static void acpi_cpu_quirks_piix4(void); 192 static int acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS); 193 static int acpi_cpu_usage_counters_sysctl(SYSCTL_HANDLER_ARGS); 194 static int acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc); 195 static int acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 196 static int acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 197 #if defined(__i386__) || defined(__amd64__) 198 static int acpi_cpu_method_sysctl(SYSCTL_HANDLER_ARGS); 199 #endif 200 201 static device_method_t acpi_cpu_methods[] = { 202 /* Device interface */ 203 DEVMETHOD(device_probe, acpi_cpu_probe), 204 DEVMETHOD(device_attach, acpi_cpu_attach), 205 DEVMETHOD(device_detach, bus_generic_detach), 206 DEVMETHOD(device_shutdown, acpi_cpu_shutdown), 207 DEVMETHOD(device_suspend, acpi_cpu_suspend), 208 DEVMETHOD(device_resume, acpi_cpu_resume), 209 210 /* Bus interface */ 211 DEVMETHOD(bus_add_child, acpi_cpu_add_child), 212 DEVMETHOD(bus_read_ivar, acpi_cpu_read_ivar), 213 DEVMETHOD(bus_get_resource_list, acpi_cpu_get_rlist), 214 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 215 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 216 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource), 217 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 218 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 219 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 220 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 221 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 222 223 DEVMETHOD_END 224 }; 225 226 static driver_t acpi_cpu_driver = { 227 "cpu", 228 acpi_cpu_methods, 229 sizeof(struct acpi_cpu_softc), 230 }; 231 232 static devclass_t acpi_cpu_devclass; 233 DRIVER_MODULE(cpu, acpi, acpi_cpu_driver, acpi_cpu_devclass, 0, 0); 234 MODULE_DEPEND(cpu, acpi, 1, 1, 1); 235 236 static int 237 acpi_cpu_probe(device_t dev) 238 { 239 int acpi_id, cpu_id; 240 ACPI_BUFFER buf; 241 ACPI_HANDLE handle; 242 ACPI_OBJECT *obj; 243 ACPI_STATUS status; 244 245 if (acpi_disabled("cpu") || acpi_get_type(dev) != ACPI_TYPE_PROCESSOR || 246 acpi_cpu_disabled) 247 return (ENXIO); 248 249 handle = acpi_get_handle(dev); 250 if (cpu_softc == NULL) 251 cpu_softc = malloc(sizeof(struct acpi_cpu_softc *) * 252 (mp_maxid + 1), M_TEMP /* XXX */, M_WAITOK | M_ZERO); 253 254 /* Get our Processor object. */ 255 buf.Pointer = NULL; 256 buf.Length = ACPI_ALLOCATE_BUFFER; 257 status = AcpiEvaluateObject(handle, NULL, NULL, &buf); 258 if (ACPI_FAILURE(status)) { 259 device_printf(dev, "probe failed to get Processor obj - %s\n", 260 AcpiFormatException(status)); 261 return (ENXIO); 262 } 263 obj = (ACPI_OBJECT *)buf.Pointer; 264 if (obj->Type != ACPI_TYPE_PROCESSOR) { 265 device_printf(dev, "Processor object has bad type %d\n", obj->Type); 266 AcpiOsFree(obj); 267 return (ENXIO); 268 } 269 270 /* 271 * Find the processor associated with our unit. We could use the 272 * ProcId as a key, however, some boxes do not have the same values 273 * in their Processor object as the ProcId values in the MADT. 274 */ 275 acpi_id = obj->Processor.ProcId; 276 AcpiOsFree(obj); 277 if (acpi_pcpu_get_id(dev, &acpi_id, &cpu_id) != 0) 278 return (ENXIO); 279 280 /* 281 * Check if we already probed this processor. We scan the bus twice 282 * so it's possible we've already seen this one. 283 */ 284 if (cpu_softc[cpu_id] != NULL) 285 return (ENXIO); 286 287 /* Mark this processor as in-use and save our derived id for attach. */ 288 cpu_softc[cpu_id] = (void *)1; 289 acpi_set_private(dev, (void*)(intptr_t)cpu_id); 290 device_set_desc(dev, "ACPI CPU"); 291 292 return (0); 293 } 294 295 static int 296 acpi_cpu_attach(device_t dev) 297 { 298 ACPI_BUFFER buf; 299 ACPI_OBJECT arg, *obj; 300 ACPI_OBJECT_LIST arglist; 301 struct pcpu *pcpu_data; 302 struct acpi_cpu_softc *sc; 303 struct acpi_softc *acpi_sc; 304 ACPI_STATUS status; 305 u_int features; 306 int cpu_id, drv_count, i; 307 driver_t **drivers; 308 uint32_t cap_set[3]; 309 310 /* UUID needed by _OSC evaluation */ 311 static uint8_t cpu_oscuuid[16] = { 0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29, 312 0xBE, 0x47, 0x9E, 0xBD, 0xD8, 0x70, 313 0x58, 0x71, 0x39, 0x53 }; 314 315 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 316 317 sc = device_get_softc(dev); 318 sc->cpu_dev = dev; 319 sc->cpu_handle = acpi_get_handle(dev); 320 cpu_id = (int)(intptr_t)acpi_get_private(dev); 321 cpu_softc[cpu_id] = sc; 322 pcpu_data = pcpu_find(cpu_id); 323 pcpu_data->pc_device = dev; 324 sc->cpu_pcpu = pcpu_data; 325 cpu_smi_cmd = AcpiGbl_FADT.SmiCommand; 326 cpu_cst_cnt = AcpiGbl_FADT.CstControl; 327 328 buf.Pointer = NULL; 329 buf.Length = ACPI_ALLOCATE_BUFFER; 330 status = AcpiEvaluateObject(sc->cpu_handle, NULL, NULL, &buf); 331 if (ACPI_FAILURE(status)) { 332 device_printf(dev, "attach failed to get Processor obj - %s\n", 333 AcpiFormatException(status)); 334 return (ENXIO); 335 } 336 obj = (ACPI_OBJECT *)buf.Pointer; 337 sc->cpu_p_blk = obj->Processor.PblkAddress; 338 sc->cpu_p_blk_len = obj->Processor.PblkLength; 339 sc->cpu_acpi_id = obj->Processor.ProcId; 340 AcpiOsFree(obj); 341 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "acpi_cpu%d: P_BLK at %#x/%d\n", 342 device_get_unit(dev), sc->cpu_p_blk, sc->cpu_p_blk_len)); 343 344 /* 345 * If this is the first cpu we attach, create and initialize the generic 346 * resources that will be used by all acpi cpu devices. 347 */ 348 if (device_get_unit(dev) == 0) { 349 /* Assume we won't be using generic Cx mode by default */ 350 cpu_cx_generic = FALSE; 351 352 /* Install hw.acpi.cpu sysctl tree */ 353 acpi_sc = acpi_device_get_parent_softc(dev); 354 sysctl_ctx_init(&cpu_sysctl_ctx); 355 cpu_sysctl_tree = SYSCTL_ADD_NODE(&cpu_sysctl_ctx, 356 SYSCTL_CHILDREN(acpi_sc->acpi_sysctl_tree), OID_AUTO, "cpu", 357 CTLFLAG_RD, 0, "node for CPU children"); 358 } 359 360 /* 361 * Before calling any CPU methods, collect child driver feature hints 362 * and notify ACPI of them. We support unified SMP power control 363 * so advertise this ourselves. Note this is not the same as independent 364 * SMP control where each CPU can have different settings. 365 */ 366 sc->cpu_features = ACPI_CAP_SMP_SAME | ACPI_CAP_SMP_SAME_C3 | 367 ACPI_CAP_C1_IO_HALT; 368 369 #if defined(__i386__) || defined(__amd64__) 370 /* 371 * Ask for MWAIT modes if not disabled and interrupts work 372 * reasonable with MWAIT. 373 */ 374 if (!acpi_disabled("mwait") && cpu_mwait_usable()) 375 sc->cpu_features |= ACPI_CAP_SMP_C1_NATIVE | ACPI_CAP_SMP_C3_NATIVE; 376 #endif 377 378 if (devclass_get_drivers(acpi_cpu_devclass, &drivers, &drv_count) == 0) { 379 for (i = 0; i < drv_count; i++) { 380 if (ACPI_GET_FEATURES(drivers[i], &features) == 0) 381 sc->cpu_features |= features; 382 } 383 free(drivers, M_TEMP); 384 } 385 386 /* 387 * CPU capabilities are specified in 388 * Intel Processor Vendor-Specific ACPI Interface Specification. 389 */ 390 if (sc->cpu_features) { 391 cap_set[1] = sc->cpu_features; 392 status = acpi_EvaluateOSC(sc->cpu_handle, cpu_oscuuid, 1, 2, cap_set, 393 cap_set, false); 394 if (ACPI_SUCCESS(status)) { 395 if (cap_set[0] != 0) 396 device_printf(dev, "_OSC returned status %#x\n", cap_set[0]); 397 } 398 else { 399 arglist.Pointer = &arg; 400 arglist.Count = 1; 401 arg.Type = ACPI_TYPE_BUFFER; 402 arg.Buffer.Length = sizeof(cap_set); 403 arg.Buffer.Pointer = (uint8_t *)cap_set; 404 cap_set[0] = 1; /* revision */ 405 cap_set[1] = 1; /* number of capabilities integers */ 406 cap_set[2] = sc->cpu_features; 407 AcpiEvaluateObject(sc->cpu_handle, "_PDC", &arglist, NULL); 408 } 409 } 410 411 /* Probe for Cx state support. */ 412 acpi_cpu_cx_probe(sc); 413 414 return (0); 415 } 416 417 static void 418 acpi_cpu_postattach(void *unused __unused) 419 { 420 device_t *devices; 421 int err; 422 int i, n; 423 int attached; 424 425 err = devclass_get_devices(acpi_cpu_devclass, &devices, &n); 426 if (err != 0) { 427 printf("devclass_get_devices(acpi_cpu_devclass) failed\n"); 428 return; 429 } 430 attached = 0; 431 for (i = 0; i < n; i++) 432 if (device_is_attached(devices[i]) && 433 device_get_driver(devices[i]) == &acpi_cpu_driver) 434 attached = 1; 435 for (i = 0; i < n; i++) 436 bus_generic_probe(devices[i]); 437 for (i = 0; i < n; i++) 438 bus_generic_attach(devices[i]); 439 free(devices, M_TEMP); 440 441 if (attached) { 442 #ifdef EARLY_AP_STARTUP 443 acpi_cpu_startup(NULL); 444 #else 445 /* Queue post cpu-probing task handler */ 446 AcpiOsExecute(OSL_NOTIFY_HANDLER, acpi_cpu_startup, NULL); 447 #endif 448 } 449 } 450 451 SYSINIT(acpi_cpu, SI_SUB_CONFIGURE, SI_ORDER_MIDDLE, 452 acpi_cpu_postattach, NULL); 453 454 static void 455 disable_idle(struct acpi_cpu_softc *sc) 456 { 457 cpuset_t cpuset; 458 459 CPU_SETOF(sc->cpu_pcpu->pc_cpuid, &cpuset); 460 sc->cpu_disable_idle = TRUE; 461 462 /* 463 * Ensure that the CPU is not in idle state or in acpi_cpu_idle(). 464 * Note that this code depends on the fact that the rendezvous IPI 465 * can not penetrate context where interrupts are disabled and acpi_cpu_idle 466 * is called and executed in such a context with interrupts being re-enabled 467 * right before return. 468 */ 469 smp_rendezvous_cpus(cpuset, smp_no_rendezvous_barrier, NULL, 470 smp_no_rendezvous_barrier, NULL); 471 } 472 473 static void 474 enable_idle(struct acpi_cpu_softc *sc) 475 { 476 477 sc->cpu_disable_idle = FALSE; 478 } 479 480 #if defined(__i386__) || defined(__amd64__) 481 static int 482 is_idle_disabled(struct acpi_cpu_softc *sc) 483 { 484 485 return (sc->cpu_disable_idle); 486 } 487 #endif 488 489 /* 490 * Disable any entry to the idle function during suspend and re-enable it 491 * during resume. 492 */ 493 static int 494 acpi_cpu_suspend(device_t dev) 495 { 496 int error; 497 498 error = bus_generic_suspend(dev); 499 if (error) 500 return (error); 501 disable_idle(device_get_softc(dev)); 502 return (0); 503 } 504 505 static int 506 acpi_cpu_resume(device_t dev) 507 { 508 509 enable_idle(device_get_softc(dev)); 510 return (bus_generic_resume(dev)); 511 } 512 513 /* 514 * Find the processor associated with a given ACPI ID. By default, 515 * use the MADT to map ACPI IDs to APIC IDs and use that to locate a 516 * processor. Some systems have inconsistent ASL and MADT however. 517 * For these systems the cpu_unordered tunable can be set in which 518 * case we assume that Processor objects are listed in the same order 519 * in both the MADT and ASL. 520 */ 521 static int 522 acpi_pcpu_get_id(device_t dev, uint32_t *acpi_id, uint32_t *cpu_id) 523 { 524 struct pcpu *pc; 525 uint32_t i, idx; 526 527 KASSERT(acpi_id != NULL, ("Null acpi_id")); 528 KASSERT(cpu_id != NULL, ("Null cpu_id")); 529 idx = device_get_unit(dev); 530 531 /* 532 * If pc_acpi_id for CPU 0 is not initialized (e.g. a non-APIC 533 * UP box) use the ACPI ID from the first processor we find. 534 */ 535 if (idx == 0 && mp_ncpus == 1) { 536 pc = pcpu_find(0); 537 if (pc->pc_acpi_id == 0xffffffff) 538 pc->pc_acpi_id = *acpi_id; 539 *cpu_id = 0; 540 return (0); 541 } 542 543 CPU_FOREACH(i) { 544 pc = pcpu_find(i); 545 KASSERT(pc != NULL, ("no pcpu data for %d", i)); 546 if (cpu_unordered) { 547 if (idx-- == 0) { 548 /* 549 * If pc_acpi_id doesn't match the ACPI ID from the 550 * ASL, prefer the MADT-derived value. 551 */ 552 if (pc->pc_acpi_id != *acpi_id) 553 *acpi_id = pc->pc_acpi_id; 554 *cpu_id = pc->pc_cpuid; 555 return (0); 556 } 557 } else { 558 if (pc->pc_acpi_id == *acpi_id) { 559 if (bootverbose) 560 device_printf(dev, 561 "Processor %s (ACPI ID %u) -> APIC ID %d\n", 562 acpi_name(acpi_get_handle(dev)), *acpi_id, 563 pc->pc_cpuid); 564 *cpu_id = pc->pc_cpuid; 565 return (0); 566 } 567 } 568 } 569 570 if (bootverbose) 571 printf("ACPI: Processor %s (ACPI ID %u) ignored\n", 572 acpi_name(acpi_get_handle(dev)), *acpi_id); 573 574 return (ESRCH); 575 } 576 577 static struct resource_list * 578 acpi_cpu_get_rlist(device_t dev, device_t child) 579 { 580 struct acpi_cpu_device *ad; 581 582 ad = device_get_ivars(child); 583 if (ad == NULL) 584 return (NULL); 585 return (&ad->ad_rl); 586 } 587 588 static device_t 589 acpi_cpu_add_child(device_t dev, u_int order, const char *name, int unit) 590 { 591 struct acpi_cpu_device *ad; 592 device_t child; 593 594 if ((ad = malloc(sizeof(*ad), M_TEMP, M_NOWAIT | M_ZERO)) == NULL) 595 return (NULL); 596 597 resource_list_init(&ad->ad_rl); 598 599 child = device_add_child_ordered(dev, order, name, unit); 600 if (child != NULL) 601 device_set_ivars(child, ad); 602 else 603 free(ad, M_TEMP); 604 return (child); 605 } 606 607 static int 608 acpi_cpu_read_ivar(device_t dev, device_t child, int index, uintptr_t *result) 609 { 610 struct acpi_cpu_softc *sc; 611 612 sc = device_get_softc(dev); 613 switch (index) { 614 case ACPI_IVAR_HANDLE: 615 *result = (uintptr_t)sc->cpu_handle; 616 break; 617 case CPU_IVAR_PCPU: 618 *result = (uintptr_t)sc->cpu_pcpu; 619 break; 620 #if defined(__amd64__) || defined(__i386__) 621 case CPU_IVAR_NOMINAL_MHZ: 622 if (tsc_is_invariant) { 623 *result = (uintptr_t)(atomic_load_acq_64(&tsc_freq) / 1000000); 624 break; 625 } 626 /* FALLTHROUGH */ 627 #endif 628 default: 629 return (ENOENT); 630 } 631 return (0); 632 } 633 634 static int 635 acpi_cpu_shutdown(device_t dev) 636 { 637 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 638 639 /* Allow children to shutdown first. */ 640 bus_generic_shutdown(dev); 641 642 /* 643 * Disable any entry to the idle function. 644 */ 645 disable_idle(device_get_softc(dev)); 646 647 /* 648 * CPU devices are not truly detached and remain referenced, 649 * so their resources are not freed. 650 */ 651 652 return_VALUE (0); 653 } 654 655 static void 656 acpi_cpu_cx_probe(struct acpi_cpu_softc *sc) 657 { 658 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 659 660 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 661 sc->cpu_prev_sleep = 1000000; 662 sc->cpu_cx_lowest = 0; 663 sc->cpu_cx_lowest_lim = 0; 664 665 /* 666 * Check for the ACPI 2.0 _CST sleep states object. If we can't find 667 * any, we'll revert to generic FADT/P_BLK Cx control method which will 668 * be handled by acpi_cpu_startup. We need to defer to after having 669 * probed all the cpus in the system before probing for generic Cx 670 * states as we may already have found cpus with valid _CST packages 671 */ 672 if (!cpu_cx_generic && acpi_cpu_cx_cst(sc) != 0) { 673 /* 674 * We were unable to find a _CST package for this cpu or there 675 * was an error parsing it. Switch back to generic mode. 676 */ 677 cpu_cx_generic = TRUE; 678 if (bootverbose) 679 device_printf(sc->cpu_dev, "switching to generic Cx mode\n"); 680 } 681 682 /* 683 * TODO: _CSD Package should be checked here. 684 */ 685 } 686 687 static void 688 acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc) 689 { 690 ACPI_GENERIC_ADDRESS gas; 691 struct acpi_cx *cx_ptr; 692 693 sc->cpu_cx_count = 0; 694 cx_ptr = sc->cpu_cx_states; 695 696 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 697 sc->cpu_prev_sleep = 1000000; 698 699 /* C1 has been required since just after ACPI 1.0 */ 700 cx_ptr->type = ACPI_STATE_C1; 701 cx_ptr->trans_lat = 0; 702 cx_ptr++; 703 sc->cpu_non_c2 = sc->cpu_cx_count; 704 sc->cpu_non_c3 = sc->cpu_cx_count; 705 sc->cpu_cx_count++; 706 707 /* 708 * The spec says P_BLK must be 6 bytes long. However, some systems 709 * use it to indicate a fractional set of features present so we 710 * take 5 as C2. Some may also have a value of 7 to indicate 711 * another C3 but most use _CST for this (as required) and having 712 * "only" C1-C3 is not a hardship. 713 */ 714 if (sc->cpu_p_blk_len < 5) 715 return; 716 717 /* Validate and allocate resources for C2 (P_LVL2). */ 718 gas.SpaceId = ACPI_ADR_SPACE_SYSTEM_IO; 719 gas.BitWidth = 8; 720 if (AcpiGbl_FADT.C2Latency <= 100) { 721 gas.Address = sc->cpu_p_blk + 4; 722 cx_ptr->res_rid = 0; 723 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &cx_ptr->res_rid, 724 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE); 725 if (cx_ptr->p_lvlx != NULL) { 726 cx_ptr->type = ACPI_STATE_C2; 727 cx_ptr->trans_lat = AcpiGbl_FADT.C2Latency; 728 cx_ptr++; 729 sc->cpu_non_c3 = sc->cpu_cx_count; 730 sc->cpu_cx_count++; 731 } 732 } 733 if (sc->cpu_p_blk_len < 6) 734 return; 735 736 /* Validate and allocate resources for C3 (P_LVL3). */ 737 if (AcpiGbl_FADT.C3Latency <= 1000 && !(cpu_quirks & CPU_QUIRK_NO_C3)) { 738 gas.Address = sc->cpu_p_blk + 5; 739 cx_ptr->res_rid = 1; 740 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &cx_ptr->res_rid, 741 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE); 742 if (cx_ptr->p_lvlx != NULL) { 743 cx_ptr->type = ACPI_STATE_C3; 744 cx_ptr->trans_lat = AcpiGbl_FADT.C3Latency; 745 cx_ptr++; 746 sc->cpu_cx_count++; 747 } 748 } 749 } 750 751 #if defined(__i386__) || defined(__amd64__) 752 static void 753 acpi_cpu_cx_cst_mwait(struct acpi_cx *cx_ptr, uint64_t address, int accsize) 754 { 755 756 cx_ptr->do_mwait = true; 757 cx_ptr->mwait_hint = address & 0xffffffff; 758 cx_ptr->mwait_hw_coord = (accsize & CST_FFH_MWAIT_HW_COORD) != 0; 759 cx_ptr->mwait_bm_avoidance = (accsize & CST_FFH_MWAIT_BM_AVOID) != 0; 760 } 761 #endif 762 763 static void 764 acpi_cpu_cx_cst_free_plvlx(device_t cpu_dev, struct acpi_cx *cx_ptr) 765 { 766 767 if (cx_ptr->p_lvlx == NULL) 768 return; 769 bus_release_resource(cpu_dev, cx_ptr->res_type, cx_ptr->res_rid, 770 cx_ptr->p_lvlx); 771 cx_ptr->p_lvlx = NULL; 772 } 773 774 /* 775 * Parse a _CST package and set up its Cx states. Since the _CST object 776 * can change dynamically, our notify handler may call this function 777 * to clean up and probe the new _CST package. 778 */ 779 static int 780 acpi_cpu_cx_cst(struct acpi_cpu_softc *sc) 781 { 782 struct acpi_cx *cx_ptr; 783 ACPI_STATUS status; 784 ACPI_BUFFER buf; 785 ACPI_OBJECT *top; 786 ACPI_OBJECT *pkg; 787 uint32_t count; 788 int i; 789 #if defined(__i386__) || defined(__amd64__) 790 uint64_t address; 791 int vendor, class, accsize; 792 #endif 793 794 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 795 796 buf.Pointer = NULL; 797 buf.Length = ACPI_ALLOCATE_BUFFER; 798 status = AcpiEvaluateObject(sc->cpu_handle, "_CST", NULL, &buf); 799 if (ACPI_FAILURE(status)) 800 return (ENXIO); 801 802 /* _CST is a package with a count and at least one Cx package. */ 803 top = (ACPI_OBJECT *)buf.Pointer; 804 if (!ACPI_PKG_VALID(top, 2) || acpi_PkgInt32(top, 0, &count) != 0) { 805 device_printf(sc->cpu_dev, "invalid _CST package\n"); 806 AcpiOsFree(buf.Pointer); 807 return (ENXIO); 808 } 809 if (count != top->Package.Count - 1) { 810 device_printf(sc->cpu_dev, "invalid _CST state count (%d != %d)\n", 811 count, top->Package.Count - 1); 812 count = top->Package.Count - 1; 813 } 814 if (count > MAX_CX_STATES) { 815 device_printf(sc->cpu_dev, "_CST has too many states (%d)\n", count); 816 count = MAX_CX_STATES; 817 } 818 819 sc->cpu_non_c2 = 0; 820 sc->cpu_non_c3 = 0; 821 sc->cpu_cx_count = 0; 822 cx_ptr = sc->cpu_cx_states; 823 824 /* 825 * C1 has been required since just after ACPI 1.0. 826 * Reserve the first slot for it. 827 */ 828 cx_ptr->type = ACPI_STATE_C0; 829 cx_ptr++; 830 sc->cpu_cx_count++; 831 832 /* Set up all valid states. */ 833 for (i = 0; i < count; i++) { 834 pkg = &top->Package.Elements[i + 1]; 835 if (!ACPI_PKG_VALID(pkg, 4) || 836 acpi_PkgInt32(pkg, 1, &cx_ptr->type) != 0 || 837 acpi_PkgInt32(pkg, 2, &cx_ptr->trans_lat) != 0 || 838 acpi_PkgInt32(pkg, 3, &cx_ptr->power) != 0) { 839 840 device_printf(sc->cpu_dev, "skipping invalid Cx state package\n"); 841 continue; 842 } 843 844 /* Validate the state to see if we should use it. */ 845 switch (cx_ptr->type) { 846 case ACPI_STATE_C1: 847 acpi_cpu_cx_cst_free_plvlx(sc->cpu_dev, cx_ptr); 848 #if defined(__i386__) || defined(__amd64__) 849 if (acpi_PkgFFH_IntelCpu(pkg, 0, &vendor, &class, &address, 850 &accsize) == 0 && vendor == CST_FFH_VENDOR_INTEL) { 851 if (class == CST_FFH_INTEL_CL_C1IO) { 852 /* C1 I/O then Halt */ 853 cx_ptr->res_rid = sc->cpu_cx_count; 854 bus_set_resource(sc->cpu_dev, SYS_RES_IOPORT, 855 cx_ptr->res_rid, address, 1); 856 cx_ptr->p_lvlx = bus_alloc_resource_any(sc->cpu_dev, 857 SYS_RES_IOPORT, &cx_ptr->res_rid, RF_ACTIVE | 858 RF_SHAREABLE); 859 if (cx_ptr->p_lvlx == NULL) { 860 bus_delete_resource(sc->cpu_dev, SYS_RES_IOPORT, 861 cx_ptr->res_rid); 862 device_printf(sc->cpu_dev, 863 "C1 I/O failed to allocate port %d, " 864 "degrading to C1 Halt", (int)address); 865 } 866 } else if (class == CST_FFH_INTEL_CL_MWAIT) { 867 acpi_cpu_cx_cst_mwait(cx_ptr, address, accsize); 868 } 869 } 870 #endif 871 if (sc->cpu_cx_states[0].type == ACPI_STATE_C0) { 872 /* This is the first C1 state. Use the reserved slot. */ 873 sc->cpu_cx_states[0] = *cx_ptr; 874 } else { 875 sc->cpu_non_c2 = sc->cpu_cx_count; 876 sc->cpu_non_c3 = sc->cpu_cx_count; 877 cx_ptr++; 878 sc->cpu_cx_count++; 879 } 880 continue; 881 case ACPI_STATE_C2: 882 sc->cpu_non_c3 = sc->cpu_cx_count; 883 break; 884 case ACPI_STATE_C3: 885 default: 886 if ((cpu_quirks & CPU_QUIRK_NO_C3) != 0) { 887 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 888 "acpi_cpu%d: C3[%d] not available.\n", 889 device_get_unit(sc->cpu_dev), i)); 890 continue; 891 } 892 break; 893 } 894 895 /* Free up any previous register. */ 896 acpi_cpu_cx_cst_free_plvlx(sc->cpu_dev, cx_ptr); 897 898 /* Allocate the control register for C2 or C3. */ 899 #if defined(__i386__) || defined(__amd64__) 900 if (acpi_PkgFFH_IntelCpu(pkg, 0, &vendor, &class, &address, 901 &accsize) == 0 && vendor == CST_FFH_VENDOR_INTEL && 902 class == CST_FFH_INTEL_CL_MWAIT) { 903 /* Native C State Instruction use (mwait) */ 904 acpi_cpu_cx_cst_mwait(cx_ptr, address, accsize); 905 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 906 "acpi_cpu%d: Got C%d/mwait - %d latency\n", 907 device_get_unit(sc->cpu_dev), cx_ptr->type, cx_ptr->trans_lat)); 908 cx_ptr++; 909 sc->cpu_cx_count++; 910 } else 911 #endif 912 { 913 cx_ptr->res_rid = sc->cpu_cx_count; 914 acpi_PkgGas(sc->cpu_dev, pkg, 0, &cx_ptr->res_type, 915 &cx_ptr->res_rid, &cx_ptr->p_lvlx, RF_SHAREABLE); 916 if (cx_ptr->p_lvlx) { 917 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 918 "acpi_cpu%d: Got C%d - %d latency\n", 919 device_get_unit(sc->cpu_dev), cx_ptr->type, 920 cx_ptr->trans_lat)); 921 cx_ptr++; 922 sc->cpu_cx_count++; 923 } 924 } 925 } 926 AcpiOsFree(buf.Pointer); 927 928 /* If C1 state was not found, we need one now. */ 929 cx_ptr = sc->cpu_cx_states; 930 if (cx_ptr->type == ACPI_STATE_C0) { 931 cx_ptr->type = ACPI_STATE_C1; 932 cx_ptr->trans_lat = 0; 933 } 934 935 return (0); 936 } 937 938 /* 939 * Call this *after* all CPUs have been attached. 940 */ 941 static void 942 acpi_cpu_startup(void *arg) 943 { 944 struct acpi_cpu_softc *sc; 945 int i; 946 947 /* Get set of CPU devices */ 948 devclass_get_devices(acpi_cpu_devclass, &cpu_devices, &cpu_ndevices); 949 950 /* 951 * Setup any quirks that might necessary now that we have probed 952 * all the CPUs 953 */ 954 acpi_cpu_quirks(); 955 956 if (cpu_cx_generic) { 957 /* 958 * We are using generic Cx mode, probe for available Cx states 959 * for all processors. 960 */ 961 for (i = 0; i < cpu_ndevices; i++) { 962 sc = device_get_softc(cpu_devices[i]); 963 acpi_cpu_generic_cx_probe(sc); 964 } 965 } else { 966 /* 967 * We are using _CST mode, remove C3 state if necessary. 968 * As we now know for sure that we will be using _CST mode 969 * install our notify handler. 970 */ 971 for (i = 0; i < cpu_ndevices; i++) { 972 sc = device_get_softc(cpu_devices[i]); 973 if (cpu_quirks & CPU_QUIRK_NO_C3) { 974 sc->cpu_cx_count = min(sc->cpu_cx_count, sc->cpu_non_c3 + 1); 975 } 976 AcpiInstallNotifyHandler(sc->cpu_handle, ACPI_DEVICE_NOTIFY, 977 acpi_cpu_notify, sc); 978 } 979 } 980 981 /* Perform Cx final initialization. */ 982 for (i = 0; i < cpu_ndevices; i++) { 983 sc = device_get_softc(cpu_devices[i]); 984 acpi_cpu_startup_cx(sc); 985 } 986 987 /* Add a sysctl handler to handle global Cx lowest setting */ 988 SYSCTL_ADD_PROC(&cpu_sysctl_ctx, SYSCTL_CHILDREN(cpu_sysctl_tree), 989 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW, 990 NULL, 0, acpi_cpu_global_cx_lowest_sysctl, "A", 991 "Global lowest Cx sleep state to use"); 992 993 /* Take over idling from cpu_idle_default(). */ 994 cpu_cx_lowest_lim = 0; 995 for (i = 0; i < cpu_ndevices; i++) { 996 sc = device_get_softc(cpu_devices[i]); 997 enable_idle(sc); 998 } 999 #if defined(__i386__) || defined(__amd64__) 1000 cpu_idle_hook = acpi_cpu_idle; 1001 #endif 1002 } 1003 1004 static void 1005 acpi_cpu_cx_list(struct acpi_cpu_softc *sc) 1006 { 1007 struct sbuf sb; 1008 int i; 1009 1010 /* 1011 * Set up the list of Cx states 1012 */ 1013 sbuf_new(&sb, sc->cpu_cx_supported, sizeof(sc->cpu_cx_supported), 1014 SBUF_FIXEDLEN); 1015 for (i = 0; i < sc->cpu_cx_count; i++) 1016 sbuf_printf(&sb, "C%d/%d/%d ", i + 1, sc->cpu_cx_states[i].type, 1017 sc->cpu_cx_states[i].trans_lat); 1018 sbuf_trim(&sb); 1019 sbuf_finish(&sb); 1020 } 1021 1022 static void 1023 acpi_cpu_startup_cx(struct acpi_cpu_softc *sc) 1024 { 1025 acpi_cpu_cx_list(sc); 1026 1027 SYSCTL_ADD_STRING(&sc->cpu_sysctl_ctx, 1028 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 1029 OID_AUTO, "cx_supported", CTLFLAG_RD, 1030 sc->cpu_cx_supported, 0, 1031 "Cx/microsecond values for supported Cx states"); 1032 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1033 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 1034 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW, 1035 (void *)sc, 0, acpi_cpu_cx_lowest_sysctl, "A", 1036 "lowest Cx sleep state to use"); 1037 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1038 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 1039 OID_AUTO, "cx_usage", CTLTYPE_STRING | CTLFLAG_RD, 1040 (void *)sc, 0, acpi_cpu_usage_sysctl, "A", 1041 "percent usage for each Cx state"); 1042 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1043 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 1044 OID_AUTO, "cx_usage_counters", CTLTYPE_STRING | CTLFLAG_RD, 1045 (void *)sc, 0, acpi_cpu_usage_counters_sysctl, "A", 1046 "Cx sleep state counters"); 1047 #if defined(__i386__) || defined(__amd64__) 1048 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1049 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 1050 OID_AUTO, "cx_method", CTLTYPE_STRING | CTLFLAG_RD, 1051 (void *)sc, 0, acpi_cpu_method_sysctl, "A", 1052 "Cx entrance methods"); 1053 #endif 1054 1055 /* Signal platform that we can handle _CST notification. */ 1056 if (!cpu_cx_generic && cpu_cst_cnt != 0) { 1057 ACPI_LOCK(acpi); 1058 AcpiOsWritePort(cpu_smi_cmd, cpu_cst_cnt, 8); 1059 ACPI_UNLOCK(acpi); 1060 } 1061 } 1062 1063 #if defined(__i386__) || defined(__amd64__) 1064 /* 1065 * Idle the CPU in the lowest state possible. This function is called with 1066 * interrupts disabled. Note that once it re-enables interrupts, a task 1067 * switch can occur so do not access shared data (i.e. the softc) after 1068 * interrupts are re-enabled. 1069 */ 1070 static void 1071 acpi_cpu_idle(sbintime_t sbt) 1072 { 1073 struct acpi_cpu_softc *sc; 1074 struct acpi_cx *cx_next; 1075 uint64_t cputicks; 1076 uint32_t start_time, end_time; 1077 ACPI_STATUS status; 1078 int bm_active, cx_next_idx, i, us; 1079 1080 /* 1081 * Look up our CPU id to get our softc. If it's NULL, we'll use C1 1082 * since there is no ACPI processor object for this CPU. This occurs 1083 * for logical CPUs in the HTT case. 1084 */ 1085 sc = cpu_softc[PCPU_GET(cpuid)]; 1086 if (sc == NULL) { 1087 acpi_cpu_c1(); 1088 return; 1089 } 1090 1091 /* If disabled, take the safe path. */ 1092 if (is_idle_disabled(sc)) { 1093 acpi_cpu_c1(); 1094 return; 1095 } 1096 1097 /* Find the lowest state that has small enough latency. */ 1098 us = sc->cpu_prev_sleep; 1099 if (sbt >= 0 && us > (sbt >> 12)) 1100 us = (sbt >> 12); 1101 cx_next_idx = 0; 1102 if (cpu_disable_c2_sleep) 1103 i = min(sc->cpu_cx_lowest, sc->cpu_non_c2); 1104 else if (cpu_disable_c3_sleep) 1105 i = min(sc->cpu_cx_lowest, sc->cpu_non_c3); 1106 else 1107 i = sc->cpu_cx_lowest; 1108 for (; i >= 0; i--) { 1109 if (sc->cpu_cx_states[i].trans_lat * 3 <= us) { 1110 cx_next_idx = i; 1111 break; 1112 } 1113 } 1114 1115 /* 1116 * Check for bus master activity. If there was activity, clear 1117 * the bit and use the lowest non-C3 state. Note that the USB 1118 * driver polling for new devices keeps this bit set all the 1119 * time if USB is loaded. 1120 */ 1121 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0 && 1122 cx_next_idx > sc->cpu_non_c3) { 1123 status = AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active); 1124 if (ACPI_SUCCESS(status) && bm_active != 0) { 1125 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1); 1126 cx_next_idx = sc->cpu_non_c3; 1127 } 1128 } 1129 1130 /* Select the next state and update statistics. */ 1131 cx_next = &sc->cpu_cx_states[cx_next_idx]; 1132 sc->cpu_cx_stats[cx_next_idx]++; 1133 KASSERT(cx_next->type != ACPI_STATE_C0, ("acpi_cpu_idle: C0 sleep")); 1134 1135 /* 1136 * Execute HLT (or equivalent) and wait for an interrupt. We can't 1137 * precisely calculate the time spent in C1 since the place we wake up 1138 * is an ISR. Assume we slept no more then half of quantum, unless 1139 * we are called inside critical section, delaying context switch. 1140 */ 1141 if (cx_next->type == ACPI_STATE_C1) { 1142 cputicks = cpu_ticks(); 1143 if (cx_next->p_lvlx != NULL) { 1144 /* C1 I/O then Halt */ 1145 CPU_GET_REG(cx_next->p_lvlx, 1); 1146 } 1147 if (cx_next->do_mwait) 1148 acpi_cpu_idle_mwait(cx_next->mwait_hint); 1149 else 1150 acpi_cpu_c1(); 1151 end_time = ((cpu_ticks() - cputicks) << 20) / cpu_tickrate(); 1152 if (curthread->td_critnest == 0) 1153 end_time = min(end_time, 500000 / hz); 1154 /* acpi_cpu_c1() returns with interrupts enabled. */ 1155 if (cx_next->do_mwait) 1156 ACPI_ENABLE_IRQS(); 1157 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + end_time) / 4; 1158 return; 1159 } 1160 1161 /* 1162 * For C3, disable bus master arbitration and enable bus master wake 1163 * if BM control is available, otherwise flush the CPU cache. 1164 */ 1165 if (cx_next->type == ACPI_STATE_C3 || cx_next->mwait_bm_avoidance) { 1166 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 1167 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1); 1168 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1); 1169 } else 1170 ACPI_FLUSH_CPU_CACHE(); 1171 } 1172 1173 /* 1174 * Read from P_LVLx to enter C2(+), checking time spent asleep. 1175 * Use the ACPI timer for measuring sleep time. Since we need to 1176 * get the time very close to the CPU start/stop clock logic, this 1177 * is the only reliable time source. 1178 */ 1179 if (cx_next->type == ACPI_STATE_C3) { 1180 AcpiHwRead(&start_time, &AcpiGbl_FADT.XPmTimerBlock); 1181 cputicks = 0; 1182 } else { 1183 start_time = 0; 1184 cputicks = cpu_ticks(); 1185 } 1186 if (cx_next->do_mwait) 1187 acpi_cpu_idle_mwait(cx_next->mwait_hint); 1188 else 1189 CPU_GET_REG(cx_next->p_lvlx, 1); 1190 1191 /* 1192 * Read the end time twice. Since it may take an arbitrary time 1193 * to enter the idle state, the first read may be executed before 1194 * the processor has stopped. Doing it again provides enough 1195 * margin that we are certain to have a correct value. 1196 */ 1197 AcpiHwRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock); 1198 if (cx_next->type == ACPI_STATE_C3) { 1199 AcpiHwRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock); 1200 end_time = acpi_TimerDelta(end_time, start_time); 1201 } else 1202 end_time = ((cpu_ticks() - cputicks) << 20) / cpu_tickrate(); 1203 1204 /* Enable bus master arbitration and disable bus master wakeup. */ 1205 if ((cx_next->type == ACPI_STATE_C3 || cx_next->mwait_bm_avoidance) && 1206 (cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 1207 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0); 1208 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 1209 } 1210 ACPI_ENABLE_IRQS(); 1211 1212 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + PM_USEC(end_time)) / 4; 1213 } 1214 #endif 1215 1216 /* 1217 * Re-evaluate the _CST object when we are notified that it changed. 1218 */ 1219 static void 1220 acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context) 1221 { 1222 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)context; 1223 1224 if (notify != ACPI_NOTIFY_CX_STATES) 1225 return; 1226 1227 /* 1228 * C-state data for target CPU is going to be in flux while we execute 1229 * acpi_cpu_cx_cst, so disable entering acpi_cpu_idle. 1230 * Also, it may happen that multiple ACPI taskqueues may concurrently 1231 * execute notifications for the same CPU. ACPI_SERIAL is used to 1232 * protect against that. 1233 */ 1234 ACPI_SERIAL_BEGIN(cpu); 1235 disable_idle(sc); 1236 1237 /* Update the list of Cx states. */ 1238 acpi_cpu_cx_cst(sc); 1239 acpi_cpu_cx_list(sc); 1240 acpi_cpu_set_cx_lowest(sc); 1241 1242 enable_idle(sc); 1243 ACPI_SERIAL_END(cpu); 1244 1245 acpi_UserNotify("PROCESSOR", sc->cpu_handle, notify); 1246 } 1247 1248 static void 1249 acpi_cpu_quirks(void) 1250 { 1251 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 1252 1253 /* 1254 * Bus mastering arbitration control is needed to keep caches coherent 1255 * while sleeping in C3. If it's not present but a working flush cache 1256 * instruction is present, flush the caches before entering C3 instead. 1257 * Otherwise, just disable C3 completely. 1258 */ 1259 if (AcpiGbl_FADT.Pm2ControlBlock == 0 || 1260 AcpiGbl_FADT.Pm2ControlLength == 0) { 1261 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) && 1262 (AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) { 1263 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 1264 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1265 "acpi_cpu: no BM control, using flush cache method\n")); 1266 } else { 1267 cpu_quirks |= CPU_QUIRK_NO_C3; 1268 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1269 "acpi_cpu: no BM control, C3 not available\n")); 1270 } 1271 } 1272 1273 /* 1274 * If we are using generic Cx mode, C3 on multiple CPUs requires using 1275 * the expensive flush cache instruction. 1276 */ 1277 if (cpu_cx_generic && mp_ncpus > 1) { 1278 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 1279 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1280 "acpi_cpu: SMP, using flush cache mode for C3\n")); 1281 } 1282 1283 /* Look for various quirks of the PIIX4 part. */ 1284 acpi_cpu_quirks_piix4(); 1285 } 1286 1287 static void 1288 acpi_cpu_quirks_piix4(void) 1289 { 1290 #ifdef __i386__ 1291 device_t acpi_dev; 1292 uint32_t val; 1293 ACPI_STATUS status; 1294 1295 acpi_dev = pci_find_device(PCI_VENDOR_INTEL, PCI_DEVICE_82371AB_3); 1296 if (acpi_dev != NULL) { 1297 switch (pci_get_revid(acpi_dev)) { 1298 /* 1299 * Disable C3 support for all PIIX4 chipsets. Some of these parts 1300 * do not report the BMIDE status to the BM status register and 1301 * others have a livelock bug if Type-F DMA is enabled. Linux 1302 * works around the BMIDE bug by reading the BM status directly 1303 * but we take the simpler approach of disabling C3 for these 1304 * parts. 1305 * 1306 * See erratum #18 ("C3 Power State/BMIDE and Type-F DMA 1307 * Livelock") from the January 2002 PIIX4 specification update. 1308 * Applies to all PIIX4 models. 1309 * 1310 * Also, make sure that all interrupts cause a "Stop Break" 1311 * event to exit from C2 state. 1312 * Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak) 1313 * should be set to zero, otherwise it causes C2 to short-sleep. 1314 * PIIX4 doesn't properly support C3 and bus master activity 1315 * need not break out of C2. 1316 */ 1317 case PCI_REVISION_A_STEP: 1318 case PCI_REVISION_B_STEP: 1319 case PCI_REVISION_4E: 1320 case PCI_REVISION_4M: 1321 cpu_quirks |= CPU_QUIRK_NO_C3; 1322 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1323 "acpi_cpu: working around PIIX4 bug, disabling C3\n")); 1324 1325 val = pci_read_config(acpi_dev, PIIX4_DEVACTB_REG, 4); 1326 if ((val & PIIX4_STOP_BREAK_MASK) != PIIX4_STOP_BREAK_MASK) { 1327 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1328 "acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n")); 1329 val |= PIIX4_STOP_BREAK_MASK; 1330 pci_write_config(acpi_dev, PIIX4_DEVACTB_REG, val, 4); 1331 } 1332 status = AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_RLD, &val); 1333 if (ACPI_SUCCESS(status) && val != 0) { 1334 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1335 "acpi_cpu: PIIX4: reset BRLD_EN_BM\n")); 1336 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 1337 } 1338 break; 1339 default: 1340 break; 1341 } 1342 } 1343 #endif 1344 } 1345 1346 static int 1347 acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS) 1348 { 1349 struct acpi_cpu_softc *sc; 1350 struct sbuf sb; 1351 char buf[128]; 1352 int i; 1353 uintmax_t fract, sum, whole; 1354 1355 sc = (struct acpi_cpu_softc *) arg1; 1356 sum = 0; 1357 for (i = 0; i < sc->cpu_cx_count; i++) 1358 sum += sc->cpu_cx_stats[i]; 1359 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN); 1360 for (i = 0; i < sc->cpu_cx_count; i++) { 1361 if (sum > 0) { 1362 whole = (uintmax_t)sc->cpu_cx_stats[i] * 100; 1363 fract = (whole % sum) * 100; 1364 sbuf_printf(&sb, "%u.%02u%% ", (u_int)(whole / sum), 1365 (u_int)(fract / sum)); 1366 } else 1367 sbuf_printf(&sb, "0.00%% "); 1368 } 1369 sbuf_printf(&sb, "last %dus", sc->cpu_prev_sleep); 1370 sbuf_trim(&sb); 1371 sbuf_finish(&sb); 1372 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 1373 sbuf_delete(&sb); 1374 1375 return (0); 1376 } 1377 1378 /* 1379 * XXX TODO: actually add support to count each entry/exit 1380 * from the Cx states. 1381 */ 1382 static int 1383 acpi_cpu_usage_counters_sysctl(SYSCTL_HANDLER_ARGS) 1384 { 1385 struct acpi_cpu_softc *sc; 1386 struct sbuf sb; 1387 char buf[128]; 1388 int i; 1389 1390 sc = (struct acpi_cpu_softc *) arg1; 1391 1392 /* Print out the raw counters */ 1393 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN); 1394 1395 for (i = 0; i < sc->cpu_cx_count; i++) { 1396 sbuf_printf(&sb, "%u ", sc->cpu_cx_stats[i]); 1397 } 1398 1399 sbuf_trim(&sb); 1400 sbuf_finish(&sb); 1401 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 1402 sbuf_delete(&sb); 1403 1404 return (0); 1405 } 1406 1407 #if defined(__i386__) || defined(__amd64__) 1408 static int 1409 acpi_cpu_method_sysctl(SYSCTL_HANDLER_ARGS) 1410 { 1411 struct acpi_cpu_softc *sc; 1412 struct acpi_cx *cx; 1413 struct sbuf sb; 1414 char buf[128]; 1415 int i; 1416 1417 sc = (struct acpi_cpu_softc *)arg1; 1418 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN); 1419 for (i = 0; i < sc->cpu_cx_count; i++) { 1420 cx = &sc->cpu_cx_states[i]; 1421 sbuf_printf(&sb, "C%d/", i + 1); 1422 if (cx->do_mwait) { 1423 sbuf_cat(&sb, "mwait"); 1424 if (cx->mwait_hw_coord) 1425 sbuf_cat(&sb, "/hwc"); 1426 if (cx->mwait_bm_avoidance) 1427 sbuf_cat(&sb, "/bma"); 1428 } else if (cx->type == ACPI_STATE_C1) { 1429 sbuf_cat(&sb, "hlt"); 1430 } else { 1431 sbuf_cat(&sb, "io"); 1432 } 1433 if (cx->type == ACPI_STATE_C1 && cx->p_lvlx != NULL) 1434 sbuf_cat(&sb, "/iohlt"); 1435 sbuf_putc(&sb, ' '); 1436 } 1437 sbuf_trim(&sb); 1438 sbuf_finish(&sb); 1439 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 1440 sbuf_delete(&sb); 1441 return (0); 1442 } 1443 #endif 1444 1445 static int 1446 acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc) 1447 { 1448 int i; 1449 1450 ACPI_SERIAL_ASSERT(cpu); 1451 sc->cpu_cx_lowest = min(sc->cpu_cx_lowest_lim, sc->cpu_cx_count - 1); 1452 1453 /* If not disabling, cache the new lowest non-C3 state. */ 1454 sc->cpu_non_c3 = 0; 1455 for (i = sc->cpu_cx_lowest; i >= 0; i--) { 1456 if (sc->cpu_cx_states[i].type < ACPI_STATE_C3) { 1457 sc->cpu_non_c3 = i; 1458 break; 1459 } 1460 } 1461 1462 /* Reset the statistics counters. */ 1463 bzero(sc->cpu_cx_stats, sizeof(sc->cpu_cx_stats)); 1464 return (0); 1465 } 1466 1467 static int 1468 acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1469 { 1470 struct acpi_cpu_softc *sc; 1471 char state[8]; 1472 int val, error; 1473 1474 sc = (struct acpi_cpu_softc *) arg1; 1475 snprintf(state, sizeof(state), "C%d", sc->cpu_cx_lowest_lim + 1); 1476 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1477 if (error != 0 || req->newptr == NULL) 1478 return (error); 1479 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1480 return (EINVAL); 1481 if (strcasecmp(state, "Cmax") == 0) 1482 val = MAX_CX_STATES; 1483 else { 1484 val = (int) strtol(state + 1, NULL, 10); 1485 if (val < 1 || val > MAX_CX_STATES) 1486 return (EINVAL); 1487 } 1488 1489 ACPI_SERIAL_BEGIN(cpu); 1490 sc->cpu_cx_lowest_lim = val - 1; 1491 acpi_cpu_set_cx_lowest(sc); 1492 ACPI_SERIAL_END(cpu); 1493 1494 return (0); 1495 } 1496 1497 static int 1498 acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1499 { 1500 struct acpi_cpu_softc *sc; 1501 char state[8]; 1502 int val, error, i; 1503 1504 snprintf(state, sizeof(state), "C%d", cpu_cx_lowest_lim + 1); 1505 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1506 if (error != 0 || req->newptr == NULL) 1507 return (error); 1508 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1509 return (EINVAL); 1510 if (strcasecmp(state, "Cmax") == 0) 1511 val = MAX_CX_STATES; 1512 else { 1513 val = (int) strtol(state + 1, NULL, 10); 1514 if (val < 1 || val > MAX_CX_STATES) 1515 return (EINVAL); 1516 } 1517 1518 /* Update the new lowest useable Cx state for all CPUs. */ 1519 ACPI_SERIAL_BEGIN(cpu); 1520 cpu_cx_lowest_lim = val - 1; 1521 for (i = 0; i < cpu_ndevices; i++) { 1522 sc = device_get_softc(cpu_devices[i]); 1523 sc->cpu_cx_lowest_lim = cpu_cx_lowest_lim; 1524 acpi_cpu_set_cx_lowest(sc); 1525 } 1526 ACPI_SERIAL_END(cpu); 1527 1528 return (0); 1529 } 1530