1 /*- 2 * Copyright (c) 2005 Poul-Henning Kamp 3 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_acpi.h" 32 33 #if defined(__amd64__) 34 #define DEV_APIC 35 #else 36 #include "opt_apic.h" 37 #endif 38 #include <sys/param.h> 39 #include <sys/conf.h> 40 #include <sys/bus.h> 41 #include <sys/kernel.h> 42 #include <sys/module.h> 43 #include <sys/proc.h> 44 #include <sys/rman.h> 45 #include <sys/mman.h> 46 #include <sys/time.h> 47 #include <sys/smp.h> 48 #include <sys/sysctl.h> 49 #include <sys/timeet.h> 50 #include <sys/timetc.h> 51 #include <sys/vdso.h> 52 53 #include <contrib/dev/acpica/include/acpi.h> 54 #include <contrib/dev/acpica/include/accommon.h> 55 56 #include <dev/acpica/acpivar.h> 57 #include <dev/acpica/acpi_hpet.h> 58 59 #ifdef DEV_APIC 60 #include "pcib_if.h" 61 #endif 62 63 #define HPET_VENDID_AMD 0x4353 64 #define HPET_VENDID_AMD2 0x1022 65 #define HPET_VENDID_INTEL 0x8086 66 #define HPET_VENDID_NVIDIA 0x10de 67 #define HPET_VENDID_SW 0x1166 68 69 ACPI_SERIAL_DECL(hpet, "ACPI HPET support"); 70 71 static devclass_t hpet_devclass; 72 73 /* ACPI CA debugging */ 74 #define _COMPONENT ACPI_TIMER 75 ACPI_MODULE_NAME("HPET") 76 77 struct hpet_softc { 78 device_t dev; 79 int mem_rid; 80 int intr_rid; 81 int irq; 82 int useirq; 83 int legacy_route; 84 int per_cpu; 85 uint32_t allowed_irqs; 86 struct resource *mem_res; 87 struct resource *intr_res; 88 void *intr_handle; 89 ACPI_HANDLE handle; 90 uint32_t acpi_uid; 91 uint64_t freq; 92 uint32_t caps; 93 struct timecounter tc; 94 struct hpet_timer { 95 struct eventtimer et; 96 struct hpet_softc *sc; 97 int num; 98 int mode; 99 #define TIMER_STOPPED 0 100 #define TIMER_PERIODIC 1 101 #define TIMER_ONESHOT 2 102 int intr_rid; 103 int irq; 104 int pcpu_cpu; 105 int pcpu_misrouted; 106 int pcpu_master; 107 int pcpu_slaves[MAXCPU]; 108 struct resource *intr_res; 109 void *intr_handle; 110 uint32_t caps; 111 uint32_t vectors; 112 uint32_t div; 113 uint32_t next; 114 char name[8]; 115 } t[32]; 116 int num_timers; 117 struct cdev *pdev; 118 int mmap_allow; 119 int mmap_allow_write; 120 }; 121 122 static d_open_t hpet_open; 123 static d_mmap_t hpet_mmap; 124 125 static struct cdevsw hpet_cdevsw = { 126 .d_version = D_VERSION, 127 .d_name = "hpet", 128 .d_open = hpet_open, 129 .d_mmap = hpet_mmap, 130 }; 131 132 static u_int hpet_get_timecount(struct timecounter *tc); 133 static void hpet_test(struct hpet_softc *sc); 134 135 static char *hpet_ids[] = { "PNP0103", NULL }; 136 137 /* Knob to disable acpi_hpet device */ 138 bool acpi_hpet_disabled = false; 139 140 static u_int 141 hpet_get_timecount(struct timecounter *tc) 142 { 143 struct hpet_softc *sc; 144 145 sc = tc->tc_priv; 146 return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER)); 147 } 148 149 uint32_t 150 hpet_vdso_timehands(struct vdso_timehands *vdso_th, struct timecounter *tc) 151 { 152 struct hpet_softc *sc; 153 154 sc = tc->tc_priv; 155 vdso_th->th_algo = VDSO_TH_ALGO_X86_HPET; 156 vdso_th->th_x86_shift = 0; 157 vdso_th->th_x86_hpet_idx = device_get_unit(sc->dev); 158 bzero(vdso_th->th_res, sizeof(vdso_th->th_res)); 159 return (sc->mmap_allow != 0); 160 } 161 162 #ifdef COMPAT_FREEBSD32 163 uint32_t 164 hpet_vdso_timehands32(struct vdso_timehands32 *vdso_th32, 165 struct timecounter *tc) 166 { 167 struct hpet_softc *sc; 168 169 sc = tc->tc_priv; 170 vdso_th32->th_algo = VDSO_TH_ALGO_X86_HPET; 171 vdso_th32->th_x86_shift = 0; 172 vdso_th32->th_x86_hpet_idx = device_get_unit(sc->dev); 173 bzero(vdso_th32->th_res, sizeof(vdso_th32->th_res)); 174 return (sc->mmap_allow != 0); 175 } 176 #endif 177 178 static void 179 hpet_enable(struct hpet_softc *sc) 180 { 181 uint32_t val; 182 183 val = bus_read_4(sc->mem_res, HPET_CONFIG); 184 if (sc->legacy_route) 185 val |= HPET_CNF_LEG_RT; 186 else 187 val &= ~HPET_CNF_LEG_RT; 188 val |= HPET_CNF_ENABLE; 189 bus_write_4(sc->mem_res, HPET_CONFIG, val); 190 } 191 192 static void 193 hpet_disable(struct hpet_softc *sc) 194 { 195 uint32_t val; 196 197 val = bus_read_4(sc->mem_res, HPET_CONFIG); 198 val &= ~HPET_CNF_ENABLE; 199 bus_write_4(sc->mem_res, HPET_CONFIG, val); 200 } 201 202 static int 203 hpet_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 204 { 205 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 206 struct hpet_timer *t; 207 struct hpet_softc *sc = mt->sc; 208 uint32_t fdiv, now; 209 210 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 211 if (period != 0) { 212 t->mode = TIMER_PERIODIC; 213 t->div = (sc->freq * period) >> 32; 214 } else { 215 t->mode = TIMER_ONESHOT; 216 t->div = 0; 217 } 218 if (first != 0) 219 fdiv = (sc->freq * first) >> 32; 220 else 221 fdiv = t->div; 222 if (t->irq < 0) 223 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 224 t->caps |= HPET_TCNF_INT_ENB; 225 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 226 restart: 227 t->next = now + fdiv; 228 if (t->mode == TIMER_PERIODIC && (t->caps & HPET_TCAP_PER_INT)) { 229 t->caps |= HPET_TCNF_TYPE; 230 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 231 t->caps | HPET_TCNF_VAL_SET); 232 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 233 t->next); 234 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 235 t->div); 236 } else { 237 t->caps &= ~HPET_TCNF_TYPE; 238 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 239 t->caps); 240 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 241 t->next); 242 } 243 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 244 if ((int32_t)(now - t->next + HPET_MIN_CYCLES) >= 0) { 245 fdiv *= 2; 246 goto restart; 247 } 248 return (0); 249 } 250 251 static int 252 hpet_stop(struct eventtimer *et) 253 { 254 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 255 struct hpet_timer *t; 256 struct hpet_softc *sc = mt->sc; 257 258 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 259 t->mode = TIMER_STOPPED; 260 t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE); 261 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 262 return (0); 263 } 264 265 static int 266 hpet_intr_single(void *arg) 267 { 268 struct hpet_timer *t = (struct hpet_timer *)arg; 269 struct hpet_timer *mt; 270 struct hpet_softc *sc = t->sc; 271 uint32_t now; 272 273 if (t->mode == TIMER_STOPPED) 274 return (FILTER_STRAY); 275 /* Check that per-CPU timer interrupt reached right CPU. */ 276 if (t->pcpu_cpu >= 0 && t->pcpu_cpu != curcpu) { 277 if ((++t->pcpu_misrouted) % 32 == 0) { 278 printf("HPET interrupt routed to the wrong CPU" 279 " (timer %d CPU %d -> %d)!\n", 280 t->num, t->pcpu_cpu, curcpu); 281 } 282 283 /* 284 * Reload timer, hoping that next time may be more lucky 285 * (system will manage proper interrupt binding). 286 */ 287 if ((t->mode == TIMER_PERIODIC && 288 (t->caps & HPET_TCAP_PER_INT) == 0) || 289 t->mode == TIMER_ONESHOT) { 290 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) + 291 sc->freq / 8; 292 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 293 t->next); 294 } 295 return (FILTER_HANDLED); 296 } 297 if (t->mode == TIMER_PERIODIC && 298 (t->caps & HPET_TCAP_PER_INT) == 0) { 299 t->next += t->div; 300 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 301 if ((int32_t)((now + t->div / 2) - t->next) > 0) 302 t->next = now + t->div / 2; 303 bus_write_4(sc->mem_res, 304 HPET_TIMER_COMPARATOR(t->num), t->next); 305 } else if (t->mode == TIMER_ONESHOT) 306 t->mode = TIMER_STOPPED; 307 mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master]; 308 if (mt->et.et_active) 309 mt->et.et_event_cb(&mt->et, mt->et.et_arg); 310 return (FILTER_HANDLED); 311 } 312 313 static int 314 hpet_intr(void *arg) 315 { 316 struct hpet_softc *sc = (struct hpet_softc *)arg; 317 int i; 318 uint32_t val; 319 320 val = bus_read_4(sc->mem_res, HPET_ISR); 321 if (val) { 322 bus_write_4(sc->mem_res, HPET_ISR, val); 323 val &= sc->useirq; 324 for (i = 0; i < sc->num_timers; i++) { 325 if ((val & (1 << i)) == 0) 326 continue; 327 hpet_intr_single(&sc->t[i]); 328 } 329 return (FILTER_HANDLED); 330 } 331 return (FILTER_STRAY); 332 } 333 334 uint32_t 335 hpet_get_uid(device_t dev) 336 { 337 struct hpet_softc *sc; 338 339 sc = device_get_softc(dev); 340 return (sc->acpi_uid); 341 } 342 343 static ACPI_STATUS 344 hpet_find(ACPI_HANDLE handle, UINT32 level, void *context, 345 void **status) 346 { 347 char **ids; 348 uint32_t id = (uint32_t)(uintptr_t)context; 349 uint32_t uid = 0; 350 351 for (ids = hpet_ids; *ids != NULL; ids++) { 352 if (acpi_MatchHid(handle, *ids)) 353 break; 354 } 355 if (*ids == NULL) 356 return (AE_OK); 357 if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) || 358 id == uid) 359 *status = acpi_get_device(handle); 360 return (AE_OK); 361 } 362 363 /* 364 * Find an existing IRQ resource that matches the requested IRQ range 365 * and return its RID. If one is not found, use a new RID. 366 */ 367 static int 368 hpet_find_irq_rid(device_t dev, u_long start, u_long end) 369 { 370 rman_res_t irq; 371 int error, rid; 372 373 for (rid = 0;; rid++) { 374 error = bus_get_resource(dev, SYS_RES_IRQ, rid, &irq, NULL); 375 if (error != 0 || (start <= irq && irq <= end)) 376 return (rid); 377 } 378 } 379 380 static int 381 hpet_open(struct cdev *cdev, int oflags, int devtype, struct thread *td) 382 { 383 struct hpet_softc *sc; 384 385 sc = cdev->si_drv1; 386 if (!sc->mmap_allow) 387 return (EPERM); 388 else 389 return (0); 390 } 391 392 static int 393 hpet_mmap(struct cdev *cdev, vm_ooffset_t offset, vm_paddr_t *paddr, 394 int nprot, vm_memattr_t *memattr) 395 { 396 struct hpet_softc *sc; 397 398 sc = cdev->si_drv1; 399 if (offset >= rman_get_size(sc->mem_res)) 400 return (EINVAL); 401 if (!sc->mmap_allow_write && (nprot & PROT_WRITE)) 402 return (EPERM); 403 *paddr = rman_get_start(sc->mem_res) + offset; 404 *memattr = VM_MEMATTR_UNCACHEABLE; 405 406 return (0); 407 } 408 409 /* Discover the HPET via the ACPI table of the same name. */ 410 static void 411 hpet_identify(driver_t *driver, device_t parent) 412 { 413 ACPI_TABLE_HPET *hpet; 414 ACPI_STATUS status; 415 device_t child; 416 int i; 417 418 /* Only one HPET device can be added. */ 419 if (devclass_get_device(hpet_devclass, 0)) 420 return; 421 for (i = 1; ; i++) { 422 /* Search for HPET table. */ 423 status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet); 424 if (ACPI_FAILURE(status)) 425 return; 426 /* Search for HPET device with same ID. */ 427 child = NULL; 428 AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, 429 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence, 430 (void *)&child); 431 /* If found - let it be probed in normal way. */ 432 if (child) { 433 if (bus_get_resource(child, SYS_RES_MEMORY, 0, 434 NULL, NULL) != 0) 435 bus_set_resource(child, SYS_RES_MEMORY, 0, 436 hpet->Address.Address, HPET_MEM_WIDTH); 437 continue; 438 } 439 /* If not - create it from table info. */ 440 child = BUS_ADD_CHILD(parent, 2, "hpet", 0); 441 if (child == NULL) { 442 printf("%s: can't add child\n", __func__); 443 continue; 444 } 445 bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address, 446 HPET_MEM_WIDTH); 447 } 448 } 449 450 static int 451 hpet_probe(device_t dev) 452 { 453 int rv; 454 455 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 456 if (acpi_disabled("hpet") || acpi_hpet_disabled) 457 return (ENXIO); 458 rv = ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids, NULL); 459 if (rv <= 0) 460 device_set_desc(dev, "High Precision Event Timer"); 461 return (rv); 462 } 463 464 static int 465 hpet_attach(device_t dev) 466 { 467 struct hpet_softc *sc; 468 struct hpet_timer *t; 469 struct make_dev_args mda; 470 int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu; 471 int pcpu_master, error; 472 static int maxhpetet = 0; 473 uint32_t val, val2, cvectors, dvectors; 474 uint16_t vendor, rev; 475 476 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 477 478 sc = device_get_softc(dev); 479 sc->dev = dev; 480 sc->handle = acpi_get_handle(dev); 481 482 sc->mem_rid = 0; 483 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 484 RF_ACTIVE); 485 if (sc->mem_res == NULL) 486 return (ENOMEM); 487 488 /* Validate that we can access the whole region. */ 489 if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) { 490 device_printf(dev, "memory region width %jd too small\n", 491 rman_get_size(sc->mem_res)); 492 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 493 return (ENXIO); 494 } 495 496 /* Be sure timer is enabled. */ 497 hpet_enable(sc); 498 499 /* Read basic statistics about the timer. */ 500 val = bus_read_4(sc->mem_res, HPET_PERIOD); 501 if (val == 0) { 502 device_printf(dev, "invalid period\n"); 503 hpet_disable(sc); 504 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 505 return (ENXIO); 506 } 507 508 sc->freq = (1000000000000000LL + val / 2) / val; 509 sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES); 510 vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16; 511 rev = sc->caps & HPET_CAP_REV_ID; 512 num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8); 513 /* 514 * ATI/AMD violates IA-PC HPET (High Precision Event Timers) 515 * Specification and provides an off by one number 516 * of timers/comparators. 517 * Additionally, they use unregistered value in VENDOR_ID field. 518 */ 519 if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0) 520 num_timers--; 521 sc->num_timers = num_timers; 522 if (bootverbose) { 523 device_printf(dev, 524 "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n", 525 vendor, rev, sc->freq, 526 (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "", 527 num_timers, 528 (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : ""); 529 } 530 for (i = 0; i < num_timers; i++) { 531 t = &sc->t[i]; 532 t->sc = sc; 533 t->num = i; 534 t->mode = TIMER_STOPPED; 535 t->intr_rid = -1; 536 t->irq = -1; 537 t->pcpu_cpu = -1; 538 t->pcpu_misrouted = 0; 539 t->pcpu_master = -1; 540 t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i)); 541 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4); 542 if (bootverbose) { 543 device_printf(dev, 544 " t%d: irqs 0x%08x (%d)%s%s%s\n", i, 545 t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9, 546 (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "", 547 (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "", 548 (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : ""); 549 } 550 } 551 if (testenv("debug.acpi.hpet_test")) 552 hpet_test(sc); 553 /* 554 * Don't attach if the timer never increments. Since the spec 555 * requires it to be at least 10 MHz, it has to change in 1 us. 556 */ 557 val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 558 DELAY(1); 559 val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 560 if (val == val2) { 561 device_printf(dev, "HPET never increments, disabling\n"); 562 hpet_disable(sc); 563 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 564 return (ENXIO); 565 } 566 /* Announce first HPET as timecounter. */ 567 if (device_get_unit(dev) == 0) { 568 sc->tc.tc_get_timecount = hpet_get_timecount, 569 sc->tc.tc_counter_mask = ~0u, 570 sc->tc.tc_name = "HPET", 571 sc->tc.tc_quality = 950, 572 sc->tc.tc_frequency = sc->freq; 573 sc->tc.tc_priv = sc; 574 sc->tc.tc_fill_vdso_timehands = hpet_vdso_timehands; 575 #ifdef COMPAT_FREEBSD32 576 sc->tc.tc_fill_vdso_timehands32 = hpet_vdso_timehands32; 577 #endif 578 tc_init(&sc->tc); 579 } 580 /* If not disabled - setup and announce event timers. */ 581 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 582 "clock", &i) == 0 && i == 0) 583 return (0); 584 585 /* Check whether we can and want legacy routing. */ 586 sc->legacy_route = 0; 587 resource_int_value(device_get_name(dev), device_get_unit(dev), 588 "legacy_route", &sc->legacy_route); 589 if ((sc->caps & HPET_CAP_LEG_RT) == 0) 590 sc->legacy_route = 0; 591 if (sc->legacy_route) { 592 sc->t[0].vectors = 0; 593 sc->t[1].vectors = 0; 594 } 595 596 /* Check what IRQs we want use. */ 597 /* By default allow any PCI IRQs. */ 598 sc->allowed_irqs = 0xffff0000; 599 /* 600 * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16 601 * Lower are also not always working for different reasons. 602 * SB800 fixed it, but seems do not implements level triggering 603 * properly, that makes it very unreliable - it freezes after any 604 * interrupt loss. Avoid legacy IRQs for AMD. 605 */ 606 if (vendor == HPET_VENDID_AMD || vendor == HPET_VENDID_AMD2) 607 sc->allowed_irqs = 0x00000000; 608 /* 609 * NVidia MCP5x chipsets have number of unexplained interrupt 610 * problems. For some reason, using HPET interrupts breaks HDA sound. 611 */ 612 if (vendor == HPET_VENDID_NVIDIA && rev <= 0x01) 613 sc->allowed_irqs = 0x00000000; 614 /* 615 * ServerWorks HT1000 reported to have problems with IRQs >= 16. 616 * Lower IRQs are working, but allowed mask is not set correctly. 617 * Legacy_route mode works fine. 618 */ 619 if (vendor == HPET_VENDID_SW && rev <= 0x01) 620 sc->allowed_irqs = 0x00000000; 621 /* 622 * Neither QEMU nor VirtualBox report supported IRQs correctly. 623 * The only way to use HPET there is to specify IRQs manually 624 * and/or use legacy_route. Legacy_route mode works on both. 625 */ 626 if (vm_guest) 627 sc->allowed_irqs = 0x00000000; 628 /* Let user override. */ 629 resource_int_value(device_get_name(dev), device_get_unit(dev), 630 "allowed_irqs", &sc->allowed_irqs); 631 632 /* Get how much per-CPU timers we should try to provide. */ 633 sc->per_cpu = 1; 634 resource_int_value(device_get_name(dev), device_get_unit(dev), 635 "per_cpu", &sc->per_cpu); 636 637 num_msi = 0; 638 sc->useirq = 0; 639 /* Find IRQ vectors for all timers. */ 640 cvectors = sc->allowed_irqs & 0xffff0000; 641 dvectors = sc->allowed_irqs & 0x0000ffff; 642 if (sc->legacy_route) 643 dvectors &= 0x0000fefe; 644 for (i = 0; i < num_timers; i++) { 645 t = &sc->t[i]; 646 if (sc->legacy_route && i < 2) 647 t->irq = (i == 0) ? 0 : 8; 648 #ifdef DEV_APIC 649 else if (t->caps & HPET_TCAP_FSB_INT_DEL) { 650 if ((j = PCIB_ALLOC_MSIX( 651 device_get_parent(device_get_parent(dev)), dev, 652 &t->irq))) { 653 device_printf(dev, 654 "Can't allocate interrupt for t%d: %d\n", 655 i, j); 656 } 657 } 658 #endif 659 else if (dvectors & t->vectors) { 660 t->irq = ffs(dvectors & t->vectors) - 1; 661 dvectors &= ~(1 << t->irq); 662 } 663 if (t->irq >= 0) { 664 t->intr_rid = hpet_find_irq_rid(dev, t->irq, t->irq); 665 t->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 666 &t->intr_rid, t->irq, t->irq, 1, RF_ACTIVE); 667 if (t->intr_res == NULL) { 668 t->irq = -1; 669 device_printf(dev, 670 "Can't map interrupt for t%d.\n", i); 671 } else if (bus_setup_intr(dev, t->intr_res, 672 INTR_TYPE_CLK, hpet_intr_single, NULL, t, 673 &t->intr_handle) != 0) { 674 t->irq = -1; 675 device_printf(dev, 676 "Can't setup interrupt for t%d.\n", i); 677 } else { 678 bus_describe_intr(dev, t->intr_res, 679 t->intr_handle, "t%d", i); 680 num_msi++; 681 } 682 } 683 if (t->irq < 0 && (cvectors & t->vectors) != 0) { 684 cvectors &= t->vectors; 685 sc->useirq |= (1 << i); 686 } 687 } 688 if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0) 689 sc->legacy_route = 0; 690 if (sc->legacy_route) 691 hpet_enable(sc); 692 /* Group timers for per-CPU operation. */ 693 num_percpu_et = min(num_msi / mp_ncpus, sc->per_cpu); 694 num_percpu_t = num_percpu_et * mp_ncpus; 695 pcpu_master = 0; 696 cur_cpu = CPU_FIRST(); 697 for (i = 0; i < num_timers; i++) { 698 t = &sc->t[i]; 699 if (t->irq >= 0 && num_percpu_t > 0) { 700 if (cur_cpu == CPU_FIRST()) 701 pcpu_master = i; 702 t->pcpu_cpu = cur_cpu; 703 t->pcpu_master = pcpu_master; 704 sc->t[pcpu_master]. 705 pcpu_slaves[cur_cpu] = i; 706 bus_bind_intr(dev, t->intr_res, cur_cpu); 707 cur_cpu = CPU_NEXT(cur_cpu); 708 num_percpu_t--; 709 } else if (t->irq >= 0) 710 bus_bind_intr(dev, t->intr_res, CPU_FIRST()); 711 } 712 bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff); 713 sc->irq = -1; 714 /* If at least one timer needs legacy IRQ - set it up. */ 715 if (sc->useirq) { 716 j = i = fls(cvectors) - 1; 717 while (j > 0 && (cvectors & (1 << (j - 1))) != 0) 718 j--; 719 sc->intr_rid = hpet_find_irq_rid(dev, j, i); 720 sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 721 &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE); 722 if (sc->intr_res == NULL) 723 device_printf(dev, "Can't map interrupt.\n"); 724 else if (bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK, 725 hpet_intr, NULL, sc, &sc->intr_handle) != 0) { 726 device_printf(dev, "Can't setup interrupt.\n"); 727 } else { 728 sc->irq = rman_get_start(sc->intr_res); 729 /* Bind IRQ to BSP to avoid live migration. */ 730 bus_bind_intr(dev, sc->intr_res, CPU_FIRST()); 731 } 732 } 733 /* Program and announce event timers. */ 734 for (i = 0; i < num_timers; i++) { 735 t = &sc->t[i]; 736 t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE); 737 t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB); 738 t->caps &= ~(HPET_TCNF_INT_TYPE); 739 t->caps |= HPET_TCNF_32MODE; 740 if (t->irq >= 0 && sc->legacy_route && i < 2) { 741 /* Legacy route doesn't need more configuration. */ 742 } else 743 #ifdef DEV_APIC 744 if ((t->caps & HPET_TCAP_FSB_INT_DEL) && t->irq >= 0) { 745 uint64_t addr; 746 uint32_t data; 747 748 if (PCIB_MAP_MSI( 749 device_get_parent(device_get_parent(dev)), dev, 750 t->irq, &addr, &data) == 0) { 751 bus_write_4(sc->mem_res, 752 HPET_TIMER_FSB_ADDR(i), addr); 753 bus_write_4(sc->mem_res, 754 HPET_TIMER_FSB_VAL(i), data); 755 t->caps |= HPET_TCNF_FSB_EN; 756 } else 757 t->irq = -2; 758 } else 759 #endif 760 if (t->irq >= 0) 761 t->caps |= (t->irq << 9); 762 else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq))) 763 t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE; 764 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps); 765 /* Skip event timers without set up IRQ. */ 766 if (t->irq < 0 && 767 (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0)) 768 continue; 769 /* Announce the reset. */ 770 if (maxhpetet == 0) 771 t->et.et_name = "HPET"; 772 else { 773 sprintf(t->name, "HPET%d", maxhpetet); 774 t->et.et_name = t->name; 775 } 776 t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 777 t->et.et_quality = 450; 778 if (t->pcpu_master >= 0) { 779 t->et.et_flags |= ET_FLAGS_PERCPU; 780 t->et.et_quality += 100; 781 } else if (mp_ncpus >= 8) 782 t->et.et_quality -= 100; 783 if ((t->caps & HPET_TCAP_PER_INT) == 0) 784 t->et.et_quality -= 10; 785 t->et.et_frequency = sc->freq; 786 t->et.et_min_period = 787 ((uint64_t)(HPET_MIN_CYCLES * 2) << 32) / sc->freq; 788 t->et.et_max_period = (0xfffffffeLLU << 32) / sc->freq; 789 t->et.et_start = hpet_start; 790 t->et.et_stop = hpet_stop; 791 t->et.et_priv = &sc->t[i]; 792 if (t->pcpu_master < 0 || t->pcpu_master == i) { 793 et_register(&t->et); 794 maxhpetet++; 795 } 796 } 797 acpi_GetInteger(sc->handle, "_UID", &sc->acpi_uid); 798 799 make_dev_args_init(&mda); 800 mda.mda_devsw = &hpet_cdevsw; 801 mda.mda_uid = UID_ROOT; 802 mda.mda_gid = GID_WHEEL; 803 mda.mda_mode = 0644; 804 mda.mda_si_drv1 = sc; 805 error = make_dev_s(&mda, &sc->pdev, "hpet%d", device_get_unit(dev)); 806 if (error == 0) { 807 sc->mmap_allow = 1; 808 TUNABLE_INT_FETCH("hw.acpi.hpet.mmap_allow", 809 &sc->mmap_allow); 810 sc->mmap_allow_write = 0; 811 TUNABLE_INT_FETCH("hw.acpi.hpet.mmap_allow_write", 812 &sc->mmap_allow_write); 813 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 814 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 815 OID_AUTO, "mmap_allow", 816 CTLFLAG_RW, &sc->mmap_allow, 0, 817 "Allow userland to memory map HPET"); 818 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 819 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 820 OID_AUTO, "mmap_allow_write", 821 CTLFLAG_RW, &sc->mmap_allow_write, 0, 822 "Allow userland write to the HPET register space"); 823 } else { 824 device_printf(dev, "could not create /dev/hpet%d, error %d\n", 825 device_get_unit(dev), error); 826 } 827 828 return (0); 829 } 830 831 static int 832 hpet_detach(device_t dev) 833 { 834 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 835 836 /* XXX Without a tc_remove() function, we can't detach. */ 837 return (EBUSY); 838 } 839 840 static int 841 hpet_suspend(device_t dev) 842 { 843 // struct hpet_softc *sc; 844 845 /* 846 * Disable the timer during suspend. The timer will not lose 847 * its state in S1 or S2, but we are required to disable 848 * it. 849 */ 850 // sc = device_get_softc(dev); 851 // hpet_disable(sc); 852 853 return (0); 854 } 855 856 static int 857 hpet_resume(device_t dev) 858 { 859 struct hpet_softc *sc; 860 struct hpet_timer *t; 861 int i; 862 863 /* Re-enable the timer after a resume to keep the clock advancing. */ 864 sc = device_get_softc(dev); 865 hpet_enable(sc); 866 /* Restart event timers that were running on suspend. */ 867 for (i = 0; i < sc->num_timers; i++) { 868 t = &sc->t[i]; 869 #ifdef DEV_APIC 870 if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) { 871 uint64_t addr; 872 uint32_t data; 873 874 if (PCIB_MAP_MSI( 875 device_get_parent(device_get_parent(dev)), dev, 876 t->irq, &addr, &data) == 0) { 877 bus_write_4(sc->mem_res, 878 HPET_TIMER_FSB_ADDR(i), addr); 879 bus_write_4(sc->mem_res, 880 HPET_TIMER_FSB_VAL(i), data); 881 } 882 } 883 #endif 884 if (t->mode == TIMER_STOPPED) 885 continue; 886 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 887 if (t->mode == TIMER_PERIODIC && 888 (t->caps & HPET_TCAP_PER_INT) != 0) { 889 t->caps |= HPET_TCNF_TYPE; 890 t->next += t->div; 891 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 892 t->caps | HPET_TCNF_VAL_SET); 893 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 894 t->next); 895 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 896 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 897 t->div); 898 } else { 899 t->next += sc->freq / 1024; 900 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 901 t->next); 902 } 903 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 904 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 905 } 906 return (0); 907 } 908 909 /* Print some basic latency/rate information to assist in debugging. */ 910 static void 911 hpet_test(struct hpet_softc *sc) 912 { 913 int i; 914 uint32_t u1, u2; 915 struct bintime b0, b1, b2; 916 struct timespec ts; 917 918 binuptime(&b0); 919 binuptime(&b0); 920 binuptime(&b1); 921 u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 922 for (i = 1; i < 1000; i++) 923 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 924 binuptime(&b2); 925 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 926 927 bintime_sub(&b2, &b1); 928 bintime_sub(&b1, &b0); 929 bintime_sub(&b2, &b1); 930 bintime2timespec(&b2, &ts); 931 932 device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n", 933 (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1); 934 935 device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000); 936 } 937 938 #ifdef DEV_APIC 939 static int 940 hpet_remap_intr(device_t dev, device_t child, u_int irq) 941 { 942 struct hpet_softc *sc = device_get_softc(dev); 943 struct hpet_timer *t; 944 uint64_t addr; 945 uint32_t data; 946 int error, i; 947 948 for (i = 0; i < sc->num_timers; i++) { 949 t = &sc->t[i]; 950 if (t->irq != irq) 951 continue; 952 error = PCIB_MAP_MSI( 953 device_get_parent(device_get_parent(dev)), dev, 954 irq, &addr, &data); 955 if (error) 956 return (error); 957 hpet_disable(sc); /* Stop timer to avoid interrupt loss. */ 958 bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr); 959 bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data); 960 hpet_enable(sc); 961 return (0); 962 } 963 return (ENOENT); 964 } 965 #endif 966 967 static device_method_t hpet_methods[] = { 968 /* Device interface */ 969 DEVMETHOD(device_identify, hpet_identify), 970 DEVMETHOD(device_probe, hpet_probe), 971 DEVMETHOD(device_attach, hpet_attach), 972 DEVMETHOD(device_detach, hpet_detach), 973 DEVMETHOD(device_suspend, hpet_suspend), 974 DEVMETHOD(device_resume, hpet_resume), 975 976 #ifdef DEV_APIC 977 DEVMETHOD(bus_remap_intr, hpet_remap_intr), 978 #endif 979 980 DEVMETHOD_END 981 }; 982 983 static driver_t hpet_driver = { 984 "hpet", 985 hpet_methods, 986 sizeof(struct hpet_softc), 987 }; 988 989 DRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0); 990 MODULE_DEPEND(hpet, acpi, 1, 1, 1); 991