1 /*- 2 * Core definitions and data structures shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2001 Justin T. Gibbs. 5 * Copyright (c) 2000-2001 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.h#85 $ 41 * 42 * $FreeBSD$ 43 */ 44 45 #ifndef _AIC7XXX_H_ 46 #define _AIC7XXX_H_ 47 48 /* Register Definitions */ 49 #include "aic7xxx_reg.h" 50 51 /************************* Forward Declarations *******************************/ 52 struct ahc_platform_data; 53 struct scb_platform_data; 54 struct seeprom_descriptor; 55 56 /****************************** Useful Macros *********************************/ 57 #ifndef MAX 58 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 59 #endif 60 61 #ifndef MIN 62 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 63 #endif 64 65 #ifndef TRUE 66 #define TRUE 1 67 #endif 68 #ifndef FALSE 69 #define FALSE 0 70 #endif 71 72 #define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 73 74 #define ALL_CHANNELS '\0' 75 #define ALL_TARGETS_MASK 0xFFFF 76 #define INITIATOR_WILDCARD (~0) 77 78 #define SCSIID_TARGET(ahc, scsiid) \ 79 (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \ 80 >> TID_SHIFT) 81 #define SCSIID_OUR_ID(scsiid) \ 82 ((scsiid) & OID) 83 #define SCSIID_CHANNEL(ahc, scsiid) \ 84 ((((ahc)->features & AHC_TWIN) != 0) \ 85 ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \ 86 : 'A') 87 #define SCB_IS_SCSIBUS_B(ahc, scb) \ 88 (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B') 89 #define SCB_GET_OUR_ID(scb) \ 90 SCSIID_OUR_ID((scb)->hscb->scsiid) 91 #define SCB_GET_TARGET(ahc, scb) \ 92 SCSIID_TARGET((ahc), (scb)->hscb->scsiid) 93 #define SCB_GET_CHANNEL(ahc, scb) \ 94 SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) 95 #define SCB_GET_LUN(scb) \ 96 ((scb)->hscb->lun & LID) 97 #define SCB_GET_TARGET_OFFSET(ahc, scb) \ 98 (SCB_GET_TARGET(ahc, scb) + (SCB_IS_SCSIBUS_B(ahc, scb) ? 8 : 0)) 99 #define SCB_GET_TARGET_MASK(ahc, scb) \ 100 (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb))) 101 #ifdef AHC_DEBUG 102 #define SCB_IS_SILENT(scb) \ 103 ((ahc_debug & AHC_SHOW_MASKED_ERRORS) == 0 \ 104 && (((scb)->flags & SCB_SILENT) != 0)) 105 #else 106 #define SCB_IS_SILENT(scb) \ 107 (((scb)->flags & SCB_SILENT) != 0) 108 #endif 109 #define TCL_TARGET_OFFSET(tcl) \ 110 ((((tcl) >> 4) & TID) >> 4) 111 #define TCL_LUN(tcl) \ 112 (tcl & (AHC_NUM_LUNS - 1)) 113 #define BUILD_TCL(scsiid, lun) \ 114 ((lun) | (((scsiid) & TID) << 4)) 115 116 #ifndef AHC_TARGET_MODE 117 #undef AHC_TMODE_ENABLE 118 #define AHC_TMODE_ENABLE 0 119 #endif 120 121 /**************************** Driver Constants ********************************/ 122 /* 123 * The maximum number of supported targets. 124 */ 125 #define AHC_NUM_TARGETS 16 126 127 /* 128 * The maximum number of supported luns. 129 * The identify message only supports 64 luns in SPI3. 130 * You can have 2^64 luns when information unit transfers are enabled, 131 * but it is doubtful this driver will ever support IUTs. 132 */ 133 #define AHC_NUM_LUNS 64 134 135 /* 136 * The maximum transfer per S/G segment. 137 */ 138 #define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 139 140 /* 141 * The maximum amount of SCB storage in hardware on a controller. 142 * This value represents an upper bound. Controllers vary in the number 143 * they actually support. 144 */ 145 #define AHC_SCB_MAX 255 146 147 /* 148 * The maximum number of concurrent transactions supported per driver instance. 149 * Sequencer Control Blocks (SCBs) store per-transaction information. Although 150 * the space for SCBs on the host adapter varies by model, the driver will 151 * page the SCBs between host and controller memory as needed. We are limited 152 * to 253 because: 153 * 1) The 8bit nature of the RISC engine holds us to an 8bit value. 154 * 2) We reserve one value, 255, to represent the invalid element. 155 * 3) Our input queue scheme requires one SCB to always be reserved 156 * in advance of queuing any SCBs. This takes us down to 254. 157 * 4) To handle our output queue correctly on machines that only 158 * support 32bit stores, we must clear the array 4 bytes at a 159 * time. To avoid colliding with a DMA write from the sequencer, 160 * we must be sure that 4 slots are empty when we write to clear 161 * the queue. This reduces us to 253 SCBs: 1 that just completed 162 * and the known three additional empty slots in the queue that 163 * precede it. 164 */ 165 #define AHC_MAX_QUEUE 253 166 167 /* 168 * The maximum amount of SCB storage we allocate in host memory. This 169 * number should reflect the 1 additional SCB we require to handle our 170 * qinfifo mechanism. 171 */ 172 #define AHC_SCB_MAX_ALLOC (AHC_MAX_QUEUE+1) 173 174 /* 175 * Ring Buffer of incoming target commands. 176 * We allocate 256 to simplify the logic in the sequencer 177 * by using the natural wrap point of an 8bit counter. 178 */ 179 #define AHC_TMODE_CMDS 256 180 181 /* Reset line assertion time in us */ 182 #define AHC_BUSRESET_DELAY 25 183 184 /* Phase change constants used in target mode. */ 185 #define AHC_BUSSETTLE_DELAY 400 186 #define AHC_DATARELEASE_DELAY 400 187 188 /******************* Chip Characteristics/Operating Settings *****************/ 189 /* 190 * Chip Type 191 * The chip order is from least sophisticated to most sophisticated. 192 */ 193 typedef enum { 194 AHC_NONE = 0x0000, 195 AHC_CHIPID_MASK = 0x00FF, 196 AHC_AIC7770 = 0x0001, 197 AHC_AIC7850 = 0x0002, 198 AHC_AIC7855 = 0x0003, 199 AHC_AIC7859 = 0x0004, 200 AHC_AIC7860 = 0x0005, 201 AHC_AIC7870 = 0x0006, 202 AHC_AIC7880 = 0x0007, 203 AHC_AIC7895 = 0x0008, 204 AHC_AIC7895C = 0x0009, 205 AHC_AIC7890 = 0x000a, 206 AHC_AIC7896 = 0x000b, 207 AHC_AIC7892 = 0x000c, 208 AHC_AIC7899 = 0x000d, 209 AHC_VL = 0x0100, /* Bus type VL */ 210 AHC_EISA = 0x0200, /* Bus type EISA/ISA */ 211 AHC_PCI = 0x0400, /* Bus type PCI */ 212 AHC_BUS_MASK = 0x0F00 213 } ahc_chip; 214 215 /* 216 * Features available in each chip type. 217 */ 218 typedef enum { 219 AHC_FENONE = 0x00000, 220 AHC_ULTRA = 0x00001, /* Supports 20MHz Transfers */ 221 AHC_ULTRA2 = 0x00002, /* Supports 40MHz Transfers */ 222 AHC_WIDE = 0x00004, /* Wide Channel */ 223 AHC_TWIN = 0x00008, /* Twin Channel */ 224 AHC_MORE_SRAM = 0x00010, /* 80 bytes instead of 64 */ 225 AHC_CMD_CHAN = 0x00020, /* Has a Command DMA Channel */ 226 AHC_QUEUE_REGS = 0x00040, /* Has Queue management registers */ 227 AHC_SG_PRELOAD = 0x00080, /* Can perform auto-SG preload */ 228 AHC_SPIOCAP = 0x00100, /* Has a Serial Port I/O Cap Register */ 229 AHC_MULTI_TID = 0x00200, /* Has bitmask of TIDs for select-in */ 230 AHC_HS_MAILBOX = 0x00400, /* Has HS_MAILBOX register */ 231 AHC_DT = 0x00800, /* Double Transition transfers */ 232 AHC_NEW_TERMCTL = 0x01000, /* Newer termination scheme */ 233 AHC_MULTI_FUNC = 0x02000, /* Multi-Function Twin Channel Device */ 234 AHC_LARGE_SCBS = 0x04000, /* 64byte SCBs */ 235 AHC_AUTORATE = 0x08000, /* Automatic update of SCSIRATE/OFFSET*/ 236 AHC_AUTOPAUSE = 0x10000, /* Automatic pause on register access */ 237 AHC_TARGETMODE = 0x20000, /* Has tested target mode support */ 238 AHC_MULTIROLE = 0x40000, /* Space for two roles at a time */ 239 AHC_REMOVABLE = 0x80000, /* Hot-Swap supported */ 240 AHC_AIC7770_FE = AHC_FENONE, 241 /* 242 * The real 7850 does not support Ultra modes, but there are 243 * several cards that use the generic 7850 PCI ID even though 244 * they are using an Ultra capable chip (7859/7860). We start 245 * out with the AHC_ULTRA feature set and then check the DEVSTATUS 246 * register to determine if the capability is really present. 247 */ 248 AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE|AHC_TARGETMODE|AHC_ULTRA, 249 AHC_AIC7860_FE = AHC_AIC7850_FE, 250 AHC_AIC7870_FE = AHC_TARGETMODE|AHC_AUTOPAUSE, 251 AHC_AIC7880_FE = AHC_AIC7870_FE|AHC_ULTRA, 252 /* 253 * Although we have space for both the initiator and 254 * target roles on ULTRA2 chips, we currently disable 255 * the initiator role to allow multi-scsi-id target mode 256 * configurations. We can only respond on the same SCSI 257 * ID as our initiator role if we allow initiator operation. 258 * At some point, we should add a configuration knob to 259 * allow both roles to be loaded. 260 */ 261 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2 262 |AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID 263 |AHC_HS_MAILBOX|AHC_NEW_TERMCTL|AHC_LARGE_SCBS 264 |AHC_TARGETMODE, 265 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE, 266 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE 267 |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS, 268 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID, 269 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC, 270 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC 271 } ahc_feature; 272 273 /* 274 * Bugs in the silicon that we work around in software. 275 */ 276 typedef enum { 277 AHC_BUGNONE = 0x00, 278 /* 279 * On all chips prior to the U2 product line, 280 * the WIDEODD S/G segment feature does not 281 * work during scsi->HostBus transfers. 282 */ 283 AHC_TMODE_WIDEODD_BUG = 0x01, 284 /* 285 * On the aic7890/91 Rev 0 chips, the autoflush 286 * feature does not work. A manual flush of 287 * the DMA FIFO is required. 288 */ 289 AHC_AUTOFLUSH_BUG = 0x02, 290 /* 291 * On many chips, cacheline streaming does not work. 292 */ 293 AHC_CACHETHEN_BUG = 0x04, 294 /* 295 * On the aic7896/97 chips, cacheline 296 * streaming must be enabled. 297 */ 298 AHC_CACHETHEN_DIS_BUG = 0x08, 299 /* 300 * PCI 2.1 Retry failure on non-empty data fifo. 301 */ 302 AHC_PCI_2_1_RETRY_BUG = 0x10, 303 /* 304 * Controller does not handle cacheline residuals 305 * properly on S/G segments if PCI MWI instructions 306 * are allowed. 307 */ 308 AHC_PCI_MWI_BUG = 0x20, 309 /* 310 * An SCB upload using the SCB channel's 311 * auto array entry copy feature may 312 * corrupt data. This appears to only 313 * occur on 66MHz systems. 314 */ 315 AHC_SCBCHAN_UPLOAD_BUG = 0x40 316 } ahc_bug; 317 318 /* 319 * Configuration specific settings. 320 * The driver determines these settings by probing the 321 * chip/controller's configuration. 322 */ 323 typedef enum { 324 AHC_FNONE = 0x000, 325 AHC_PRIMARY_CHANNEL = 0x003, /* 326 * The channel that should 327 * be probed first. 328 */ 329 AHC_USEDEFAULTS = 0x004, /* 330 * For cards without an seeprom 331 * or a BIOS to initialize the chip's 332 * SRAM, we use the default target 333 * settings. 334 */ 335 AHC_SEQUENCER_DEBUG = 0x008, 336 AHC_SHARED_SRAM = 0x010, 337 AHC_LARGE_SEEPROM = 0x020, /* Uses C56_66 not C46 */ 338 AHC_RESET_BUS_A = 0x040, 339 AHC_RESET_BUS_B = 0x080, 340 AHC_EXTENDED_TRANS_A = 0x100, 341 AHC_EXTENDED_TRANS_B = 0x200, 342 AHC_TERM_ENB_A = 0x400, 343 AHC_TERM_ENB_B = 0x800, 344 AHC_INITIATORROLE = 0x1000, /* 345 * Allow initiator operations on 346 * this controller. 347 */ 348 AHC_TARGETROLE = 0x2000, /* 349 * Allow target operations on this 350 * controller. 351 */ 352 AHC_NEWEEPROM_FMT = 0x4000, 353 AHC_RESOURCE_SHORTAGE = 0x8000, 354 AHC_TQINFIFO_BLOCKED = 0x10000, /* Blocked waiting for ATIOs */ 355 AHC_INT50_SPEEDFLEX = 0x20000, /* 356 * Internal 50pin connector 357 * sits behind an aic3860 358 */ 359 AHC_SCB_BTT = 0x40000, /* 360 * The busy targets table is 361 * stored in SCB space rather 362 * than SRAM. 363 */ 364 AHC_BIOS_ENABLED = 0x80000, 365 AHC_ALL_INTERRUPTS = 0x100000, 366 AHC_PAGESCBS = 0x400000, /* Enable SCB paging */ 367 AHC_EDGE_INTERRUPT = 0x800000, /* Device uses edge triggered ints */ 368 AHC_39BIT_ADDRESSING = 0x1000000, /* Use 39 bit addressing scheme. */ 369 AHC_LSCBS_ENABLED = 0x2000000, /* 64Byte SCBs enabled */ 370 AHC_SCB_CONFIG_USED = 0x4000000, /* No SEEPROM but SCB2 had info. */ 371 AHC_NO_BIOS_INIT = 0x8000000, /* No BIOS left over settings. */ 372 AHC_DISABLE_PCI_PERR = 0x10000000, 373 AHC_HAS_TERM_LOGIC = 0x20000000, 374 AHC_SHUTDOWN_RECOVERY = 0x40000000 /* Terminate recovery thread. */ 375 } ahc_flag; 376 377 /************************* Hardware SCB Definition ***************************/ 378 379 /* 380 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 381 * consists of a "hardware SCB" mirroring the fields available on the card 382 * and additional information the kernel stores for each transaction. 383 * 384 * To minimize space utilization, a portion of the hardware scb stores 385 * different data during different portions of a SCSI transaction. 386 * As initialized by the host driver for the initiator role, this area 387 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 388 * the cdb has been presented to the target, this area serves to store 389 * residual transfer information and the SCSI status byte. 390 * For the target role, the contents of this area do not change, but 391 * still serve a different purpose than for the initiator role. See 392 * struct target_data for details. 393 */ 394 395 /* 396 * Status information embedded in the shared poriton of 397 * an SCB after passing the cdb to the target. The kernel 398 * driver will only read this data for transactions that 399 * complete abnormally (non-zero status byte). 400 */ 401 struct status_pkt { 402 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 403 uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 404 uint8_t scsi_status; /* Standard SCSI status byte */ 405 }; 406 407 /* 408 * Target mode version of the shared data SCB segment. 409 */ 410 struct target_data { 411 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 412 uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 413 uint8_t scsi_status; /* SCSI status to give to initiator */ 414 uint8_t target_phases; /* Bitmap of phases to execute */ 415 uint8_t data_phase; /* Data-In or Data-Out */ 416 uint8_t initiator_tag; /* Initiator's transaction tag */ 417 }; 418 419 #define MAX_CDB_LEN 16 420 struct hardware_scb { 421 /*0*/ union { 422 /* 423 * If the cdb is 12 bytes or less, we embed it directly 424 * in the SCB. For longer cdbs, we embed the address 425 * of the cdb payload as seen by the chip and a DMA 426 * is used to pull it in. 427 */ 428 uint8_t cdb[12]; 429 uint32_t cdb_ptr; 430 struct status_pkt status; 431 struct target_data tdata; 432 } shared_data; 433 /* 434 * A word about residuals. 435 * The scb is presented to the sequencer with the dataptr and datacnt 436 * fields initialized to the contents of the first S/G element to 437 * transfer. The sgptr field is initialized to the bus address for 438 * the S/G element that follows the first in the in core S/G array 439 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 440 * S/G entry for this transfer (single S/G element transfer with the 441 * first elements address and length preloaded in the dataptr/datacnt 442 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 443 * The SG_FULL_RESID flag ensures that the residual will be correctly 444 * noted even if no data transfers occur. Once the data phase is entered, 445 * the residual sgptr and datacnt are loaded from the sgptr and the 446 * datacnt fields. After each S/G element's dataptr and length are 447 * loaded into the hardware, the residual sgptr is advanced. After 448 * each S/G element is expired, its datacnt field is checked to see 449 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 450 * residual sg ptr and the transfer is considered complete. If the 451 * sequencer determines that there is a residual in the transfer, it 452 * will set the SG_RESID_VALID flag in sgptr and dma the scb back into 453 * host memory. To sumarize: 454 * 455 * Sequencer: 456 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 457 * or residual_sgptr does not have SG_LIST_NULL set. 458 * 459 * o We are transferring the last segment if residual_datacnt has 460 * the SG_LAST_SEG flag set. 461 * 462 * Host: 463 * o A residual has occurred if a completed scb has the 464 * SG_RESID_VALID flag set. 465 * 466 * o residual_sgptr and sgptr refer to the "next" sg entry 467 * and so may point beyond the last valid sg entry for the 468 * transfer. 469 */ 470 /*12*/ uint32_t dataptr; 471 /*16*/ uint32_t datacnt; /* 472 * Byte 3 (numbered from 0) of 473 * the datacnt is really the 474 * 4th byte in that data address. 475 */ 476 /*20*/ uint32_t sgptr; 477 #define SG_PTR_MASK 0xFFFFFFF8 478 /*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */ 479 /*25*/ uint8_t scsiid; /* what to load in the SCSIID register */ 480 /*26*/ uint8_t lun; 481 /*27*/ uint8_t tag; /* 482 * Index into our kernel SCB array. 483 * Also used as the tag for tagged I/O 484 */ 485 /*28*/ uint8_t cdb_len; 486 /*29*/ uint8_t scsirate; /* Value for SCSIRATE register */ 487 /*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */ 488 /*31*/ uint8_t next; /* 489 * Used for threading SCBs in the 490 * "Waiting for Selection" and 491 * "Disconnected SCB" lists down 492 * in the sequencer. 493 */ 494 /*32*/ uint8_t cdb32[32]; /* 495 * CDB storage for cdbs of size 496 * 13->32. We store them here 497 * because hardware scbs are 498 * allocated from DMA safe 499 * memory so we are guaranteed 500 * the controller can access 501 * this data. 502 */ 503 }; 504 505 /************************ Kernel SCB Definitions ******************************/ 506 /* 507 * Some fields of the SCB are OS dependent. Here we collect the 508 * definitions for elements that all OS platforms need to include 509 * in there SCB definition. 510 */ 511 512 /* 513 * Definition of a scatter/gather element as transferred to the controller. 514 * The aic7xxx chips only support a 24bit length. We use the top byte of 515 * the length to store additional address bits and a flag to indicate 516 * that a given segment terminates the transfer. This gives us an 517 * addressable range of 512GB on machines with 64bit PCI or with chips 518 * that can support dual address cycles on 32bit PCI busses. 519 */ 520 struct ahc_dma_seg { 521 uint32_t addr; 522 uint32_t len; 523 #define AHC_DMA_LAST_SEG 0x80000000 524 #define AHC_SG_HIGH_ADDR_MASK 0x7F000000 525 #define AHC_SG_LEN_MASK 0x00FFFFFF 526 }; 527 528 struct sg_map_node { 529 bus_dmamap_t sg_dmamap; 530 bus_addr_t sg_physaddr; 531 struct ahc_dma_seg* sg_vaddr; 532 SLIST_ENTRY(sg_map_node) links; 533 }; 534 535 /* 536 * The current state of this SCB. 537 */ 538 typedef enum { 539 SCB_FLAG_NONE = 0x0000, 540 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 541 * Another device was active 542 * during the first timeout for 543 * this SCB so we gave ourselves 544 * an additional timeout period 545 * in case it was hogging the 546 * bus. 547 */ 548 SCB_DEVICE_RESET = 0x0004, 549 SCB_SENSE = 0x0008, 550 SCB_CDB32_PTR = 0x0010, 551 SCB_RECOVERY_SCB = 0x0020, 552 SCB_AUTO_NEGOTIATE = 0x0040,/* Negotiate to achieve goal. */ 553 SCB_NEGOTIATE = 0x0080,/* Negotiation forced for command. */ 554 SCB_ABORT = 0x0100, 555 SCB_UNTAGGEDQ = 0x0200, 556 SCB_ACTIVE = 0x0400, 557 SCB_TARGET_IMMEDIATE = 0x0800, 558 SCB_TRANSMISSION_ERROR = 0x1000,/* 559 * We detected a parity or CRC 560 * error that has effected the 561 * payload of the command. This 562 * flag is checked when normal 563 * status is returned to catch 564 * the case of a target not 565 * responding to our attempt 566 * to report the error. 567 */ 568 SCB_TARGET_SCB = 0x2000, 569 SCB_SILENT = 0x4000,/* 570 * Be quiet about transmission type 571 * errors. They are expected and we 572 * don't want to upset the user. This 573 * flag is typically used during DV. 574 */ 575 SCB_TIMEDOUT = 0x8000 /* 576 * SCB has timed out and is on the 577 * timedout list. 578 */ 579 } scb_flag; 580 581 struct scb { 582 struct hardware_scb *hscb; 583 union { 584 SLIST_ENTRY(scb) sle; 585 TAILQ_ENTRY(scb) tqe; 586 } links; 587 LIST_ENTRY(scb) pending_links; 588 LIST_ENTRY(scb) timedout_links; 589 aic_io_ctx_t io_ctx; 590 struct ahc_softc *ahc_softc; 591 scb_flag flags; 592 #ifndef __linux__ 593 bus_dmamap_t dmamap; 594 #endif 595 struct scb_platform_data *platform_data; 596 struct sg_map_node *sg_map; 597 struct ahc_dma_seg *sg_list; 598 bus_addr_t sg_list_phys; 599 u_int sg_count;/* How full ahc_dma_seg is */ 600 aic_timer_t io_timer; 601 }; 602 603 struct scb_data { 604 SLIST_HEAD(, scb) free_scbs; /* 605 * Pool of SCBs ready to be assigned 606 * commands to execute. 607 */ 608 struct scb *scbindex[256]; /* 609 * Mapping from tag to SCB. 610 * As tag identifiers are an 611 * 8bit value, we provide space 612 * for all possible tag values. 613 * Any lookups to entries at or 614 * above AHC_SCB_MAX_ALLOC will 615 * always fail. 616 */ 617 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 618 struct scb *scbarray; /* Array of kernel SCBs */ 619 struct scsi_sense_data *sense; /* Per SCB sense data */ 620 621 u_int recovery_scbs; /* Transactions currently in recovery */ 622 623 /* 624 * "Bus" addresses of our data structures. 625 */ 626 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 627 bus_dmamap_t hscb_dmamap; 628 bus_addr_t hscb_busaddr; 629 bus_dma_tag_t sense_dmat; 630 bus_dmamap_t sense_dmamap; 631 bus_addr_t sense_busaddr; 632 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 633 SLIST_HEAD(, sg_map_node) sg_maps; 634 uint8_t numscbs; 635 uint8_t maxhscbs; /* Number of SCBs on the card */ 636 uint8_t init_level; /* 637 * How far we've initialized 638 * this structure. 639 */ 640 }; 641 642 /************************ Target Mode Definitions *****************************/ 643 644 /* 645 * Connection desciptor for select-in requests in target mode. 646 */ 647 struct target_cmd { 648 uint8_t scsiid; /* Our ID and the initiator's ID */ 649 uint8_t identify; /* Identify message */ 650 uint8_t bytes[22]; /* 651 * Bytes contains any additional message 652 * bytes terminated by 0xFF. The remainder 653 * is the cdb to execute. 654 */ 655 uint8_t cmd_valid; /* 656 * When a command is complete, the firmware 657 * will set cmd_valid to all bits set. 658 * After the host has seen the command, 659 * the bits are cleared. This allows us 660 * to just peek at host memory to determine 661 * if more work is complete. cmd_valid is on 662 * an 8 byte boundary to simplify setting 663 * it on aic7880 hardware which only has 664 * limited direct access to the DMA FIFO. 665 */ 666 uint8_t pad[7]; 667 }; 668 669 /* 670 * Number of events we can buffer up if we run out 671 * of immediate notify ccbs. 672 */ 673 #define AHC_TMODE_EVENT_BUFFER_SIZE 8 674 struct ahc_tmode_event { 675 uint8_t initiator_id; 676 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 677 #define EVENT_TYPE_BUS_RESET 0xFF 678 uint8_t event_arg; 679 }; 680 681 /* 682 * Per enabled lun target mode state. 683 * As this state is directly influenced by the host OS'es target mode 684 * environment, we let the OS module define it. Forward declare the 685 * structure here so we can store arrays of them, etc. in OS neutral 686 * data structures. 687 */ 688 #ifdef AHC_TARGET_MODE 689 struct ahc_tmode_lstate { 690 struct cam_path *path; 691 struct ccb_hdr_slist accept_tios; 692 struct ccb_hdr_slist immed_notifies; 693 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE]; 694 uint8_t event_r_idx; 695 uint8_t event_w_idx; 696 }; 697 #else 698 struct ahc_tmode_lstate; 699 #endif 700 701 /******************** Transfer Negotiation Datastructures *********************/ 702 #define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 703 #define AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 704 #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 705 #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 706 707 #define AHC_WIDTH_UNKNOWN 0xFF 708 #define AHC_PERIOD_UNKNOWN 0xFF 709 #define AHC_OFFSET_UNKNOWN 0xFF 710 #define AHC_PPR_OPTS_UNKNOWN 0xFF 711 712 /* 713 * Transfer Negotiation Information. 714 */ 715 struct ahc_transinfo { 716 uint8_t protocol_version; /* SCSI Revision level */ 717 uint8_t transport_version; /* SPI Revision level */ 718 uint8_t width; /* Bus width */ 719 uint8_t period; /* Sync rate factor */ 720 uint8_t offset; /* Sync offset */ 721 uint8_t ppr_options; /* Parallel Protocol Request options */ 722 }; 723 724 /* 725 * Per-initiator current, goal and user transfer negotiation information. */ 726 struct ahc_initiator_tinfo { 727 uint8_t scsirate; /* Computed value for SCSIRATE reg */ 728 struct ahc_transinfo curr; 729 struct ahc_transinfo goal; 730 struct ahc_transinfo user; 731 }; 732 733 /* 734 * Per enabled target ID state. 735 * Pointers to lun target state as well as sync/wide negotiation information 736 * for each initiator<->target mapping. For the initiator role we pretend 737 * that we are the target and the targets are the initiators since the 738 * negotiation is the same regardless of role. 739 */ 740 struct ahc_tmode_tstate { 741 struct ahc_tmode_lstate* enabled_luns[AHC_NUM_LUNS]; 742 struct ahc_initiator_tinfo transinfo[AHC_NUM_TARGETS]; 743 744 /* 745 * Per initiator state bitmasks. 746 */ 747 uint16_t auto_negotiate;/* Auto Negotiation Required */ 748 uint16_t ultraenb; /* Using ultra sync rate */ 749 uint16_t discenable; /* Disconnection allowed */ 750 uint16_t tagenable; /* Tagged Queuing allowed */ 751 }; 752 753 /* 754 * Data structure for our table of allowed synchronous transfer rates. 755 */ 756 struct ahc_syncrate { 757 u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */ 758 u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */ 759 #define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */ 760 #define ST_SXFR 0x010 /* Rate Single Transition Only */ 761 #define DT_SXFR 0x040 /* Rate Double Transition Only */ 762 uint8_t period; /* Period to send to SCSI target */ 763 char *rate; 764 }; 765 766 /* Safe and valid period for async negotiations. */ 767 #define AHC_ASYNC_XFER_PERIOD 0x45 768 #define AHC_ULTRA2_XFER_PERIOD 0x0a 769 770 /* 771 * Indexes into our table of synchronous transfer rates. 772 */ 773 #define AHC_SYNCRATE_DT 0 774 #define AHC_SYNCRATE_ULTRA2 1 775 #define AHC_SYNCRATE_ULTRA 3 776 #define AHC_SYNCRATE_FAST 6 777 #define AHC_SYNCRATE_MAX AHC_SYNCRATE_DT 778 #define AHC_SYNCRATE_MIN 13 779 780 /***************************** Lookup Tables **********************************/ 781 /* 782 * Phase -> name and message out response 783 * to parity errors in each phase table. 784 */ 785 struct ahc_phase_table_entry { 786 uint8_t phase; 787 uint8_t mesg_out; /* Message response to parity errors */ 788 char *phasemsg; 789 }; 790 791 /************************** Serial EEPROM Format ******************************/ 792 793 struct seeprom_config { 794 /* 795 * Per SCSI ID Configuration Flags 796 */ 797 uint16_t device_flags[16]; /* words 0-15 */ 798 #define CFXFER 0x0007 /* synchronous transfer rate */ 799 #define CFSYNCH 0x0008 /* enable synchronous transfer */ 800 #define CFDISC 0x0010 /* enable disconnection */ 801 #define CFWIDEB 0x0020 /* wide bus device */ 802 #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 803 #define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */ 804 #define CFSTART 0x0100 /* send start unit SCSI command */ 805 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 806 #define CFRNFOUND 0x0400 /* report even if not found */ 807 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 808 #define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */ 809 #define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */ 810 811 /* 812 * BIOS Control Bits 813 */ 814 uint16_t bios_control; /* word 16 */ 815 #define CFSUPREM 0x0001 /* support all removeable drives */ 816 #define CFSUPREMB 0x0002 /* support removeable boot drives */ 817 #define CFBIOSEN 0x0004 /* BIOS enabled */ 818 #define CFBIOS_BUSSCAN 0x0008 /* Have the BIOS Scan the Bus */ 819 #define CFSM2DRV 0x0010 /* support more than two drives */ 820 #define CFSTPWLEVEL 0x0010 /* Termination level control */ 821 #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 822 #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 823 #define CFTERM_MENU 0x0040 /* BIOS displays termination menu */ 824 #define CFEXTEND 0x0080 /* extended translation enabled */ 825 #define CFSCAMEN 0x0100 /* SCAM enable */ 826 #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 827 #define CFMSG_VERBOSE 0x0000 828 #define CFMSG_SILENT 0x0200 829 #define CFMSG_DIAG 0x0400 830 #define CFBOOTCD 0x0800 /* Support Bootable CD-ROM */ 831 /* UNUSED 0xff00 */ 832 833 /* 834 * Host Adapter Control Bits 835 */ 836 uint16_t adapter_control; /* word 17 */ 837 #define CFAUTOTERM 0x0001 /* Perform Auto termination */ 838 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 839 #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 840 #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 841 #define CFSTERM 0x0004 /* SCSI low byte termination */ 842 #define CFWSTERM 0x0008 /* SCSI high byte termination */ 843 #define CFSPARITY 0x0010 /* SCSI parity */ 844 #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 845 #define CFMULTILUN 0x0020 846 #define CFRESETB 0x0040 /* reset SCSI bus at boot */ 847 #define CFCLUSTERENB 0x0080 /* Cluster Enable */ 848 #define CFBOOTCHAN 0x0300 /* probe this channel first */ 849 #define CFBOOTCHANSHIFT 8 850 #define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/ 851 #define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */ 852 #define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */ 853 #define CFENABLEDV 0x4000 /* Perform Domain Validation*/ 854 855 /* 856 * Bus Release Time, Host Adapter ID 857 */ 858 uint16_t brtime_id; /* word 18 */ 859 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 860 /* UNUSED 0x00f0 */ 861 #define CFBRTIME 0xff00 /* bus release time */ 862 863 /* 864 * Maximum targets 865 */ 866 uint16_t max_targets; /* word 19 */ 867 #define CFMAXTARG 0x00ff /* maximum targets */ 868 #define CFBOOTLUN 0x0f00 /* Lun to boot from */ 869 #define CFBOOTID 0xf000 /* Target to boot from */ 870 uint16_t res_1[10]; /* words 20-29 */ 871 uint16_t signature; /* Signature == 0x250 */ 872 #define CFSIGNATURE 0x250 873 #define CFSIGNATURE2 0x300 874 uint16_t checksum; /* word 31 */ 875 }; 876 877 /**************************** Message Buffer *********************************/ 878 typedef enum { 879 MSG_TYPE_NONE = 0x00, 880 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 881 MSG_TYPE_INITIATOR_MSGIN = 0x02, 882 MSG_TYPE_TARGET_MSGOUT = 0x03, 883 MSG_TYPE_TARGET_MSGIN = 0x04 884 } ahc_msg_type; 885 886 typedef enum { 887 MSGLOOP_IN_PROG, 888 MSGLOOP_MSGCOMPLETE, 889 MSGLOOP_TERMINATED 890 } msg_loop_stat; 891 892 /*********************** Software Configuration Structure *********************/ 893 TAILQ_HEAD(scb_tailq, scb); 894 895 struct ahc_aic7770_softc { 896 /* 897 * Saved register state used for chip_init(). 898 */ 899 uint8_t busspd; 900 uint8_t bustime; 901 }; 902 903 struct ahc_pci_softc { 904 /* 905 * Saved register state used for chip_init(). 906 */ 907 uint32_t devconfig; 908 uint16_t targcrccnt; 909 uint8_t command; 910 uint8_t csize_lattime; 911 uint8_t optionmode; 912 uint8_t crccontrol1; 913 uint8_t dscommand0; 914 uint8_t dspcistatus; 915 uint8_t scbbaddr; 916 uint8_t dff_thrsh; 917 }; 918 919 union ahc_bus_softc { 920 struct ahc_aic7770_softc aic7770_softc; 921 struct ahc_pci_softc pci_softc; 922 }; 923 924 typedef void (*ahc_bus_intr_t)(struct ahc_softc *); 925 typedef int (*ahc_bus_chip_init_t)(struct ahc_softc *); 926 typedef int (*ahc_bus_suspend_t)(struct ahc_softc *); 927 typedef int (*ahc_bus_resume_t)(struct ahc_softc *); 928 typedef void ahc_callback_t (void *); 929 930 #define AIC_SCB_DATA(softc) ((softc)->scb_data) 931 932 struct ahc_softc { 933 bus_space_tag_t tag; 934 bus_space_handle_t bsh; 935 #ifndef __linux__ 936 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 937 #endif 938 struct scb_data *scb_data; 939 940 struct scb *next_queued_scb; 941 942 /* 943 * SCBs that have been sent to the controller 944 */ 945 LIST_HEAD(, scb) pending_scbs; 946 947 /* 948 * SCBs whose timeout routine has been called. 949 */ 950 LIST_HEAD(, scb) timedout_scbs; 951 952 /* 953 * Counting lock for deferring the release of additional 954 * untagged transactions from the untagged_queues. When 955 * the lock is decremented to 0, all queues in the 956 * untagged_queues array are run. 957 */ 958 u_int untagged_queue_lock; 959 960 /* 961 * Per-target queue of untagged-transactions. The 962 * transaction at the head of the queue is the 963 * currently pending untagged transaction for the 964 * target. The driver only allows a single untagged 965 * transaction per target. 966 */ 967 struct scb_tailq untagged_queues[AHC_NUM_TARGETS]; 968 969 /* 970 * Bus attachment specific data. 971 */ 972 union ahc_bus_softc bus_softc; 973 974 /* 975 * Platform specific data. 976 */ 977 struct ahc_platform_data *platform_data; 978 979 /* 980 * Platform specific device information. 981 */ 982 aic_dev_softc_t dev_softc; 983 984 /* 985 * Bus specific device information. 986 */ 987 ahc_bus_intr_t bus_intr; 988 989 /* 990 * Bus specific initialization required 991 * after a chip reset. 992 */ 993 ahc_bus_chip_init_t bus_chip_init; 994 995 /* 996 * Bus specific suspend routine. 997 */ 998 ahc_bus_suspend_t bus_suspend; 999 1000 /* 1001 * Bus specific resume routine. 1002 */ 1003 ahc_bus_resume_t bus_resume; 1004 1005 /* 1006 * Target mode related state kept on a per enabled lun basis. 1007 * Targets that are not enabled will have null entries. 1008 * As an initiator, we keep one target entry for our initiator 1009 * ID to store our sync/wide transfer settings. 1010 */ 1011 struct ahc_tmode_tstate *enabled_targets[AHC_NUM_TARGETS]; 1012 1013 /* 1014 * The black hole device responsible for handling requests for 1015 * disabled luns on enabled targets. 1016 */ 1017 struct ahc_tmode_lstate *black_hole; 1018 1019 /* 1020 * Device instance currently on the bus awaiting a continue TIO 1021 * for a command that was not given the disconnect priveledge. 1022 */ 1023 struct ahc_tmode_lstate *pending_device; 1024 1025 /* 1026 * Card characteristics 1027 */ 1028 ahc_chip chip; 1029 ahc_feature features; 1030 ahc_bug bugs; 1031 ahc_flag flags; 1032 struct seeprom_config *seep_config; 1033 1034 /* Values to store in the SEQCTL register for pause and unpause */ 1035 uint8_t unpause; 1036 uint8_t pause; 1037 1038 /* Command Queues */ 1039 uint8_t qoutfifonext; 1040 uint8_t qinfifonext; 1041 uint8_t *qoutfifo; 1042 uint8_t *qinfifo; 1043 1044 /* Critical Section Data */ 1045 struct cs *critical_sections; 1046 u_int num_critical_sections; 1047 1048 /* Links for chaining softcs */ 1049 TAILQ_ENTRY(ahc_softc) links; 1050 1051 /* Channel Names ('A', 'B', etc.) */ 1052 char channel; 1053 char channel_b; 1054 1055 /* Initiator Bus ID */ 1056 uint8_t our_id; 1057 uint8_t our_id_b; 1058 1059 /* 1060 * PCI error detection. 1061 */ 1062 int unsolicited_ints; 1063 1064 /* 1065 * Target incoming command FIFO. 1066 */ 1067 struct target_cmd *targetcmds; 1068 uint8_t tqinfifonext; 1069 1070 /* 1071 * Cached copy of the sequencer control register. 1072 */ 1073 uint8_t seqctl; 1074 1075 /* 1076 * Incoming and outgoing message handling. 1077 */ 1078 uint8_t send_msg_perror; 1079 ahc_msg_type msg_type; 1080 uint8_t msgout_buf[12];/* Message we are sending */ 1081 uint8_t msgin_buf[12];/* Message we are receiving */ 1082 u_int msgout_len; /* Length of message to send */ 1083 u_int msgout_index; /* Current index in msgout */ 1084 u_int msgin_index; /* Current index in msgin */ 1085 1086 /* 1087 * Mapping information for data structures shared 1088 * between the sequencer and kernel. 1089 */ 1090 bus_dma_tag_t parent_dmat; 1091 bus_dma_tag_t shared_data_dmat; 1092 bus_dmamap_t shared_data_dmamap; 1093 bus_addr_t shared_data_busaddr; 1094 1095 /* 1096 * Bus address of the one byte buffer used to 1097 * work-around a DMA bug for chips <= aic7880 1098 * in target mode. 1099 */ 1100 bus_addr_t dma_bug_buf; 1101 1102 /* Number of enabled target mode device on this card */ 1103 u_int enabled_luns; 1104 1105 /* Initialization level of this data structure */ 1106 u_int init_level; 1107 1108 /* PCI cacheline size. */ 1109 u_int pci_cachesize; 1110 1111 /* 1112 * Count of parity errors we have seen as a target. 1113 * We auto-disable parity error checking after seeing 1114 * AHC_PCI_TARGET_PERR_THRESH number of errors. 1115 */ 1116 u_int pci_target_perr_count; 1117 #define AHC_PCI_TARGET_PERR_THRESH 10 1118 1119 /* Maximum number of sequencer instructions supported. */ 1120 u_int instruction_ram_size; 1121 1122 /* Per-Unit descriptive information */ 1123 const char *description; 1124 char *name; 1125 int unit; 1126 1127 /* Selection Timer settings */ 1128 int seltime; 1129 int seltime_b; 1130 1131 uint16_t user_discenable;/* Disconnection allowed */ 1132 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1133 }; 1134 1135 TAILQ_HEAD(ahc_softc_tailq, ahc_softc); 1136 extern struct ahc_softc_tailq ahc_tailq; 1137 1138 /************************ Active Device Information ***************************/ 1139 typedef enum { 1140 ROLE_UNKNOWN, 1141 ROLE_INITIATOR, 1142 ROLE_TARGET 1143 } role_t; 1144 1145 struct ahc_devinfo { 1146 int our_scsiid; 1147 int target_offset; 1148 uint16_t target_mask; 1149 u_int target; 1150 u_int lun; 1151 char channel; 1152 role_t role; /* 1153 * Only guaranteed to be correct if not 1154 * in the busfree state. 1155 */ 1156 }; 1157 1158 /****************************** PCI Structures ********************************/ 1159 #define AHC_PCI_IOADDR PCIR_BAR(0) /* I/O Address */ 1160 #define AHC_PCI_MEMADDR PCIR_BAR(1) /* Mem I/O Address */ 1161 1162 typedef int (ahc_device_setup_t)(struct ahc_softc *); 1163 1164 struct ahc_pci_identity { 1165 uint64_t full_id; 1166 uint64_t id_mask; 1167 char *name; 1168 ahc_device_setup_t *setup; 1169 }; 1170 extern struct ahc_pci_identity ahc_pci_ident_table[]; 1171 extern const u_int ahc_num_pci_devs; 1172 1173 /*************************** VL/EISA/ISA Declarations *************************/ 1174 struct aic7770_identity { 1175 uint32_t full_id; 1176 uint32_t id_mask; 1177 const char *name; 1178 ahc_device_setup_t *setup; 1179 }; 1180 extern struct aic7770_identity aic7770_ident_table[]; 1181 extern const int ahc_num_aic7770_devs; 1182 1183 #define AHC_EISA_SLOT_SIZE 0x1000 1184 #define AHC_EISA_SLOT_OFFSET 0xc00 1185 #define AHC_EISA_IOSIZE 0x100 1186 1187 /*************************** Function Declarations ****************************/ 1188 /******************************************************************************/ 1189 u_int ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl); 1190 void ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl); 1191 void ahc_busy_tcl(struct ahc_softc *ahc, 1192 u_int tcl, u_int busyid); 1193 1194 /***************************** PCI Front End *********************************/ 1195 struct ahc_pci_identity *ahc_find_pci_device(aic_dev_softc_t); 1196 int ahc_pci_config(struct ahc_softc *, 1197 struct ahc_pci_identity *); 1198 int ahc_pci_test_register_access(struct ahc_softc *); 1199 1200 /*************************** ISA/EISA/VL Front End ****************************/ 1201 struct aic7770_identity *aic7770_find_device(uint32_t); 1202 int aic7770_config(struct ahc_softc *ahc, 1203 struct aic7770_identity *, 1204 u_int port); 1205 1206 /************************** SCB and SCB queue management **********************/ 1207 int ahc_probe_scbs(struct ahc_softc *); 1208 void ahc_run_untagged_queues(struct ahc_softc *ahc); 1209 void ahc_run_untagged_queue(struct ahc_softc *ahc, 1210 struct scb_tailq *queue); 1211 void ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, 1212 struct scb *scb); 1213 int ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, 1214 int target, char channel, int lun, 1215 u_int tag, role_t role); 1216 1217 /****************************** Initialization ********************************/ 1218 struct ahc_softc *ahc_alloc(void *platform_arg, char *name); 1219 int ahc_softc_init(struct ahc_softc *); 1220 void ahc_controller_info(struct ahc_softc *ahc, char *buf); 1221 int ahc_chip_init(struct ahc_softc *ahc); 1222 int ahc_init(struct ahc_softc *ahc); 1223 void ahc_intr_enable(struct ahc_softc *ahc, int enable); 1224 void ahc_pause_and_flushwork(struct ahc_softc *ahc); 1225 int ahc_suspend(struct ahc_softc *ahc); 1226 int ahc_resume(struct ahc_softc *ahc); 1227 void ahc_softc_insert(struct ahc_softc *); 1228 void ahc_set_unit(struct ahc_softc *, int); 1229 void ahc_set_name(struct ahc_softc *, char *); 1230 int ahc_alloc_scbs(struct ahc_softc *ahc); 1231 void ahc_free(struct ahc_softc *ahc); 1232 int ahc_reset(struct ahc_softc *ahc, int reinit); 1233 void ahc_shutdown(void *arg); 1234 1235 /*************************** Interrupt Services *******************************/ 1236 void ahc_clear_intstat(struct ahc_softc *ahc); 1237 void ahc_run_qoutfifo(struct ahc_softc *ahc); 1238 #ifdef AHC_TARGET_MODE 1239 void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused); 1240 #endif 1241 void ahc_handle_brkadrint(struct ahc_softc *ahc); 1242 void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat); 1243 void ahc_handle_scsiint(struct ahc_softc *ahc, 1244 u_int intstat); 1245 void ahc_clear_critical_section(struct ahc_softc *ahc); 1246 1247 /***************************** Error Recovery *********************************/ 1248 typedef enum { 1249 SEARCH_COMPLETE, 1250 SEARCH_COUNT, 1251 SEARCH_REMOVE 1252 } ahc_search_action; 1253 int ahc_search_qinfifo(struct ahc_softc *ahc, int target, 1254 char channel, int lun, u_int tag, 1255 role_t role, uint32_t status, 1256 ahc_search_action action); 1257 int ahc_search_untagged_queues(struct ahc_softc *ahc, 1258 aic_io_ctx_t ctx, 1259 int target, char channel, 1260 int lun, uint32_t status, 1261 ahc_search_action action); 1262 int ahc_search_disc_list(struct ahc_softc *ahc, int target, 1263 char channel, int lun, u_int tag, 1264 int stop_on_first, int remove, 1265 int save_state); 1266 void ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb); 1267 int ahc_reset_channel(struct ahc_softc *ahc, char channel, 1268 int initiate_reset); 1269 int ahc_abort_scbs(struct ahc_softc *ahc, int target, 1270 char channel, int lun, u_int tag, 1271 role_t role, uint32_t status); 1272 void ahc_restart(struct ahc_softc *ahc); 1273 void ahc_calc_residual(struct ahc_softc *ahc, 1274 struct scb *scb); 1275 void ahc_timeout(struct scb *scb); 1276 void ahc_recover_commands(struct ahc_softc *ahc); 1277 /*************************** Utility Functions ********************************/ 1278 struct ahc_phase_table_entry* 1279 ahc_lookup_phase_entry(int phase); 1280 void ahc_compile_devinfo(struct ahc_devinfo *devinfo, 1281 u_int our_id, u_int target, 1282 u_int lun, char channel, 1283 role_t role); 1284 /************************** Transfer Negotiation ******************************/ 1285 struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1286 u_int *ppr_options, u_int maxsync); 1287 u_int ahc_find_period(struct ahc_softc *ahc, 1288 u_int scsirate, u_int maxsync); 1289 void ahc_validate_offset(struct ahc_softc *ahc, 1290 struct ahc_initiator_tinfo *tinfo, 1291 struct ahc_syncrate *syncrate, 1292 u_int *offset, int wide, 1293 role_t role); 1294 void ahc_validate_width(struct ahc_softc *ahc, 1295 struct ahc_initiator_tinfo *tinfo, 1296 u_int *bus_width, 1297 role_t role); 1298 /* 1299 * Negotiation types. These are used to qualify if we should renegotiate 1300 * even if our goal and current transport parameters are identical. 1301 */ 1302 typedef enum { 1303 AHC_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */ 1304 AHC_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */ 1305 AHC_NEG_ALWAYS /* Renegotiat even if goal is async. */ 1306 } ahc_neg_type; 1307 int ahc_update_neg_request(struct ahc_softc*, 1308 struct ahc_devinfo*, 1309 struct ahc_tmode_tstate*, 1310 struct ahc_initiator_tinfo*, 1311 ahc_neg_type); 1312 void ahc_set_width(struct ahc_softc *ahc, 1313 struct ahc_devinfo *devinfo, 1314 u_int width, u_int type, int paused); 1315 void ahc_set_syncrate(struct ahc_softc *ahc, 1316 struct ahc_devinfo *devinfo, 1317 struct ahc_syncrate *syncrate, 1318 u_int period, u_int offset, 1319 u_int ppr_options, 1320 u_int type, int paused); 1321 typedef enum { 1322 AHC_QUEUE_NONE, 1323 AHC_QUEUE_BASIC, 1324 AHC_QUEUE_TAGGED 1325 } ahc_queue_alg; 1326 1327 void ahc_set_tags(struct ahc_softc *ahc, 1328 struct ahc_devinfo *devinfo, 1329 ahc_queue_alg alg); 1330 1331 /**************************** Target Mode *************************************/ 1332 #ifdef AHC_TARGET_MODE 1333 void ahc_send_lstate_events(struct ahc_softc *, 1334 struct ahc_tmode_lstate *); 1335 void ahc_handle_en_lun(struct ahc_softc *ahc, 1336 struct cam_sim *sim, union ccb *ccb); 1337 cam_status ahc_find_tmode_devs(struct ahc_softc *ahc, 1338 struct cam_sim *sim, union ccb *ccb, 1339 struct ahc_tmode_tstate **tstate, 1340 struct ahc_tmode_lstate **lstate, 1341 int notfound_failure); 1342 #ifndef AHC_TMODE_ENABLE 1343 #define AHC_TMODE_ENABLE 0 1344 #endif 1345 #endif 1346 /******************************* Debug ***************************************/ 1347 #ifdef AHC_DEBUG 1348 extern uint32_t ahc_debug; 1349 #define AHC_SHOW_MISC 0x0001 1350 #define AHC_SHOW_SENSE 0x0002 1351 #define AHC_DUMP_SEEPROM 0x0004 1352 #define AHC_SHOW_TERMCTL 0x0008 1353 #define AHC_SHOW_MEMORY 0x0010 1354 #define AHC_SHOW_MESSAGES 0x0020 1355 #define AHC_SHOW_DV 0x0040 1356 #define AHC_SHOW_SELTO 0x0080 1357 #define AHC_SHOW_QFULL 0x0200 1358 #define AHC_SHOW_QUEUE 0x0400 1359 #define AHC_SHOW_TQIN 0x0800 1360 #define AHC_SHOW_MASKED_ERRORS 0x1000 1361 #define AHC_DEBUG_SEQUENCER 0x2000 1362 #endif 1363 void ahc_print_scb(struct scb *scb); 1364 void ahc_print_devinfo(struct ahc_softc *ahc, 1365 struct ahc_devinfo *dev); 1366 void ahc_dump_card_state(struct ahc_softc *ahc); 1367 int ahc_print_register(ahc_reg_parse_entry_t *table, 1368 u_int num_entries, 1369 const char *name, 1370 u_int address, 1371 u_int value, 1372 u_int *cur_column, 1373 u_int wrap_point); 1374 /******************************* SEEPROM *************************************/ 1375 int ahc_acquire_seeprom(struct ahc_softc *ahc, 1376 struct seeprom_descriptor *sd); 1377 void ahc_release_seeprom(struct seeprom_descriptor *sd); 1378 #endif /* _AIC7XXX_H_ */ 1379