1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/endian.h> 39 #include <sys/kernel.h> 40 #include <sys/lock.h> 41 #include <sys/malloc.h> 42 #include <sys/mbuf.h> 43 #include <sys/module.h> 44 #include <sys/mutex.h> 45 #include <sys/rman.h> 46 #include <sys/queue.h> 47 #include <sys/socket.h> 48 #include <sys/sockio.h> 49 #include <sys/sysctl.h> 50 #include <sys/taskqueue.h> 51 52 #include <net/bpf.h> 53 #include <net/debugnet.h> 54 #include <net/if.h> 55 #include <net/if_var.h> 56 #include <net/if_arp.h> 57 #include <net/ethernet.h> 58 #include <net/if_dl.h> 59 #include <net/if_llc.h> 60 #include <net/if_media.h> 61 #include <net/if_types.h> 62 #include <net/if_vlan_var.h> 63 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/ip.h> 67 #include <netinet/tcp.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 72 #include <dev/pci/pcireg.h> 73 #include <dev/pci/pcivar.h> 74 75 #include <machine/bus.h> 76 #include <machine/in_cksum.h> 77 78 #include <dev/alc/if_alcreg.h> 79 #include <dev/alc/if_alcvar.h> 80 81 /* "device miibus" required. See GENERIC if you get errors here. */ 82 #include "miibus_if.h" 83 #undef ALC_USE_CUSTOM_CSUM 84 85 #ifdef ALC_USE_CUSTOM_CSUM 86 #define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 87 #else 88 #define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 89 #endif 90 91 MODULE_DEPEND(alc, pci, 1, 1, 1); 92 MODULE_DEPEND(alc, ether, 1, 1, 1); 93 MODULE_DEPEND(alc, miibus, 1, 1, 1); 94 95 /* Tunables. */ 96 static int msi_disable = 0; 97 static int msix_disable = 0; 98 TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 99 TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 100 101 /* 102 * Devices supported by this driver. 103 */ 104 static struct alc_ident alc_ident_table[] = { 105 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, 106 "Atheros AR8131 PCIe Gigabit Ethernet" }, 107 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, 108 "Atheros AR8132 PCIe Fast Ethernet" }, 109 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, 110 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 111 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, 112 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 113 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, 114 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 115 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, 116 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 117 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8161, 9 * 1024, 118 "Atheros AR8161 PCIe Gigabit Ethernet" }, 119 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8162, 9 * 1024, 120 "Atheros AR8162 PCIe Fast Ethernet" }, 121 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8171, 9 * 1024, 122 "Atheros AR8171 PCIe Gigabit Ethernet" }, 123 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8172, 9 * 1024, 124 "Atheros AR8172 PCIe Fast Ethernet" }, 125 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2200, 9 * 1024, 126 "Killer E2200 Gigabit Ethernet" }, 127 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2400, 9 * 1024, 128 "Killer E2400 Gigabit Ethernet" }, 129 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2500, 9 * 1024, 130 "Killer E2500 Gigabit Ethernet" }, 131 { 0, 0, 0, NULL} 132 }; 133 134 static void alc_aspm(struct alc_softc *, int, int); 135 static void alc_aspm_813x(struct alc_softc *, int); 136 static void alc_aspm_816x(struct alc_softc *, int); 137 static int alc_attach(device_t); 138 static int alc_check_boundary(struct alc_softc *); 139 static void alc_config_msi(struct alc_softc *); 140 static int alc_detach(device_t); 141 static void alc_disable_l0s_l1(struct alc_softc *); 142 static int alc_dma_alloc(struct alc_softc *); 143 static void alc_dma_free(struct alc_softc *); 144 static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 145 static void alc_dsp_fixup(struct alc_softc *, int); 146 static int alc_encap(struct alc_softc *, struct mbuf **); 147 static struct alc_ident * 148 alc_find_ident(device_t); 149 #ifndef __NO_STRICT_ALIGNMENT 150 static struct mbuf * 151 alc_fixup_rx(if_t, struct mbuf *); 152 #endif 153 static void alc_get_macaddr(struct alc_softc *); 154 static void alc_get_macaddr_813x(struct alc_softc *); 155 static void alc_get_macaddr_816x(struct alc_softc *); 156 static void alc_get_macaddr_par(struct alc_softc *); 157 static void alc_init(void *); 158 static void alc_init_cmb(struct alc_softc *); 159 static void alc_init_locked(struct alc_softc *); 160 static void alc_init_rr_ring(struct alc_softc *); 161 static int alc_init_rx_ring(struct alc_softc *); 162 static void alc_init_smb(struct alc_softc *); 163 static void alc_init_tx_ring(struct alc_softc *); 164 static void alc_int_task(void *, int); 165 static int alc_intr(void *); 166 static int alc_ioctl(if_t, u_long, caddr_t); 167 static void alc_mac_config(struct alc_softc *); 168 static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int); 169 static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int); 170 static uint32_t alc_mii_writereg_813x(struct alc_softc *, int, int, int); 171 static uint32_t alc_mii_writereg_816x(struct alc_softc *, int, int, int); 172 static int alc_miibus_readreg(device_t, int, int); 173 static void alc_miibus_statchg(device_t); 174 static int alc_miibus_writereg(device_t, int, int, int); 175 static uint32_t alc_miidbg_readreg(struct alc_softc *, int); 176 static uint32_t alc_miidbg_writereg(struct alc_softc *, int, int); 177 static uint32_t alc_miiext_readreg(struct alc_softc *, int, int); 178 static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int); 179 static int alc_mediachange(if_t); 180 static int alc_mediachange_locked(struct alc_softc *); 181 static void alc_mediastatus(if_t, struct ifmediareq *); 182 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 183 static void alc_osc_reset(struct alc_softc *); 184 static void alc_phy_down(struct alc_softc *); 185 static void alc_phy_reset(struct alc_softc *); 186 static void alc_phy_reset_813x(struct alc_softc *); 187 static void alc_phy_reset_816x(struct alc_softc *); 188 static int alc_probe(device_t); 189 static void alc_reset(struct alc_softc *); 190 static int alc_resume(device_t); 191 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 192 static int alc_rxintr(struct alc_softc *, int); 193 static void alc_rxfilter(struct alc_softc *); 194 static void alc_rxvlan(struct alc_softc *); 195 static void alc_setlinkspeed(struct alc_softc *); 196 static void alc_setwol(struct alc_softc *); 197 static void alc_setwol_813x(struct alc_softc *); 198 static void alc_setwol_816x(struct alc_softc *); 199 static int alc_shutdown(device_t); 200 static void alc_start(if_t); 201 static void alc_start_locked(if_t); 202 static void alc_start_queue(struct alc_softc *); 203 static void alc_start_tx(struct alc_softc *); 204 static void alc_stats_clear(struct alc_softc *); 205 static void alc_stats_update(struct alc_softc *); 206 static void alc_stop(struct alc_softc *); 207 static void alc_stop_mac(struct alc_softc *); 208 static void alc_stop_queue(struct alc_softc *); 209 static int alc_suspend(device_t); 210 static void alc_sysctl_node(struct alc_softc *); 211 static void alc_tick(void *); 212 static void alc_txeof(struct alc_softc *); 213 static void alc_watchdog(struct alc_softc *); 214 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 215 static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 216 static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 217 218 DEBUGNET_DEFINE(alc); 219 220 static device_method_t alc_methods[] = { 221 /* Device interface. */ 222 DEVMETHOD(device_probe, alc_probe), 223 DEVMETHOD(device_attach, alc_attach), 224 DEVMETHOD(device_detach, alc_detach), 225 DEVMETHOD(device_shutdown, alc_shutdown), 226 DEVMETHOD(device_suspend, alc_suspend), 227 DEVMETHOD(device_resume, alc_resume), 228 229 /* MII interface. */ 230 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 231 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 232 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 233 234 DEVMETHOD_END 235 }; 236 237 static driver_t alc_driver = { 238 "alc", 239 alc_methods, 240 sizeof(struct alc_softc) 241 }; 242 243 DRIVER_MODULE(alc, pci, alc_driver, 0, 0); 244 MODULE_PNP_INFO("U16:vendor;U16:device", pci, alc, alc_ident_table, 245 nitems(alc_ident_table) - 1); 246 DRIVER_MODULE(miibus, alc, miibus_driver, 0, 0); 247 248 static struct resource_spec alc_res_spec_mem[] = { 249 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 250 { -1, 0, 0 } 251 }; 252 253 static struct resource_spec alc_irq_spec_legacy[] = { 254 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 255 { -1, 0, 0 } 256 }; 257 258 static struct resource_spec alc_irq_spec_msi[] = { 259 { SYS_RES_IRQ, 1, RF_ACTIVE }, 260 { -1, 0, 0 } 261 }; 262 263 static struct resource_spec alc_irq_spec_msix[] = { 264 { SYS_RES_IRQ, 1, RF_ACTIVE }, 265 { -1, 0, 0 } 266 }; 267 268 static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0, 0 }; 269 270 static int 271 alc_miibus_readreg(device_t dev, int phy, int reg) 272 { 273 struct alc_softc *sc; 274 int v; 275 276 sc = device_get_softc(dev); 277 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 278 v = alc_mii_readreg_816x(sc, phy, reg); 279 else 280 v = alc_mii_readreg_813x(sc, phy, reg); 281 return (v); 282 } 283 284 static uint32_t 285 alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg) 286 { 287 uint32_t v; 288 int i; 289 290 /* 291 * For AR8132 fast ethernet controller, do not report 1000baseT 292 * capability to mii(4). Even though AR8132 uses the same 293 * model/revision number of F1 gigabit PHY, the PHY has no 294 * ability to establish 1000baseT link. 295 */ 296 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 297 reg == MII_EXTSR) 298 return (0); 299 300 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 301 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 302 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 303 DELAY(5); 304 v = CSR_READ_4(sc, ALC_MDIO); 305 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 306 break; 307 } 308 309 if (i == 0) { 310 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 311 return (0); 312 } 313 314 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 315 } 316 317 static uint32_t 318 alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg) 319 { 320 uint32_t clk, v; 321 int i; 322 323 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 324 clk = MDIO_CLK_25_128; 325 else 326 clk = MDIO_CLK_25_4; 327 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 328 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 329 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 330 DELAY(5); 331 v = CSR_READ_4(sc, ALC_MDIO); 332 if ((v & MDIO_OP_BUSY) == 0) 333 break; 334 } 335 336 if (i == 0) { 337 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 338 return (0); 339 } 340 341 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 342 } 343 344 static int 345 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 346 { 347 struct alc_softc *sc; 348 int v; 349 350 sc = device_get_softc(dev); 351 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 352 v = alc_mii_writereg_816x(sc, phy, reg, val); 353 else 354 v = alc_mii_writereg_813x(sc, phy, reg, val); 355 return (v); 356 } 357 358 static uint32_t 359 alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val) 360 { 361 uint32_t v; 362 int i; 363 364 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 365 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 366 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 367 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 368 DELAY(5); 369 v = CSR_READ_4(sc, ALC_MDIO); 370 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 371 break; 372 } 373 374 if (i == 0) 375 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 376 377 return (0); 378 } 379 380 static uint32_t 381 alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val) 382 { 383 uint32_t clk, v; 384 int i; 385 386 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 387 clk = MDIO_CLK_25_128; 388 else 389 clk = MDIO_CLK_25_4; 390 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 391 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 392 MDIO_SUP_PREAMBLE | clk); 393 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 394 DELAY(5); 395 v = CSR_READ_4(sc, ALC_MDIO); 396 if ((v & MDIO_OP_BUSY) == 0) 397 break; 398 } 399 400 if (i == 0) 401 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 402 403 return (0); 404 } 405 406 static void 407 alc_miibus_statchg(device_t dev) 408 { 409 struct alc_softc *sc; 410 struct mii_data *mii; 411 if_t ifp; 412 uint32_t reg; 413 414 sc = device_get_softc(dev); 415 416 mii = device_get_softc(sc->alc_miibus); 417 ifp = sc->alc_ifp; 418 if (mii == NULL || ifp == NULL || 419 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 420 return; 421 422 sc->alc_flags &= ~ALC_FLAG_LINK; 423 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 424 (IFM_ACTIVE | IFM_AVALID)) { 425 switch (IFM_SUBTYPE(mii->mii_media_active)) { 426 case IFM_10_T: 427 case IFM_100_TX: 428 sc->alc_flags |= ALC_FLAG_LINK; 429 break; 430 case IFM_1000_T: 431 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 432 sc->alc_flags |= ALC_FLAG_LINK; 433 break; 434 default: 435 break; 436 } 437 } 438 /* Stop Rx/Tx MACs. */ 439 alc_stop_mac(sc); 440 441 /* Program MACs with resolved speed/duplex/flow-control. */ 442 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 443 alc_start_queue(sc); 444 alc_mac_config(sc); 445 /* Re-enable Tx/Rx MACs. */ 446 reg = CSR_READ_4(sc, ALC_MAC_CFG); 447 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 448 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 449 } 450 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 451 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 452 } 453 454 static uint32_t 455 alc_miidbg_readreg(struct alc_softc *sc, int reg) 456 { 457 458 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 459 reg); 460 return (alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 461 ALC_MII_DBG_DATA)); 462 } 463 464 static uint32_t 465 alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) 466 { 467 468 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 469 reg); 470 return (alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 471 ALC_MII_DBG_DATA, val)); 472 } 473 474 static uint32_t 475 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) 476 { 477 uint32_t clk, v; 478 int i; 479 480 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 481 EXT_MDIO_DEVADDR(devaddr)); 482 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 483 clk = MDIO_CLK_25_128; 484 else 485 clk = MDIO_CLK_25_4; 486 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 487 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 488 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 489 DELAY(5); 490 v = CSR_READ_4(sc, ALC_MDIO); 491 if ((v & MDIO_OP_BUSY) == 0) 492 break; 493 } 494 495 if (i == 0) { 496 device_printf(sc->alc_dev, "phy ext read timeout : %d, %d\n", 497 devaddr, reg); 498 return (0); 499 } 500 501 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 502 } 503 504 static uint32_t 505 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) 506 { 507 uint32_t clk, v; 508 int i; 509 510 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 511 EXT_MDIO_DEVADDR(devaddr)); 512 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 513 clk = MDIO_CLK_25_128; 514 else 515 clk = MDIO_CLK_25_4; 516 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 517 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 518 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 519 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 520 DELAY(5); 521 v = CSR_READ_4(sc, ALC_MDIO); 522 if ((v & MDIO_OP_BUSY) == 0) 523 break; 524 } 525 526 if (i == 0) 527 device_printf(sc->alc_dev, "phy ext write timeout : %d, %d\n", 528 devaddr, reg); 529 530 return (0); 531 } 532 533 static void 534 alc_dsp_fixup(struct alc_softc *sc, int media) 535 { 536 uint16_t agc, len, val; 537 538 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 539 return; 540 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 541 return; 542 543 /* 544 * Vendor PHY magic. 545 * 1000BT/AZ, wrong cable length 546 */ 547 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 548 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); 549 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 550 EXT_CLDCTL6_CAB_LEN_MASK; 551 agc = alc_miidbg_readreg(sc, MII_DBG_AGC); 552 agc = (agc >> DBG_AGC_2_VGA_SHIFT) & DBG_AGC_2_VGA_MASK; 553 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 554 agc > DBG_AGC_LONG1G_LIMT) || 555 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 556 agc > DBG_AGC_LONG1G_LIMT)) { 557 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 558 DBG_AZ_ANADECT_LONG); 559 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 560 MII_EXT_ANEG_AFE); 561 val |= ANEG_AFEE_10BT_100M_TH; 562 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 563 val); 564 } else { 565 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 566 DBG_AZ_ANADECT_DEFAULT); 567 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 568 MII_EXT_ANEG_AFE); 569 val &= ~ANEG_AFEE_10BT_100M_TH; 570 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 571 val); 572 } 573 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 574 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 575 if (media == IFM_1000_T) { 576 /* 577 * Giga link threshold, raise the tolerance of 578 * noise 50%. 579 */ 580 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 581 val &= ~DBG_MSE20DB_TH_MASK; 582 val |= (DBG_MSE20DB_TH_HI << 583 DBG_MSE20DB_TH_SHIFT); 584 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 585 } else if (media == IFM_100_TX) 586 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 587 DBG_MSE16DB_UP); 588 } 589 } else { 590 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); 591 val &= ~ANEG_AFEE_10BT_100M_TH; 592 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 593 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 594 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 595 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 596 DBG_MSE16DB_DOWN); 597 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 598 val &= ~DBG_MSE20DB_TH_MASK; 599 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 600 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 601 } 602 } 603 } 604 605 static void 606 alc_mediastatus(if_t ifp, struct ifmediareq *ifmr) 607 { 608 struct alc_softc *sc; 609 struct mii_data *mii; 610 611 sc = if_getsoftc(ifp); 612 ALC_LOCK(sc); 613 if ((if_getflags(ifp) & IFF_UP) == 0) { 614 ALC_UNLOCK(sc); 615 return; 616 } 617 mii = device_get_softc(sc->alc_miibus); 618 619 mii_pollstat(mii); 620 ifmr->ifm_status = mii->mii_media_status; 621 ifmr->ifm_active = mii->mii_media_active; 622 ALC_UNLOCK(sc); 623 } 624 625 static int 626 alc_mediachange(if_t ifp) 627 { 628 struct alc_softc *sc; 629 int error; 630 631 sc = if_getsoftc(ifp); 632 ALC_LOCK(sc); 633 error = alc_mediachange_locked(sc); 634 ALC_UNLOCK(sc); 635 636 return (error); 637 } 638 639 static int 640 alc_mediachange_locked(struct alc_softc *sc) 641 { 642 struct mii_data *mii; 643 struct mii_softc *miisc; 644 int error; 645 646 ALC_LOCK_ASSERT(sc); 647 648 mii = device_get_softc(sc->alc_miibus); 649 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 650 PHY_RESET(miisc); 651 error = mii_mediachg(mii); 652 653 return (error); 654 } 655 656 static struct alc_ident * 657 alc_find_ident(device_t dev) 658 { 659 struct alc_ident *ident; 660 uint16_t vendor, devid; 661 662 vendor = pci_get_vendor(dev); 663 devid = pci_get_device(dev); 664 for (ident = alc_ident_table; ident->name != NULL; ident++) { 665 if (vendor == ident->vendorid && devid == ident->deviceid) 666 return (ident); 667 } 668 669 return (NULL); 670 } 671 672 static int 673 alc_probe(device_t dev) 674 { 675 struct alc_ident *ident; 676 677 ident = alc_find_ident(dev); 678 if (ident != NULL) { 679 device_set_desc(dev, ident->name); 680 return (BUS_PROBE_DEFAULT); 681 } 682 683 return (ENXIO); 684 } 685 686 static void 687 alc_get_macaddr(struct alc_softc *sc) 688 { 689 690 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 691 alc_get_macaddr_816x(sc); 692 else 693 alc_get_macaddr_813x(sc); 694 } 695 696 static void 697 alc_get_macaddr_813x(struct alc_softc *sc) 698 { 699 uint32_t opt; 700 uint16_t val; 701 int eeprom, i; 702 703 eeprom = 0; 704 opt = CSR_READ_4(sc, ALC_OPT_CFG); 705 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 706 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 707 /* 708 * EEPROM found, let TWSI reload EEPROM configuration. 709 * This will set ethernet address of controller. 710 */ 711 eeprom++; 712 switch (sc->alc_ident->deviceid) { 713 case DEVICEID_ATHEROS_AR8131: 714 case DEVICEID_ATHEROS_AR8132: 715 if ((opt & OPT_CFG_CLK_ENB) == 0) { 716 opt |= OPT_CFG_CLK_ENB; 717 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 718 CSR_READ_4(sc, ALC_OPT_CFG); 719 DELAY(1000); 720 } 721 break; 722 case DEVICEID_ATHEROS_AR8151: 723 case DEVICEID_ATHEROS_AR8151_V2: 724 case DEVICEID_ATHEROS_AR8152_B: 725 case DEVICEID_ATHEROS_AR8152_B2: 726 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 727 ALC_MII_DBG_ADDR, 0x00); 728 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 729 ALC_MII_DBG_DATA); 730 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 731 ALC_MII_DBG_DATA, val & 0xFF7F); 732 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 733 ALC_MII_DBG_ADDR, 0x3B); 734 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 735 ALC_MII_DBG_DATA); 736 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 737 ALC_MII_DBG_DATA, val | 0x0008); 738 DELAY(20); 739 break; 740 } 741 742 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 743 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 744 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 745 CSR_READ_4(sc, ALC_WOL_CFG); 746 747 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 748 TWSI_CFG_SW_LD_START); 749 for (i = 100; i > 0; i--) { 750 DELAY(1000); 751 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 752 TWSI_CFG_SW_LD_START) == 0) 753 break; 754 } 755 if (i == 0) 756 device_printf(sc->alc_dev, 757 "reloading EEPROM timeout!\n"); 758 } else { 759 if (bootverbose) 760 device_printf(sc->alc_dev, "EEPROM not found!\n"); 761 } 762 if (eeprom != 0) { 763 switch (sc->alc_ident->deviceid) { 764 case DEVICEID_ATHEROS_AR8131: 765 case DEVICEID_ATHEROS_AR8132: 766 if ((opt & OPT_CFG_CLK_ENB) != 0) { 767 opt &= ~OPT_CFG_CLK_ENB; 768 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 769 CSR_READ_4(sc, ALC_OPT_CFG); 770 DELAY(1000); 771 } 772 break; 773 case DEVICEID_ATHEROS_AR8151: 774 case DEVICEID_ATHEROS_AR8151_V2: 775 case DEVICEID_ATHEROS_AR8152_B: 776 case DEVICEID_ATHEROS_AR8152_B2: 777 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 778 ALC_MII_DBG_ADDR, 0x00); 779 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 780 ALC_MII_DBG_DATA); 781 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 782 ALC_MII_DBG_DATA, val | 0x0080); 783 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 784 ALC_MII_DBG_ADDR, 0x3B); 785 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 786 ALC_MII_DBG_DATA); 787 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 788 ALC_MII_DBG_DATA, val & 0xFFF7); 789 DELAY(20); 790 break; 791 } 792 } 793 794 alc_get_macaddr_par(sc); 795 } 796 797 static void 798 alc_get_macaddr_816x(struct alc_softc *sc) 799 { 800 uint32_t reg; 801 int i, reloaded; 802 803 reloaded = 0; 804 /* Try to reload station address via TWSI. */ 805 for (i = 100; i > 0; i--) { 806 reg = CSR_READ_4(sc, ALC_SLD); 807 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 808 break; 809 DELAY(1000); 810 } 811 if (i != 0) { 812 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 813 for (i = 100; i > 0; i--) { 814 DELAY(1000); 815 reg = CSR_READ_4(sc, ALC_SLD); 816 if ((reg & SLD_START) == 0) 817 break; 818 } 819 if (i != 0) 820 reloaded++; 821 else if (bootverbose) 822 device_printf(sc->alc_dev, 823 "reloading station address via TWSI timed out!\n"); 824 } 825 826 /* Try to reload station address from EEPROM or FLASH. */ 827 if (reloaded == 0) { 828 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 829 if ((reg & (EEPROM_LD_EEPROM_EXIST | 830 EEPROM_LD_FLASH_EXIST)) != 0) { 831 for (i = 100; i > 0; i--) { 832 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 833 if ((reg & (EEPROM_LD_PROGRESS | 834 EEPROM_LD_START)) == 0) 835 break; 836 DELAY(1000); 837 } 838 if (i != 0) { 839 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 840 EEPROM_LD_START); 841 for (i = 100; i > 0; i--) { 842 DELAY(1000); 843 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 844 if ((reg & EEPROM_LD_START) == 0) 845 break; 846 } 847 } else if (bootverbose) 848 device_printf(sc->alc_dev, 849 "reloading EEPROM/FLASH timed out!\n"); 850 } 851 } 852 853 alc_get_macaddr_par(sc); 854 } 855 856 static void 857 alc_get_macaddr_par(struct alc_softc *sc) 858 { 859 uint32_t ea[2]; 860 861 ea[0] = CSR_READ_4(sc, ALC_PAR0); 862 ea[1] = CSR_READ_4(sc, ALC_PAR1); 863 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 864 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 865 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 866 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 867 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 868 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 869 } 870 871 static void 872 alc_disable_l0s_l1(struct alc_softc *sc) 873 { 874 uint32_t pmcfg; 875 876 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 877 /* Another magic from vendor. */ 878 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 879 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 880 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 881 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 882 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 883 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 884 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 885 } 886 } 887 888 static void 889 alc_phy_reset(struct alc_softc *sc) 890 { 891 892 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 893 alc_phy_reset_816x(sc); 894 else 895 alc_phy_reset_813x(sc); 896 } 897 898 static void 899 alc_phy_reset_813x(struct alc_softc *sc) 900 { 901 uint16_t data; 902 903 /* Reset magic from Linux. */ 904 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 905 CSR_READ_2(sc, ALC_GPHY_CFG); 906 DELAY(10 * 1000); 907 908 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 909 GPHY_CFG_SEL_ANA_RESET); 910 CSR_READ_2(sc, ALC_GPHY_CFG); 911 DELAY(10 * 1000); 912 913 /* DSP fixup, Vendor magic. */ 914 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 915 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 916 ALC_MII_DBG_ADDR, 0x000A); 917 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 918 ALC_MII_DBG_DATA); 919 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 920 ALC_MII_DBG_DATA, data & 0xDFFF); 921 } 922 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 923 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 924 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 925 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 926 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 927 ALC_MII_DBG_ADDR, 0x003B); 928 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 929 ALC_MII_DBG_DATA); 930 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 931 ALC_MII_DBG_DATA, data & 0xFFF7); 932 DELAY(20 * 1000); 933 } 934 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { 935 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 936 ALC_MII_DBG_ADDR, 0x0029); 937 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 938 ALC_MII_DBG_DATA, 0x929D); 939 } 940 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 941 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || 942 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 943 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 944 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 945 ALC_MII_DBG_ADDR, 0x0029); 946 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 947 ALC_MII_DBG_DATA, 0xB6DD); 948 } 949 950 /* Load DSP codes, vendor magic. */ 951 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 952 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 953 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 954 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 955 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 956 ALC_MII_DBG_DATA, data); 957 958 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 959 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 960 ANA_SERDES_EN_LCKDT; 961 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 962 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 963 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 964 ALC_MII_DBG_DATA, data); 965 966 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 967 ANA_LONG_CABLE_TH_100_MASK) | 968 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 969 ANA_SHORT_CABLE_TH_100_SHIFT) | 970 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 971 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 972 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 973 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 974 ALC_MII_DBG_DATA, data); 975 976 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 977 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 978 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 979 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 980 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 981 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 982 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 983 ALC_MII_DBG_DATA, data); 984 985 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 986 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 987 ANA_OEN_125M; 988 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 989 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 990 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 991 ALC_MII_DBG_DATA, data); 992 DELAY(1000); 993 994 /* Disable hibernation. */ 995 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 996 0x0029); 997 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 998 ALC_MII_DBG_DATA); 999 data &= ~0x8000; 1000 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 1001 data); 1002 1003 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 1004 0x000B); 1005 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 1006 ALC_MII_DBG_DATA); 1007 data &= ~0x8000; 1008 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 1009 data); 1010 } 1011 1012 static void 1013 alc_phy_reset_816x(struct alc_softc *sc) 1014 { 1015 uint32_t val; 1016 1017 val = CSR_READ_4(sc, ALC_GPHY_CFG); 1018 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1019 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 1020 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 1021 val |= GPHY_CFG_SEL_ANA_RESET; 1022 #ifdef notyet 1023 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET; 1024 #else 1025 /* Disable PHY hibernation. */ 1026 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 1027 #endif 1028 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 1029 DELAY(10); 1030 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 1031 DELAY(800); 1032 1033 /* Vendor PHY magic. */ 1034 #ifdef notyet 1035 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT); 1036 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT); 1037 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS, 1038 EXT_VDRVBIAS_DEFAULT); 1039 #else 1040 /* Disable PHY hibernation. */ 1041 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 1042 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 1043 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, 1044 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 1045 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 1046 #endif 1047 1048 /* XXX Disable EEE. */ 1049 val = CSR_READ_4(sc, ALC_LPI_CTL); 1050 val &= ~LPI_CTL_ENB; 1051 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 1052 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 1053 1054 /* PHY power saving. */ 1055 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 1056 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 1057 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 1058 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 1059 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1060 val &= ~DBG_GREENCFG2_GATE_DFSE_EN; 1061 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1062 1063 /* RTL8139C, 120m issue. */ 1064 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 1065 ANEG_NLP78_120M_DEFAULT); 1066 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 1067 ANEG_S3DIG10_DEFAULT); 1068 1069 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 1070 /* Turn off half amplitude. */ 1071 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); 1072 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 1073 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); 1074 /* Turn off Green feature. */ 1075 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1076 val |= DBG_GREENCFG2_BP_GREEN; 1077 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1078 /* Turn off half bias. */ 1079 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); 1080 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 1081 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); 1082 } 1083 } 1084 1085 static void 1086 alc_phy_down(struct alc_softc *sc) 1087 { 1088 uint32_t gphy; 1089 1090 switch (sc->alc_ident->deviceid) { 1091 case DEVICEID_ATHEROS_AR8161: 1092 case DEVICEID_ATHEROS_E2200: 1093 case DEVICEID_ATHEROS_E2400: 1094 case DEVICEID_ATHEROS_E2500: 1095 case DEVICEID_ATHEROS_AR8162: 1096 case DEVICEID_ATHEROS_AR8171: 1097 case DEVICEID_ATHEROS_AR8172: 1098 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 1099 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1100 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 1101 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 1102 GPHY_CFG_SEL_ANA_RESET; 1103 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 1104 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 1105 break; 1106 case DEVICEID_ATHEROS_AR8151: 1107 case DEVICEID_ATHEROS_AR8151_V2: 1108 case DEVICEID_ATHEROS_AR8152_B: 1109 case DEVICEID_ATHEROS_AR8152_B2: 1110 /* 1111 * GPHY power down caused more problems on AR8151 v2.0. 1112 * When driver is reloaded after GPHY power down, 1113 * accesses to PHY/MAC registers hung the system. Only 1114 * cold boot recovered from it. I'm not sure whether 1115 * AR8151 v1.0 also requires this one though. I don't 1116 * have AR8151 v1.0 controller in hand. 1117 * The only option left is to isolate the PHY and 1118 * initiates power down the PHY which in turn saves 1119 * more power when driver is unloaded. 1120 */ 1121 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1122 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 1123 break; 1124 default: 1125 /* Force PHY down. */ 1126 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 1127 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 1128 GPHY_CFG_PWDOWN_HW); 1129 DELAY(1000); 1130 break; 1131 } 1132 } 1133 1134 static void 1135 alc_aspm(struct alc_softc *sc, int init, int media) 1136 { 1137 1138 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1139 alc_aspm_816x(sc, init); 1140 else 1141 alc_aspm_813x(sc, media); 1142 } 1143 1144 static void 1145 alc_aspm_813x(struct alc_softc *sc, int media) 1146 { 1147 uint32_t pmcfg; 1148 uint16_t linkcfg; 1149 1150 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1151 return; 1152 1153 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1154 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 1155 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 1156 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 1157 PCIER_LINK_CTL); 1158 else 1159 linkcfg = 0; 1160 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 1161 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 1162 pmcfg |= PM_CFG_MAC_ASPM_CHK; 1163 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 1164 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1165 1166 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1167 /* Disable extended sync except AR8152 B v1.0 */ 1168 linkcfg &= ~PCIEM_LINK_CTL_EXTENDED_SYNC; 1169 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1170 sc->alc_rev == ATHEROS_AR8152_B_V10) 1171 linkcfg |= PCIEM_LINK_CTL_EXTENDED_SYNC; 1172 CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL, 1173 linkcfg); 1174 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 1175 PM_CFG_HOTRST); 1176 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 1177 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1178 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1179 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 1180 PM_CFG_PM_REQ_TIMER_SHIFT); 1181 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 1182 } 1183 1184 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1185 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 1186 pmcfg |= PM_CFG_ASPM_L0S_ENB; 1187 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1188 pmcfg |= PM_CFG_ASPM_L1_ENB; 1189 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1190 if (sc->alc_ident->deviceid == 1191 DEVICEID_ATHEROS_AR8152_B) 1192 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 1193 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 1194 PM_CFG_SERDES_PLL_L1_ENB | 1195 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1196 pmcfg |= PM_CFG_CLK_SWH_L1; 1197 if (media == IFM_100_TX || media == IFM_1000_T) { 1198 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1199 switch (sc->alc_ident->deviceid) { 1200 case DEVICEID_ATHEROS_AR8152_B: 1201 pmcfg |= (7 << 1202 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1203 break; 1204 case DEVICEID_ATHEROS_AR8152_B2: 1205 case DEVICEID_ATHEROS_AR8151_V2: 1206 pmcfg |= (4 << 1207 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1208 break; 1209 default: 1210 pmcfg |= (15 << 1211 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1212 break; 1213 } 1214 } 1215 } else { 1216 pmcfg |= PM_CFG_SERDES_L1_ENB | 1217 PM_CFG_SERDES_PLL_L1_ENB | 1218 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1219 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1220 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1221 } 1222 } else { 1223 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1224 PM_CFG_SERDES_PLL_L1_ENB); 1225 pmcfg |= PM_CFG_CLK_SWH_L1; 1226 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1227 pmcfg |= PM_CFG_ASPM_L1_ENB; 1228 } 1229 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1230 } 1231 1232 static void 1233 alc_aspm_816x(struct alc_softc *sc, int init) 1234 { 1235 uint32_t pmcfg; 1236 1237 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1238 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1239 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1240 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1241 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1242 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1243 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1244 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1245 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1246 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1247 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1248 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1249 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1250 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1251 (sc->alc_rev & 0x01) != 0) 1252 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1253 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1254 /* Link up, enable both L0s, L1s. */ 1255 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1256 PM_CFG_MAC_ASPM_CHK; 1257 } else { 1258 if (init != 0) 1259 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1260 PM_CFG_MAC_ASPM_CHK; 1261 else if ((if_getdrvflags(sc->alc_ifp) & IFF_DRV_RUNNING) != 0) 1262 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1263 } 1264 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1265 } 1266 1267 static void 1268 alc_init_pcie(struct alc_softc *sc) 1269 { 1270 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1271 uint32_t cap, ctl, val; 1272 int state; 1273 1274 /* Clear data link and flow-control protocol error. */ 1275 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1276 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1277 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1278 1279 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1280 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1281 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1282 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1283 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1284 PCIE_PHYMISC_FORCE_RCV_DET); 1285 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1286 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1287 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1288 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1289 PCIE_PHYMISC2_SERDES_TH_MASK); 1290 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1291 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1292 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1293 } 1294 /* Disable ASPM L0S and L1. */ 1295 cap = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CAP); 1296 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1297 ctl = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CTL); 1298 if ((ctl & PCIEM_LINK_CTL_RCB) != 0) 1299 sc->alc_rcb = DMA_CFG_RCB_128; 1300 if (bootverbose) 1301 device_printf(sc->alc_dev, "RCB %u bytes\n", 1302 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1303 state = ctl & PCIEM_LINK_CTL_ASPMC; 1304 if (state & PCIEM_LINK_CTL_ASPMC_L0S) 1305 sc->alc_flags |= ALC_FLAG_L0S; 1306 if (state & PCIEM_LINK_CTL_ASPMC_L1) 1307 sc->alc_flags |= ALC_FLAG_L1S; 1308 if (bootverbose) 1309 device_printf(sc->alc_dev, "ASPM %s %s\n", 1310 aspm_state[state], 1311 state == 0 ? "disabled" : "enabled"); 1312 alc_disable_l0s_l1(sc); 1313 } else { 1314 if (bootverbose) 1315 device_printf(sc->alc_dev, 1316 "no ASPM support\n"); 1317 } 1318 } else { 1319 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1320 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1321 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1322 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1323 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1324 (sc->alc_rev & 0x01) != 0) { 1325 if ((val & MASTER_WAKEN_25M) == 0 || 1326 (val & MASTER_CLK_SEL_DIS) == 0) { 1327 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1328 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1329 } 1330 } else { 1331 if ((val & MASTER_WAKEN_25M) == 0 || 1332 (val & MASTER_CLK_SEL_DIS) != 0) { 1333 val |= MASTER_WAKEN_25M; 1334 val &= ~MASTER_CLK_SEL_DIS; 1335 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1336 } 1337 } 1338 } 1339 alc_aspm(sc, 1, IFM_UNKNOWN); 1340 } 1341 1342 static void 1343 alc_config_msi(struct alc_softc *sc) 1344 { 1345 uint32_t ctl, mod; 1346 1347 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 1348 /* 1349 * It seems interrupt moderation is controlled by 1350 * ALC_MSI_RETRANS_TIMER register if MSI/MSIX is active. 1351 * Driver uses RX interrupt moderation parameter to 1352 * program ALC_MSI_RETRANS_TIMER register. 1353 */ 1354 ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER); 1355 ctl &= ~MSI_RETRANS_TIMER_MASK; 1356 ctl &= ~MSI_RETRANS_MASK_SEL_LINE; 1357 mod = ALC_USECS(sc->alc_int_rx_mod); 1358 if (mod == 0) 1359 mod = 1; 1360 ctl |= mod; 1361 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1362 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1363 MSI_RETRANS_MASK_SEL_STD); 1364 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1365 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1366 MSI_RETRANS_MASK_SEL_LINE); 1367 else 1368 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0); 1369 } 1370 } 1371 1372 static int 1373 alc_attach(device_t dev) 1374 { 1375 struct alc_softc *sc; 1376 if_t ifp; 1377 int base, error, i, msic, msixc; 1378 uint16_t burst; 1379 1380 error = 0; 1381 sc = device_get_softc(dev); 1382 sc->alc_dev = dev; 1383 sc->alc_rev = pci_get_revid(dev); 1384 1385 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1386 MTX_DEF); 1387 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0); 1388 NET_TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 1389 sc->alc_ident = alc_find_ident(dev); 1390 1391 /* Map the device. */ 1392 pci_enable_busmaster(dev); 1393 sc->alc_res_spec = alc_res_spec_mem; 1394 sc->alc_irq_spec = alc_irq_spec_legacy; 1395 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 1396 if (error != 0) { 1397 device_printf(dev, "cannot allocate memory resources.\n"); 1398 goto fail; 1399 } 1400 1401 /* Set PHY address. */ 1402 sc->alc_phyaddr = ALC_PHY_ADDR; 1403 1404 /* 1405 * One odd thing is AR8132 uses the same PHY hardware(F1 1406 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1407 * the PHY supports 1000Mbps but that's not true. The PHY 1408 * used in AR8132 can't establish gigabit link even if it 1409 * shows the same PHY model/revision number of AR8131. 1410 */ 1411 switch (sc->alc_ident->deviceid) { 1412 case DEVICEID_ATHEROS_E2200: 1413 case DEVICEID_ATHEROS_E2400: 1414 case DEVICEID_ATHEROS_E2500: 1415 sc->alc_flags |= ALC_FLAG_E2X00; 1416 /* FALLTHROUGH */ 1417 case DEVICEID_ATHEROS_AR8161: 1418 if (pci_get_subvendor(dev) == VENDORID_ATHEROS && 1419 pci_get_subdevice(dev) == 0x0091 && sc->alc_rev == 0) 1420 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1421 /* FALLTHROUGH */ 1422 case DEVICEID_ATHEROS_AR8171: 1423 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1424 break; 1425 case DEVICEID_ATHEROS_AR8162: 1426 case DEVICEID_ATHEROS_AR8172: 1427 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1428 break; 1429 case DEVICEID_ATHEROS_AR8152_B: 1430 case DEVICEID_ATHEROS_AR8152_B2: 1431 sc->alc_flags |= ALC_FLAG_APS; 1432 /* FALLTHROUGH */ 1433 case DEVICEID_ATHEROS_AR8132: 1434 sc->alc_flags |= ALC_FLAG_FASTETHER; 1435 break; 1436 case DEVICEID_ATHEROS_AR8151: 1437 case DEVICEID_ATHEROS_AR8151_V2: 1438 sc->alc_flags |= ALC_FLAG_APS; 1439 if (CSR_READ_4(sc, ALC_MT_MAGIC) == MT_MAGIC) 1440 sc->alc_flags |= ALC_FLAG_MT; 1441 /* FALLTHROUGH */ 1442 default: 1443 break; 1444 } 1445 sc->alc_flags |= ALC_FLAG_JUMBO; 1446 1447 /* 1448 * It seems that AR813x/AR815x has silicon bug for SMB. In 1449 * addition, Atheros said that enabling SMB wouldn't improve 1450 * performance. However I think it's bad to access lots of 1451 * registers to extract MAC statistics. 1452 */ 1453 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1454 /* 1455 * Don't use Tx CMB. It is known to have silicon bug. 1456 */ 1457 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1458 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1459 MASTER_CHIP_REV_SHIFT; 1460 if (bootverbose) { 1461 device_printf(dev, "PCI device revision : 0x%04x\n", 1462 sc->alc_rev); 1463 device_printf(dev, "Chip id/revision : 0x%04x\n", 1464 sc->alc_chip_rev); 1465 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1466 device_printf(dev, "AR816x revision : 0x%x\n", 1467 AR816X_REV(sc->alc_rev)); 1468 } 1469 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 1470 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1471 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1472 1473 /* Initialize DMA parameters. */ 1474 sc->alc_dma_rd_burst = 0; 1475 sc->alc_dma_wr_burst = 0; 1476 sc->alc_rcb = DMA_CFG_RCB_64; 1477 if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) { 1478 sc->alc_flags |= ALC_FLAG_PCIE; 1479 sc->alc_expcap = base; 1480 burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL); 1481 sc->alc_dma_rd_burst = 1482 (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12; 1483 sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5; 1484 if (bootverbose) { 1485 device_printf(dev, "Read request size : %u bytes.\n", 1486 alc_dma_burst[sc->alc_dma_rd_burst]); 1487 device_printf(dev, "TLP payload size : %u bytes.\n", 1488 alc_dma_burst[sc->alc_dma_wr_burst]); 1489 } 1490 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1491 sc->alc_dma_rd_burst = 3; 1492 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1493 sc->alc_dma_wr_burst = 3; 1494 /* 1495 * Force maximum payload size to 128 bytes for 1496 * E2200/E2400/E2500/AR8162/AR8171/AR8172. 1497 * Otherwise it triggers DMA write error. 1498 */ 1499 if ((sc->alc_flags & 1500 (ALC_FLAG_E2X00 | ALC_FLAG_AR816X_FAMILY)) != 0) 1501 sc->alc_dma_wr_burst = 0; 1502 alc_init_pcie(sc); 1503 } 1504 1505 /* Reset PHY. */ 1506 alc_phy_reset(sc); 1507 1508 /* Reset the ethernet controller. */ 1509 alc_stop_mac(sc); 1510 alc_reset(sc); 1511 1512 /* Allocate IRQ resources. */ 1513 msixc = pci_msix_count(dev); 1514 msic = pci_msi_count(dev); 1515 if (bootverbose) { 1516 device_printf(dev, "MSIX count : %d\n", msixc); 1517 device_printf(dev, "MSI count : %d\n", msic); 1518 } 1519 if (msixc > 1) 1520 msixc = 1; 1521 if (msic > 1) 1522 msic = 1; 1523 /* 1524 * Prefer MSIX over MSI. 1525 * AR816x controller has a silicon bug that MSI interrupt 1526 * does not assert if PCIM_CMD_INTxDIS bit of command 1527 * register is set. pci(4) was taught to handle that case. 1528 */ 1529 if (msix_disable == 0 || msi_disable == 0) { 1530 if (msix_disable == 0 && msixc > 0 && 1531 pci_alloc_msix(dev, &msixc) == 0) { 1532 if (msic == 1) { 1533 device_printf(dev, 1534 "Using %d MSIX message(s).\n", msixc); 1535 sc->alc_flags |= ALC_FLAG_MSIX; 1536 sc->alc_irq_spec = alc_irq_spec_msix; 1537 } else 1538 pci_release_msi(dev); 1539 } 1540 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 1541 msic > 0 && pci_alloc_msi(dev, &msic) == 0) { 1542 if (msic == 1) { 1543 device_printf(dev, 1544 "Using %d MSI message(s).\n", msic); 1545 sc->alc_flags |= ALC_FLAG_MSI; 1546 sc->alc_irq_spec = alc_irq_spec_msi; 1547 } else 1548 pci_release_msi(dev); 1549 } 1550 } 1551 1552 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1553 if (error != 0) { 1554 device_printf(dev, "cannot allocate IRQ resources.\n"); 1555 goto fail; 1556 } 1557 1558 /* Create device sysctl node. */ 1559 alc_sysctl_node(sc); 1560 1561 if ((error = alc_dma_alloc(sc)) != 0) 1562 goto fail; 1563 1564 /* Load station address. */ 1565 alc_get_macaddr(sc); 1566 1567 ifp = sc->alc_ifp = if_alloc(IFT_ETHER); 1568 if (ifp == NULL) { 1569 device_printf(dev, "cannot allocate ifnet structure.\n"); 1570 error = ENXIO; 1571 goto fail; 1572 } 1573 1574 if_setsoftc(ifp, sc); 1575 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1576 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1577 if_setioctlfn(ifp, alc_ioctl); 1578 if_setstartfn(ifp, alc_start); 1579 if_setinitfn(ifp, alc_init); 1580 if_setsendqlen(ifp, ALC_TX_RING_CNT - 1); 1581 if_setsendqready(ifp); 1582 if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_TSO4); 1583 if_sethwassist(ifp, ALC_CSUM_FEATURES | CSUM_TSO); 1584 if (pci_find_cap(dev, PCIY_PMG, &base) == 0) { 1585 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST, 0); 1586 sc->alc_flags |= ALC_FLAG_PM; 1587 sc->alc_pmcap = base; 1588 } 1589 if_setcapenable(ifp, if_getcapabilities(ifp)); 1590 1591 /* Set up MII bus. */ 1592 error = mii_attach(dev, &sc->alc_miibus, ifp, alc_mediachange, 1593 alc_mediastatus, BMSR_DEFCAPMASK, sc->alc_phyaddr, MII_OFFSET_ANY, 1594 MIIF_DOPAUSE); 1595 if (error != 0) { 1596 device_printf(dev, "attaching PHYs failed\n"); 1597 goto fail; 1598 } 1599 1600 ether_ifattach(ifp, sc->alc_eaddr); 1601 1602 /* VLAN capability setup. */ 1603 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 1604 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 1605 if_setcapenable(ifp, if_getcapabilities(ifp)); 1606 /* 1607 * XXX 1608 * It seems enabling Tx checksum offloading makes more trouble. 1609 * Sometimes the controller does not receive any frames when 1610 * Tx checksum offloading is enabled. I'm not sure whether this 1611 * is a bug in Tx checksum offloading logic or I got broken 1612 * sample boards. To safety, don't enable Tx checksum offloading 1613 * by default but give chance to users to toggle it if they know 1614 * their controllers work without problems. 1615 * Fortunately, Tx checksum offloading for AR816x family 1616 * seems to work. 1617 */ 1618 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1619 if_setcapenablebit(ifp, 0, IFCAP_TXCSUM); 1620 if_sethwassistbits(ifp, 0, ALC_CSUM_FEATURES); 1621 } 1622 1623 /* Tell the upper layer(s) we support long frames. */ 1624 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 1625 1626 /* Create local taskq. */ 1627 sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK, 1628 taskqueue_thread_enqueue, &sc->alc_tq); 1629 if (sc->alc_tq == NULL) { 1630 device_printf(dev, "could not create taskqueue.\n"); 1631 ether_ifdetach(ifp); 1632 error = ENXIO; 1633 goto fail; 1634 } 1635 taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq", 1636 device_get_nameunit(sc->alc_dev)); 1637 1638 alc_config_msi(sc); 1639 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1640 msic = ALC_MSIX_MESSAGES; 1641 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1642 msic = ALC_MSI_MESSAGES; 1643 else 1644 msic = 1; 1645 for (i = 0; i < msic; i++) { 1646 error = bus_setup_intr(dev, sc->alc_irq[i], 1647 INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc, 1648 &sc->alc_intrhand[i]); 1649 if (error != 0) 1650 break; 1651 } 1652 if (error != 0) { 1653 device_printf(dev, "could not set up interrupt handler.\n"); 1654 taskqueue_free(sc->alc_tq); 1655 sc->alc_tq = NULL; 1656 ether_ifdetach(ifp); 1657 goto fail; 1658 } 1659 1660 /* Attach driver debugnet methods. */ 1661 DEBUGNET_SET(ifp, alc); 1662 1663 fail: 1664 if (error != 0) 1665 alc_detach(dev); 1666 1667 return (error); 1668 } 1669 1670 static int 1671 alc_detach(device_t dev) 1672 { 1673 struct alc_softc *sc; 1674 if_t ifp; 1675 int i, msic; 1676 1677 sc = device_get_softc(dev); 1678 1679 ifp = sc->alc_ifp; 1680 if (device_is_attached(dev)) { 1681 ether_ifdetach(ifp); 1682 ALC_LOCK(sc); 1683 alc_stop(sc); 1684 ALC_UNLOCK(sc); 1685 callout_drain(&sc->alc_tick_ch); 1686 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1687 } 1688 1689 if (sc->alc_tq != NULL) { 1690 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1691 taskqueue_free(sc->alc_tq); 1692 sc->alc_tq = NULL; 1693 } 1694 1695 if (sc->alc_miibus != NULL) { 1696 device_delete_child(dev, sc->alc_miibus); 1697 sc->alc_miibus = NULL; 1698 } 1699 bus_generic_detach(dev); 1700 alc_dma_free(sc); 1701 1702 if (ifp != NULL) { 1703 if_free(ifp); 1704 sc->alc_ifp = NULL; 1705 } 1706 1707 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1708 msic = ALC_MSIX_MESSAGES; 1709 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1710 msic = ALC_MSI_MESSAGES; 1711 else 1712 msic = 1; 1713 for (i = 0; i < msic; i++) { 1714 if (sc->alc_intrhand[i] != NULL) { 1715 bus_teardown_intr(dev, sc->alc_irq[i], 1716 sc->alc_intrhand[i]); 1717 sc->alc_intrhand[i] = NULL; 1718 } 1719 } 1720 if (sc->alc_res[0] != NULL) 1721 alc_phy_down(sc); 1722 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1723 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 1724 pci_release_msi(dev); 1725 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 1726 mtx_destroy(&sc->alc_mtx); 1727 1728 return (0); 1729 } 1730 1731 #define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 1732 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1733 #define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 1734 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 1735 1736 static void 1737 alc_sysctl_node(struct alc_softc *sc) 1738 { 1739 struct sysctl_ctx_list *ctx; 1740 struct sysctl_oid_list *child, *parent; 1741 struct sysctl_oid *tree; 1742 struct alc_hw_stats *stats; 1743 int error; 1744 1745 stats = &sc->alc_stats; 1746 ctx = device_get_sysctl_ctx(sc->alc_dev); 1747 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev)); 1748 1749 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 1750 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->alc_int_rx_mod, 1751 0, sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 1752 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 1753 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->alc_int_tx_mod, 1754 0, sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 1755 /* Pull in device tunables. */ 1756 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1757 error = resource_int_value(device_get_name(sc->alc_dev), 1758 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 1759 if (error == 0) { 1760 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 1761 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 1762 device_printf(sc->alc_dev, "int_rx_mod value out of " 1763 "range; using default: %d\n", 1764 ALC_IM_RX_TIMER_DEFAULT); 1765 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1766 } 1767 } 1768 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1769 error = resource_int_value(device_get_name(sc->alc_dev), 1770 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 1771 if (error == 0) { 1772 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 1773 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 1774 device_printf(sc->alc_dev, "int_tx_mod value out of " 1775 "range; using default: %d\n", 1776 ALC_IM_TX_TIMER_DEFAULT); 1777 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1778 } 1779 } 1780 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1781 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1782 &sc->alc_process_limit, 0, sysctl_hw_alc_proc_limit, "I", 1783 "max number of Rx events to process"); 1784 /* Pull in device tunables. */ 1785 sc->alc_process_limit = ALC_PROC_DEFAULT; 1786 error = resource_int_value(device_get_name(sc->alc_dev), 1787 device_get_unit(sc->alc_dev), "process_limit", 1788 &sc->alc_process_limit); 1789 if (error == 0) { 1790 if (sc->alc_process_limit < ALC_PROC_MIN || 1791 sc->alc_process_limit > ALC_PROC_MAX) { 1792 device_printf(sc->alc_dev, 1793 "process_limit value out of range; " 1794 "using default: %d\n", ALC_PROC_DEFAULT); 1795 sc->alc_process_limit = ALC_PROC_DEFAULT; 1796 } 1797 } 1798 1799 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 1800 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ALC statistics"); 1801 parent = SYSCTL_CHILDREN(tree); 1802 1803 /* Rx statistics. */ 1804 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 1805 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 1806 child = SYSCTL_CHILDREN(tree); 1807 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1808 &stats->rx_frames, "Good frames"); 1809 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1810 &stats->rx_bcast_frames, "Good broadcast frames"); 1811 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1812 &stats->rx_mcast_frames, "Good multicast frames"); 1813 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1814 &stats->rx_pause_frames, "Pause control frames"); 1815 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1816 &stats->rx_control_frames, "Control frames"); 1817 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1818 &stats->rx_crcerrs, "CRC errors"); 1819 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1820 &stats->rx_lenerrs, "Frames with length mismatched"); 1821 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1822 &stats->rx_bytes, "Good octets"); 1823 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1824 &stats->rx_bcast_bytes, "Good broadcast octets"); 1825 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1826 &stats->rx_mcast_bytes, "Good multicast octets"); 1827 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 1828 &stats->rx_runts, "Too short frames"); 1829 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 1830 &stats->rx_fragments, "Fragmented frames"); 1831 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1832 &stats->rx_pkts_64, "64 bytes frames"); 1833 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1834 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 1835 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1836 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 1837 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1838 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 1839 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1840 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 1841 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1842 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1843 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1844 &stats->rx_pkts_1519_max, "1519 to max frames"); 1845 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1846 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1847 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1848 &stats->rx_fifo_oflows, "FIFO overflows"); 1849 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1850 &stats->rx_rrs_errs, "Return status write-back errors"); 1851 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1852 &stats->rx_alignerrs, "Alignment errors"); 1853 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1854 &stats->rx_pkts_filtered, 1855 "Frames dropped due to address filtering"); 1856 1857 /* Tx statistics. */ 1858 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 1859 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 1860 child = SYSCTL_CHILDREN(tree); 1861 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1862 &stats->tx_frames, "Good frames"); 1863 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1864 &stats->tx_bcast_frames, "Good broadcast frames"); 1865 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1866 &stats->tx_mcast_frames, "Good multicast frames"); 1867 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1868 &stats->tx_pause_frames, "Pause control frames"); 1869 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1870 &stats->tx_control_frames, "Control frames"); 1871 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1872 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1873 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1874 &stats->tx_excess_defer, "Frames with derferrals"); 1875 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1876 &stats->tx_bytes, "Good octets"); 1877 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1878 &stats->tx_bcast_bytes, "Good broadcast octets"); 1879 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1880 &stats->tx_mcast_bytes, "Good multicast octets"); 1881 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1882 &stats->tx_pkts_64, "64 bytes frames"); 1883 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1884 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1885 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1886 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1887 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1888 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1889 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1890 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1891 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1892 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1893 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1894 &stats->tx_pkts_1519_max, "1519 to max frames"); 1895 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1896 &stats->tx_single_colls, "Single collisions"); 1897 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1898 &stats->tx_multi_colls, "Multiple collisions"); 1899 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1900 &stats->tx_late_colls, "Late collisions"); 1901 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1902 &stats->tx_excess_colls, "Excessive collisions"); 1903 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1904 &stats->tx_underrun, "FIFO underruns"); 1905 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1906 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1907 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1908 &stats->tx_lenerrs, "Frames with length mismatched"); 1909 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1910 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1911 } 1912 1913 #undef ALC_SYSCTL_STAT_ADD32 1914 #undef ALC_SYSCTL_STAT_ADD64 1915 1916 struct alc_dmamap_arg { 1917 bus_addr_t alc_busaddr; 1918 }; 1919 1920 static void 1921 alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1922 { 1923 struct alc_dmamap_arg *ctx; 1924 1925 if (error != 0) 1926 return; 1927 1928 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1929 1930 ctx = (struct alc_dmamap_arg *)arg; 1931 ctx->alc_busaddr = segs[0].ds_addr; 1932 } 1933 1934 /* 1935 * Normal and high Tx descriptors shares single Tx high address. 1936 * Four Rx descriptor/return rings and CMB shares the same Rx 1937 * high address. 1938 */ 1939 static int 1940 alc_check_boundary(struct alc_softc *sc) 1941 { 1942 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1943 1944 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1945 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1946 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1947 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1948 1949 /* 4GB boundary crossing is not allowed. */ 1950 if ((ALC_ADDR_HI(rx_ring_end) != 1951 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1952 (ALC_ADDR_HI(rr_ring_end) != 1953 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1954 (ALC_ADDR_HI(cmb_end) != 1955 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1956 (ALC_ADDR_HI(tx_ring_end) != 1957 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1958 return (EFBIG); 1959 /* 1960 * Make sure Rx return descriptor/Rx descriptor/CMB use 1961 * the same high address. 1962 */ 1963 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1964 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1965 return (EFBIG); 1966 1967 return (0); 1968 } 1969 1970 static int 1971 alc_dma_alloc(struct alc_softc *sc) 1972 { 1973 struct alc_txdesc *txd; 1974 struct alc_rxdesc *rxd; 1975 bus_addr_t lowaddr; 1976 struct alc_dmamap_arg ctx; 1977 int error, i; 1978 1979 lowaddr = BUS_SPACE_MAXADDR; 1980 if (sc->alc_flags & ALC_FLAG_MT) 1981 lowaddr = BUS_SPACE_MAXSIZE_32BIT; 1982 again: 1983 /* Create parent DMA tag. */ 1984 error = bus_dma_tag_create( 1985 bus_get_dma_tag(sc->alc_dev), /* parent */ 1986 1, 0, /* alignment, boundary */ 1987 lowaddr, /* lowaddr */ 1988 BUS_SPACE_MAXADDR, /* highaddr */ 1989 NULL, NULL, /* filter, filterarg */ 1990 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1991 0, /* nsegments */ 1992 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1993 0, /* flags */ 1994 NULL, NULL, /* lockfunc, lockarg */ 1995 &sc->alc_cdata.alc_parent_tag); 1996 if (error != 0) { 1997 device_printf(sc->alc_dev, 1998 "could not create parent DMA tag.\n"); 1999 goto fail; 2000 } 2001 2002 /* Create DMA tag for Tx descriptor ring. */ 2003 error = bus_dma_tag_create( 2004 sc->alc_cdata.alc_parent_tag, /* parent */ 2005 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 2006 BUS_SPACE_MAXADDR, /* lowaddr */ 2007 BUS_SPACE_MAXADDR, /* highaddr */ 2008 NULL, NULL, /* filter, filterarg */ 2009 ALC_TX_RING_SZ, /* maxsize */ 2010 1, /* nsegments */ 2011 ALC_TX_RING_SZ, /* maxsegsize */ 2012 0, /* flags */ 2013 NULL, NULL, /* lockfunc, lockarg */ 2014 &sc->alc_cdata.alc_tx_ring_tag); 2015 if (error != 0) { 2016 device_printf(sc->alc_dev, 2017 "could not create Tx ring DMA tag.\n"); 2018 goto fail; 2019 } 2020 2021 /* Create DMA tag for Rx free descriptor ring. */ 2022 error = bus_dma_tag_create( 2023 sc->alc_cdata.alc_parent_tag, /* parent */ 2024 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 2025 BUS_SPACE_MAXADDR, /* lowaddr */ 2026 BUS_SPACE_MAXADDR, /* highaddr */ 2027 NULL, NULL, /* filter, filterarg */ 2028 ALC_RX_RING_SZ, /* maxsize */ 2029 1, /* nsegments */ 2030 ALC_RX_RING_SZ, /* maxsegsize */ 2031 0, /* flags */ 2032 NULL, NULL, /* lockfunc, lockarg */ 2033 &sc->alc_cdata.alc_rx_ring_tag); 2034 if (error != 0) { 2035 device_printf(sc->alc_dev, 2036 "could not create Rx ring DMA tag.\n"); 2037 goto fail; 2038 } 2039 /* Create DMA tag for Rx return descriptor ring. */ 2040 error = bus_dma_tag_create( 2041 sc->alc_cdata.alc_parent_tag, /* parent */ 2042 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 2043 BUS_SPACE_MAXADDR, /* lowaddr */ 2044 BUS_SPACE_MAXADDR, /* highaddr */ 2045 NULL, NULL, /* filter, filterarg */ 2046 ALC_RR_RING_SZ, /* maxsize */ 2047 1, /* nsegments */ 2048 ALC_RR_RING_SZ, /* maxsegsize */ 2049 0, /* flags */ 2050 NULL, NULL, /* lockfunc, lockarg */ 2051 &sc->alc_cdata.alc_rr_ring_tag); 2052 if (error != 0) { 2053 device_printf(sc->alc_dev, 2054 "could not create Rx return ring DMA tag.\n"); 2055 goto fail; 2056 } 2057 2058 /* Create DMA tag for coalescing message block. */ 2059 error = bus_dma_tag_create( 2060 sc->alc_cdata.alc_parent_tag, /* parent */ 2061 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 2062 BUS_SPACE_MAXADDR, /* lowaddr */ 2063 BUS_SPACE_MAXADDR, /* highaddr */ 2064 NULL, NULL, /* filter, filterarg */ 2065 ALC_CMB_SZ, /* maxsize */ 2066 1, /* nsegments */ 2067 ALC_CMB_SZ, /* maxsegsize */ 2068 0, /* flags */ 2069 NULL, NULL, /* lockfunc, lockarg */ 2070 &sc->alc_cdata.alc_cmb_tag); 2071 if (error != 0) { 2072 device_printf(sc->alc_dev, 2073 "could not create CMB DMA tag.\n"); 2074 goto fail; 2075 } 2076 /* Create DMA tag for status message block. */ 2077 error = bus_dma_tag_create( 2078 sc->alc_cdata.alc_parent_tag, /* parent */ 2079 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 2080 BUS_SPACE_MAXADDR, /* lowaddr */ 2081 BUS_SPACE_MAXADDR, /* highaddr */ 2082 NULL, NULL, /* filter, filterarg */ 2083 ALC_SMB_SZ, /* maxsize */ 2084 1, /* nsegments */ 2085 ALC_SMB_SZ, /* maxsegsize */ 2086 0, /* flags */ 2087 NULL, NULL, /* lockfunc, lockarg */ 2088 &sc->alc_cdata.alc_smb_tag); 2089 if (error != 0) { 2090 device_printf(sc->alc_dev, 2091 "could not create SMB DMA tag.\n"); 2092 goto fail; 2093 } 2094 2095 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2096 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 2097 (void **)&sc->alc_rdata.alc_tx_ring, 2098 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2099 &sc->alc_cdata.alc_tx_ring_map); 2100 if (error != 0) { 2101 device_printf(sc->alc_dev, 2102 "could not allocate DMA'able memory for Tx ring.\n"); 2103 goto fail; 2104 } 2105 ctx.alc_busaddr = 0; 2106 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 2107 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 2108 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2109 if (error != 0 || ctx.alc_busaddr == 0) { 2110 device_printf(sc->alc_dev, 2111 "could not load DMA'able memory for Tx ring.\n"); 2112 goto fail; 2113 } 2114 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 2115 2116 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2117 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 2118 (void **)&sc->alc_rdata.alc_rx_ring, 2119 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2120 &sc->alc_cdata.alc_rx_ring_map); 2121 if (error != 0) { 2122 device_printf(sc->alc_dev, 2123 "could not allocate DMA'able memory for Rx ring.\n"); 2124 goto fail; 2125 } 2126 ctx.alc_busaddr = 0; 2127 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 2128 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 2129 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2130 if (error != 0 || ctx.alc_busaddr == 0) { 2131 device_printf(sc->alc_dev, 2132 "could not load DMA'able memory for Rx ring.\n"); 2133 goto fail; 2134 } 2135 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 2136 2137 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 2138 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 2139 (void **)&sc->alc_rdata.alc_rr_ring, 2140 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2141 &sc->alc_cdata.alc_rr_ring_map); 2142 if (error != 0) { 2143 device_printf(sc->alc_dev, 2144 "could not allocate DMA'able memory for Rx return ring.\n"); 2145 goto fail; 2146 } 2147 ctx.alc_busaddr = 0; 2148 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 2149 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 2150 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 2151 if (error != 0 || ctx.alc_busaddr == 0) { 2152 device_printf(sc->alc_dev, 2153 "could not load DMA'able memory for Tx ring.\n"); 2154 goto fail; 2155 } 2156 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 2157 2158 /* Allocate DMA'able memory and load the DMA map for CMB. */ 2159 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 2160 (void **)&sc->alc_rdata.alc_cmb, 2161 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2162 &sc->alc_cdata.alc_cmb_map); 2163 if (error != 0) { 2164 device_printf(sc->alc_dev, 2165 "could not allocate DMA'able memory for CMB.\n"); 2166 goto fail; 2167 } 2168 ctx.alc_busaddr = 0; 2169 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 2170 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 2171 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 2172 if (error != 0 || ctx.alc_busaddr == 0) { 2173 device_printf(sc->alc_dev, 2174 "could not load DMA'able memory for CMB.\n"); 2175 goto fail; 2176 } 2177 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 2178 2179 /* Allocate DMA'able memory and load the DMA map for SMB. */ 2180 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 2181 (void **)&sc->alc_rdata.alc_smb, 2182 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2183 &sc->alc_cdata.alc_smb_map); 2184 if (error != 0) { 2185 device_printf(sc->alc_dev, 2186 "could not allocate DMA'able memory for SMB.\n"); 2187 goto fail; 2188 } 2189 ctx.alc_busaddr = 0; 2190 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 2191 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 2192 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 2193 if (error != 0 || ctx.alc_busaddr == 0) { 2194 device_printf(sc->alc_dev, 2195 "could not load DMA'able memory for CMB.\n"); 2196 goto fail; 2197 } 2198 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 2199 2200 /* Make sure we've not crossed 4GB boundary. */ 2201 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 2202 (error = alc_check_boundary(sc)) != 0) { 2203 device_printf(sc->alc_dev, "4GB boundary crossed, " 2204 "switching to 32bit DMA addressing mode.\n"); 2205 alc_dma_free(sc); 2206 /* 2207 * Limit max allowable DMA address space to 32bit 2208 * and try again. 2209 */ 2210 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2211 goto again; 2212 } 2213 2214 /* 2215 * Create Tx buffer parent tag. 2216 * AR81[3567]x allows 64bit DMA addressing of Tx/Rx buffers 2217 * so it needs separate parent DMA tag as parent DMA address 2218 * space could be restricted to be within 32bit address space 2219 * by 4GB boundary crossing. 2220 */ 2221 error = bus_dma_tag_create( 2222 bus_get_dma_tag(sc->alc_dev), /* parent */ 2223 1, 0, /* alignment, boundary */ 2224 lowaddr, /* lowaddr */ 2225 BUS_SPACE_MAXADDR, /* highaddr */ 2226 NULL, NULL, /* filter, filterarg */ 2227 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2228 0, /* nsegments */ 2229 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2230 0, /* flags */ 2231 NULL, NULL, /* lockfunc, lockarg */ 2232 &sc->alc_cdata.alc_buffer_tag); 2233 if (error != 0) { 2234 device_printf(sc->alc_dev, 2235 "could not create parent buffer DMA tag.\n"); 2236 goto fail; 2237 } 2238 2239 /* Create DMA tag for Tx buffers. */ 2240 error = bus_dma_tag_create( 2241 sc->alc_cdata.alc_buffer_tag, /* parent */ 2242 1, 0, /* alignment, boundary */ 2243 BUS_SPACE_MAXADDR, /* lowaddr */ 2244 BUS_SPACE_MAXADDR, /* highaddr */ 2245 NULL, NULL, /* filter, filterarg */ 2246 ALC_TSO_MAXSIZE, /* maxsize */ 2247 ALC_MAXTXSEGS, /* nsegments */ 2248 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 2249 0, /* flags */ 2250 NULL, NULL, /* lockfunc, lockarg */ 2251 &sc->alc_cdata.alc_tx_tag); 2252 if (error != 0) { 2253 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 2254 goto fail; 2255 } 2256 2257 /* Create DMA tag for Rx buffers. */ 2258 error = bus_dma_tag_create( 2259 sc->alc_cdata.alc_buffer_tag, /* parent */ 2260 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 2261 BUS_SPACE_MAXADDR, /* lowaddr */ 2262 BUS_SPACE_MAXADDR, /* highaddr */ 2263 NULL, NULL, /* filter, filterarg */ 2264 MCLBYTES, /* maxsize */ 2265 1, /* nsegments */ 2266 MCLBYTES, /* maxsegsize */ 2267 0, /* flags */ 2268 NULL, NULL, /* lockfunc, lockarg */ 2269 &sc->alc_cdata.alc_rx_tag); 2270 if (error != 0) { 2271 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 2272 goto fail; 2273 } 2274 /* Create DMA maps for Tx buffers. */ 2275 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2276 txd = &sc->alc_cdata.alc_txdesc[i]; 2277 txd->tx_m = NULL; 2278 txd->tx_dmamap = NULL; 2279 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0, 2280 &txd->tx_dmamap); 2281 if (error != 0) { 2282 device_printf(sc->alc_dev, 2283 "could not create Tx dmamap.\n"); 2284 goto fail; 2285 } 2286 } 2287 /* Create DMA maps for Rx buffers. */ 2288 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2289 &sc->alc_cdata.alc_rx_sparemap)) != 0) { 2290 device_printf(sc->alc_dev, 2291 "could not create spare Rx dmamap.\n"); 2292 goto fail; 2293 } 2294 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2295 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2296 rxd->rx_m = NULL; 2297 rxd->rx_dmamap = NULL; 2298 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2299 &rxd->rx_dmamap); 2300 if (error != 0) { 2301 device_printf(sc->alc_dev, 2302 "could not create Rx dmamap.\n"); 2303 goto fail; 2304 } 2305 } 2306 2307 fail: 2308 return (error); 2309 } 2310 2311 static void 2312 alc_dma_free(struct alc_softc *sc) 2313 { 2314 struct alc_txdesc *txd; 2315 struct alc_rxdesc *rxd; 2316 int i; 2317 2318 /* Tx buffers. */ 2319 if (sc->alc_cdata.alc_tx_tag != NULL) { 2320 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2321 txd = &sc->alc_cdata.alc_txdesc[i]; 2322 if (txd->tx_dmamap != NULL) { 2323 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 2324 txd->tx_dmamap); 2325 txd->tx_dmamap = NULL; 2326 } 2327 } 2328 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 2329 sc->alc_cdata.alc_tx_tag = NULL; 2330 } 2331 /* Rx buffers */ 2332 if (sc->alc_cdata.alc_rx_tag != NULL) { 2333 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2334 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2335 if (rxd->rx_dmamap != NULL) { 2336 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2337 rxd->rx_dmamap); 2338 rxd->rx_dmamap = NULL; 2339 } 2340 } 2341 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 2342 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2343 sc->alc_cdata.alc_rx_sparemap); 2344 sc->alc_cdata.alc_rx_sparemap = NULL; 2345 } 2346 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 2347 sc->alc_cdata.alc_rx_tag = NULL; 2348 } 2349 /* Tx descriptor ring. */ 2350 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 2351 if (sc->alc_rdata.alc_tx_ring_paddr != 0) 2352 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 2353 sc->alc_cdata.alc_tx_ring_map); 2354 if (sc->alc_rdata.alc_tx_ring != NULL) 2355 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 2356 sc->alc_rdata.alc_tx_ring, 2357 sc->alc_cdata.alc_tx_ring_map); 2358 sc->alc_rdata.alc_tx_ring_paddr = 0; 2359 sc->alc_rdata.alc_tx_ring = NULL; 2360 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 2361 sc->alc_cdata.alc_tx_ring_tag = NULL; 2362 } 2363 /* Rx ring. */ 2364 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 2365 if (sc->alc_rdata.alc_rx_ring_paddr != 0) 2366 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 2367 sc->alc_cdata.alc_rx_ring_map); 2368 if (sc->alc_rdata.alc_rx_ring != NULL) 2369 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 2370 sc->alc_rdata.alc_rx_ring, 2371 sc->alc_cdata.alc_rx_ring_map); 2372 sc->alc_rdata.alc_rx_ring_paddr = 0; 2373 sc->alc_rdata.alc_rx_ring = NULL; 2374 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 2375 sc->alc_cdata.alc_rx_ring_tag = NULL; 2376 } 2377 /* Rx return ring. */ 2378 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 2379 if (sc->alc_rdata.alc_rr_ring_paddr != 0) 2380 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 2381 sc->alc_cdata.alc_rr_ring_map); 2382 if (sc->alc_rdata.alc_rr_ring != NULL) 2383 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 2384 sc->alc_rdata.alc_rr_ring, 2385 sc->alc_cdata.alc_rr_ring_map); 2386 sc->alc_rdata.alc_rr_ring_paddr = 0; 2387 sc->alc_rdata.alc_rr_ring = NULL; 2388 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 2389 sc->alc_cdata.alc_rr_ring_tag = NULL; 2390 } 2391 /* CMB block */ 2392 if (sc->alc_cdata.alc_cmb_tag != NULL) { 2393 if (sc->alc_rdata.alc_cmb_paddr != 0) 2394 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 2395 sc->alc_cdata.alc_cmb_map); 2396 if (sc->alc_rdata.alc_cmb != NULL) 2397 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 2398 sc->alc_rdata.alc_cmb, 2399 sc->alc_cdata.alc_cmb_map); 2400 sc->alc_rdata.alc_cmb_paddr = 0; 2401 sc->alc_rdata.alc_cmb = NULL; 2402 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 2403 sc->alc_cdata.alc_cmb_tag = NULL; 2404 } 2405 /* SMB block */ 2406 if (sc->alc_cdata.alc_smb_tag != NULL) { 2407 if (sc->alc_rdata.alc_smb_paddr != 0) 2408 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 2409 sc->alc_cdata.alc_smb_map); 2410 if (sc->alc_rdata.alc_smb != NULL) 2411 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 2412 sc->alc_rdata.alc_smb, 2413 sc->alc_cdata.alc_smb_map); 2414 sc->alc_rdata.alc_smb_paddr = 0; 2415 sc->alc_rdata.alc_smb = NULL; 2416 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 2417 sc->alc_cdata.alc_smb_tag = NULL; 2418 } 2419 if (sc->alc_cdata.alc_buffer_tag != NULL) { 2420 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 2421 sc->alc_cdata.alc_buffer_tag = NULL; 2422 } 2423 if (sc->alc_cdata.alc_parent_tag != NULL) { 2424 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 2425 sc->alc_cdata.alc_parent_tag = NULL; 2426 } 2427 } 2428 2429 static int 2430 alc_shutdown(device_t dev) 2431 { 2432 2433 return (alc_suspend(dev)); 2434 } 2435 2436 /* 2437 * Note, this driver resets the link speed to 10/100Mbps by 2438 * restarting auto-negotiation in suspend/shutdown phase but we 2439 * don't know whether that auto-negotiation would succeed or not 2440 * as driver has no control after powering off/suspend operation. 2441 * If the renegotiation fail WOL may not work. Running at 1Gbps 2442 * will draw more power than 375mA at 3.3V which is specified in 2443 * PCI specification and that would result in complete 2444 * shutdowning power to ethernet controller. 2445 * 2446 * TODO 2447 * Save current negotiated media speed/duplex/flow-control to 2448 * softc and restore the same link again after resuming. PHY 2449 * handling such as power down/resetting to 100Mbps may be better 2450 * handled in suspend method in phy driver. 2451 */ 2452 static void 2453 alc_setlinkspeed(struct alc_softc *sc) 2454 { 2455 struct mii_data *mii; 2456 int aneg, i; 2457 2458 mii = device_get_softc(sc->alc_miibus); 2459 mii_pollstat(mii); 2460 aneg = 0; 2461 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2462 (IFM_ACTIVE | IFM_AVALID)) { 2463 switch IFM_SUBTYPE(mii->mii_media_active) { 2464 case IFM_10_T: 2465 case IFM_100_TX: 2466 return; 2467 case IFM_1000_T: 2468 aneg++; 2469 break; 2470 default: 2471 break; 2472 } 2473 } 2474 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 2475 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2476 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 2477 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2478 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 2479 DELAY(1000); 2480 if (aneg != 0) { 2481 /* 2482 * Poll link state until alc(4) get a 10/100Mbps link. 2483 */ 2484 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 2485 mii_pollstat(mii); 2486 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 2487 == (IFM_ACTIVE | IFM_AVALID)) { 2488 switch (IFM_SUBTYPE( 2489 mii->mii_media_active)) { 2490 case IFM_10_T: 2491 case IFM_100_TX: 2492 alc_mac_config(sc); 2493 return; 2494 default: 2495 break; 2496 } 2497 } 2498 ALC_UNLOCK(sc); 2499 pause("alclnk", hz); 2500 ALC_LOCK(sc); 2501 } 2502 if (i == MII_ANEGTICKS_GIGE) 2503 device_printf(sc->alc_dev, 2504 "establishing a link failed, WOL may not work!"); 2505 } 2506 /* 2507 * No link, force MAC to have 100Mbps, full-duplex link. 2508 * This is the last resort and may/may not work. 2509 */ 2510 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 2511 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 2512 alc_mac_config(sc); 2513 } 2514 2515 static void 2516 alc_setwol(struct alc_softc *sc) 2517 { 2518 2519 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2520 alc_setwol_816x(sc); 2521 else 2522 alc_setwol_813x(sc); 2523 } 2524 2525 static void 2526 alc_setwol_813x(struct alc_softc *sc) 2527 { 2528 if_t ifp; 2529 uint32_t reg, pmcs; 2530 uint16_t pmstat; 2531 2532 ALC_LOCK_ASSERT(sc); 2533 2534 alc_disable_l0s_l1(sc); 2535 ifp = sc->alc_ifp; 2536 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2537 /* Disable WOL. */ 2538 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2539 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2540 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2541 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2542 /* Force PHY power down. */ 2543 alc_phy_down(sc); 2544 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2545 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2546 return; 2547 } 2548 2549 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 2550 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2551 alc_setlinkspeed(sc); 2552 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2553 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 2554 } 2555 2556 pmcs = 0; 2557 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2558 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2559 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2560 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2561 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2562 MAC_CFG_BCAST); 2563 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 2564 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2565 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2566 reg |= MAC_CFG_RX_ENB; 2567 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2568 2569 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2570 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2571 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2572 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) { 2573 /* WOL disabled, PHY power down. */ 2574 alc_phy_down(sc); 2575 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2576 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2577 } 2578 /* Request PME. */ 2579 pmstat = pci_read_config(sc->alc_dev, 2580 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2581 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2582 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2583 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2584 pci_write_config(sc->alc_dev, 2585 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2586 } 2587 2588 static void 2589 alc_setwol_816x(struct alc_softc *sc) 2590 { 2591 if_t ifp; 2592 uint32_t gphy, mac, master, pmcs, reg; 2593 uint16_t pmstat; 2594 2595 ALC_LOCK_ASSERT(sc); 2596 2597 ifp = sc->alc_ifp; 2598 master = CSR_READ_4(sc, ALC_MASTER_CFG); 2599 master &= ~MASTER_CLK_SEL_DIS; 2600 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 2601 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | GPHY_CFG_100AB_ENB | 2602 GPHY_CFG_PHY_PLL_ON); 2603 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET; 2604 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2605 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2606 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 2607 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2608 } else { 2609 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 2610 gphy |= GPHY_CFG_EXT_RESET; 2611 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2612 alc_setlinkspeed(sc); 2613 } 2614 pmcs = 0; 2615 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2616 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2617 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2618 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2619 mac &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2620 MAC_CFG_BCAST); 2621 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 2622 mac |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2623 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2624 mac |= MAC_CFG_RX_ENB; 2625 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 2626 ANEG_S3DIG10_SL); 2627 } 2628 2629 /* Enable OSC. */ 2630 reg = CSR_READ_4(sc, ALC_MISC); 2631 reg &= ~MISC_INTNLOSC_OPEN; 2632 CSR_WRITE_4(sc, ALC_MISC, reg); 2633 reg |= MISC_INTNLOSC_OPEN; 2634 CSR_WRITE_4(sc, ALC_MISC, reg); 2635 CSR_WRITE_4(sc, ALC_MASTER_CFG, master); 2636 CSR_WRITE_4(sc, ALC_MAC_CFG, mac); 2637 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 2638 reg = CSR_READ_4(sc, ALC_PDLL_TRNS1); 2639 reg |= PDLL_TRNS1_D3PLLOFF_ENB; 2640 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, reg); 2641 2642 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2643 /* Request PME. */ 2644 pmstat = pci_read_config(sc->alc_dev, 2645 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2646 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2647 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2648 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2649 pci_write_config(sc->alc_dev, 2650 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2651 } 2652 } 2653 2654 static int 2655 alc_suspend(device_t dev) 2656 { 2657 struct alc_softc *sc; 2658 2659 sc = device_get_softc(dev); 2660 2661 ALC_LOCK(sc); 2662 alc_stop(sc); 2663 alc_setwol(sc); 2664 ALC_UNLOCK(sc); 2665 2666 return (0); 2667 } 2668 2669 static int 2670 alc_resume(device_t dev) 2671 { 2672 struct alc_softc *sc; 2673 if_t ifp; 2674 uint16_t pmstat; 2675 2676 sc = device_get_softc(dev); 2677 2678 ALC_LOCK(sc); 2679 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2680 /* Disable PME and clear PME status. */ 2681 pmstat = pci_read_config(sc->alc_dev, 2682 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2683 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2684 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2685 pci_write_config(sc->alc_dev, 2686 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2687 } 2688 } 2689 /* Reset PHY. */ 2690 alc_phy_reset(sc); 2691 ifp = sc->alc_ifp; 2692 if ((if_getflags(ifp) & IFF_UP) != 0) { 2693 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2694 alc_init_locked(sc); 2695 } 2696 ALC_UNLOCK(sc); 2697 2698 return (0); 2699 } 2700 2701 static int 2702 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 2703 { 2704 struct alc_txdesc *txd, *txd_last; 2705 struct tx_desc *desc; 2706 struct mbuf *m; 2707 struct ip *ip; 2708 struct tcphdr *tcp; 2709 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 2710 bus_dmamap_t map; 2711 uint32_t cflags, hdrlen, ip_off, poff, vtag; 2712 int error, idx, nsegs, prod; 2713 2714 ALC_LOCK_ASSERT(sc); 2715 2716 M_ASSERTPKTHDR((*m_head)); 2717 2718 m = *m_head; 2719 ip = NULL; 2720 tcp = NULL; 2721 ip_off = poff = 0; 2722 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 2723 /* 2724 * AR81[3567]x requires offset of TCP/UDP header in its 2725 * Tx descriptor to perform Tx checksum offloading. TSO 2726 * also requires TCP header offset and modification of 2727 * IP/TCP header. This kind of operation takes many CPU 2728 * cycles on FreeBSD so fast host CPU is required to get 2729 * smooth TSO performance. 2730 */ 2731 struct ether_header *eh; 2732 2733 if (M_WRITABLE(m) == 0) { 2734 /* Get a writable copy. */ 2735 m = m_dup(*m_head, M_NOWAIT); 2736 /* Release original mbufs. */ 2737 m_freem(*m_head); 2738 if (m == NULL) { 2739 *m_head = NULL; 2740 return (ENOBUFS); 2741 } 2742 *m_head = m; 2743 } 2744 2745 ip_off = sizeof(struct ether_header); 2746 m = m_pullup(m, ip_off); 2747 if (m == NULL) { 2748 *m_head = NULL; 2749 return (ENOBUFS); 2750 } 2751 eh = mtod(m, struct ether_header *); 2752 /* 2753 * Check if hardware VLAN insertion is off. 2754 * Additional check for LLC/SNAP frame? 2755 */ 2756 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2757 ip_off = sizeof(struct ether_vlan_header); 2758 m = m_pullup(m, ip_off); 2759 if (m == NULL) { 2760 *m_head = NULL; 2761 return (ENOBUFS); 2762 } 2763 } 2764 m = m_pullup(m, ip_off + sizeof(struct ip)); 2765 if (m == NULL) { 2766 *m_head = NULL; 2767 return (ENOBUFS); 2768 } 2769 ip = (struct ip *)(mtod(m, char *) + ip_off); 2770 poff = ip_off + (ip->ip_hl << 2); 2771 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2772 m = m_pullup(m, poff + sizeof(struct tcphdr)); 2773 if (m == NULL) { 2774 *m_head = NULL; 2775 return (ENOBUFS); 2776 } 2777 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2778 m = m_pullup(m, poff + (tcp->th_off << 2)); 2779 if (m == NULL) { 2780 *m_head = NULL; 2781 return (ENOBUFS); 2782 } 2783 /* 2784 * Due to strict adherence of Microsoft NDIS 2785 * Large Send specification, hardware expects 2786 * a pseudo TCP checksum inserted by upper 2787 * stack. Unfortunately the pseudo TCP 2788 * checksum that NDIS refers to does not include 2789 * TCP payload length so driver should recompute 2790 * the pseudo checksum here. Hopefully this 2791 * wouldn't be much burden on modern CPUs. 2792 * 2793 * Reset IP checksum and recompute TCP pseudo 2794 * checksum as NDIS specification said. 2795 */ 2796 ip = (struct ip *)(mtod(m, char *) + ip_off); 2797 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2798 ip->ip_sum = 0; 2799 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 2800 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2801 } 2802 *m_head = m; 2803 } 2804 2805 prod = sc->alc_cdata.alc_tx_prod; 2806 txd = &sc->alc_cdata.alc_txdesc[prod]; 2807 txd_last = txd; 2808 map = txd->tx_dmamap; 2809 2810 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2811 *m_head, txsegs, &nsegs, 0); 2812 if (error == EFBIG) { 2813 m = m_collapse(*m_head, M_NOWAIT, ALC_MAXTXSEGS); 2814 if (m == NULL) { 2815 m_freem(*m_head); 2816 *m_head = NULL; 2817 return (ENOMEM); 2818 } 2819 *m_head = m; 2820 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2821 *m_head, txsegs, &nsegs, 0); 2822 if (error != 0) { 2823 m_freem(*m_head); 2824 *m_head = NULL; 2825 return (error); 2826 } 2827 } else if (error != 0) 2828 return (error); 2829 if (nsegs == 0) { 2830 m_freem(*m_head); 2831 *m_head = NULL; 2832 return (EIO); 2833 } 2834 2835 /* Check descriptor overrun. */ 2836 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 2837 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 2838 return (ENOBUFS); 2839 } 2840 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2841 2842 m = *m_head; 2843 cflags = TD_ETHERNET; 2844 vtag = 0; 2845 desc = NULL; 2846 idx = 0; 2847 /* Configure VLAN hardware tag insertion. */ 2848 if ((m->m_flags & M_VLANTAG) != 0) { 2849 vtag = htons(m->m_pkthdr.ether_vtag); 2850 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 2851 cflags |= TD_INS_VLAN_TAG; 2852 } 2853 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2854 /* Request TSO and set MSS. */ 2855 cflags |= TD_TSO | TD_TSO_DESCV1; 2856 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 2857 TD_MSS_MASK; 2858 /* Set TCP header offset. */ 2859 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 2860 TD_TCPHDR_OFFSET_MASK; 2861 /* 2862 * AR81[3567]x requires the first buffer should 2863 * only hold IP/TCP header data. Payload should 2864 * be handled in other descriptors. 2865 */ 2866 hdrlen = poff + (tcp->th_off << 2); 2867 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2868 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 2869 desc->flags = htole32(cflags); 2870 desc->addr = htole64(txsegs[0].ds_addr); 2871 sc->alc_cdata.alc_tx_cnt++; 2872 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2873 if (m->m_len - hdrlen > 0) { 2874 /* Handle remaining payload of the first fragment. */ 2875 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2876 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 2877 vtag)); 2878 desc->flags = htole32(cflags); 2879 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 2880 sc->alc_cdata.alc_tx_cnt++; 2881 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2882 } 2883 /* Handle remaining fragments. */ 2884 idx = 1; 2885 } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 2886 /* Configure Tx checksum offload. */ 2887 #ifdef ALC_USE_CUSTOM_CSUM 2888 cflags |= TD_CUSTOM_CSUM; 2889 /* Set checksum start offset. */ 2890 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 2891 TD_PLOAD_OFFSET_MASK; 2892 /* Set checksum insertion position of TCP/UDP. */ 2893 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 2894 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 2895 #else 2896 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2897 cflags |= TD_IPCSUM; 2898 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2899 cflags |= TD_TCPCSUM; 2900 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2901 cflags |= TD_UDPCSUM; 2902 /* Set TCP/UDP header offset. */ 2903 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 2904 TD_L4HDR_OFFSET_MASK; 2905 #endif 2906 } 2907 for (; idx < nsegs; idx++) { 2908 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2909 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 2910 desc->flags = htole32(cflags); 2911 desc->addr = htole64(txsegs[idx].ds_addr); 2912 sc->alc_cdata.alc_tx_cnt++; 2913 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2914 } 2915 /* Update producer index. */ 2916 sc->alc_cdata.alc_tx_prod = prod; 2917 2918 /* Finally set EOP on the last descriptor. */ 2919 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2920 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2921 desc->flags |= htole32(TD_EOP); 2922 2923 /* Swap dmamap of the first and the last. */ 2924 txd = &sc->alc_cdata.alc_txdesc[prod]; 2925 map = txd_last->tx_dmamap; 2926 txd_last->tx_dmamap = txd->tx_dmamap; 2927 txd->tx_dmamap = map; 2928 txd->tx_m = m; 2929 2930 return (0); 2931 } 2932 2933 static void 2934 alc_start(if_t ifp) 2935 { 2936 struct alc_softc *sc; 2937 2938 sc = if_getsoftc(ifp); 2939 ALC_LOCK(sc); 2940 alc_start_locked(ifp); 2941 ALC_UNLOCK(sc); 2942 } 2943 2944 static void 2945 alc_start_locked(if_t ifp) 2946 { 2947 struct alc_softc *sc; 2948 struct mbuf *m_head; 2949 int enq; 2950 2951 sc = if_getsoftc(ifp); 2952 2953 ALC_LOCK_ASSERT(sc); 2954 2955 /* Reclaim transmitted frames. */ 2956 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2957 alc_txeof(sc); 2958 2959 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2960 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) 2961 return; 2962 2963 for (enq = 0; !if_sendq_empty(ifp); ) { 2964 m_head = if_dequeue(ifp); 2965 if (m_head == NULL) 2966 break; 2967 /* 2968 * Pack the data into the transmit ring. If we 2969 * don't have room, set the OACTIVE flag and wait 2970 * for the NIC to drain the ring. 2971 */ 2972 if (alc_encap(sc, &m_head)) { 2973 if (m_head == NULL) 2974 break; 2975 if_sendq_prepend(ifp, m_head); 2976 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2977 break; 2978 } 2979 2980 enq++; 2981 /* 2982 * If there's a BPF listener, bounce a copy of this frame 2983 * to him. 2984 */ 2985 ETHER_BPF_MTAP(ifp, m_head); 2986 } 2987 2988 if (enq > 0) 2989 alc_start_tx(sc); 2990 } 2991 2992 static void 2993 alc_start_tx(struct alc_softc *sc) 2994 { 2995 2996 /* Sync descriptors. */ 2997 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2998 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 2999 /* Kick. Assume we're using normal Tx priority queue. */ 3000 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3001 CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX, 3002 (uint16_t)sc->alc_cdata.alc_tx_prod); 3003 else 3004 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 3005 (sc->alc_cdata.alc_tx_prod << 3006 MBOX_TD_PROD_LO_IDX_SHIFT) & 3007 MBOX_TD_PROD_LO_IDX_MASK); 3008 /* Set a timeout in case the chip goes out to lunch. */ 3009 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 3010 } 3011 3012 static void 3013 alc_watchdog(struct alc_softc *sc) 3014 { 3015 if_t ifp; 3016 3017 ALC_LOCK_ASSERT(sc); 3018 3019 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 3020 return; 3021 3022 ifp = sc->alc_ifp; 3023 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 3024 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 3025 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3026 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3027 alc_init_locked(sc); 3028 return; 3029 } 3030 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 3031 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3032 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3033 alc_init_locked(sc); 3034 if (!if_sendq_empty(ifp)) 3035 alc_start_locked(ifp); 3036 } 3037 3038 static int 3039 alc_ioctl(if_t ifp, u_long cmd, caddr_t data) 3040 { 3041 struct alc_softc *sc; 3042 struct ifreq *ifr; 3043 struct mii_data *mii; 3044 int error, mask; 3045 3046 sc = if_getsoftc(ifp); 3047 ifr = (struct ifreq *)data; 3048 error = 0; 3049 switch (cmd) { 3050 case SIOCSIFMTU: 3051 if (ifr->ifr_mtu < ETHERMIN || 3052 ifr->ifr_mtu > (sc->alc_ident->max_framelen - 3053 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || 3054 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 3055 ifr->ifr_mtu > ETHERMTU)) 3056 error = EINVAL; 3057 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 3058 ALC_LOCK(sc); 3059 if_setmtu(ifp, ifr->ifr_mtu); 3060 /* AR81[3567]x has 13 bits MSS field. */ 3061 if (if_getmtu(ifp) > ALC_TSO_MTU && 3062 (if_getcapenable(ifp) & IFCAP_TSO4) != 0) { 3063 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 3064 if_sethwassistbits(ifp, 0, CSUM_TSO); 3065 VLAN_CAPABILITIES(ifp); 3066 } 3067 ALC_UNLOCK(sc); 3068 } 3069 break; 3070 case SIOCSIFFLAGS: 3071 ALC_LOCK(sc); 3072 if ((if_getflags(ifp) & IFF_UP) != 0) { 3073 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 3074 ((if_getflags(ifp) ^ sc->alc_if_flags) & 3075 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3076 alc_rxfilter(sc); 3077 else 3078 alc_init_locked(sc); 3079 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3080 alc_stop(sc); 3081 sc->alc_if_flags = if_getflags(ifp); 3082 ALC_UNLOCK(sc); 3083 break; 3084 case SIOCADDMULTI: 3085 case SIOCDELMULTI: 3086 ALC_LOCK(sc); 3087 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3088 alc_rxfilter(sc); 3089 ALC_UNLOCK(sc); 3090 break; 3091 case SIOCSIFMEDIA: 3092 case SIOCGIFMEDIA: 3093 mii = device_get_softc(sc->alc_miibus); 3094 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 3095 break; 3096 case SIOCSIFCAP: 3097 ALC_LOCK(sc); 3098 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 3099 if ((mask & IFCAP_TXCSUM) != 0 && 3100 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 3101 if_togglecapenable(ifp, IFCAP_TXCSUM); 3102 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 3103 if_sethwassistbits(ifp, ALC_CSUM_FEATURES, 0); 3104 else 3105 if_sethwassistbits(ifp, 0, ALC_CSUM_FEATURES); 3106 } 3107 if ((mask & IFCAP_TSO4) != 0 && 3108 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 3109 if_togglecapenable(ifp, IFCAP_TSO4); 3110 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) { 3111 /* AR81[3567]x has 13 bits MSS field. */ 3112 if (if_getmtu(ifp) > ALC_TSO_MTU) { 3113 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 3114 if_sethwassistbits(ifp, 0, CSUM_TSO); 3115 } else 3116 if_sethwassistbits(ifp, CSUM_TSO, 0); 3117 } else 3118 if_sethwassistbits(ifp, 0, CSUM_TSO); 3119 } 3120 if ((mask & IFCAP_WOL_MCAST) != 0 && 3121 (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0) 3122 if_togglecapenable(ifp, IFCAP_WOL_MCAST); 3123 if ((mask & IFCAP_WOL_MAGIC) != 0 && 3124 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 3125 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 3126 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3127 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 3128 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 3129 alc_rxvlan(sc); 3130 } 3131 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 3132 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 3133 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 3134 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3135 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 3136 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 3137 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 3138 if_setcapenablebit(ifp, 0, 3139 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 3140 ALC_UNLOCK(sc); 3141 VLAN_CAPABILITIES(ifp); 3142 break; 3143 default: 3144 error = ether_ioctl(ifp, cmd, data); 3145 break; 3146 } 3147 3148 return (error); 3149 } 3150 3151 static void 3152 alc_mac_config(struct alc_softc *sc) 3153 { 3154 struct mii_data *mii; 3155 uint32_t reg; 3156 3157 ALC_LOCK_ASSERT(sc); 3158 3159 mii = device_get_softc(sc->alc_miibus); 3160 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3161 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 3162 MAC_CFG_SPEED_MASK); 3163 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3164 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 3165 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 3166 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 3167 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3168 /* Reprogram MAC with resolved speed/duplex. */ 3169 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3170 case IFM_10_T: 3171 case IFM_100_TX: 3172 reg |= MAC_CFG_SPEED_10_100; 3173 break; 3174 case IFM_1000_T: 3175 reg |= MAC_CFG_SPEED_1000; 3176 break; 3177 } 3178 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 3179 reg |= MAC_CFG_FULL_DUPLEX; 3180 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 3181 reg |= MAC_CFG_TX_FC; 3182 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 3183 reg |= MAC_CFG_RX_FC; 3184 } 3185 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3186 } 3187 3188 static void 3189 alc_stats_clear(struct alc_softc *sc) 3190 { 3191 struct smb sb, *smb; 3192 uint32_t *reg; 3193 int i; 3194 3195 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3196 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3197 sc->alc_cdata.alc_smb_map, 3198 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3199 smb = sc->alc_rdata.alc_smb; 3200 /* Update done, clear. */ 3201 smb->updated = 0; 3202 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3203 sc->alc_cdata.alc_smb_map, 3204 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3205 } else { 3206 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3207 reg++) { 3208 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3209 i += sizeof(uint32_t); 3210 } 3211 /* Read Tx statistics. */ 3212 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3213 reg++) { 3214 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3215 i += sizeof(uint32_t); 3216 } 3217 } 3218 } 3219 3220 static void 3221 alc_stats_update(struct alc_softc *sc) 3222 { 3223 struct alc_hw_stats *stat; 3224 struct smb sb, *smb; 3225 if_t ifp; 3226 uint32_t *reg; 3227 int i; 3228 3229 ALC_LOCK_ASSERT(sc); 3230 3231 ifp = sc->alc_ifp; 3232 stat = &sc->alc_stats; 3233 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3234 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3235 sc->alc_cdata.alc_smb_map, 3236 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3237 smb = sc->alc_rdata.alc_smb; 3238 if (smb->updated == 0) 3239 return; 3240 } else { 3241 smb = &sb; 3242 /* Read Rx statistics. */ 3243 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3244 reg++) { 3245 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3246 i += sizeof(uint32_t); 3247 } 3248 /* Read Tx statistics. */ 3249 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3250 reg++) { 3251 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3252 i += sizeof(uint32_t); 3253 } 3254 } 3255 3256 /* Rx stats. */ 3257 stat->rx_frames += smb->rx_frames; 3258 stat->rx_bcast_frames += smb->rx_bcast_frames; 3259 stat->rx_mcast_frames += smb->rx_mcast_frames; 3260 stat->rx_pause_frames += smb->rx_pause_frames; 3261 stat->rx_control_frames += smb->rx_control_frames; 3262 stat->rx_crcerrs += smb->rx_crcerrs; 3263 stat->rx_lenerrs += smb->rx_lenerrs; 3264 stat->rx_bytes += smb->rx_bytes; 3265 stat->rx_runts += smb->rx_runts; 3266 stat->rx_fragments += smb->rx_fragments; 3267 stat->rx_pkts_64 += smb->rx_pkts_64; 3268 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 3269 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 3270 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 3271 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 3272 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 3273 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 3274 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 3275 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 3276 stat->rx_rrs_errs += smb->rx_rrs_errs; 3277 stat->rx_alignerrs += smb->rx_alignerrs; 3278 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 3279 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 3280 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 3281 3282 /* Tx stats. */ 3283 stat->tx_frames += smb->tx_frames; 3284 stat->tx_bcast_frames += smb->tx_bcast_frames; 3285 stat->tx_mcast_frames += smb->tx_mcast_frames; 3286 stat->tx_pause_frames += smb->tx_pause_frames; 3287 stat->tx_excess_defer += smb->tx_excess_defer; 3288 stat->tx_control_frames += smb->tx_control_frames; 3289 stat->tx_deferred += smb->tx_deferred; 3290 stat->tx_bytes += smb->tx_bytes; 3291 stat->tx_pkts_64 += smb->tx_pkts_64; 3292 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 3293 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 3294 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 3295 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 3296 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 3297 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 3298 stat->tx_single_colls += smb->tx_single_colls; 3299 stat->tx_multi_colls += smb->tx_multi_colls; 3300 stat->tx_late_colls += smb->tx_late_colls; 3301 stat->tx_excess_colls += smb->tx_excess_colls; 3302 stat->tx_underrun += smb->tx_underrun; 3303 stat->tx_desc_underrun += smb->tx_desc_underrun; 3304 stat->tx_lenerrs += smb->tx_lenerrs; 3305 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 3306 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 3307 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 3308 3309 /* Update counters in ifnet. */ 3310 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 3311 3312 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 3313 smb->tx_multi_colls * 2 + smb->tx_late_colls + 3314 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 3315 3316 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls + 3317 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated); 3318 3319 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 3320 3321 if_inc_counter(ifp, IFCOUNTER_IERRORS, 3322 smb->rx_crcerrs + smb->rx_lenerrs + 3323 smb->rx_runts + smb->rx_pkts_truncated + 3324 smb->rx_fifo_oflows + smb->rx_rrs_errs + 3325 smb->rx_alignerrs); 3326 3327 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3328 /* Update done, clear. */ 3329 smb->updated = 0; 3330 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3331 sc->alc_cdata.alc_smb_map, 3332 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3333 } 3334 } 3335 3336 static int 3337 alc_intr(void *arg) 3338 { 3339 struct alc_softc *sc; 3340 uint32_t status; 3341 3342 sc = (struct alc_softc *)arg; 3343 3344 if (sc->alc_flags & ALC_FLAG_MT) { 3345 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3346 return (FILTER_HANDLED); 3347 } 3348 3349 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3350 if ((status & ALC_INTRS) == 0) 3351 return (FILTER_STRAY); 3352 /* Disable interrupts. */ 3353 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 3354 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3355 3356 return (FILTER_HANDLED); 3357 } 3358 3359 static void 3360 alc_int_task(void *arg, int pending) 3361 { 3362 struct alc_softc *sc; 3363 if_t ifp; 3364 uint32_t status; 3365 int more; 3366 3367 sc = (struct alc_softc *)arg; 3368 ifp = sc->alc_ifp; 3369 3370 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3371 ALC_LOCK(sc); 3372 if (sc->alc_morework != 0) { 3373 sc->alc_morework = 0; 3374 status |= INTR_RX_PKT; 3375 } 3376 if ((status & ALC_INTRS) == 0) 3377 goto done; 3378 3379 /* Acknowledge interrupts but still disable interrupts. */ 3380 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 3381 3382 more = 0; 3383 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 3384 if ((status & INTR_RX_PKT) != 0) { 3385 more = alc_rxintr(sc, sc->alc_process_limit); 3386 if (more == EAGAIN) 3387 sc->alc_morework = 1; 3388 else if (more == EIO) { 3389 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3390 alc_init_locked(sc); 3391 ALC_UNLOCK(sc); 3392 return; 3393 } 3394 } 3395 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 3396 INTR_TXQ_TO_RST)) != 0) { 3397 if ((status & INTR_DMA_RD_TO_RST) != 0) 3398 device_printf(sc->alc_dev, 3399 "DMA read error! -- resetting\n"); 3400 if ((status & INTR_DMA_WR_TO_RST) != 0) 3401 device_printf(sc->alc_dev, 3402 "DMA write error! -- resetting\n"); 3403 if ((status & INTR_TXQ_TO_RST) != 0) 3404 device_printf(sc->alc_dev, 3405 "TxQ reset! -- resetting\n"); 3406 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3407 alc_init_locked(sc); 3408 ALC_UNLOCK(sc); 3409 return; 3410 } 3411 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 3412 !if_sendq_empty(ifp)) 3413 alc_start_locked(ifp); 3414 } 3415 3416 if (more == EAGAIN || 3417 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 3418 ALC_UNLOCK(sc); 3419 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3420 return; 3421 } 3422 3423 done: 3424 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 3425 /* Re-enable interrupts if we're running. */ 3426 if (sc->alc_flags & ALC_FLAG_MT) 3427 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3428 else 3429 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 3430 } 3431 ALC_UNLOCK(sc); 3432 } 3433 3434 static void 3435 alc_txeof(struct alc_softc *sc) 3436 { 3437 if_t ifp; 3438 struct alc_txdesc *txd; 3439 uint32_t cons, prod; 3440 3441 ALC_LOCK_ASSERT(sc); 3442 3443 ifp = sc->alc_ifp; 3444 3445 if (sc->alc_cdata.alc_tx_cnt == 0) 3446 return; 3447 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3448 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 3449 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3450 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3451 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 3452 prod = sc->alc_rdata.alc_cmb->cons; 3453 } else { 3454 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3455 prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX); 3456 else { 3457 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 3458 /* Assume we're using normal Tx priority queue. */ 3459 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 3460 MBOX_TD_CONS_LO_IDX_SHIFT; 3461 } 3462 } 3463 cons = sc->alc_cdata.alc_tx_cons; 3464 /* 3465 * Go through our Tx list and free mbufs for those 3466 * frames which have been transmitted. 3467 */ 3468 for (; cons != prod; ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 3469 if (sc->alc_cdata.alc_tx_cnt <= 0) 3470 break; 3471 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 3472 sc->alc_cdata.alc_tx_cnt--; 3473 txd = &sc->alc_cdata.alc_txdesc[cons]; 3474 if (txd->tx_m != NULL) { 3475 /* Reclaim transmitted mbufs. */ 3476 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3477 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3478 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3479 txd->tx_dmamap); 3480 m_freem(txd->tx_m); 3481 txd->tx_m = NULL; 3482 } 3483 } 3484 3485 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3486 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3487 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 3488 sc->alc_cdata.alc_tx_cons = cons; 3489 /* 3490 * Unarm watchdog timer only when there is no pending 3491 * frames in Tx queue. 3492 */ 3493 if (sc->alc_cdata.alc_tx_cnt == 0) 3494 sc->alc_watchdog_timer = 0; 3495 } 3496 3497 static int 3498 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 3499 { 3500 struct mbuf *m; 3501 bus_dma_segment_t segs[1]; 3502 bus_dmamap_t map; 3503 int nsegs; 3504 3505 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3506 if (m == NULL) 3507 return (ENOBUFS); 3508 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 3509 #ifndef __NO_STRICT_ALIGNMENT 3510 m_adj(m, sizeof(uint64_t)); 3511 #endif 3512 3513 if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag, 3514 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3515 m_freem(m); 3516 return (ENOBUFS); 3517 } 3518 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3519 3520 if (rxd->rx_m != NULL) { 3521 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3522 BUS_DMASYNC_POSTREAD); 3523 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 3524 } 3525 map = rxd->rx_dmamap; 3526 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 3527 sc->alc_cdata.alc_rx_sparemap = map; 3528 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3529 BUS_DMASYNC_PREREAD); 3530 rxd->rx_m = m; 3531 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 3532 return (0); 3533 } 3534 3535 static int 3536 alc_rxintr(struct alc_softc *sc, int count) 3537 { 3538 if_t ifp; 3539 struct rx_rdesc *rrd; 3540 uint32_t nsegs, status; 3541 int rr_cons, prog; 3542 3543 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3544 sc->alc_cdata.alc_rr_ring_map, 3545 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3546 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3547 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 3548 rr_cons = sc->alc_cdata.alc_rr_cons; 3549 ifp = sc->alc_ifp; 3550 for (prog = 0; (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0;) { 3551 if (count-- <= 0) 3552 break; 3553 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 3554 status = le32toh(rrd->status); 3555 if ((status & RRD_VALID) == 0) 3556 break; 3557 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 3558 if (nsegs == 0) { 3559 /* This should not happen! */ 3560 device_printf(sc->alc_dev, 3561 "unexpected segment count -- resetting\n"); 3562 return (EIO); 3563 } 3564 alc_rxeof(sc, rrd); 3565 /* Clear Rx return status. */ 3566 rrd->status = 0; 3567 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 3568 sc->alc_cdata.alc_rx_cons += nsegs; 3569 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 3570 prog += nsegs; 3571 } 3572 3573 if (prog > 0) { 3574 /* Update the consumer index. */ 3575 sc->alc_cdata.alc_rr_cons = rr_cons; 3576 /* Sync Rx return descriptors. */ 3577 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3578 sc->alc_cdata.alc_rr_ring_map, 3579 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3580 /* 3581 * Sync updated Rx descriptors such that controller see 3582 * modified buffer addresses. 3583 */ 3584 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3585 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3586 /* 3587 * Let controller know availability of new Rx buffers. 3588 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 3589 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 3590 * only when Rx buffer pre-fetching is required. In 3591 * addition we already set ALC_RX_RD_FREE_THRESH to 3592 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 3593 * it still seems that pre-fetching needs more 3594 * experimentation. 3595 */ 3596 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3597 CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX, 3598 (uint16_t)sc->alc_cdata.alc_rx_cons); 3599 else 3600 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 3601 sc->alc_cdata.alc_rx_cons); 3602 } 3603 3604 return (count > 0 ? 0 : EAGAIN); 3605 } 3606 3607 #ifndef __NO_STRICT_ALIGNMENT 3608 static struct mbuf * 3609 alc_fixup_rx(if_t ifp, struct mbuf *m) 3610 { 3611 struct mbuf *n; 3612 int i; 3613 uint16_t *src, *dst; 3614 3615 src = mtod(m, uint16_t *); 3616 dst = src - 3; 3617 3618 if (m->m_next == NULL) { 3619 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 3620 *dst++ = *src++; 3621 m->m_data -= 6; 3622 return (m); 3623 } 3624 /* 3625 * Append a new mbuf to received mbuf chain and copy ethernet 3626 * header from the mbuf chain. This can save lots of CPU 3627 * cycles for jumbo frame. 3628 */ 3629 MGETHDR(n, M_NOWAIT, MT_DATA); 3630 if (n == NULL) { 3631 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3632 m_freem(m); 3633 return (NULL); 3634 } 3635 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 3636 m->m_data += ETHER_HDR_LEN; 3637 m->m_len -= ETHER_HDR_LEN; 3638 n->m_len = ETHER_HDR_LEN; 3639 M_MOVE_PKTHDR(n, m); 3640 n->m_next = m; 3641 return (n); 3642 } 3643 #endif 3644 3645 /* Receive a frame. */ 3646 static void 3647 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 3648 { 3649 struct alc_rxdesc *rxd; 3650 if_t ifp; 3651 struct mbuf *mp, *m; 3652 uint32_t rdinfo, status, vtag; 3653 int count, nsegs, rx_cons; 3654 3655 ifp = sc->alc_ifp; 3656 status = le32toh(rrd->status); 3657 rdinfo = le32toh(rrd->rdinfo); 3658 rx_cons = RRD_RD_IDX(rdinfo); 3659 nsegs = RRD_RD_CNT(rdinfo); 3660 3661 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 3662 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 3663 /* 3664 * We want to pass the following frames to upper 3665 * layer regardless of error status of Rx return 3666 * ring. 3667 * 3668 * o IP/TCP/UDP checksum is bad. 3669 * o frame length and protocol specific length 3670 * does not match. 3671 * 3672 * Force network stack compute checksum for 3673 * errored frames. 3674 */ 3675 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 3676 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 3677 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 3678 return; 3679 } 3680 3681 for (count = 0; count < nsegs; count++, 3682 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 3683 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 3684 mp = rxd->rx_m; 3685 /* Add a new receive buffer to the ring. */ 3686 if (alc_newbuf(sc, rxd) != 0) { 3687 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3688 /* Reuse Rx buffers. */ 3689 if (sc->alc_cdata.alc_rxhead != NULL) 3690 m_freem(sc->alc_cdata.alc_rxhead); 3691 break; 3692 } 3693 3694 /* 3695 * Assume we've received a full sized frame. 3696 * Actual size is fixed when we encounter the end of 3697 * multi-segmented frame. 3698 */ 3699 mp->m_len = sc->alc_buf_size; 3700 3701 /* Chain received mbufs. */ 3702 if (sc->alc_cdata.alc_rxhead == NULL) { 3703 sc->alc_cdata.alc_rxhead = mp; 3704 sc->alc_cdata.alc_rxtail = mp; 3705 } else { 3706 mp->m_flags &= ~M_PKTHDR; 3707 sc->alc_cdata.alc_rxprev_tail = 3708 sc->alc_cdata.alc_rxtail; 3709 sc->alc_cdata.alc_rxtail->m_next = mp; 3710 sc->alc_cdata.alc_rxtail = mp; 3711 } 3712 3713 if (count == nsegs - 1) { 3714 /* Last desc. for this frame. */ 3715 m = sc->alc_cdata.alc_rxhead; 3716 m->m_flags |= M_PKTHDR; 3717 /* 3718 * It seems that L1C/L2C controller has no way 3719 * to tell hardware to strip CRC bytes. 3720 */ 3721 m->m_pkthdr.len = 3722 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 3723 if (nsegs > 1) { 3724 /* Set last mbuf size. */ 3725 mp->m_len = sc->alc_cdata.alc_rxlen - 3726 (nsegs - 1) * sc->alc_buf_size; 3727 /* Remove the CRC bytes in chained mbufs. */ 3728 if (mp->m_len <= ETHER_CRC_LEN) { 3729 sc->alc_cdata.alc_rxtail = 3730 sc->alc_cdata.alc_rxprev_tail; 3731 sc->alc_cdata.alc_rxtail->m_len -= 3732 (ETHER_CRC_LEN - mp->m_len); 3733 sc->alc_cdata.alc_rxtail->m_next = NULL; 3734 m_freem(mp); 3735 } else { 3736 mp->m_len -= ETHER_CRC_LEN; 3737 } 3738 } else 3739 m->m_len = m->m_pkthdr.len; 3740 m->m_pkthdr.rcvif = ifp; 3741 /* 3742 * Due to hardware bugs, Rx checksum offloading 3743 * was intentionally disabled. 3744 */ 3745 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 3746 (status & RRD_VLAN_TAG) != 0) { 3747 vtag = RRD_VLAN(le32toh(rrd->vtag)); 3748 m->m_pkthdr.ether_vtag = ntohs(vtag); 3749 m->m_flags |= M_VLANTAG; 3750 } 3751 #ifndef __NO_STRICT_ALIGNMENT 3752 m = alc_fixup_rx(ifp, m); 3753 if (m != NULL) 3754 #endif 3755 { 3756 /* Pass it on. */ 3757 ALC_UNLOCK(sc); 3758 if_input(ifp, m); 3759 ALC_LOCK(sc); 3760 } 3761 } 3762 } 3763 /* Reset mbuf chains. */ 3764 ALC_RXCHAIN_RESET(sc); 3765 } 3766 3767 static void 3768 alc_tick(void *arg) 3769 { 3770 struct alc_softc *sc; 3771 struct mii_data *mii; 3772 3773 sc = (struct alc_softc *)arg; 3774 3775 ALC_LOCK_ASSERT(sc); 3776 3777 mii = device_get_softc(sc->alc_miibus); 3778 mii_tick(mii); 3779 alc_stats_update(sc); 3780 /* 3781 * alc(4) does not rely on Tx completion interrupts to reclaim 3782 * transferred buffers. Instead Tx completion interrupts are 3783 * used to hint for scheduling Tx task. So it's necessary to 3784 * release transmitted buffers by kicking Tx completion 3785 * handler. This limits the maximum reclamation delay to a hz. 3786 */ 3787 alc_txeof(sc); 3788 alc_watchdog(sc); 3789 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3790 } 3791 3792 static void 3793 alc_osc_reset(struct alc_softc *sc) 3794 { 3795 uint32_t reg; 3796 3797 reg = CSR_READ_4(sc, ALC_MISC3); 3798 reg &= ~MISC3_25M_BY_SW; 3799 reg |= MISC3_25M_NOTO_INTNL; 3800 CSR_WRITE_4(sc, ALC_MISC3, reg); 3801 3802 reg = CSR_READ_4(sc, ALC_MISC); 3803 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 3804 /* 3805 * Restore over-current protection default value. 3806 * This value could be reset by MAC reset. 3807 */ 3808 reg &= ~MISC_PSW_OCP_MASK; 3809 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 3810 reg &= ~MISC_INTNLOSC_OPEN; 3811 CSR_WRITE_4(sc, ALC_MISC, reg); 3812 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3813 reg = CSR_READ_4(sc, ALC_MISC2); 3814 reg &= ~MISC2_CALB_START; 3815 CSR_WRITE_4(sc, ALC_MISC2, reg); 3816 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 3817 3818 } else { 3819 reg &= ~MISC_INTNLOSC_OPEN; 3820 /* Disable isolate for revision A devices. */ 3821 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3822 reg &= ~MISC_ISO_ENB; 3823 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3824 CSR_WRITE_4(sc, ALC_MISC, reg); 3825 } 3826 3827 DELAY(20); 3828 } 3829 3830 static void 3831 alc_reset(struct alc_softc *sc) 3832 { 3833 uint32_t pmcfg, reg; 3834 int i; 3835 3836 pmcfg = 0; 3837 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3838 /* Reset workaround. */ 3839 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 3840 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3841 (sc->alc_rev & 0x01) != 0) { 3842 /* Disable L0s/L1s before reset. */ 3843 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 3844 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3845 != 0) { 3846 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 3847 PM_CFG_ASPM_L1_ENB); 3848 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3849 } 3850 } 3851 } 3852 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3853 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 3854 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3855 3856 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3857 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3858 DELAY(10); 3859 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 3860 break; 3861 } 3862 if (i == 0) 3863 device_printf(sc->alc_dev, "MAC reset timeout!\n"); 3864 } 3865 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3866 DELAY(10); 3867 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 3868 break; 3869 } 3870 if (i == 0) 3871 device_printf(sc->alc_dev, "master reset timeout!\n"); 3872 3873 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3874 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3875 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 3876 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3877 break; 3878 DELAY(10); 3879 } 3880 if (i == 0) 3881 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 3882 3883 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3884 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3885 (sc->alc_rev & 0x01) != 0) { 3886 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3887 reg |= MASTER_CLK_SEL_DIS; 3888 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3889 /* Restore L0s/L1s config. */ 3890 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3891 != 0) 3892 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3893 } 3894 3895 alc_osc_reset(sc); 3896 reg = CSR_READ_4(sc, ALC_MISC3); 3897 reg &= ~MISC3_25M_BY_SW; 3898 reg |= MISC3_25M_NOTO_INTNL; 3899 CSR_WRITE_4(sc, ALC_MISC3, reg); 3900 reg = CSR_READ_4(sc, ALC_MISC); 3901 reg &= ~MISC_INTNLOSC_OPEN; 3902 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3903 reg &= ~MISC_ISO_ENB; 3904 CSR_WRITE_4(sc, ALC_MISC, reg); 3905 DELAY(20); 3906 } 3907 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3908 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3909 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) 3910 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 3911 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 3912 SERDES_PHY_CLK_SLOWDOWN); 3913 } 3914 3915 static void 3916 alc_init(void *xsc) 3917 { 3918 struct alc_softc *sc; 3919 3920 sc = (struct alc_softc *)xsc; 3921 ALC_LOCK(sc); 3922 alc_init_locked(sc); 3923 ALC_UNLOCK(sc); 3924 } 3925 3926 static void 3927 alc_init_locked(struct alc_softc *sc) 3928 { 3929 if_t ifp; 3930 uint8_t eaddr[ETHER_ADDR_LEN]; 3931 bus_addr_t paddr; 3932 uint32_t reg, rxf_hi, rxf_lo; 3933 3934 ALC_LOCK_ASSERT(sc); 3935 3936 ifp = sc->alc_ifp; 3937 3938 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3939 return; 3940 /* 3941 * Cancel any pending I/O. 3942 */ 3943 alc_stop(sc); 3944 /* 3945 * Reset the chip to a known state. 3946 */ 3947 alc_reset(sc); 3948 3949 /* Initialize Rx descriptors. */ 3950 if (alc_init_rx_ring(sc) != 0) { 3951 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 3952 alc_stop(sc); 3953 return; 3954 } 3955 alc_init_rr_ring(sc); 3956 alc_init_tx_ring(sc); 3957 alc_init_cmb(sc); 3958 alc_init_smb(sc); 3959 3960 /* Enable all clocks. */ 3961 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3962 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 3963 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 3964 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 3965 CLK_GATING_RXMAC_ENB); 3966 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 3967 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 3968 IDLE_DECISN_TIMER_DEFAULT_1MS); 3969 } else 3970 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 3971 3972 /* Reprogram the station address. */ 3973 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN); 3974 CSR_WRITE_4(sc, ALC_PAR0, 3975 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 3976 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 3977 /* 3978 * Clear WOL status and disable all WOL feature as WOL 3979 * would interfere Rx operation under normal environments. 3980 */ 3981 CSR_READ_4(sc, ALC_WOL_CFG); 3982 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 3983 /* Set Tx descriptor base addresses. */ 3984 paddr = sc->alc_rdata.alc_tx_ring_paddr; 3985 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3986 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3987 /* We don't use high priority ring. */ 3988 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 3989 /* Set Tx descriptor counter. */ 3990 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 3991 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 3992 /* Set Rx descriptor base addresses. */ 3993 paddr = sc->alc_rdata.alc_rx_ring_paddr; 3994 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3995 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3996 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3997 /* We use one Rx ring. */ 3998 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 3999 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 4000 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 4001 } 4002 /* Set Rx descriptor counter. */ 4003 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 4004 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 4005 4006 /* 4007 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 4008 * if it do not fit the buffer size. Rx return descriptor holds 4009 * a counter that indicates how many fragments were made by the 4010 * hardware. The buffer size should be multiple of 8 bytes. 4011 * Since hardware has limit on the size of buffer size, always 4012 * use the maximum value. 4013 * For strict-alignment architectures make sure to reduce buffer 4014 * size by 8 bytes to make room for alignment fixup. 4015 */ 4016 #ifndef __NO_STRICT_ALIGNMENT 4017 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 4018 #else 4019 sc->alc_buf_size = RX_BUF_SIZE_MAX; 4020 #endif 4021 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 4022 4023 paddr = sc->alc_rdata.alc_rr_ring_paddr; 4024 /* Set Rx return descriptor base addresses. */ 4025 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 4026 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4027 /* We use one Rx return ring. */ 4028 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 4029 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 4030 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 4031 } 4032 /* Set Rx return descriptor counter. */ 4033 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 4034 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 4035 paddr = sc->alc_rdata.alc_cmb_paddr; 4036 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4037 paddr = sc->alc_rdata.alc_smb_paddr; 4038 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 4039 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4040 4041 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 4042 /* Reconfigure SRAM - Vendor magic. */ 4043 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 4044 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 4045 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 4046 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 4047 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 4048 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 4049 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 4050 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 4051 } 4052 4053 /* Tell hardware that we're ready to load DMA blocks. */ 4054 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 4055 4056 /* Configure interrupt moderation timer. */ 4057 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 4058 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 4059 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 4060 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 4061 /* 4062 * We don't want to automatic interrupt clear as task queue 4063 * for the interrupt should know interrupt status. 4064 */ 4065 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 4066 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 4067 reg |= MASTER_SA_TIMER_ENB; 4068 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 4069 reg |= MASTER_IM_RX_TIMER_ENB; 4070 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 4071 ALC_USECS(sc->alc_int_tx_mod) != 0) 4072 reg |= MASTER_IM_TX_TIMER_ENB; 4073 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 4074 /* 4075 * Disable interrupt re-trigger timer. We don't want automatic 4076 * re-triggering of un-ACKed interrupts. 4077 */ 4078 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 4079 /* Configure CMB. */ 4080 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4081 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 4082 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 4083 ALC_USECS(sc->alc_int_tx_mod)); 4084 } else { 4085 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 4086 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 4087 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 4088 } else 4089 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 4090 } 4091 /* 4092 * Hardware can be configured to issue SMB interrupt based 4093 * on programmed interval. Since there is a callout that is 4094 * invoked for every hz in driver we use that instead of 4095 * relying on periodic SMB interrupt. 4096 */ 4097 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 4098 /* Clear MAC statistics. */ 4099 alc_stats_clear(sc); 4100 4101 /* 4102 * Always use maximum frame size that controller can support. 4103 * Otherwise received frames that has larger frame length 4104 * than alc(4) MTU would be silently dropped in hardware. This 4105 * would make path-MTU discovery hard as sender wouldn't get 4106 * any responses from receiver. alc(4) supports 4107 * multi-fragmented frames on Rx path so it has no issue on 4108 * assembling fragmented frames. Using maximum frame size also 4109 * removes the need to reinitialize hardware when interface 4110 * MTU configuration was changed. 4111 * 4112 * Be conservative in what you do, be liberal in what you 4113 * accept from others - RFC 793. 4114 */ 4115 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 4116 4117 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4118 /* Disable header split(?) */ 4119 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 4120 4121 /* Configure IPG/IFG parameters. */ 4122 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 4123 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 4124 IPG_IFG_IPGT_MASK) | 4125 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 4126 IPG_IFG_MIFG_MASK) | 4127 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 4128 IPG_IFG_IPG1_MASK) | 4129 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 4130 IPG_IFG_IPG2_MASK)); 4131 /* Set parameters for half-duplex media. */ 4132 CSR_WRITE_4(sc, ALC_HDPX_CFG, 4133 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 4134 HDPX_CFG_LCOL_MASK) | 4135 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 4136 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 4137 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 4138 HDPX_CFG_ABEBT_MASK) | 4139 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 4140 HDPX_CFG_JAMIPG_MASK)); 4141 } 4142 4143 /* 4144 * Set TSO/checksum offload threshold. For frames that is 4145 * larger than this threshold, hardware wouldn't do 4146 * TSO/checksum offloading. 4147 */ 4148 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 4149 TSO_OFFLOAD_THRESH_MASK; 4150 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 4151 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 4152 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 4153 /* Configure TxQ. */ 4154 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 4155 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 4156 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 4157 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4158 reg >>= 1; 4159 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 4160 TXQ_CFG_TD_BURST_MASK; 4161 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 4162 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 4163 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4164 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 4165 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 4166 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 4167 HQTD_CFG_BURST_ENB); 4168 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 4169 reg = WRR_PRI_RESTRICT_NONE; 4170 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 4171 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 4172 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 4173 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 4174 CSR_WRITE_4(sc, ALC_WRR, reg); 4175 } else { 4176 /* Configure Rx free descriptor pre-fetching. */ 4177 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 4178 ((RX_RD_FREE_THRESH_HI_DEFAULT << 4179 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 4180 ((RX_RD_FREE_THRESH_LO_DEFAULT << 4181 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 4182 } 4183 4184 /* 4185 * Configure flow control parameters. 4186 * XON : 80% of Rx FIFO 4187 * XOFF : 30% of Rx FIFO 4188 */ 4189 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4190 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4191 reg &= SRAM_RX_FIFO_LEN_MASK; 4192 reg *= 8; 4193 if (reg > 8 * 1024) 4194 reg -= RX_FIFO_PAUSE_816X_RSVD; 4195 else 4196 reg -= RX_BUF_SIZE_MAX; 4197 reg /= 8; 4198 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4199 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4200 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4201 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 4202 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4203 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4204 } else if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 4205 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { 4206 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4207 rxf_hi = (reg * 8) / 10; 4208 rxf_lo = (reg * 3) / 10; 4209 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4210 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4211 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4212 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4213 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4214 } 4215 4216 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4217 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 4218 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 4219 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 4220 } 4221 4222 /* Configure RxQ. */ 4223 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 4224 RXQ_CFG_RD_BURST_MASK; 4225 reg |= RXQ_CFG_RSS_MODE_DIS; 4226 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4227 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 4228 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 4229 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 4230 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 4231 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4232 } else { 4233 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 4234 sc->alc_ident->deviceid != DEVICEID_ATHEROS_AR8151_V2) 4235 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4236 } 4237 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4238 4239 /* Configure DMA parameters. */ 4240 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 4241 reg |= sc->alc_rcb; 4242 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 4243 reg |= DMA_CFG_CMB_ENB; 4244 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 4245 reg |= DMA_CFG_SMB_ENB; 4246 else 4247 reg |= DMA_CFG_SMB_DIS; 4248 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 4249 DMA_CFG_RD_BURST_SHIFT; 4250 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 4251 DMA_CFG_WR_BURST_SHIFT; 4252 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 4253 DMA_CFG_RD_DELAY_CNT_MASK; 4254 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 4255 DMA_CFG_WR_DELAY_CNT_MASK; 4256 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4257 switch (AR816X_REV(sc->alc_rev)) { 4258 case AR816X_REV_A0: 4259 case AR816X_REV_A1: 4260 reg |= DMA_CFG_RD_CHNL_SEL_2; 4261 break; 4262 case AR816X_REV_B0: 4263 /* FALLTHROUGH */ 4264 default: 4265 reg |= DMA_CFG_RD_CHNL_SEL_4; 4266 break; 4267 } 4268 } 4269 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4270 4271 /* 4272 * Configure Tx/Rx MACs. 4273 * - Auto-padding for short frames. 4274 * - Enable CRC generation. 4275 * Actual reconfiguration of MAC for resolved speed/duplex 4276 * is followed after detection of link establishment. 4277 * AR813x/AR815x always does checksum computation regardless 4278 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 4279 * have bug in protocol field in Rx return structure so 4280 * these controllers can't handle fragmented frames. Disable 4281 * Rx checksum offloading until there is a newer controller 4282 * that has sane implementation. 4283 */ 4284 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 4285 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 4286 MAC_CFG_PREAMBLE_MASK); 4287 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 4288 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 4289 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 4290 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4291 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 4292 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 4293 reg |= MAC_CFG_SPEED_10_100; 4294 else 4295 reg |= MAC_CFG_SPEED_1000; 4296 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4297 4298 /* Set up the receive filter. */ 4299 alc_rxfilter(sc); 4300 alc_rxvlan(sc); 4301 4302 /* Acknowledge all pending interrupts and clear it. */ 4303 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 4304 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4305 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 4306 4307 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 4308 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 4309 4310 sc->alc_flags &= ~ALC_FLAG_LINK; 4311 /* Switch to the current media. */ 4312 alc_mediachange_locked(sc); 4313 4314 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 4315 } 4316 4317 static void 4318 alc_stop(struct alc_softc *sc) 4319 { 4320 if_t ifp; 4321 struct alc_txdesc *txd; 4322 struct alc_rxdesc *rxd; 4323 uint32_t reg; 4324 int i; 4325 4326 ALC_LOCK_ASSERT(sc); 4327 /* 4328 * Mark the interface down and cancel the watchdog timer. 4329 */ 4330 ifp = sc->alc_ifp; 4331 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 4332 sc->alc_flags &= ~ALC_FLAG_LINK; 4333 callout_stop(&sc->alc_tick_ch); 4334 sc->alc_watchdog_timer = 0; 4335 alc_stats_update(sc); 4336 /* Disable interrupts. */ 4337 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 4338 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4339 /* Disable DMA. */ 4340 reg = CSR_READ_4(sc, ALC_DMA_CFG); 4341 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 4342 reg |= DMA_CFG_SMB_DIS; 4343 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4344 DELAY(1000); 4345 /* Stop Rx/Tx MACs. */ 4346 alc_stop_mac(sc); 4347 /* Disable interrupts which might be touched in taskq handler. */ 4348 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4349 /* Disable L0s/L1s */ 4350 alc_aspm(sc, 0, IFM_UNKNOWN); 4351 /* Reclaim Rx buffers that have been processed. */ 4352 if (sc->alc_cdata.alc_rxhead != NULL) 4353 m_freem(sc->alc_cdata.alc_rxhead); 4354 ALC_RXCHAIN_RESET(sc); 4355 /* 4356 * Free Tx/Rx mbufs still in the queues. 4357 */ 4358 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4359 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4360 if (rxd->rx_m != NULL) { 4361 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 4362 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4363 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 4364 rxd->rx_dmamap); 4365 m_freem(rxd->rx_m); 4366 rxd->rx_m = NULL; 4367 } 4368 } 4369 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4370 txd = &sc->alc_cdata.alc_txdesc[i]; 4371 if (txd->tx_m != NULL) { 4372 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 4373 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4374 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 4375 txd->tx_dmamap); 4376 m_freem(txd->tx_m); 4377 txd->tx_m = NULL; 4378 } 4379 } 4380 } 4381 4382 static void 4383 alc_stop_mac(struct alc_softc *sc) 4384 { 4385 uint32_t reg; 4386 int i; 4387 4388 alc_stop_queue(sc); 4389 /* Disable Rx/Tx MAC. */ 4390 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4391 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 4392 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 4393 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4394 } 4395 for (i = ALC_TIMEOUT; i > 0; i--) { 4396 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4397 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 4398 break; 4399 DELAY(10); 4400 } 4401 if (i == 0) 4402 device_printf(sc->alc_dev, 4403 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 4404 } 4405 4406 static void 4407 alc_start_queue(struct alc_softc *sc) 4408 { 4409 uint32_t qcfg[] = { 4410 0, 4411 RXQ_CFG_QUEUE0_ENB, 4412 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 4413 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 4414 RXQ_CFG_ENB 4415 }; 4416 uint32_t cfg; 4417 4418 ALC_LOCK_ASSERT(sc); 4419 4420 /* Enable RxQ. */ 4421 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 4422 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4423 cfg &= ~RXQ_CFG_ENB; 4424 cfg |= qcfg[1]; 4425 } else 4426 cfg |= RXQ_CFG_QUEUE0_ENB; 4427 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 4428 /* Enable TxQ. */ 4429 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 4430 cfg |= TXQ_CFG_ENB; 4431 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 4432 } 4433 4434 static void 4435 alc_stop_queue(struct alc_softc *sc) 4436 { 4437 uint32_t reg; 4438 int i; 4439 4440 /* Disable RxQ. */ 4441 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 4442 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4443 if ((reg & RXQ_CFG_ENB) != 0) { 4444 reg &= ~RXQ_CFG_ENB; 4445 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4446 } 4447 } else { 4448 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 4449 reg &= ~RXQ_CFG_QUEUE0_ENB; 4450 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4451 } 4452 } 4453 /* Disable TxQ. */ 4454 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 4455 if ((reg & TXQ_CFG_ENB) != 0) { 4456 reg &= ~TXQ_CFG_ENB; 4457 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 4458 } 4459 DELAY(40); 4460 for (i = ALC_TIMEOUT; i > 0; i--) { 4461 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4462 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 4463 break; 4464 DELAY(10); 4465 } 4466 if (i == 0) 4467 device_printf(sc->alc_dev, 4468 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 4469 } 4470 4471 static void 4472 alc_init_tx_ring(struct alc_softc *sc) 4473 { 4474 struct alc_ring_data *rd; 4475 struct alc_txdesc *txd; 4476 int i; 4477 4478 ALC_LOCK_ASSERT(sc); 4479 4480 sc->alc_cdata.alc_tx_prod = 0; 4481 sc->alc_cdata.alc_tx_cons = 0; 4482 sc->alc_cdata.alc_tx_cnt = 0; 4483 4484 rd = &sc->alc_rdata; 4485 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 4486 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4487 txd = &sc->alc_cdata.alc_txdesc[i]; 4488 txd->tx_m = NULL; 4489 } 4490 4491 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 4492 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 4493 } 4494 4495 static int 4496 alc_init_rx_ring(struct alc_softc *sc) 4497 { 4498 struct alc_ring_data *rd; 4499 struct alc_rxdesc *rxd; 4500 int i; 4501 4502 ALC_LOCK_ASSERT(sc); 4503 4504 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 4505 sc->alc_morework = 0; 4506 rd = &sc->alc_rdata; 4507 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 4508 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4509 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4510 rxd->rx_m = NULL; 4511 rxd->rx_desc = &rd->alc_rx_ring[i]; 4512 if (alc_newbuf(sc, rxd) != 0) 4513 return (ENOBUFS); 4514 } 4515 4516 /* 4517 * Since controller does not update Rx descriptors, driver 4518 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 4519 * is enough to ensure coherence. 4520 */ 4521 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 4522 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 4523 /* Let controller know availability of new Rx buffers. */ 4524 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 4525 4526 return (0); 4527 } 4528 4529 static void 4530 alc_init_rr_ring(struct alc_softc *sc) 4531 { 4532 struct alc_ring_data *rd; 4533 4534 ALC_LOCK_ASSERT(sc); 4535 4536 sc->alc_cdata.alc_rr_cons = 0; 4537 ALC_RXCHAIN_RESET(sc); 4538 4539 rd = &sc->alc_rdata; 4540 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 4541 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 4542 sc->alc_cdata.alc_rr_ring_map, 4543 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4544 } 4545 4546 static void 4547 alc_init_cmb(struct alc_softc *sc) 4548 { 4549 struct alc_ring_data *rd; 4550 4551 ALC_LOCK_ASSERT(sc); 4552 4553 rd = &sc->alc_rdata; 4554 bzero(rd->alc_cmb, ALC_CMB_SZ); 4555 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 4556 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4557 } 4558 4559 static void 4560 alc_init_smb(struct alc_softc *sc) 4561 { 4562 struct alc_ring_data *rd; 4563 4564 ALC_LOCK_ASSERT(sc); 4565 4566 rd = &sc->alc_rdata; 4567 bzero(rd->alc_smb, ALC_SMB_SZ); 4568 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 4569 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4570 } 4571 4572 static void 4573 alc_rxvlan(struct alc_softc *sc) 4574 { 4575 if_t ifp; 4576 uint32_t reg; 4577 4578 ALC_LOCK_ASSERT(sc); 4579 4580 ifp = sc->alc_ifp; 4581 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4582 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 4583 reg |= MAC_CFG_VLAN_TAG_STRIP; 4584 else 4585 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 4586 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4587 } 4588 4589 static u_int 4590 alc_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 4591 { 4592 uint32_t *mchash = arg; 4593 uint32_t crc; 4594 4595 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 4596 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 4597 4598 return (1); 4599 } 4600 4601 static void 4602 alc_rxfilter(struct alc_softc *sc) 4603 { 4604 if_t ifp; 4605 uint32_t mchash[2]; 4606 uint32_t rxcfg; 4607 4608 ALC_LOCK_ASSERT(sc); 4609 4610 ifp = sc->alc_ifp; 4611 4612 bzero(mchash, sizeof(mchash)); 4613 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 4614 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 4615 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 4616 rxcfg |= MAC_CFG_BCAST; 4617 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 4618 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 4619 rxcfg |= MAC_CFG_PROMISC; 4620 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 4621 rxcfg |= MAC_CFG_ALLMULTI; 4622 mchash[0] = 0xFFFFFFFF; 4623 mchash[1] = 0xFFFFFFFF; 4624 goto chipit; 4625 } 4626 4627 if_foreach_llmaddr(ifp, alc_hash_maddr, mchash); 4628 4629 chipit: 4630 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 4631 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 4632 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 4633 } 4634 4635 static int 4636 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4637 { 4638 int error, value; 4639 4640 if (arg1 == NULL) 4641 return (EINVAL); 4642 value = *(int *)arg1; 4643 error = sysctl_handle_int(oidp, &value, 0, req); 4644 if (error || req->newptr == NULL) 4645 return (error); 4646 if (value < low || value > high) 4647 return (EINVAL); 4648 *(int *)arg1 = value; 4649 4650 return (0); 4651 } 4652 4653 static int 4654 sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 4655 { 4656 return (sysctl_int_range(oidp, arg1, arg2, req, 4657 ALC_PROC_MIN, ALC_PROC_MAX)); 4658 } 4659 4660 static int 4661 sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 4662 { 4663 4664 return (sysctl_int_range(oidp, arg1, arg2, req, 4665 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 4666 } 4667 4668 #ifdef DEBUGNET 4669 static void 4670 alc_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 4671 { 4672 struct alc_softc *sc __diagused; 4673 4674 sc = if_getsoftc(ifp); 4675 KASSERT(sc->alc_buf_size <= MCLBYTES, ("incorrect cluster size")); 4676 4677 *nrxr = ALC_RX_RING_CNT; 4678 *ncl = DEBUGNET_MAX_IN_FLIGHT; 4679 *clsize = MCLBYTES; 4680 } 4681 4682 static void 4683 alc_debugnet_event(if_t ifp __unused, enum debugnet_ev event __unused) 4684 { 4685 } 4686 4687 static int 4688 alc_debugnet_transmit(if_t ifp, struct mbuf *m) 4689 { 4690 struct alc_softc *sc; 4691 int error; 4692 4693 sc = if_getsoftc(ifp); 4694 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4695 IFF_DRV_RUNNING) 4696 return (EBUSY); 4697 4698 error = alc_encap(sc, &m); 4699 if (error == 0) 4700 alc_start_tx(sc); 4701 return (error); 4702 } 4703 4704 static int 4705 alc_debugnet_poll(if_t ifp, int count) 4706 { 4707 struct alc_softc *sc; 4708 4709 sc = if_getsoftc(ifp); 4710 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4711 IFF_DRV_RUNNING) 4712 return (EBUSY); 4713 4714 alc_txeof(sc); 4715 return (alc_rxintr(sc, count)); 4716 } 4717 #endif /* DEBUGNET */ 4718