1 /*- 2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMATES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMATE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #ifndef _IF_ALCREG_H 31 #define _IF_ALCREG_H 32 33 /* 34 * Atheros Communucations, Inc. PCI vendor ID 35 */ 36 #define VENDORID_ATHEROS 0x1969 37 38 /* 39 * Atheros AR813x/AR815x device ID 40 */ 41 #define DEVICEID_ATHEROS_AR8131 0x1063 /* L1C */ 42 #define DEVICEID_ATHEROS_AR8132 0x1062 /* L2C */ 43 #define DEVICEID_ATHEROS_AR8151 0x1073 /* L1D V1.0 */ 44 #define DEVICEID_ATHEROS_AR8151_V2 0x1083 /* L1D V2.0 */ 45 #define DEVICEID_ATHEROS_AR8152_B 0x2060 /* L2C V1.1 */ 46 #define DEVICEID_ATHEROS_AR8152_B2 0x2062 /* L2C V2.0 */ 47 48 #define ATHEROS_AR8152_B_V10 0xC0 49 #define ATHEROS_AR8152_B_V11 0xC1 50 51 /* 0x0000 - 0x02FF : PCIe configuration space */ 52 53 #define ALC_PEX_UNC_ERR_SEV 0x10C 54 #define PEX_UNC_ERR_SEV_TRN 0x00000001 55 #define PEX_UNC_ERR_SEV_DLP 0x00000010 56 #define PEX_UNC_ERR_SEV_PSN_TLP 0x00001000 57 #define PEX_UNC_ERR_SEV_FCP 0x00002000 58 #define PEX_UNC_ERR_SEV_CPL_TO 0x00004000 59 #define PEX_UNC_ERR_SEV_CA 0x00008000 60 #define PEX_UNC_ERR_SEV_UC 0x00010000 61 #define PEX_UNC_ERR_SEV_ROV 0x00020000 62 #define PEX_UNC_ERR_SEV_MLFP 0x00040000 63 #define PEX_UNC_ERR_SEV_ECRC 0x00080000 64 #define PEX_UNC_ERR_SEV_UR 0x00100000 65 66 #define ALC_TWSI_CFG 0x218 67 #define TWSI_CFG_SW_LD_START 0x00000800 68 #define TWSI_CFG_HW_LD_START 0x00001000 69 #define TWSI_CFG_LD_EXIST 0x00400000 70 71 #define ALC_PCIE_PHYMISC 0x1000 72 #define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004 73 74 #define ALC_PCIE_PHYMISC2 0x1004 75 #define PCIE_PHYMISC2_SERDES_CDR_MASK 0x00030000 76 #define PCIE_PHYMISC2_SERDES_TH_MASK 0x000C0000 77 #define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16 78 #define PCIE_PHYMISC2_SERDES_TH_SHIFT 18 79 80 #define ALC_TWSI_DEBUG 0x1108 81 #define TWSI_DEBUG_DEV_EXIST 0x20000000 82 83 #define ALC_EEPROM_CFG 0x12C0 84 #define EEPROM_CFG_DATA_HI_MASK 0x0000FFFF 85 #define EEPROM_CFG_ADDR_MASK 0x03FF0000 86 #define EEPROM_CFG_ACK 0x40000000 87 #define EEPROM_CFG_RW 0x80000000 88 #define EEPROM_CFG_DATA_HI_SHIFT 0 89 #define EEPROM_CFG_ADDR_SHIFT 16 90 91 #define ALC_EEPROM_DATA_LO 0x12C4 92 93 #define ALC_OPT_CFG 0x12F0 94 #define OPT_CFG_CLK_ENB 0x00000002 95 96 #define ALC_PM_CFG 0x12F8 97 #define PM_CFG_SERDES_ENB 0x00000001 98 #define PM_CFG_RBER_ENB 0x00000002 99 #define PM_CFG_CLK_REQ_ENB 0x00000004 100 #define PM_CFG_ASPM_L1_ENB 0x00000008 101 #define PM_CFG_SERDES_L1_ENB 0x00000010 102 #define PM_CFG_SERDES_PLL_L1_ENB 0x00000020 103 #define PM_CFG_SERDES_PD_EX_L1 0x00000040 104 #define PM_CFG_SERDES_BUDS_RX_L1_ENB 0x00000080 105 #define PM_CFG_L0S_ENTRY_TIMER_MASK 0x00000F00 106 #define PM_CFG_ASPM_L0S_ENB 0x00001000 107 #define PM_CFG_CLK_SWH_L1 0x00002000 108 #define PM_CFG_CLK_PWM_VER1_1 0x00004000 109 #define PM_CFG_PCIE_RECV 0x00008000 110 #define PM_CFG_L1_ENTRY_TIMER_MASK 0x000F0000 111 #define PM_CFG_PM_REQ_TIMER_MASK 0x00F00000 112 #define PM_CFG_LCKDET_TIMER_MASK 0x3F000000 113 #define PM_CFG_EN_BUFS_RX_L0S 0x10000000 114 #define PM_CFG_SA_DLY_ENB 0x20000000 115 #define PM_CFG_MAC_ASPM_CHK 0x40000000 116 #define PM_CFG_HOTRST 0x80000000 117 #define PM_CFG_L0S_ENTRY_TIMER_SHIFT 8 118 #define PM_CFG_L1_ENTRY_TIMER_SHIFT 16 119 #define PM_CFG_PM_REQ_TIMER_SHIFT 20 120 #define PM_CFG_LCKDET_TIMER_SHIFT 24 121 122 #define PM_CFG_L0S_ENTRY_TIMER_DEFAULT 6 123 #define PM_CFG_L1_ENTRY_TIMER_DEFAULT 12 124 #define PM_CFG_PM_REQ_TIMER_DEFAULT 1 125 126 #define ALC_LTSSM_ID_CFG 0x12FC 127 #define LTSSM_ID_WRO_ENB 0x00001000 128 129 #define ALC_MASTER_CFG 0x1400 130 #define MASTER_RESET 0x00000001 131 #define MASTER_TEST_MODE_MASK 0x0000000C 132 #define MASTER_BERT_START 0x00000010 133 #define MASTER_OOB_DIS_OFF 0x00000040 134 #define MASTER_SA_TIMER_ENB 0x00000080 135 #define MASTER_MTIMER_ENB 0x00000100 136 #define MASTER_MANUAL_INTR_ENB 0x00000200 137 #define MASTER_IM_TX_TIMER_ENB 0x00000400 138 #define MASTER_IM_RX_TIMER_ENB 0x00000800 139 #define MASTER_CLK_SEL_DIS 0x00001000 140 #define MASTER_CLK_SWH_MODE 0x00002000 141 #define MASTER_INTR_RD_CLR 0x00004000 142 #define MASTER_CHIP_REV_MASK 0x00FF0000 143 #define MASTER_CHIP_ID_MASK 0x7F000000 144 #define MASTER_OTP_SEL 0x80000000 145 #define MASTER_TEST_MODE_SHIFT 2 146 #define MASTER_CHIP_REV_SHIFT 16 147 #define MASTER_CHIP_ID_SHIFT 24 148 149 /* Number of ticks per usec for AR813x/AR815x. */ 150 #define ALC_TICK_USECS 2 151 #define ALC_USECS(x) ((x) / ALC_TICK_USECS) 152 153 #define ALC_MANUAL_TIMER 0x1404 154 155 #define ALC_IM_TIMER 0x1408 156 #define IM_TIMER_TX_MASK 0x0000FFFF 157 #define IM_TIMER_RX_MASK 0xFFFF0000 158 #define IM_TIMER_TX_SHIFT 0 159 #define IM_TIMER_RX_SHIFT 16 160 #define ALC_IM_TIMER_MIN 0 161 #define ALC_IM_TIMER_MAX 130000 /* 130ms */ 162 /* 163 * 100us will ensure alc(4) wouldn't generate more than 10000 Rx 164 * interrupts in a second. 165 */ 166 #define ALC_IM_RX_TIMER_DEFAULT 100 /* 100us */ 167 /* 168 * alc(4) does not rely on Tx completion interrupts, so set it 169 * somewhat large value to reduce Tx completion interrupts. 170 */ 171 #define ALC_IM_TX_TIMER_DEFAULT 1000 /* 1ms */ 172 173 #define ALC_GPHY_CFG 0x140C /* 16bits */ 174 #define GPHY_CFG_EXT_RESET 0x0001 175 #define GPHY_CFG_RTL_MODE 0x0002 176 #define GPHY_CFG_LED_MODE 0x0004 177 #define GPHY_CFG_ANEG_NOW 0x0008 178 #define GPHY_CFG_RECV_ANEG 0x0010 179 #define GPHY_CFG_GATE_25M_ENB 0x0020 180 #define GPHY_CFG_LPW_EXIT 0x0040 181 #define GPHY_CFG_PHY_IDDQ 0x0080 182 #define GPHY_CFG_PHY_IDDQ_DIS 0x0100 183 #define GPHY_CFG_PCLK_SEL_DIS 0x0200 184 #define GPHY_CFG_HIB_EN 0x0400 185 #define GPHY_CFG_HIB_PULSE 0x0800 186 #define GPHY_CFG_SEL_ANA_RESET 0x1000 187 #define GPHY_CFG_PHY_PLL_ON 0x2000 188 #define GPHY_CFG_PWDOWN_HW 0x4000 189 #define GPHY_CFG_PHY_PLL_BYPASS 0x8000 190 191 #define ALC_IDLE_STATUS 0x1410 192 #define IDLE_STATUS_RXMAC 0x00000001 193 #define IDLE_STATUS_TXMAC 0x00000002 194 #define IDLE_STATUS_RXQ 0x00000004 195 #define IDLE_STATUS_TXQ 0x00000008 196 #define IDLE_STATUS_DMARD 0x00000010 197 #define IDLE_STATUS_DMAWR 0x00000020 198 #define IDLE_STATUS_SMB 0x00000040 199 #define IDLE_STATUS_CMB 0x00000080 200 201 #define ALC_MDIO 0x1414 202 #define MDIO_DATA_MASK 0x0000FFFF 203 #define MDIO_REG_ADDR_MASK 0x001F0000 204 #define MDIO_OP_READ 0x00200000 205 #define MDIO_OP_WRITE 0x00000000 206 #define MDIO_SUP_PREAMBLE 0x00400000 207 #define MDIO_OP_EXECUTE 0x00800000 208 #define MDIO_CLK_25_4 0x00000000 209 #define MDIO_CLK_25_6 0x02000000 210 #define MDIO_CLK_25_8 0x03000000 211 #define MDIO_CLK_25_10 0x04000000 212 #define MDIO_CLK_25_14 0x05000000 213 #define MDIO_CLK_25_20 0x06000000 214 #define MDIO_CLK_25_28 0x07000000 215 #define MDIO_OP_BUSY 0x08000000 216 #define MDIO_AP_ENB 0x10000000 217 #define MDIO_DATA_SHIFT 0 218 #define MDIO_REG_ADDR_SHIFT 16 219 220 #define MDIO_REG_ADDR(x) \ 221 (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK) 222 /* Default PHY address. */ 223 #define ALC_PHY_ADDR 0 224 225 #define ALC_PHY_STATUS 0x1418 226 #define PHY_STATUS_RECV_ENB 0x00000001 227 #define PHY_STATUS_GENERAL_MASK 0x0000FFFF 228 #define PHY_STATUS_OE_PWSP_MASK 0x07FF0000 229 #define PHY_STATUS_LPW_STATE 0x80000000 230 #define PHY_STATIS_OE_PWSP_SHIFT 16 231 232 /* Packet memory BIST. */ 233 #define ALC_BIST0 0x141C 234 #define BIST0_ENB 0x00000001 235 #define BIST0_SRAM_FAIL 0x00000002 236 #define BIST0_FUSE_FLAG 0x00000004 237 238 /* PCIe retry buffer BIST. */ 239 #define ALC_BIST1 0x1420 240 #define BIST1_ENB 0x00000001 241 #define BIST1_SRAM_FAIL 0x00000002 242 #define BIST1_FUSE_FLAG 0x00000004 243 244 #define ALC_SERDES_LOCK 0x1424 245 #define SERDES_LOCK_DET 0x00000001 246 #define SERDES_LOCK_DET_ENB 0x00000002 247 #define SERDES_MAC_CLK_SLOWDOWN 0x00020000 248 #define SERDES_PHY_CLK_SLOWDOWN 0x00040000 249 250 #define ALC_MAC_CFG 0x1480 251 #define MAC_CFG_TX_ENB 0x00000001 252 #define MAC_CFG_RX_ENB 0x00000002 253 #define MAC_CFG_TX_FC 0x00000004 254 #define MAC_CFG_RX_FC 0x00000008 255 #define MAC_CFG_LOOP 0x00000010 256 #define MAC_CFG_FULL_DUPLEX 0x00000020 257 #define MAC_CFG_TX_CRC_ENB 0x00000040 258 #define MAC_CFG_TX_AUTO_PAD 0x00000080 259 #define MAC_CFG_TX_LENCHK 0x00000100 260 #define MAC_CFG_RX_JUMBO_ENB 0x00000200 261 #define MAC_CFG_PREAMBLE_MASK 0x00003C00 262 #define MAC_CFG_VLAN_TAG_STRIP 0x00004000 263 #define MAC_CFG_PROMISC 0x00008000 264 #define MAC_CFG_TX_PAUSE 0x00010000 265 #define MAC_CFG_SCNT 0x00020000 266 #define MAC_CFG_SYNC_RST_TX 0x00040000 267 #define MAC_CFG_SIM_RST_TX 0x00080000 268 #define MAC_CFG_SPEED_MASK 0x00300000 269 #define MAC_CFG_SPEED_10_100 0x00100000 270 #define MAC_CFG_SPEED_1000 0x00200000 271 #define MAC_CFG_DBG_TX_BACKOFF 0x00400000 272 #define MAC_CFG_TX_JUMBO_ENB 0x00800000 273 #define MAC_CFG_RXCSUM_ENB 0x01000000 274 #define MAC_CFG_ALLMULTI 0x02000000 275 #define MAC_CFG_BCAST 0x04000000 276 #define MAC_CFG_DBG 0x08000000 277 #define MAC_CFG_SINGLE_PAUSE_ENB 0x10000000 278 #define MAC_CFG_HASH_ALG_CRC32 0x20000000 279 #define MAC_CFG_SPEED_MODE_SW 0x40000000 280 #define MAC_CFG_PREAMBLE_SHIFT 10 281 #define MAC_CFG_PREAMBLE_DEFAULT 7 282 283 #define ALC_IPG_IFG_CFG 0x1484 284 #define IPG_IFG_IPGT_MASK 0x0000007F 285 #define IPG_IFG_MIFG_MASK 0x0000FF00 286 #define IPG_IFG_IPG1_MASK 0x007F0000 287 #define IPG_IFG_IPG2_MASK 0x7F000000 288 #define IPG_IFG_IPGT_SHIFT 0 289 #define IPG_IFG_IPGT_DEFAULT 0x60 290 #define IPG_IFG_MIFG_SHIFT 8 291 #define IPG_IFG_MIFG_DEFAULT 0x50 292 #define IPG_IFG_IPG1_SHIFT 16 293 #define IPG_IFG_IPG1_DEFAULT 0x40 294 #define IPG_IFG_IPG2_SHIFT 24 295 #define IPG_IFG_IPG2_DEFAULT 0x60 296 297 /* Station address. */ 298 #define ALC_PAR0 0x1488 299 #define ALC_PAR1 0x148C 300 301 /* 64bit multicast hash register. */ 302 #define ALC_MAR0 0x1490 303 #define ALC_MAR1 0x1494 304 305 /* half-duplex parameter configuration. */ 306 #define ALC_HDPX_CFG 0x1498 307 #define HDPX_CFG_LCOL_MASK 0x000003FF 308 #define HDPX_CFG_RETRY_MASK 0x0000F000 309 #define HDPX_CFG_EXC_DEF_EN 0x00010000 310 #define HDPX_CFG_NO_BACK_C 0x00020000 311 #define HDPX_CFG_NO_BACK_P 0x00040000 312 #define HDPX_CFG_ABEBE 0x00080000 313 #define HDPX_CFG_ABEBT_MASK 0x00F00000 314 #define HDPX_CFG_JAMIPG_MASK 0x0F000000 315 #define HDPX_CFG_LCOL_SHIFT 0 316 #define HDPX_CFG_LCOL_DEFAULT 0x37 317 #define HDPX_CFG_RETRY_SHIFT 12 318 #define HDPX_CFG_RETRY_DEFAULT 0x0F 319 #define HDPX_CFG_ABEBT_SHIFT 20 320 #define HDPX_CFG_ABEBT_DEFAULT 0x0A 321 #define HDPX_CFG_JAMIPG_SHIFT 24 322 #define HDPX_CFG_JAMIPG_DEFAULT 0x07 323 324 #define ALC_FRAME_SIZE 0x149C 325 326 #define ALC_WOL_CFG 0x14A0 327 #define WOL_CFG_PATTERN 0x00000001 328 #define WOL_CFG_PATTERN_ENB 0x00000002 329 #define WOL_CFG_MAGIC 0x00000004 330 #define WOL_CFG_MAGIC_ENB 0x00000008 331 #define WOL_CFG_LINK_CHG 0x00000010 332 #define WOL_CFG_LINK_CHG_ENB 0x00000020 333 #define WOL_CFG_PATTERN_DET 0x00000100 334 #define WOL_CFG_MAGIC_DET 0x00000200 335 #define WOL_CFG_LINK_CHG_DET 0x00000400 336 #define WOL_CFG_CLK_SWITCH_ENB 0x00008000 337 #define WOL_CFG_PATTERN0 0x00010000 338 #define WOL_CFG_PATTERN1 0x00020000 339 #define WOL_CFG_PATTERN2 0x00040000 340 #define WOL_CFG_PATTERN3 0x00080000 341 #define WOL_CFG_PATTERN4 0x00100000 342 #define WOL_CFG_PATTERN5 0x00200000 343 #define WOL_CFG_PATTERN6 0x00400000 344 345 /* WOL pattern length. */ 346 #define ALC_PATTERN_CFG0 0x14A4 347 #define PATTERN_CFG_0_LEN_MASK 0x0000007F 348 #define PATTERN_CFG_1_LEN_MASK 0x00007F00 349 #define PATTERN_CFG_2_LEN_MASK 0x007F0000 350 #define PATTERN_CFG_3_LEN_MASK 0x7F000000 351 352 #define ALC_PATTERN_CFG1 0x14A8 353 #define PATTERN_CFG_4_LEN_MASK 0x0000007F 354 #define PATTERN_CFG_5_LEN_MASK 0x00007F00 355 #define PATTERN_CFG_6_LEN_MASK 0x007F0000 356 357 /* RSS */ 358 #define ALC_RSS_KEY0 0x14B0 359 360 #define ALC_RSS_KEY1 0x14B4 361 362 #define ALC_RSS_KEY2 0x14B8 363 364 #define ALC_RSS_KEY3 0x14BC 365 366 #define ALC_RSS_KEY4 0x14C0 367 368 #define ALC_RSS_KEY5 0x14C4 369 370 #define ALC_RSS_KEY6 0x14C8 371 372 #define ALC_RSS_KEY7 0x14CC 373 374 #define ALC_RSS_KEY8 0x14D0 375 376 #define ALC_RSS_KEY9 0x14D4 377 378 #define ALC_RSS_IDT_TABLE0 0x14E0 379 380 #define ALC_RSS_IDT_TABLE1 0x14E4 381 382 #define ALC_RSS_IDT_TABLE2 0x14E8 383 384 #define ALC_RSS_IDT_TABLE3 0x14EC 385 386 #define ALC_RSS_IDT_TABLE4 0x14F0 387 388 #define ALC_RSS_IDT_TABLE5 0x14F4 389 390 #define ALC_RSS_IDT_TABLE6 0x14F8 391 392 #define ALC_RSS_IDT_TABLE7 0x14FC 393 394 #define ALC_SRAM_RD0_ADDR 0x1500 395 396 #define ALC_SRAM_RD1_ADDR 0x1504 397 398 #define ALC_SRAM_RD2_ADDR 0x1508 399 400 #define ALC_SRAM_RD3_ADDR 0x150C 401 402 #define RD_HEAD_ADDR_MASK 0x000003FF 403 #define RD_TAIL_ADDR_MASK 0x03FF0000 404 #define RD_HEAD_ADDR_SHIFT 0 405 #define RD_TAIL_ADDR_SHIFT 16 406 407 #define ALC_RD_NIC_LEN0 0x1510 /* 8 bytes unit */ 408 #define RD_NIC_LEN_MASK 0x000003FF 409 410 #define ALC_RD_NIC_LEN1 0x1514 411 412 #define ALC_SRAM_TD_ADDR 0x1518 413 #define TD_HEAD_ADDR_MASK 0x000003FF 414 #define TD_TAIL_ADDR_MASK 0x03FF0000 415 #define TD_HEAD_ADDR_SHIFT 0 416 #define TD_TAIL_ADDR_SHIFT 16 417 418 #define ALC_SRAM_TD_LEN 0x151C /* 8 bytes unit */ 419 #define SRAM_TD_LEN_MASK 0x000003FF 420 421 #define ALC_SRAM_RX_FIFO_ADDR 0x1520 422 423 #define ALC_SRAM_RX_FIFO_LEN 0x1524 424 425 #define ALC_SRAM_TX_FIFO_ADDR 0x1528 426 427 #define ALC_SRAM_TX_FIFO_LEN 0x152C 428 429 #define ALC_SRAM_TCPH_ADDR 0x1530 430 #define SRAM_TCPH_ADDR_MASK 0x00000FFF 431 #define SRAM_PATH_ADDR_MASK 0x0FFF0000 432 #define SRAM_TCPH_ADDR_SHIFT 0 433 #define SRAM_PKTH_ADDR_SHIFT 16 434 435 #define ALC_DMA_BLOCK 0x1534 436 #define DMA_BLOCK_LOAD 0x00000001 437 438 #define ALC_RX_BASE_ADDR_HI 0x1540 439 440 #define ALC_TX_BASE_ADDR_HI 0x1544 441 442 #define ALC_SMB_BASE_ADDR_HI 0x1548 443 444 #define ALC_SMB_BASE_ADDR_LO 0x154C 445 446 #define ALC_RD0_HEAD_ADDR_LO 0x1550 447 448 #define ALC_RD1_HEAD_ADDR_LO 0x1554 449 450 #define ALC_RD2_HEAD_ADDR_LO 0x1558 451 452 #define ALC_RD3_HEAD_ADDR_LO 0x155C 453 454 #define ALC_RD_RING_CNT 0x1560 455 #define RD_RING_CNT_MASK 0x00000FFF 456 #define RD_RING_CNT_SHIFT 0 457 458 #define ALC_RX_BUF_SIZE 0x1564 459 #define RX_BUF_SIZE_MASK 0x0000FFFF 460 /* 461 * If larger buffer size than 1536 is specified the controller 462 * will be locked up. This is hardware limitation. 463 */ 464 #define RX_BUF_SIZE_MAX 1536 465 466 #define ALC_RRD0_HEAD_ADDR_LO 0x1568 467 468 #define ALC_RRD1_HEAD_ADDR_LO 0x156C 469 470 #define ALC_RRD2_HEAD_ADDR_LO 0x1570 471 472 #define ALC_RRD3_HEAD_ADDR_LO 0x1574 473 474 #define ALC_RRD_RING_CNT 0x1578 475 #define RRD_RING_CNT_MASK 0x00000FFF 476 #define RRD_RING_CNT_SHIFT 0 477 478 #define ALC_TDH_HEAD_ADDR_LO 0x157C 479 480 #define ALC_TDL_HEAD_ADDR_LO 0x1580 481 482 #define ALC_TD_RING_CNT 0x1584 483 #define TD_RING_CNT_MASK 0x0000FFFF 484 #define TD_RING_CNT_SHIFT 0 485 486 #define ALC_CMB_BASE_ADDR_LO 0x1588 487 488 #define ALC_TXQ_CFG 0x1590 489 #define TXQ_CFG_TD_BURST_MASK 0x0000000F 490 #define TXQ_CFG_IP_OPTION_ENB 0x00000010 491 #define TXQ_CFG_ENB 0x00000020 492 #define TXQ_CFG_ENHANCED_MODE 0x00000040 493 #define TXQ_CFG_8023_ENB 0x00000080 494 #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000 495 #define TXQ_CFG_TD_BURST_SHIFT 0 496 #define TXQ_CFG_TD_BURST_DEFAULT 5 497 #define TXQ_CFG_TX_FIFO_BURST_SHIFT 16 498 499 #define ALC_TSO_OFFLOAD_THRESH 0x1594 /* 8 bytes unit */ 500 #define TSO_OFFLOAD_THRESH_MASK 0x000007FF 501 #define TSO_OFFLOAD_THRESH_SHIFT 0 502 #define TSO_OFFLOAD_THRESH_UNIT 8 503 #define TSO_OFFLOAD_THRESH_UNIT_SHIFT 3 504 505 #define ALC_TXF_WATER_MARK 0x1598 /* 8 bytes unit */ 506 #define TXF_WATER_MARK_HI_MASK 0x00000FFF 507 #define TXF_WATER_MARK_LO_MASK 0x0FFF0000 508 #define TXF_WATER_MARK_BURST_ENB 0x80000000 509 #define TXF_WATER_MARK_LO_SHIFT 0 510 #define TXF_WATER_MARK_HI_SHIFT 16 511 512 #define ALC_THROUGHPUT_MON 0x159C 513 #define THROUGHPUT_MON_RATE_MASK 0x00000003 514 #define THROUGHPUT_MON_ENB 0x00000080 515 #define THROUGHPUT_MON_RATE_SHIFT 0 516 517 #define ALC_RXQ_CFG 0x15A0 518 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_MASK 0x00000003 519 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_NONE 0x00000000 520 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M 0x00000001 521 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_10M 0x00000002 522 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M 0x00000003 523 #define RXQ_CFG_QUEUE1_ENB 0x00000010 524 #define RXQ_CFG_QUEUE2_ENB 0x00000020 525 #define RXQ_CFG_QUEUE3_ENB 0x00000040 526 #define RXQ_CFG_IPV6_CSUM_ENB 0x00000080 527 #define RXQ_CFG_RSS_HASH_TBL_LEN_MASK 0x0000FF00 528 #define RXQ_CFG_RSS_HASH_IPV4 0x00010000 529 #define RXQ_CFG_RSS_HASH_IPV4_TCP 0x00020000 530 #define RXQ_CFG_RSS_HASH_IPV6 0x00040000 531 #define RXQ_CFG_RSS_HASH_IPV6_TCP 0x00080000 532 #define RXQ_CFG_RD_BURST_MASK 0x03F00000 533 #define RXQ_CFG_RSS_MODE_DIS 0x00000000 534 #define RXQ_CFG_RSS_MODE_SQSINT 0x04000000 535 #define RXQ_CFG_RSS_MODE_MQUESINT 0x08000000 536 #define RXQ_CFG_RSS_MODE_MQUEMINT 0x0C000000 537 #define RXQ_CFG_NIP_QUEUE_SEL_TBL 0x10000000 538 #define RXQ_CFG_RSS_HASH_ENB 0x20000000 539 #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000 540 #define RXQ_CFG_QUEUE0_ENB 0x80000000 541 #define RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT 8 542 #define RXQ_CFG_RD_BURST_DEFAULT 8 543 #define RXQ_CFG_RD_BURST_SHIFT 20 544 #define RXQ_CFG_ENB \ 545 (RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | \ 546 RXQ_CFG_QUEUE2_ENB | RXQ_CFG_QUEUE3_ENB) 547 548 #define ALC_RX_RD_FREE_THRESH 0x15A4 /* 8 bytes unit. */ 549 #define RX_RD_FREE_THRESH_HI_MASK 0x0000003F 550 #define RX_RD_FREE_THRESH_LO_MASK 0x00000FC0 551 #define RX_RD_FREE_THRESH_HI_SHIFT 0 552 #define RX_RD_FREE_THRESH_LO_SHIFT 6 553 #define RX_RD_FREE_THRESH_HI_DEFAULT 16 554 #define RX_RD_FREE_THRESH_LO_DEFAULT 8 555 556 #define ALC_RX_FIFO_PAUSE_THRESH 0x15A8 557 #define RX_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF 558 #define RX_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF0000 559 #define RX_FIFO_PAUSE_THRESH_LO_SHIFT 0 560 #define RX_FIFO_PAUSE_THRESH_HI_SHIFT 16 561 562 #define ALC_RD_DMA_CFG 0x15AC 563 #define RD_DMA_CFG_THRESH_MASK 0x00000FFF /* 8 bytes unit */ 564 #define RD_DMA_CFG_TIMER_MASK 0xFFFF0000 565 #define RD_DMA_CFG_THRESH_SHIFT 0 566 #define RD_DMA_CFG_TIMER_SHIFT 16 567 #define RD_DMA_CFG_THRESH_DEFAULT 0x100 568 #define RD_DMA_CFG_TIMER_DEFAULT 0 569 #define RD_DMA_CFG_TICK_USECS 8 570 #define ALC_RD_DMA_CFG_USECS(x) ((x) / RD_DMA_CFG_TICK_USECS) 571 572 #define ALC_RSS_HASH_VALUE 0x15B0 573 574 #define ALC_RSS_HASH_FLAG 0x15B4 575 576 #define ALC_RSS_CPU 0x15B8 577 578 #define ALC_DMA_CFG 0x15C0 579 #define DMA_CFG_IN_ORDER 0x00000001 580 #define DMA_CFG_ENH_ORDER 0x00000002 581 #define DMA_CFG_OUT_ORDER 0x00000004 582 #define DMA_CFG_RCB_64 0x00000000 583 #define DMA_CFG_RCB_128 0x00000008 584 #define DMA_CFG_RD_BURST_128 0x00000000 585 #define DMA_CFG_RD_BURST_256 0x00000010 586 #define DMA_CFG_RD_BURST_512 0x00000020 587 #define DMA_CFG_RD_BURST_1024 0x00000030 588 #define DMA_CFG_RD_BURST_2048 0x00000040 589 #define DMA_CFG_RD_BURST_4096 0x00000050 590 #define DMA_CFG_WR_BURST_128 0x00000000 591 #define DMA_CFG_WR_BURST_256 0x00000080 592 #define DMA_CFG_WR_BURST_512 0x00000100 593 #define DMA_CFG_WR_BURST_1024 0x00000180 594 #define DMA_CFG_WR_BURST_2048 0x00000200 595 #define DMA_CFG_WR_BURST_4096 0x00000280 596 #define DMA_CFG_RD_REQ_PRI 0x00000400 597 #define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800 598 #define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000 599 #define DMA_CFG_CMB_ENB 0x00100000 600 #define DMA_CFG_SMB_ENB 0x00200000 601 #define DMA_CFG_CMB_NOW 0x00400000 602 #define DMA_CFG_SMB_DIS 0x01000000 603 #define DMA_CFG_SMB_NOW 0x80000000 604 #define DMA_CFG_RD_BURST_MASK 0x07 605 #define DMA_CFG_RD_BURST_SHIFT 4 606 #define DMA_CFG_WR_BURST_MASK 0x07 607 #define DMA_CFG_WR_BURST_SHIFT 7 608 #define DMA_CFG_RD_DELAY_CNT_SHIFT 11 609 #define DMA_CFG_WR_DELAY_CNT_SHIFT 16 610 #define DMA_CFG_RD_DELAY_CNT_DEFAULT 15 611 #define DMA_CFG_WR_DELAY_CNT_DEFAULT 4 612 613 #define ALC_SMB_STAT_TIMER 0x15C4 614 #define SMB_STAT_TIMER_MASK 0x00FFFFFF 615 #define SMB_STAT_TIMER_SHIFT 0 616 617 #define ALC_CMB_TD_THRESH 0x15C8 618 #define CMB_TD_THRESH_MASK 0x0000FFFF 619 #define CMB_TD_THRESH_SHIFT 0 620 621 #define ALC_CMB_TX_TIMER 0x15CC 622 #define CMB_TX_TIMER_MASK 0x0000FFFF 623 #define CMB_TX_TIMER_SHIFT 0 624 625 #define ALC_MBOX_RD0_PROD_IDX 0x15E0 626 627 #define ALC_MBOX_RD1_PROD_IDX 0x15E4 628 629 #define ALC_MBOX_RD2_PROD_IDX 0x15E8 630 631 #define ALC_MBOX_RD3_PROD_IDX 0x15EC 632 633 #define ALC_MBOX_RD_PROD_MASK 0x0000FFFF 634 #define MBOX_RD_PROD_SHIFT 0 635 636 #define ALC_MBOX_TD_PROD_IDX 0x15F0 637 #define MBOX_TD_PROD_HI_IDX_MASK 0x0000FFFF 638 #define MBOX_TD_PROD_LO_IDX_MASK 0xFFFF0000 639 #define MBOX_TD_PROD_HI_IDX_SHIFT 0 640 #define MBOX_TD_PROD_LO_IDX_SHIFT 16 641 642 #define ALC_MBOX_TD_CONS_IDX 0x15F4 643 #define MBOX_TD_CONS_HI_IDX_MASK 0x0000FFFF 644 #define MBOX_TD_CONS_LO_IDX_MASK 0xFFFF0000 645 #define MBOX_TD_CONS_HI_IDX_SHIFT 0 646 #define MBOX_TD_CONS_LO_IDX_SHIFT 16 647 648 #define ALC_MBOX_RD01_CONS_IDX 0x15F8 649 #define MBOX_RD0_CONS_IDX_MASK 0x0000FFFF 650 #define MBOX_RD1_CONS_IDX_MASK 0xFFFF0000 651 #define MBOX_RD0_CONS_IDX_SHIFT 0 652 #define MBOX_RD1_CONS_IDX_SHIFT 16 653 654 #define ALC_MBOX_RD23_CONS_IDX 0x15FC 655 #define MBOX_RD2_CONS_IDX_MASK 0x0000FFFF 656 #define MBOX_RD3_CONS_IDX_MASK 0xFFFF0000 657 #define MBOX_RD2_CONS_IDX_SHIFT 0 658 #define MBOX_RD3_CONS_IDX_SHIFT 16 659 660 #define ALC_INTR_STATUS 0x1600 661 #define INTR_SMB 0x00000001 662 #define INTR_TIMER 0x00000002 663 #define INTR_MANUAL_TIMER 0x00000004 664 #define INTR_RX_FIFO_OFLOW 0x00000008 665 #define INTR_RD0_UNDERRUN 0x00000010 666 #define INTR_RD1_UNDERRUN 0x00000020 667 #define INTR_RD2_UNDERRUN 0x00000040 668 #define INTR_RD3_UNDERRUN 0x00000080 669 #define INTR_TX_FIFO_UNDERRUN 0x00000100 670 #define INTR_DMA_RD_TO_RST 0x00000200 671 #define INTR_DMA_WR_TO_RST 0x00000400 672 #define INTR_TX_CREDIT 0x00000800 673 #define INTR_GPHY 0x00001000 674 #define INTR_GPHY_LOW_PW 0x00002000 675 #define INTR_TXQ_TO_RST 0x00004000 676 #define INTR_TX_PKT 0x00008000 677 #define INTR_RX_PKT0 0x00010000 678 #define INTR_RX_PKT1 0x00020000 679 #define INTR_RX_PKT2 0x00040000 680 #define INTR_RX_PKT3 0x00080000 681 #define INTR_MAC_RX 0x00100000 682 #define INTR_MAC_TX 0x00200000 683 #define INTR_UNDERRUN 0x00400000 684 #define INTR_FRAME_ERROR 0x00800000 685 #define INTR_FRAME_OK 0x01000000 686 #define INTR_CSUM_ERROR 0x02000000 687 #define INTR_PHY_LINK_DOWN 0x04000000 688 #define INTR_DIS_INT 0x80000000 689 690 /* Interrupt Mask Register */ 691 #define ALC_INTR_MASK 0x1604 692 693 #ifdef notyet 694 #define INTR_RX_PKT \ 695 (INTR_RX_PKT0 | INTR_RX_PKT1 | INTR_RX_PKT2 | \ 696 INTR_RX_PKT3) 697 #define INTR_RD_UNDERRUN \ 698 (INTR_RD0_UNDERRUN | INTR_RD1_UNDERRUN | \ 699 INTR_RD2_UNDERRUN | INTR_RD3_UNDERRUN) 700 #else 701 #define INTR_RX_PKT INTR_RX_PKT0 702 #define INTR_RD_UNDERRUN INTR_RD0_UNDERRUN 703 #endif 704 705 #define ALC_INTRS \ 706 (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \ 707 INTR_TXQ_TO_RST | INTR_RX_PKT | INTR_TX_PKT | \ 708 INTR_RX_FIFO_OFLOW | INTR_RD_UNDERRUN | \ 709 INTR_TX_FIFO_UNDERRUN) 710 711 #define ALC_INTR_RETRIG_TIMER 0x1608 712 #define INTR_RETRIG_TIMER_MASK 0x0000FFFF 713 #define INTR_RETRIG_TIMER_SHIFT 0 714 715 #define ALC_HDS_CFG 0x160C 716 #define HDS_CFG_ENB 0x00000001 717 #define HDS_CFG_BACKFILLSIZE_MASK 0x000FFF00 718 #define HDS_CFG_MAX_HDRSIZE_MASK 0xFFF00000 719 #define HDS_CFG_BACKFILLSIZE_SHIFT 8 720 #define HDS_CFG_MAX_HDRSIZE_SHIFT 20 721 722 /* AR813x/AR815x registers for MAC statistics */ 723 #define ALC_RX_MIB_BASE 0x1700 724 725 #define ALC_TX_MIB_BASE 0x1760 726 727 #define ALC_DEBUG_DATA0 0x1900 728 729 #define ALC_DEBUG_DATA1 0x1904 730 731 #define ALC_MII_DBG_ADDR 0x1D 732 #define ALC_MII_DBG_DATA 0x1E 733 734 #define MII_ANA_CFG0 0x00 735 #define ANA_RESTART_CAL 0x0001 736 #define ANA_MANUL_SWICH_ON_MASK 0x001E 737 #define ANA_MAN_ENABLE 0x0020 738 #define ANA_SEL_HSP 0x0040 739 #define ANA_EN_HB 0x0080 740 #define ANA_EN_HBIAS 0x0100 741 #define ANA_OEN_125M 0x0200 742 #define ANA_EN_LCKDT 0x0400 743 #define ANA_LCKDT_PHY 0x0800 744 #define ANA_AFE_MODE 0x1000 745 #define ANA_VCO_SLOW 0x2000 746 #define ANA_VCO_FAST 0x4000 747 #define ANA_SEL_CLK125M_DSP 0x8000 748 #define ANA_MANUL_SWICH_ON_SHIFT 1 749 750 #define MII_ANA_CFG4 0x04 751 #define ANA_IECHO_ADJ_MASK 0x0F 752 #define ANA_IECHO_ADJ_3_MASK 0x000F 753 #define ANA_IECHO_ADJ_2_MASK 0x00F0 754 #define ANA_IECHO_ADJ_1_MASK 0x0F00 755 #define ANA_IECHO_ADJ_0_MASK 0xF000 756 #define ANA_IECHO_ADJ_3_SHIFT 0 757 #define ANA_IECHO_ADJ_2_SHIFT 4 758 #define ANA_IECHO_ADJ_1_SHIFT 8 759 #define ANA_IECHO_ADJ_0_SHIFT 12 760 761 #define MII_ANA_CFG5 0x05 762 #define ANA_SERDES_CDR_BW_MASK 0x0003 763 #define ANA_MS_PAD_DBG 0x0004 764 #define ANA_SPEEDUP_DBG 0x0008 765 #define ANA_SERDES_TH_LOS_MASK 0x0030 766 #define ANA_SERDES_EN_DEEM 0x0040 767 #define ANA_SERDES_TXELECIDLE 0x0080 768 #define ANA_SERDES_BEACON 0x0100 769 #define ANA_SERDES_HALFTXDR 0x0200 770 #define ANA_SERDES_SEL_HSP 0x0400 771 #define ANA_SERDES_EN_PLL 0x0800 772 #define ANA_SERDES_EN 0x1000 773 #define ANA_SERDES_EN_LCKDT 0x2000 774 #define ANA_SERDES_CDR_BW_SHIFT 0 775 #define ANA_SERDES_TH_LOS_SHIFT 4 776 777 #define MII_ANA_CFG11 0x0B 778 #define ANA_PS_HIB_EN 0x8000 779 780 #define MII_ANA_CFG18 0x12 781 #define ANA_TEST_MODE_10BT_01MASK 0x0003 782 #define ANA_LOOP_SEL_10BT 0x0004 783 #define ANA_RGMII_MODE_SW 0x0008 784 #define ANA_EN_LONGECABLE 0x0010 785 #define ANA_TEST_MODE_10BT_2 0x0020 786 #define ANA_EN_10BT_IDLE 0x0400 787 #define ANA_EN_MASK_TB 0x0800 788 #define ANA_TRIGGER_SEL_TIMER_MASK 0x3000 789 #define ANA_INTERVAL_SEL_TIMER_MASK 0xC000 790 #define ANA_TEST_MODE_10BT_01SHIFT 0 791 #define ANA_TRIGGER_SEL_TIMER_SHIFT 12 792 #define ANA_INTERVAL_SEL_TIMER_SHIFT 14 793 794 #define MII_ANA_CFG41 0x29 795 #define ANA_TOP_PS_EN 0x8000 796 797 #define MII_ANA_CFG54 0x36 798 #define ANA_LONG_CABLE_TH_100_MASK 0x003F 799 #define ANA_DESERVED 0x0040 800 #define ANA_EN_LIT_CH 0x0080 801 #define ANA_SHORT_CABLE_TH_100_MASK 0x3F00 802 #define ANA_BP_BAD_LINK_ACCUM 0x4000 803 #define ANA_BP_SMALL_BW 0x8000 804 #define ANA_LONG_CABLE_TH_100_SHIFT 0 805 #define ANA_SHORT_CABLE_TH_100_SHIFT 8 806 807 /* Statistics counters collected by the MAC. */ 808 struct smb { 809 /* Rx stats. */ 810 uint32_t rx_frames; 811 uint32_t rx_bcast_frames; 812 uint32_t rx_mcast_frames; 813 uint32_t rx_pause_frames; 814 uint32_t rx_control_frames; 815 uint32_t rx_crcerrs; 816 uint32_t rx_lenerrs; 817 uint32_t rx_bytes; 818 uint32_t rx_runts; 819 uint32_t rx_fragments; 820 uint32_t rx_pkts_64; 821 uint32_t rx_pkts_65_127; 822 uint32_t rx_pkts_128_255; 823 uint32_t rx_pkts_256_511; 824 uint32_t rx_pkts_512_1023; 825 uint32_t rx_pkts_1024_1518; 826 uint32_t rx_pkts_1519_max; 827 uint32_t rx_pkts_truncated; 828 uint32_t rx_fifo_oflows; 829 uint32_t rx_rrs_errs; 830 uint32_t rx_alignerrs; 831 uint32_t rx_bcast_bytes; 832 uint32_t rx_mcast_bytes; 833 uint32_t rx_pkts_filtered; 834 /* Tx stats. */ 835 uint32_t tx_frames; 836 uint32_t tx_bcast_frames; 837 uint32_t tx_mcast_frames; 838 uint32_t tx_pause_frames; 839 uint32_t tx_excess_defer; 840 uint32_t tx_control_frames; 841 uint32_t tx_deferred; 842 uint32_t tx_bytes; 843 uint32_t tx_pkts_64; 844 uint32_t tx_pkts_65_127; 845 uint32_t tx_pkts_128_255; 846 uint32_t tx_pkts_256_511; 847 uint32_t tx_pkts_512_1023; 848 uint32_t tx_pkts_1024_1518; 849 uint32_t tx_pkts_1519_max; 850 uint32_t tx_single_colls; 851 uint32_t tx_multi_colls; 852 uint32_t tx_late_colls; 853 uint32_t tx_excess_colls; 854 uint32_t tx_abort; 855 uint32_t tx_underrun; 856 uint32_t tx_desc_underrun; 857 uint32_t tx_lenerrs; 858 uint32_t tx_pkts_truncated; 859 uint32_t tx_bcast_bytes; 860 uint32_t tx_mcast_bytes; 861 uint32_t updated; 862 }; 863 864 /* CMB(Coalesing message block) */ 865 struct cmb { 866 uint32_t cons; 867 }; 868 869 /* Rx free descriptor */ 870 struct rx_desc { 871 uint64_t addr; 872 }; 873 874 /* Rx return descriptor */ 875 struct rx_rdesc { 876 uint32_t rdinfo; 877 #define RRD_CSUM_MASK 0x0000FFFF 878 #define RRD_RD_CNT_MASK 0x000F0000 879 #define RRD_RD_IDX_MASK 0xFFF00000 880 #define RRD_CSUM_SHIFT 0 881 #define RRD_RD_CNT_SHIFT 16 882 #define RRD_RD_IDX_SHIFT 20 883 #define RRD_CSUM(x) \ 884 (((x) & RRD_CSUM_MASK) >> RRD_CSUM_SHIFT) 885 #define RRD_RD_CNT(x) \ 886 (((x) & RRD_RD_CNT_MASK) >> RRD_RD_CNT_SHIFT) 887 #define RRD_RD_IDX(x) \ 888 (((x) & RRD_RD_IDX_MASK) >> RRD_RD_IDX_SHIFT) 889 uint32_t rss; 890 uint32_t vtag; 891 #define RRD_VLAN_MASK 0x0000FFFF 892 #define RRD_HEAD_LEN_MASK 0x00FF0000 893 #define RRD_HDS_MASK 0x03000000 894 #define RRD_HDS_NONE 0x00000000 895 #define RRD_HDS_HEAD 0x01000000 896 #define RRD_HDS_DATA 0x02000000 897 #define RRD_CPU_MASK 0x0C000000 898 #define RRD_HASH_FLAG_MASK 0xF0000000 899 #define RRD_VLAN_SHIFT 0 900 #define RRD_HEAD_LEN_SHIFT 16 901 #define RRD_HDS_SHIFT 24 902 #define RRD_CPU_SHIFT 26 903 #define RRD_HASH_FLAG_SHIFT 28 904 #define RRD_VLAN(x) \ 905 (((x) & RRD_VLAN_MASK) >> RRD_VLAN_SHIFT) 906 #define RRD_HEAD_LEN(x) \ 907 (((x) & RRD_HEAD_LEN_MASK) >> RRD_HEAD_LEN_SHIFT) 908 #define RRD_CPU(x) \ 909 (((x) & RRD_CPU_MASK) >> RRD_CPU_SHIFT) 910 uint32_t status; 911 #define RRD_LEN_MASK 0x00003FFF 912 #define RRD_LEN_SHIFT 0 913 #define RRD_TCP_UDPCSUM_NOK 0x00004000 914 #define RRD_IPCSUM_NOK 0x00008000 915 #define RRD_VLAN_TAG 0x00010000 916 #define RRD_PROTO_MASK 0x000E0000 917 #define RRD_PROTO_IPV4 0x00020000 918 #define RRD_PROTO_IPV6 0x000C0000 919 #define RRD_ERR_SUM 0x00100000 920 #define RRD_ERR_CRC 0x00200000 921 #define RRD_ERR_ALIGN 0x00400000 922 #define RRD_ERR_TRUNC 0x00800000 923 #define RRD_ERR_RUNT 0x01000000 924 #define RRD_ERR_ICMP 0x02000000 925 #define RRD_BCAST 0x04000000 926 #define RRD_MCAST 0x08000000 927 #define RRD_SNAP_LLC 0x10000000 928 #define RRD_ETHER 0x00000000 929 #define RRD_FIFO_FULL 0x20000000 930 #define RRD_ERR_LENGTH 0x40000000 931 #define RRD_VALID 0x80000000 932 #define RRD_BYTES(x) \ 933 (((x) & RRD_LEN_MASK) >> RRD_LEN_SHIFT) 934 #define RRD_IPV4(x) \ 935 (((x) & RRD_PROTO_MASK) == RRD_PROTO_IPV4) 936 }; 937 938 /* Tx descriptor */ 939 struct tx_desc { 940 uint32_t len; 941 #define TD_BUFLEN_MASK 0x00003FFF 942 #define TD_VLAN_MASK 0xFFFF0000 943 #define TD_BUFLEN_SHIFT 0 944 #define TX_BYTES(x) \ 945 (((x) << TD_BUFLEN_SHIFT) & TD_BUFLEN_MASK) 946 #define TD_VLAN_SHIFT 16 947 uint32_t flags; 948 #define TD_L4HDR_OFFSET_MASK 0x000000FF /* byte unit */ 949 #define TD_TCPHDR_OFFSET_MASK 0x000000FF /* byte unit */ 950 #define TD_PLOAD_OFFSET_MASK 0x000000FF /* 2 bytes unit */ 951 #define TD_CUSTOM_CSUM 0x00000100 952 #define TD_IPCSUM 0x00000200 953 #define TD_TCPCSUM 0x00000400 954 #define TD_UDPCSUM 0x00000800 955 #define TD_TSO 0x00001000 956 #define TD_TSO_DESCV1 0x00000000 957 #define TD_TSO_DESCV2 0x00002000 958 #define TD_CON_VLAN_TAG 0x00004000 959 #define TD_INS_VLAN_TAG 0x00008000 960 #define TD_IPV4_DESCV2 0x00010000 961 #define TD_LLC_SNAP 0x00020000 962 #define TD_ETHERNET 0x00000000 963 #define TD_CUSTOM_CSUM_OFFSET_MASK 0x03FC0000 /* 2 bytes unit */ 964 #define TD_CUSTOM_CSUM_EVEN_PAD 0x40000000 965 #define TD_MSS_MASK 0x7FFC0000 966 #define TD_EOP 0x80000000 967 #define TD_L4HDR_OFFSET_SHIFT 0 968 #define TD_TCPHDR_OFFSET_SHIFT 0 969 #define TD_PLOAD_OFFSET_SHIFT 0 970 #define TD_CUSTOM_CSUM_OFFSET_SHIFT 18 971 #define TD_MSS_SHIFT 18 972 uint64_t addr; 973 }; 974 975 #endif /* _IF_ALCREG_H */ 976