1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012, 2013 Bjoern A. Zeeb 5 * Copyright (c) 2014 Robert N. M. Watson 6 * Copyright (c) 2016-2017 Ruslan Bukin <br@bsdpad.com> 7 * All rights reserved. 8 * 9 * This software was developed by SRI International and the University of 10 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-11-C-0249) 11 * ("MRC2"), as part of the DARPA MRC research programme. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 /* 35 * Altera Triple-Speed Ethernet MegaCore, Function User Guide 36 * UG-01008-3.0, Software Version: 12.0, June 2012. 37 * Available at the time of writing at: 38 * http://www.altera.com/literature/ug/ug_ethernet.pdf 39 * 40 * We are using an Marvell E1111 (Alaska) PHY on the DE4. See mii/e1000phy.c. 41 */ 42 /* 43 * XXX-BZ NOTES: 44 * - ifOutBroadcastPkts are only counted if both ether dst and src are all-1s; 45 * seems an IP core bug, they count ether broadcasts as multicast. Is this 46 * still the case? 47 * - figure out why the TX FIFO fill status and intr did not work as expected. 48 * - test 100Mbit/s and 10Mbit/s 49 * - blacklist the one special factory programmed ethernet address (for now 50 * hardcoded, later from loader?) 51 * - resolve all XXX, left as reminders to shake out details later 52 * - Jumbo frame support 53 */ 54 55 #include <sys/cdefs.h> 56 __FBSDID("$FreeBSD$"); 57 58 #include "opt_device_polling.h" 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/kernel.h> 63 #include <sys/bus.h> 64 #include <sys/endian.h> 65 #include <sys/jail.h> 66 #include <sys/lock.h> 67 #include <sys/module.h> 68 #include <sys/mutex.h> 69 #include <sys/proc.h> 70 #include <sys/socket.h> 71 #include <sys/sockio.h> 72 #include <sys/types.h> 73 74 #include <net/ethernet.h> 75 #include <net/if.h> 76 #include <net/if_var.h> 77 #include <net/if_dl.h> 78 #include <net/if_media.h> 79 #include <net/if_types.h> 80 #include <net/if_vlan_var.h> 81 82 #include <net/bpf.h> 83 84 #include <machine/bus.h> 85 #include <machine/resource.h> 86 #include <sys/rman.h> 87 88 #include <dev/mii/mii.h> 89 #include <dev/mii/miivar.h> 90 91 #include <dev/altera/atse/if_atsereg.h> 92 #include <dev/xdma/xdma.h> 93 94 #define RX_QUEUE_SIZE 4096 95 #define TX_QUEUE_SIZE 4096 96 #define NUM_RX_MBUF 512 97 #define BUFRING_SIZE 8192 98 99 #include <machine/cache.h> 100 101 /* XXX once we'd do parallel attach, we need a global lock for this. */ 102 #define ATSE_ETHERNET_OPTION_BITS_UNDEF 0 103 #define ATSE_ETHERNET_OPTION_BITS_READ 1 104 static int atse_ethernet_option_bits_flag = ATSE_ETHERNET_OPTION_BITS_UNDEF; 105 static uint8_t atse_ethernet_option_bits[ALTERA_ETHERNET_OPTION_BITS_LEN]; 106 107 /* 108 * Softc and critical resource locking. 109 */ 110 #define ATSE_LOCK(_sc) mtx_lock(&(_sc)->atse_mtx) 111 #define ATSE_UNLOCK(_sc) mtx_unlock(&(_sc)->atse_mtx) 112 #define ATSE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->atse_mtx, MA_OWNED) 113 114 #define ATSE_DEBUG 115 #undef ATSE_DEBUG 116 117 #ifdef ATSE_DEBUG 118 #define DPRINTF(format, ...) printf(format, __VA_ARGS__) 119 #else 120 #define DPRINTF(format, ...) 121 #endif 122 123 /* 124 * Register space access macros. 125 */ 126 static inline void 127 csr_write_4(struct atse_softc *sc, uint32_t reg, uint32_t val4, 128 const char *f, const int l) 129 { 130 131 val4 = htole32(val4); 132 DPRINTF("[%s:%d] CSR W %s 0x%08x (0x%08x) = 0x%08x\n", f, l, 133 "atse_mem_res", reg, reg * 4, val4); 134 bus_write_4(sc->atse_mem_res, reg * 4, val4); 135 } 136 137 static inline uint32_t 138 csr_read_4(struct atse_softc *sc, uint32_t reg, const char *f, const int l) 139 { 140 uint32_t val4; 141 142 val4 = le32toh(bus_read_4(sc->atse_mem_res, reg * 4)); 143 DPRINTF("[%s:%d] CSR R %s 0x%08x (0x%08x) = 0x%08x\n", f, l, 144 "atse_mem_res", reg, reg * 4, val4); 145 146 return (val4); 147 } 148 149 /* 150 * See page 5-2 that it's all dword offsets and the MS 16 bits need to be zero 151 * on write and ignored on read. 152 */ 153 static inline void 154 pxx_write_2(struct atse_softc *sc, bus_addr_t bmcr, uint32_t reg, uint16_t val, 155 const char *f, const int l, const char *s) 156 { 157 uint32_t val4; 158 159 val4 = htole32(val & 0x0000ffff); 160 DPRINTF("[%s:%d] %s W %s 0x%08x (0x%08jx) = 0x%08x\n", f, l, s, 161 "atse_mem_res", reg, (bmcr + reg) * 4, val4); 162 bus_write_4(sc->atse_mem_res, (bmcr + reg) * 4, val4); 163 } 164 165 static inline uint16_t 166 pxx_read_2(struct atse_softc *sc, bus_addr_t bmcr, uint32_t reg, const char *f, 167 const int l, const char *s) 168 { 169 uint32_t val4; 170 uint16_t val; 171 172 val4 = bus_read_4(sc->atse_mem_res, (bmcr + reg) * 4); 173 val = le32toh(val4) & 0x0000ffff; 174 DPRINTF("[%s:%d] %s R %s 0x%08x (0x%08jx) = 0x%04x\n", f, l, s, 175 "atse_mem_res", reg, (bmcr + reg) * 4, val); 176 177 return (val); 178 } 179 180 #define CSR_WRITE_4(sc, reg, val) \ 181 csr_write_4((sc), (reg), (val), __func__, __LINE__) 182 #define CSR_READ_4(sc, reg) \ 183 csr_read_4((sc), (reg), __func__, __LINE__) 184 #define PCS_WRITE_2(sc, reg, val) \ 185 pxx_write_2((sc), sc->atse_bmcr0, (reg), (val), __func__, __LINE__, \ 186 "PCS") 187 #define PCS_READ_2(sc, reg) \ 188 pxx_read_2((sc), sc->atse_bmcr0, (reg), __func__, __LINE__, "PCS") 189 #define PHY_WRITE_2(sc, reg, val) \ 190 pxx_write_2((sc), sc->atse_bmcr1, (reg), (val), __func__, __LINE__, \ 191 "PHY") 192 #define PHY_READ_2(sc, reg) \ 193 pxx_read_2((sc), sc->atse_bmcr1, (reg), __func__, __LINE__, "PHY") 194 195 static void atse_tick(void *); 196 static int atse_detach(device_t); 197 198 devclass_t atse_devclass; 199 200 static int 201 atse_rx_enqueue(struct atse_softc *sc, uint32_t n) 202 { 203 struct mbuf *m; 204 int i; 205 206 for (i = 0; i < n; i++) { 207 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 208 if (m == NULL) { 209 device_printf(sc->dev, 210 "%s: Can't alloc rx mbuf\n", __func__); 211 return (-1); 212 } 213 214 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 215 xdma_enqueue_mbuf(sc->xchan_rx, &m, 0, 4, 4, XDMA_DEV_TO_MEM); 216 } 217 218 return (0); 219 } 220 221 static int 222 atse_xdma_tx_intr(void *arg, xdma_transfer_status_t *status) 223 { 224 xdma_transfer_status_t st; 225 struct atse_softc *sc; 226 struct ifnet *ifp; 227 struct mbuf *m; 228 int err; 229 230 sc = arg; 231 232 ATSE_LOCK(sc); 233 234 ifp = sc->atse_ifp; 235 236 for (;;) { 237 err = xdma_dequeue_mbuf(sc->xchan_tx, &m, &st); 238 if (err != 0) { 239 break; 240 } 241 242 if (st.error != 0) { 243 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 244 } 245 246 m_freem(m); 247 sc->txcount--; 248 } 249 250 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 251 252 ATSE_UNLOCK(sc); 253 254 return (0); 255 } 256 257 static int 258 atse_xdma_rx_intr(void *arg, xdma_transfer_status_t *status) 259 { 260 xdma_transfer_status_t st; 261 struct atse_softc *sc; 262 struct ifnet *ifp; 263 struct mbuf *m; 264 int err; 265 uint32_t cnt_processed; 266 267 sc = arg; 268 269 ATSE_LOCK(sc); 270 271 ifp = sc->atse_ifp; 272 273 cnt_processed = 0; 274 for (;;) { 275 err = xdma_dequeue_mbuf(sc->xchan_rx, &m, &st); 276 if (err != 0) { 277 break; 278 } 279 cnt_processed++; 280 281 if (st.error != 0) { 282 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 283 m_freem(m); 284 continue; 285 } 286 287 m->m_pkthdr.len = m->m_len = st.transferred; 288 m->m_pkthdr.rcvif = ifp; 289 m_adj(m, ETHER_ALIGN); 290 ATSE_UNLOCK(sc); 291 (*ifp->if_input)(ifp, m); 292 ATSE_LOCK(sc); 293 } 294 295 atse_rx_enqueue(sc, cnt_processed); 296 297 ATSE_UNLOCK(sc); 298 299 return (0); 300 } 301 302 static int 303 atse_transmit_locked(struct ifnet *ifp) 304 { 305 struct atse_softc *sc; 306 struct mbuf *m; 307 struct buf_ring *br; 308 int error; 309 int enq; 310 311 sc = ifp->if_softc; 312 br = sc->br; 313 314 enq = 0; 315 316 while ((m = drbr_peek(ifp, br)) != NULL) { 317 error = xdma_enqueue_mbuf(sc->xchan_tx, &m, 0, 4, 4, XDMA_MEM_TO_DEV); 318 if (error != 0) { 319 /* No space in request queue available yet. */ 320 drbr_putback(ifp, br, m); 321 break; 322 } 323 324 drbr_advance(ifp, br); 325 326 sc->txcount++; 327 enq++; 328 329 /* If anyone is interested give them a copy. */ 330 ETHER_BPF_MTAP(ifp, m); 331 } 332 333 if (enq > 0) 334 xdma_queue_submit(sc->xchan_tx); 335 336 return (0); 337 } 338 339 static int 340 atse_transmit(struct ifnet *ifp, struct mbuf *m) 341 { 342 struct atse_softc *sc; 343 struct buf_ring *br; 344 int error; 345 346 sc = ifp->if_softc; 347 br = sc->br; 348 349 ATSE_LOCK(sc); 350 351 mtx_lock(&sc->br_mtx); 352 353 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != IFF_DRV_RUNNING) { 354 error = drbr_enqueue(ifp, sc->br, m); 355 mtx_unlock(&sc->br_mtx); 356 ATSE_UNLOCK(sc); 357 return (error); 358 } 359 360 if ((sc->atse_flags & ATSE_FLAGS_LINK) == 0) { 361 error = drbr_enqueue(ifp, sc->br, m); 362 mtx_unlock(&sc->br_mtx); 363 ATSE_UNLOCK(sc); 364 return (error); 365 } 366 367 error = drbr_enqueue(ifp, br, m); 368 if (error) { 369 mtx_unlock(&sc->br_mtx); 370 ATSE_UNLOCK(sc); 371 return (error); 372 } 373 error = atse_transmit_locked(ifp); 374 375 mtx_unlock(&sc->br_mtx); 376 ATSE_UNLOCK(sc); 377 378 return (error); 379 } 380 381 static void 382 atse_qflush(struct ifnet *ifp) 383 { 384 struct atse_softc *sc; 385 386 sc = ifp->if_softc; 387 388 printf("%s\n", __func__); 389 } 390 391 static int 392 atse_stop_locked(struct atse_softc *sc) 393 { 394 uint32_t mask, val4; 395 struct ifnet *ifp; 396 int i; 397 398 ATSE_LOCK_ASSERT(sc); 399 400 callout_stop(&sc->atse_tick); 401 402 ifp = sc->atse_ifp; 403 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 404 405 /* Disable MAC transmit and receive datapath. */ 406 mask = BASE_CFG_COMMAND_CONFIG_TX_ENA|BASE_CFG_COMMAND_CONFIG_RX_ENA; 407 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); 408 val4 &= ~mask; 409 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4); 410 411 /* Wait for bits to be cleared; i=100 is excessive. */ 412 for (i = 0; i < 100; i++) { 413 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); 414 if ((val4 & mask) == 0) { 415 break; 416 } 417 DELAY(10); 418 } 419 420 if ((val4 & mask) != 0) { 421 device_printf(sc->atse_dev, "Disabling MAC TX/RX timed out.\n"); 422 /* Punt. */ 423 } 424 425 sc->atse_flags &= ~ATSE_FLAGS_LINK; 426 427 return (0); 428 } 429 430 static u_int 431 atse_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 432 { 433 uint64_t *h = arg; 434 uint8_t *addr, x, y; 435 int i, j; 436 437 addr = LLADDR(sdl); 438 x = 0; 439 for (i = 0; i < ETHER_ADDR_LEN; i++) { 440 y = addr[i] & 0x01; 441 for (j = 1; j < 8; j++) 442 y ^= (addr[i] >> j) & 0x01; 443 x |= (y << i); 444 } 445 *h |= (1 << x); 446 447 return (1); 448 } 449 450 static int 451 atse_rxfilter_locked(struct atse_softc *sc) 452 { 453 struct ifnet *ifp; 454 uint32_t val4; 455 int i; 456 457 /* XXX-BZ can we find out if we have the MHASH synthesized? */ 458 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); 459 /* For simplicity always hash full 48 bits of addresses. */ 460 if ((val4 & BASE_CFG_COMMAND_CONFIG_MHASH_SEL) != 0) 461 val4 &= ~BASE_CFG_COMMAND_CONFIG_MHASH_SEL; 462 463 ifp = sc->atse_ifp; 464 if (ifp->if_flags & IFF_PROMISC) { 465 val4 |= BASE_CFG_COMMAND_CONFIG_PROMIS_EN; 466 } else { 467 val4 &= ~BASE_CFG_COMMAND_CONFIG_PROMIS_EN; 468 } 469 470 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4); 471 472 if (ifp->if_flags & IFF_ALLMULTI) { 473 /* Accept all multicast addresses. */ 474 for (i = 0; i <= MHASH_LEN; i++) 475 CSR_WRITE_4(sc, MHASH_START + i, 0x1); 476 } else { 477 /* 478 * Can hold MHASH_LEN entries. 479 * XXX-BZ bitstring.h would be more general. 480 */ 481 uint64_t h; 482 483 /* 484 * Re-build and re-program hash table. First build the 485 * bit-field "yes" or "no" for each slot per address, then 486 * do all the programming afterwards. 487 */ 488 h = 0; 489 (void)if_foreach_llmaddr(ifp, atse_hash_maddr, &h); 490 for (i = 0; i <= MHASH_LEN; i++) { 491 CSR_WRITE_4(sc, MHASH_START + i, 492 (h & (1 << i)) ? 0x01 : 0x00); 493 } 494 } 495 496 return (0); 497 } 498 499 static int 500 atse_ethernet_option_bits_read_fdt(device_t dev) 501 { 502 struct resource *res; 503 device_t fdev; 504 int i, rid; 505 506 if (atse_ethernet_option_bits_flag & ATSE_ETHERNET_OPTION_BITS_READ) { 507 return (0); 508 } 509 510 fdev = device_find_child(device_get_parent(dev), "cfi", 0); 511 if (fdev == NULL) { 512 return (ENOENT); 513 } 514 515 rid = 0; 516 res = bus_alloc_resource_any(fdev, SYS_RES_MEMORY, &rid, 517 RF_ACTIVE | RF_SHAREABLE); 518 if (res == NULL) { 519 return (ENXIO); 520 } 521 522 for (i = 0; i < ALTERA_ETHERNET_OPTION_BITS_LEN; i++) { 523 atse_ethernet_option_bits[i] = bus_read_1(res, 524 ALTERA_ETHERNET_OPTION_BITS_OFF + i); 525 } 526 527 bus_release_resource(fdev, SYS_RES_MEMORY, rid, res); 528 atse_ethernet_option_bits_flag |= ATSE_ETHERNET_OPTION_BITS_READ; 529 530 return (0); 531 } 532 533 static int 534 atse_ethernet_option_bits_read(device_t dev) 535 { 536 int error; 537 538 error = atse_ethernet_option_bits_read_fdt(dev); 539 if (error == 0) 540 return (0); 541 542 device_printf(dev, "Cannot read Ethernet addresses from flash.\n"); 543 544 return (error); 545 } 546 547 static int 548 atse_get_eth_address(struct atse_softc *sc) 549 { 550 unsigned long hostid; 551 uint32_t val4; 552 int unit; 553 554 /* 555 * Make sure to only ever do this once. Otherwise a reset would 556 * possibly change our ethernet address, which is not good at all. 557 */ 558 if (sc->atse_eth_addr[0] != 0x00 || sc->atse_eth_addr[1] != 0x00 || 559 sc->atse_eth_addr[2] != 0x00) { 560 return (0); 561 } 562 563 if ((atse_ethernet_option_bits_flag & 564 ATSE_ETHERNET_OPTION_BITS_READ) == 0) { 565 goto get_random; 566 } 567 568 val4 = atse_ethernet_option_bits[0] << 24; 569 val4 |= atse_ethernet_option_bits[1] << 16; 570 val4 |= atse_ethernet_option_bits[2] << 8; 571 val4 |= atse_ethernet_option_bits[3]; 572 /* They chose "safe". */ 573 if (val4 != le32toh(0x00005afe)) { 574 device_printf(sc->atse_dev, "Magic '5afe' is not safe: 0x%08x. " 575 "Falling back to random numbers for hardware address.\n", 576 val4); 577 goto get_random; 578 } 579 580 sc->atse_eth_addr[0] = atse_ethernet_option_bits[4]; 581 sc->atse_eth_addr[1] = atse_ethernet_option_bits[5]; 582 sc->atse_eth_addr[2] = atse_ethernet_option_bits[6]; 583 sc->atse_eth_addr[3] = atse_ethernet_option_bits[7]; 584 sc->atse_eth_addr[4] = atse_ethernet_option_bits[8]; 585 sc->atse_eth_addr[5] = atse_ethernet_option_bits[9]; 586 587 /* Handle factory default ethernet addresss: 00:07:ed:ff:ed:15 */ 588 if (sc->atse_eth_addr[0] == 0x00 && sc->atse_eth_addr[1] == 0x07 && 589 sc->atse_eth_addr[2] == 0xed && sc->atse_eth_addr[3] == 0xff && 590 sc->atse_eth_addr[4] == 0xed && sc->atse_eth_addr[5] == 0x15) { 591 592 device_printf(sc->atse_dev, "Factory programmed Ethernet " 593 "hardware address blacklisted. Falling back to random " 594 "address to avoid collisions.\n"); 595 device_printf(sc->atse_dev, "Please re-program your flash.\n"); 596 goto get_random; 597 } 598 599 if (sc->atse_eth_addr[0] == 0x00 && sc->atse_eth_addr[1] == 0x00 && 600 sc->atse_eth_addr[2] == 0x00 && sc->atse_eth_addr[3] == 0x00 && 601 sc->atse_eth_addr[4] == 0x00 && sc->atse_eth_addr[5] == 0x00) { 602 device_printf(sc->atse_dev, "All zero's Ethernet hardware " 603 "address blacklisted. Falling back to random address.\n"); 604 device_printf(sc->atse_dev, "Please re-program your flash.\n"); 605 goto get_random; 606 } 607 608 if (ETHER_IS_MULTICAST(sc->atse_eth_addr)) { 609 device_printf(sc->atse_dev, "Multicast Ethernet hardware " 610 "address blacklisted. Falling back to random address.\n"); 611 device_printf(sc->atse_dev, "Please re-program your flash.\n"); 612 goto get_random; 613 } 614 615 /* 616 * If we find an Altera prefixed address with a 0x0 ending 617 * adjust by device unit. If not and this is not the first 618 * Ethernet, go to random. 619 */ 620 unit = device_get_unit(sc->atse_dev); 621 if (unit == 0x00) { 622 return (0); 623 } 624 625 if (unit > 0x0f) { 626 device_printf(sc->atse_dev, "We do not support Ethernet " 627 "addresses for more than 16 MACs. Falling back to " 628 "random hadware address.\n"); 629 goto get_random; 630 } 631 if ((sc->atse_eth_addr[0] & ~0x2) != 0 || 632 sc->atse_eth_addr[1] != 0x07 || sc->atse_eth_addr[2] != 0xed || 633 (sc->atse_eth_addr[5] & 0x0f) != 0x0) { 634 device_printf(sc->atse_dev, "Ethernet address not meeting our " 635 "multi-MAC standards. Falling back to random hadware " 636 "address.\n"); 637 goto get_random; 638 } 639 sc->atse_eth_addr[5] |= (unit & 0x0f); 640 641 return (0); 642 643 get_random: 644 /* 645 * Fall back to random code we also use on bridge(4). 646 */ 647 getcredhostid(curthread->td_ucred, &hostid); 648 if (hostid == 0) { 649 arc4rand(sc->atse_eth_addr, ETHER_ADDR_LEN, 1); 650 sc->atse_eth_addr[0] &= ~1;/* clear multicast bit */ 651 sc->atse_eth_addr[0] |= 2; /* set the LAA bit */ 652 } else { 653 sc->atse_eth_addr[0] = 0x2; 654 sc->atse_eth_addr[1] = (hostid >> 24) & 0xff; 655 sc->atse_eth_addr[2] = (hostid >> 16) & 0xff; 656 sc->atse_eth_addr[3] = (hostid >> 8 ) & 0xff; 657 sc->atse_eth_addr[4] = hostid & 0xff; 658 sc->atse_eth_addr[5] = sc->atse_unit & 0xff; 659 } 660 661 return (0); 662 } 663 664 static int 665 atse_set_eth_address(struct atse_softc *sc, int n) 666 { 667 uint32_t v0, v1; 668 669 v0 = (sc->atse_eth_addr[3] << 24) | (sc->atse_eth_addr[2] << 16) | 670 (sc->atse_eth_addr[1] << 8) | sc->atse_eth_addr[0]; 671 v1 = (sc->atse_eth_addr[5] << 8) | sc->atse_eth_addr[4]; 672 673 if (n & ATSE_ETH_ADDR_DEF) { 674 CSR_WRITE_4(sc, BASE_CFG_MAC_0, v0); 675 CSR_WRITE_4(sc, BASE_CFG_MAC_1, v1); 676 } 677 if (n & ATSE_ETH_ADDR_SUPP1) { 678 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_0_0, v0); 679 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_0_1, v1); 680 } 681 if (n & ATSE_ETH_ADDR_SUPP2) { 682 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_1_0, v0); 683 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_1_1, v1); 684 } 685 if (n & ATSE_ETH_ADDR_SUPP3) { 686 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_2_0, v0); 687 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_2_1, v1); 688 } 689 if (n & ATSE_ETH_ADDR_SUPP4) { 690 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_3_0, v0); 691 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_3_1, v1); 692 } 693 694 return (0); 695 } 696 697 static int 698 atse_reset(struct atse_softc *sc) 699 { 700 uint32_t val4, mask; 701 uint16_t val; 702 int i; 703 704 /* 1. External PHY Initialization using MDIO. */ 705 /* 706 * We select the right MDIO space in atse_attach() and let MII do 707 * anything else. 708 */ 709 710 /* 2. PCS Configuration Register Initialization. */ 711 /* a. Set auto negotiation link timer to 1.6ms for SGMII. */ 712 PCS_WRITE_2(sc, PCS_EXT_LINK_TIMER_0, 0x0D40); 713 PCS_WRITE_2(sc, PCS_EXT_LINK_TIMER_1, 0x0003); 714 715 /* b. Configure SGMII. */ 716 val = PCS_EXT_IF_MODE_SGMII_ENA|PCS_EXT_IF_MODE_USE_SGMII_AN; 717 PCS_WRITE_2(sc, PCS_EXT_IF_MODE, val); 718 719 /* c. Enable auto negotiation. */ 720 /* Ignore Bits 6,8,13; should be set,set,unset. */ 721 val = PCS_READ_2(sc, PCS_CONTROL); 722 val &= ~(PCS_CONTROL_ISOLATE|PCS_CONTROL_POWERDOWN); 723 val &= ~PCS_CONTROL_LOOPBACK; /* Make this a -link1 option? */ 724 val |= PCS_CONTROL_AUTO_NEGOTIATION_ENABLE; 725 PCS_WRITE_2(sc, PCS_CONTROL, val); 726 727 /* d. PCS reset. */ 728 val = PCS_READ_2(sc, PCS_CONTROL); 729 val |= PCS_CONTROL_RESET; 730 PCS_WRITE_2(sc, PCS_CONTROL, val); 731 732 /* Wait for reset bit to clear; i=100 is excessive. */ 733 for (i = 0; i < 100; i++) { 734 val = PCS_READ_2(sc, PCS_CONTROL); 735 if ((val & PCS_CONTROL_RESET) == 0) { 736 break; 737 } 738 DELAY(10); 739 } 740 741 if ((val & PCS_CONTROL_RESET) != 0) { 742 device_printf(sc->atse_dev, "PCS reset timed out.\n"); 743 return (ENXIO); 744 } 745 746 /* 3. MAC Configuration Register Initialization. */ 747 /* a. Disable MAC transmit and receive datapath. */ 748 mask = BASE_CFG_COMMAND_CONFIG_TX_ENA|BASE_CFG_COMMAND_CONFIG_RX_ENA; 749 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); 750 val4 &= ~mask; 751 /* Samples in the manual do have the SW_RESET bit set here, why? */ 752 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4); 753 /* Wait for bits to be cleared; i=100 is excessive. */ 754 for (i = 0; i < 100; i++) { 755 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); 756 if ((val4 & mask) == 0) { 757 break; 758 } 759 DELAY(10); 760 } 761 if ((val4 & mask) != 0) { 762 device_printf(sc->atse_dev, "Disabling MAC TX/RX timed out.\n"); 763 return (ENXIO); 764 } 765 /* b. MAC FIFO configuration. */ 766 CSR_WRITE_4(sc, BASE_CFG_TX_SECTION_EMPTY, FIFO_DEPTH_TX - 16); 767 CSR_WRITE_4(sc, BASE_CFG_TX_ALMOST_FULL, 3); 768 CSR_WRITE_4(sc, BASE_CFG_TX_ALMOST_EMPTY, 8); 769 CSR_WRITE_4(sc, BASE_CFG_RX_SECTION_EMPTY, FIFO_DEPTH_RX - 16); 770 CSR_WRITE_4(sc, BASE_CFG_RX_ALMOST_FULL, 8); 771 CSR_WRITE_4(sc, BASE_CFG_RX_ALMOST_EMPTY, 8); 772 #if 0 773 CSR_WRITE_4(sc, BASE_CFG_TX_SECTION_FULL, 16); 774 CSR_WRITE_4(sc, BASE_CFG_RX_SECTION_FULL, 16); 775 #else 776 /* For store-and-forward mode, set this threshold to 0. */ 777 CSR_WRITE_4(sc, BASE_CFG_TX_SECTION_FULL, 0); 778 CSR_WRITE_4(sc, BASE_CFG_RX_SECTION_FULL, 0); 779 #endif 780 /* c. MAC address configuration. */ 781 /* Also intialize supplementary addresses to our primary one. */ 782 /* XXX-BZ FreeBSD really needs to grow and API for using these. */ 783 atse_get_eth_address(sc); 784 atse_set_eth_address(sc, ATSE_ETH_ADDR_ALL); 785 786 /* d. MAC function configuration. */ 787 CSR_WRITE_4(sc, BASE_CFG_FRM_LENGTH, 1518); /* Default. */ 788 CSR_WRITE_4(sc, BASE_CFG_TX_IPG_LENGTH, 12); 789 CSR_WRITE_4(sc, BASE_CFG_PAUSE_QUANT, 0xFFFF); 790 791 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); 792 /* 793 * If 1000BASE-X/SGMII PCS is initialized, set the ETH_SPEED (bit 3) 794 * and ENA_10 (bit 25) in command_config register to 0. If half duplex 795 * is reported in the PHY/PCS status register, set the HD_ENA (bit 10) 796 * to 1 in command_config register. 797 * BZ: We shoot for 1000 instead. 798 */ 799 #if 0 800 val4 |= BASE_CFG_COMMAND_CONFIG_ETH_SPEED; 801 #else 802 val4 &= ~BASE_CFG_COMMAND_CONFIG_ETH_SPEED; 803 #endif 804 val4 &= ~BASE_CFG_COMMAND_CONFIG_ENA_10; 805 #if 0 806 /* 807 * We do not want to set this, otherwise, we could not even send 808 * random raw ethernet frames for various other research. By default 809 * FreeBSD will use the right ether source address. 810 */ 811 val4 |= BASE_CFG_COMMAND_CONFIG_TX_ADDR_INS; 812 #endif 813 val4 |= BASE_CFG_COMMAND_CONFIG_PAD_EN; 814 val4 &= ~BASE_CFG_COMMAND_CONFIG_CRC_FWD; 815 #if 0 816 val4 |= BASE_CFG_COMMAND_CONFIG_CNTL_FRM_ENA; 817 #endif 818 #if 1 819 val4 |= BASE_CFG_COMMAND_CONFIG_RX_ERR_DISC; 820 #endif 821 val &= ~BASE_CFG_COMMAND_CONFIG_LOOP_ENA; /* link0? */ 822 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4); 823 824 /* 825 * Make sure we do not enable 32bit alignment; FreeBSD cannot 826 * cope with the additional padding (though we should!?). 827 * Also make sure we get the CRC appended. 828 */ 829 val4 = CSR_READ_4(sc, TX_CMD_STAT); 830 val4 &= ~(TX_CMD_STAT_OMIT_CRC|TX_CMD_STAT_TX_SHIFT16); 831 CSR_WRITE_4(sc, TX_CMD_STAT, val4); 832 833 val4 = CSR_READ_4(sc, RX_CMD_STAT); 834 val4 &= ~RX_CMD_STAT_RX_SHIFT16; 835 val4 |= RX_CMD_STAT_RX_SHIFT16; 836 CSR_WRITE_4(sc, RX_CMD_STAT, val4); 837 838 /* e. Reset MAC. */ 839 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); 840 val4 |= BASE_CFG_COMMAND_CONFIG_SW_RESET; 841 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4); 842 /* Wait for bits to be cleared; i=100 is excessive. */ 843 for (i = 0; i < 100; i++) { 844 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); 845 if ((val4 & BASE_CFG_COMMAND_CONFIG_SW_RESET) == 0) { 846 break; 847 } 848 DELAY(10); 849 } 850 if ((val4 & BASE_CFG_COMMAND_CONFIG_SW_RESET) != 0) { 851 device_printf(sc->atse_dev, "MAC reset timed out.\n"); 852 return (ENXIO); 853 } 854 855 /* f. Enable MAC transmit and receive datapath. */ 856 mask = BASE_CFG_COMMAND_CONFIG_TX_ENA|BASE_CFG_COMMAND_CONFIG_RX_ENA; 857 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); 858 val4 |= mask; 859 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4); 860 /* Wait for bits to be cleared; i=100 is excessive. */ 861 for (i = 0; i < 100; i++) { 862 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); 863 if ((val4 & mask) == mask) { 864 break; 865 } 866 DELAY(10); 867 } 868 if ((val4 & mask) != mask) { 869 device_printf(sc->atse_dev, "Enabling MAC TX/RX timed out.\n"); 870 return (ENXIO); 871 } 872 873 return (0); 874 } 875 876 static void 877 atse_init_locked(struct atse_softc *sc) 878 { 879 struct ifnet *ifp; 880 struct mii_data *mii; 881 uint8_t *eaddr; 882 883 ATSE_LOCK_ASSERT(sc); 884 ifp = sc->atse_ifp; 885 886 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 887 return; 888 } 889 890 /* 891 * Must update the ether address if changed. Given we do not handle 892 * in atse_ioctl() but it's in the general framework, just always 893 * do it here before atse_reset(). 894 */ 895 eaddr = IF_LLADDR(sc->atse_ifp); 896 bcopy(eaddr, &sc->atse_eth_addr, ETHER_ADDR_LEN); 897 898 /* Make things frind to halt, cleanup, ... */ 899 atse_stop_locked(sc); 900 901 atse_reset(sc); 902 903 /* ... and fire up the engine again. */ 904 atse_rxfilter_locked(sc); 905 906 sc->atse_flags &= ATSE_FLAGS_LINK; /* Preserve. */ 907 908 mii = device_get_softc(sc->atse_miibus); 909 910 sc->atse_flags &= ~ATSE_FLAGS_LINK; 911 mii_mediachg(mii); 912 913 ifp->if_drv_flags |= IFF_DRV_RUNNING; 914 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 915 916 callout_reset(&sc->atse_tick, hz, atse_tick, sc); 917 } 918 919 static void 920 atse_init(void *xsc) 921 { 922 struct atse_softc *sc; 923 924 /* 925 * XXXRW: There is some argument that we should immediately do RX 926 * processing after enabling interrupts, or one may not fire if there 927 * are buffered packets. 928 */ 929 sc = (struct atse_softc *)xsc; 930 ATSE_LOCK(sc); 931 atse_init_locked(sc); 932 ATSE_UNLOCK(sc); 933 } 934 935 static int 936 atse_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 937 { 938 struct atse_softc *sc; 939 struct ifreq *ifr; 940 int error, mask; 941 942 error = 0; 943 sc = ifp->if_softc; 944 ifr = (struct ifreq *)data; 945 946 switch (command) { 947 case SIOCSIFFLAGS: 948 ATSE_LOCK(sc); 949 if (ifp->if_flags & IFF_UP) { 950 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 951 ((ifp->if_flags ^ sc->atse_if_flags) & 952 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 953 atse_rxfilter_locked(sc); 954 else 955 atse_init_locked(sc); 956 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 957 atse_stop_locked(sc); 958 sc->atse_if_flags = ifp->if_flags; 959 ATSE_UNLOCK(sc); 960 break; 961 case SIOCSIFCAP: 962 ATSE_LOCK(sc); 963 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 964 ATSE_UNLOCK(sc); 965 break; 966 case SIOCADDMULTI: 967 case SIOCDELMULTI: 968 ATSE_LOCK(sc); 969 atse_rxfilter_locked(sc); 970 ATSE_UNLOCK(sc); 971 break; 972 case SIOCGIFMEDIA: 973 case SIOCSIFMEDIA: 974 { 975 struct mii_data *mii; 976 struct ifreq *ifr; 977 978 mii = device_get_softc(sc->atse_miibus); 979 ifr = (struct ifreq *)data; 980 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 981 break; 982 } 983 default: 984 error = ether_ioctl(ifp, command, data); 985 break; 986 } 987 988 return (error); 989 } 990 991 static void 992 atse_tick(void *xsc) 993 { 994 struct atse_softc *sc; 995 struct mii_data *mii; 996 struct ifnet *ifp; 997 998 sc = (struct atse_softc *)xsc; 999 ATSE_LOCK_ASSERT(sc); 1000 ifp = sc->atse_ifp; 1001 1002 mii = device_get_softc(sc->atse_miibus); 1003 mii_tick(mii); 1004 if ((sc->atse_flags & ATSE_FLAGS_LINK) == 0) { 1005 atse_miibus_statchg(sc->atse_dev); 1006 } 1007 1008 callout_reset(&sc->atse_tick, hz, atse_tick, sc); 1009 } 1010 1011 /* 1012 * Set media options. 1013 */ 1014 static int 1015 atse_ifmedia_upd(struct ifnet *ifp) 1016 { 1017 struct atse_softc *sc; 1018 struct mii_data *mii; 1019 struct mii_softc *miisc; 1020 int error; 1021 1022 sc = ifp->if_softc; 1023 1024 ATSE_LOCK(sc); 1025 mii = device_get_softc(sc->atse_miibus); 1026 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 1027 PHY_RESET(miisc); 1028 } 1029 error = mii_mediachg(mii); 1030 ATSE_UNLOCK(sc); 1031 1032 return (error); 1033 } 1034 1035 /* 1036 * Report current media status. 1037 */ 1038 static void 1039 atse_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1040 { 1041 struct atse_softc *sc; 1042 struct mii_data *mii; 1043 1044 sc = ifp->if_softc; 1045 1046 ATSE_LOCK(sc); 1047 mii = device_get_softc(sc->atse_miibus); 1048 mii_pollstat(mii); 1049 ifmr->ifm_active = mii->mii_media_active; 1050 ifmr->ifm_status = mii->mii_media_status; 1051 ATSE_UNLOCK(sc); 1052 } 1053 1054 static struct atse_mac_stats_regs { 1055 const char *name; 1056 const char *descr; /* Mostly copied from Altera datasheet. */ 1057 } atse_mac_stats_regs[] = { 1058 [0x1a] = 1059 { "aFramesTransmittedOK", 1060 "The number of frames that are successfully transmitted including " 1061 "the pause frames." }, 1062 { "aFramesReceivedOK", 1063 "The number of frames that are successfully received including the " 1064 "pause frames." }, 1065 { "aFrameCheckSequenceErrors", 1066 "The number of receive frames with CRC error." }, 1067 { "aAlignmentErrors", 1068 "The number of receive frames with alignment error." }, 1069 { "aOctetsTransmittedOK", 1070 "The lower 32 bits of the number of data and padding octets that " 1071 "are successfully transmitted." }, 1072 { "aOctetsReceivedOK", 1073 "The lower 32 bits of the number of data and padding octets that " 1074 " are successfully received." }, 1075 { "aTxPAUSEMACCtrlFrames", 1076 "The number of pause frames transmitted." }, 1077 { "aRxPAUSEMACCtrlFrames", 1078 "The number received pause frames received." }, 1079 { "ifInErrors", 1080 "The number of errored frames received." }, 1081 { "ifOutErrors", 1082 "The number of transmit frames with either a FIFO overflow error, " 1083 "a FIFO underflow error, or a error defined by the user " 1084 "application." }, 1085 { "ifInUcastPkts", 1086 "The number of valid unicast frames received." }, 1087 { "ifInMulticastPkts", 1088 "The number of valid multicast frames received. The count does " 1089 "not include pause frames." }, 1090 { "ifInBroadcastPkts", 1091 "The number of valid broadcast frames received." }, 1092 { "ifOutDiscards", 1093 "This statistics counter is not in use. The MAC function does not " 1094 "discard frames that are written to the FIFO buffer by the user " 1095 "application." }, 1096 { "ifOutUcastPkts", 1097 "The number of valid unicast frames transmitted." }, 1098 { "ifOutMulticastPkts", 1099 "The number of valid multicast frames transmitted, excluding pause " 1100 "frames." }, 1101 { "ifOutBroadcastPkts", 1102 "The number of valid broadcast frames transmitted." }, 1103 { "etherStatsDropEvents", 1104 "The number of frames that are dropped due to MAC internal errors " 1105 "when FIFO buffer overflow persists." }, 1106 { "etherStatsOctets", 1107 "The lower 32 bits of the total number of octets received. This " 1108 "count includes both good and errored frames." }, 1109 { "etherStatsPkts", 1110 "The total number of good and errored frames received." }, 1111 { "etherStatsUndersizePkts", 1112 "The number of frames received with length less than 64 bytes. " 1113 "This count does not include errored frames." }, 1114 { "etherStatsOversizePkts", 1115 "The number of frames received that are longer than the value " 1116 "configured in the frm_length register. This count does not " 1117 "include errored frames." }, 1118 { "etherStatsPkts64Octets", 1119 "The number of 64-byte frames received. This count includes good " 1120 "and errored frames." }, 1121 { "etherStatsPkts65to127Octets", 1122 "The number of received good and errored frames between the length " 1123 "of 65 and 127 bytes." }, 1124 { "etherStatsPkts128to255Octets", 1125 "The number of received good and errored frames between the length " 1126 "of 128 and 255 bytes." }, 1127 { "etherStatsPkts256to511Octets", 1128 "The number of received good and errored frames between the length " 1129 "of 256 and 511 bytes." }, 1130 { "etherStatsPkts512to1023Octets", 1131 "The number of received good and errored frames between the length " 1132 "of 512 and 1023 bytes." }, 1133 { "etherStatsPkts1024to1518Octets", 1134 "The number of received good and errored frames between the length " 1135 "of 1024 and 1518 bytes." }, 1136 { "etherStatsPkts1519toXOctets", 1137 "The number of received good and errored frames between the length " 1138 "of 1519 and the maximum frame length configured in the frm_length " 1139 "register." }, 1140 { "etherStatsJabbers", 1141 "Too long frames with CRC error." }, 1142 { "etherStatsFragments", 1143 "Too short frames with CRC error." }, 1144 /* 0x39 unused, 0x3a/b non-stats. */ 1145 [0x3c] = 1146 /* Extended Statistics Counters */ 1147 { "msb_aOctetsTransmittedOK", 1148 "Upper 32 bits of the number of data and padding octets that are " 1149 "successfully transmitted." }, 1150 { "msb_aOctetsReceivedOK", 1151 "Upper 32 bits of the number of data and padding octets that are " 1152 "successfully received." }, 1153 { "msb_etherStatsOctets", 1154 "Upper 32 bits of the total number of octets received. This count " 1155 "includes both good and errored frames." } 1156 }; 1157 1158 static int 1159 sysctl_atse_mac_stats_proc(SYSCTL_HANDLER_ARGS) 1160 { 1161 struct atse_softc *sc; 1162 int error, offset, s; 1163 1164 sc = arg1; 1165 offset = arg2; 1166 1167 s = CSR_READ_4(sc, offset); 1168 error = sysctl_handle_int(oidp, &s, 0, req); 1169 if (error || !req->newptr) { 1170 return (error); 1171 } 1172 1173 return (0); 1174 } 1175 1176 static struct atse_rx_err_stats_regs { 1177 const char *name; 1178 const char *descr; 1179 } atse_rx_err_stats_regs[] = { 1180 1181 #define ATSE_RX_ERR_FIFO_THRES_EOP 0 /* FIFO threshold reached, on EOP. */ 1182 #define ATSE_RX_ERR_ELEN 1 /* Frame/payload length not valid. */ 1183 #define ATSE_RX_ERR_CRC32 2 /* CRC-32 error. */ 1184 #define ATSE_RX_ERR_FIFO_THRES_TRUNC 3 /* FIFO thresh., truncated frame. */ 1185 #define ATSE_RX_ERR_4 4 /* ? */ 1186 #define ATSE_RX_ERR_5 5 /* / */ 1187 1188 { "rx_err_fifo_thres_eop", 1189 "FIFO threshold reached, reported on EOP." }, 1190 { "rx_err_fifo_elen", 1191 "Frame or payload length not valid." }, 1192 { "rx_err_fifo_crc32", 1193 "CRC-32 error." }, 1194 { "rx_err_fifo_thres_trunc", 1195 "FIFO threshold reached, truncated frame" }, 1196 { "rx_err_4", 1197 "?" }, 1198 { "rx_err_5", 1199 "?" }, 1200 }; 1201 1202 static int 1203 sysctl_atse_rx_err_stats_proc(SYSCTL_HANDLER_ARGS) 1204 { 1205 struct atse_softc *sc; 1206 int error, offset, s; 1207 1208 sc = arg1; 1209 offset = arg2; 1210 1211 s = sc->atse_rx_err[offset]; 1212 error = sysctl_handle_int(oidp, &s, 0, req); 1213 if (error || !req->newptr) { 1214 return (error); 1215 } 1216 1217 return (0); 1218 } 1219 1220 static void 1221 atse_sysctl_stats_attach(device_t dev) 1222 { 1223 struct sysctl_ctx_list *sctx; 1224 struct sysctl_oid *soid; 1225 struct atse_softc *sc; 1226 int i; 1227 1228 sc = device_get_softc(dev); 1229 sctx = device_get_sysctl_ctx(dev); 1230 soid = device_get_sysctl_tree(dev); 1231 1232 /* MAC statistics. */ 1233 for (i = 0; i < nitems(atse_mac_stats_regs); i++) { 1234 if (atse_mac_stats_regs[i].name == NULL || 1235 atse_mac_stats_regs[i].descr == NULL) { 1236 continue; 1237 } 1238 1239 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, 1240 atse_mac_stats_regs[i].name, 1241 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 1242 sc, i, sysctl_atse_mac_stats_proc, "IU", 1243 atse_mac_stats_regs[i].descr); 1244 } 1245 1246 /* rx_err[]. */ 1247 for (i = 0; i < ATSE_RX_ERR_MAX; i++) { 1248 if (atse_rx_err_stats_regs[i].name == NULL || 1249 atse_rx_err_stats_regs[i].descr == NULL) { 1250 continue; 1251 } 1252 1253 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, 1254 atse_rx_err_stats_regs[i].name, 1255 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 1256 sc, i, sysctl_atse_rx_err_stats_proc, "IU", 1257 atse_rx_err_stats_regs[i].descr); 1258 } 1259 } 1260 1261 /* 1262 * Generic device handling routines. 1263 */ 1264 int 1265 atse_attach(device_t dev) 1266 { 1267 struct atse_softc *sc; 1268 struct ifnet *ifp; 1269 uint32_t caps; 1270 int error; 1271 1272 sc = device_get_softc(dev); 1273 sc->dev = dev; 1274 1275 /* Get xDMA controller */ 1276 sc->xdma_tx = xdma_ofw_get(sc->dev, "tx"); 1277 if (sc->xdma_tx == NULL) { 1278 device_printf(dev, "Can't find DMA controller.\n"); 1279 return (ENXIO); 1280 } 1281 1282 /* 1283 * Only final (EOP) write can be less than "symbols per beat" value 1284 * so we have to defrag mbuf chain. 1285 * Chapter 15. On-Chip FIFO Memory Core. 1286 * Embedded Peripherals IP User Guide. 1287 */ 1288 caps = XCHAN_CAP_NOSEG; 1289 1290 /* Alloc xDMA virtual channel. */ 1291 sc->xchan_tx = xdma_channel_alloc(sc->xdma_tx, caps); 1292 if (sc->xchan_tx == NULL) { 1293 device_printf(dev, "Can't alloc virtual DMA channel.\n"); 1294 return (ENXIO); 1295 } 1296 1297 /* Setup interrupt handler. */ 1298 error = xdma_setup_intr(sc->xchan_tx, 0, 1299 atse_xdma_tx_intr, sc, &sc->ih_tx); 1300 if (error) { 1301 device_printf(sc->dev, 1302 "Can't setup xDMA interrupt handler.\n"); 1303 return (ENXIO); 1304 } 1305 1306 xdma_prep_sg(sc->xchan_tx, 1307 TX_QUEUE_SIZE, /* xchan requests queue size */ 1308 MCLBYTES, /* maxsegsize */ 1309 8, /* maxnsegs */ 1310 16, /* alignment */ 1311 0, /* boundary */ 1312 BUS_SPACE_MAXADDR_32BIT, 1313 BUS_SPACE_MAXADDR); 1314 1315 /* Get RX xDMA controller */ 1316 sc->xdma_rx = xdma_ofw_get(sc->dev, "rx"); 1317 if (sc->xdma_rx == NULL) { 1318 device_printf(dev, "Can't find DMA controller.\n"); 1319 return (ENXIO); 1320 } 1321 1322 /* Alloc xDMA virtual channel. */ 1323 sc->xchan_rx = xdma_channel_alloc(sc->xdma_rx, caps); 1324 if (sc->xchan_rx == NULL) { 1325 device_printf(dev, "Can't alloc virtual DMA channel.\n"); 1326 return (ENXIO); 1327 } 1328 1329 /* Setup interrupt handler. */ 1330 error = xdma_setup_intr(sc->xchan_rx, XDMA_INTR_NET, 1331 atse_xdma_rx_intr, sc, &sc->ih_rx); 1332 if (error) { 1333 device_printf(sc->dev, 1334 "Can't setup xDMA interrupt handler.\n"); 1335 return (ENXIO); 1336 } 1337 1338 xdma_prep_sg(sc->xchan_rx, 1339 RX_QUEUE_SIZE, /* xchan requests queue size */ 1340 MCLBYTES, /* maxsegsize */ 1341 1, /* maxnsegs */ 1342 16, /* alignment */ 1343 0, /* boundary */ 1344 BUS_SPACE_MAXADDR_32BIT, 1345 BUS_SPACE_MAXADDR); 1346 1347 mtx_init(&sc->br_mtx, "buf ring mtx", NULL, MTX_DEF); 1348 sc->br = buf_ring_alloc(BUFRING_SIZE, M_DEVBUF, 1349 M_NOWAIT, &sc->br_mtx); 1350 if (sc->br == NULL) { 1351 return (ENOMEM); 1352 } 1353 1354 atse_ethernet_option_bits_read(dev); 1355 1356 mtx_init(&sc->atse_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1357 MTX_DEF); 1358 1359 callout_init_mtx(&sc->atse_tick, &sc->atse_mtx, 0); 1360 1361 /* 1362 * We are only doing single-PHY with this driver currently. The 1363 * defaults would be right so that BASE_CFG_MDIO_ADDR0 points to the 1364 * 1st PHY address (0) apart from the fact that BMCR0 is always 1365 * the PCS mapping, so we always use BMCR1. See Table 5-1 0xA0-0xBF. 1366 */ 1367 #if 0 /* Always PCS. */ 1368 sc->atse_bmcr0 = MDIO_0_START; 1369 CSR_WRITE_4(sc, BASE_CFG_MDIO_ADDR0, 0x00); 1370 #endif 1371 /* Always use matching PHY for atse[0..]. */ 1372 sc->atse_phy_addr = device_get_unit(dev); 1373 sc->atse_bmcr1 = MDIO_1_START; 1374 CSR_WRITE_4(sc, BASE_CFG_MDIO_ADDR1, sc->atse_phy_addr); 1375 1376 /* Reset the adapter. */ 1377 atse_reset(sc); 1378 1379 /* Setup interface. */ 1380 ifp = sc->atse_ifp = if_alloc(IFT_ETHER); 1381 if (ifp == NULL) { 1382 device_printf(dev, "if_alloc() failed\n"); 1383 error = ENOSPC; 1384 goto err; 1385 } 1386 ifp->if_softc = sc; 1387 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1388 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1389 ifp->if_ioctl = atse_ioctl; 1390 ifp->if_transmit = atse_transmit; 1391 ifp->if_qflush = atse_qflush; 1392 ifp->if_init = atse_init; 1393 IFQ_SET_MAXLEN(&ifp->if_snd, ATSE_TX_LIST_CNT - 1); 1394 ifp->if_snd.ifq_drv_maxlen = ATSE_TX_LIST_CNT - 1; 1395 IFQ_SET_READY(&ifp->if_snd); 1396 1397 /* MII setup. */ 1398 error = mii_attach(dev, &sc->atse_miibus, ifp, atse_ifmedia_upd, 1399 atse_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 1400 if (error != 0) { 1401 device_printf(dev, "attaching PHY failed: %d\n", error); 1402 goto err; 1403 } 1404 1405 /* Call media-indepedent attach routine. */ 1406 ether_ifattach(ifp, sc->atse_eth_addr); 1407 1408 /* Tell the upper layer(s) about vlan mtu support. */ 1409 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 1410 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1411 ifp->if_capenable = ifp->if_capabilities; 1412 1413 err: 1414 if (error != 0) { 1415 atse_detach(dev); 1416 } 1417 1418 if (error == 0) { 1419 atse_sysctl_stats_attach(dev); 1420 } 1421 1422 atse_rx_enqueue(sc, NUM_RX_MBUF); 1423 xdma_queue_submit(sc->xchan_rx); 1424 1425 return (error); 1426 } 1427 1428 static int 1429 atse_detach(device_t dev) 1430 { 1431 struct atse_softc *sc; 1432 struct ifnet *ifp; 1433 1434 sc = device_get_softc(dev); 1435 KASSERT(mtx_initialized(&sc->atse_mtx), ("%s: mutex not initialized", 1436 device_get_nameunit(dev))); 1437 ifp = sc->atse_ifp; 1438 1439 /* Only cleanup if attach succeeded. */ 1440 if (device_is_attached(dev)) { 1441 ATSE_LOCK(sc); 1442 atse_stop_locked(sc); 1443 ATSE_UNLOCK(sc); 1444 callout_drain(&sc->atse_tick); 1445 ether_ifdetach(ifp); 1446 } 1447 if (sc->atse_miibus != NULL) { 1448 device_delete_child(dev, sc->atse_miibus); 1449 } 1450 1451 if (ifp != NULL) { 1452 if_free(ifp); 1453 } 1454 1455 mtx_destroy(&sc->atse_mtx); 1456 1457 xdma_channel_free(sc->xchan_tx); 1458 xdma_channel_free(sc->xchan_rx); 1459 xdma_put(sc->xdma_tx); 1460 xdma_put(sc->xdma_rx); 1461 1462 return (0); 1463 } 1464 1465 /* Shared between nexus and fdt implementation. */ 1466 void 1467 atse_detach_resources(device_t dev) 1468 { 1469 struct atse_softc *sc; 1470 1471 sc = device_get_softc(dev); 1472 1473 if (sc->atse_mem_res != NULL) { 1474 bus_release_resource(dev, SYS_RES_MEMORY, sc->atse_mem_rid, 1475 sc->atse_mem_res); 1476 sc->atse_mem_res = NULL; 1477 } 1478 } 1479 1480 int 1481 atse_detach_dev(device_t dev) 1482 { 1483 int error; 1484 1485 error = atse_detach(dev); 1486 if (error) { 1487 /* We are basically in undefined state now. */ 1488 device_printf(dev, "atse_detach() failed: %d\n", error); 1489 return (error); 1490 } 1491 1492 atse_detach_resources(dev); 1493 1494 return (0); 1495 } 1496 1497 int 1498 atse_miibus_readreg(device_t dev, int phy, int reg) 1499 { 1500 struct atse_softc *sc; 1501 int val; 1502 1503 sc = device_get_softc(dev); 1504 1505 /* 1506 * We currently do not support re-mapping of MDIO space on-the-fly 1507 * but de-facto hard-code the phy#. 1508 */ 1509 if (phy != sc->atse_phy_addr) { 1510 return (0); 1511 } 1512 1513 val = PHY_READ_2(sc, reg); 1514 1515 return (val); 1516 } 1517 1518 int 1519 atse_miibus_writereg(device_t dev, int phy, int reg, int data) 1520 { 1521 struct atse_softc *sc; 1522 1523 sc = device_get_softc(dev); 1524 1525 /* 1526 * We currently do not support re-mapping of MDIO space on-the-fly 1527 * but de-facto hard-code the phy#. 1528 */ 1529 if (phy != sc->atse_phy_addr) { 1530 return (0); 1531 } 1532 1533 PHY_WRITE_2(sc, reg, data); 1534 return (0); 1535 } 1536 1537 void 1538 atse_miibus_statchg(device_t dev) 1539 { 1540 struct atse_softc *sc; 1541 struct mii_data *mii; 1542 struct ifnet *ifp; 1543 uint32_t val4; 1544 1545 sc = device_get_softc(dev); 1546 ATSE_LOCK_ASSERT(sc); 1547 1548 mii = device_get_softc(sc->atse_miibus); 1549 ifp = sc->atse_ifp; 1550 if (mii == NULL || ifp == NULL || 1551 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1552 return; 1553 } 1554 1555 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); 1556 1557 /* Assume no link. */ 1558 sc->atse_flags &= ~ATSE_FLAGS_LINK; 1559 1560 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1561 (IFM_ACTIVE | IFM_AVALID)) { 1562 1563 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1564 case IFM_10_T: 1565 val4 |= BASE_CFG_COMMAND_CONFIG_ENA_10; 1566 val4 &= ~BASE_CFG_COMMAND_CONFIG_ETH_SPEED; 1567 sc->atse_flags |= ATSE_FLAGS_LINK; 1568 break; 1569 case IFM_100_TX: 1570 val4 &= ~BASE_CFG_COMMAND_CONFIG_ENA_10; 1571 val4 &= ~BASE_CFG_COMMAND_CONFIG_ETH_SPEED; 1572 sc->atse_flags |= ATSE_FLAGS_LINK; 1573 break; 1574 case IFM_1000_T: 1575 val4 &= ~BASE_CFG_COMMAND_CONFIG_ENA_10; 1576 val4 |= BASE_CFG_COMMAND_CONFIG_ETH_SPEED; 1577 sc->atse_flags |= ATSE_FLAGS_LINK; 1578 break; 1579 default: 1580 break; 1581 } 1582 } 1583 1584 if ((sc->atse_flags & ATSE_FLAGS_LINK) == 0) { 1585 /* Need to stop the MAC? */ 1586 return; 1587 } 1588 1589 if (IFM_OPTIONS(mii->mii_media_active & IFM_FDX) != 0) { 1590 val4 &= ~BASE_CFG_COMMAND_CONFIG_HD_ENA; 1591 } else { 1592 val4 |= BASE_CFG_COMMAND_CONFIG_HD_ENA; 1593 } 1594 1595 /* flow control? */ 1596 1597 /* Make sure the MAC is activated. */ 1598 val4 |= BASE_CFG_COMMAND_CONFIG_TX_ENA; 1599 val4 |= BASE_CFG_COMMAND_CONFIG_RX_ENA; 1600 1601 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4); 1602 } 1603 1604 MODULE_DEPEND(atse, ether, 1, 1, 1); 1605 MODULE_DEPEND(atse, miibus, 1, 1, 1); 1606