1 /*- 2 * Copyright (c) 2017-2018 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33 #include "opt_altera_msgdma.h" 34 35 /* Altera mSGDMA registers. */ 36 #define DMA_STATUS 0x00 37 #define STATUS_RESETTING (1 << 6) 38 #define DMA_CONTROL 0x04 39 #define CONTROL_GIEM (1 << 4) /* Global Interrupt Enable Mask */ 40 #define CONTROL_RESET (1 << 1) /* Reset Dispatcher */ 41 42 /* Descriptor fields. */ 43 #define CONTROL_GO (1 << 31) /* Commit all the descriptor info */ 44 #define CONTROL_OWN (1 << 30) /* Owned by hardware (prefetcher-enabled only) */ 45 #define CONTROL_EDE (1 << 24) /* Early done enable */ 46 #define CONTROL_ERR_S 16 /* Transmit Error, Error IRQ Enable */ 47 #define CONTROL_ERR_M (0xff << CONTROL_ERR_S) 48 #define CONTROL_ET_IRQ_EN (1 << 15) /* Early Termination IRQ Enable */ 49 #define CONTROL_TC_IRQ_EN (1 << 14) /* Transfer Complete IRQ Enable */ 50 #define CONTROL_END_ON_EOP (1 << 12) /* End on EOP */ 51 #define CONTROL_PARK_WR (1 << 11) /* Park Writes */ 52 #define CONTROL_PARK_RD (1 << 10) /* Park Reads */ 53 #define CONTROL_GEN_EOP (1 << 9) /* Generate EOP */ 54 #define CONTROL_GEN_SOP (1 << 8) /* Generate SOP */ 55 #define CONTROL_TX_CHANNEL_S 0 /* Transmit Channel */ 56 #define CONTROL_TX_CHANNEL_M (0xff << CONTROL_TRANSMIT_CH_S) 57 58 /* Prefetcher */ 59 #define PF_CONTROL 0x00 60 #define PF_CONTROL_GIEM (1 << 3) 61 #define PF_CONTROL_RESET (1 << 2) 62 #define PF_CONTROL_DESC_POLL_EN (1 << 1) 63 #define PF_CONTROL_RUN (1 << 0) 64 #define PF_NEXT_LO 0x04 65 #define PF_NEXT_HI 0x08 66 #define PF_POLL_FREQ 0x0C 67 #define PF_STATUS 0x10 68 #define PF_STATUS_IRQ (1 << 0) 69 70 #define READ4(_sc, _reg) \ 71 le32toh(bus_space_read_4(_sc->bst, _sc->bsh, _reg)) 72 #define WRITE4(_sc, _reg, _val) \ 73 bus_space_write_4(_sc->bst, _sc->bsh, _reg, htole32(_val)) 74 75 #define READ4_DESC(_sc, _reg) \ 76 le32toh(bus_space_read_4(_sc->bst_d, _sc->bsh_d, _reg)) 77 #define WRITE4_DESC(_sc, _reg, _val) \ 78 bus_space_write_4(_sc->bst_d, _sc->bsh_d, _reg, htole32(_val)) 79 80 #if defined(ALTERA_MSGDMA_DESC_STD) 81 82 /* Standard descriptor format with prefetcher disabled. */ 83 struct msgdma_desc { 84 uint32_t read_lo; 85 uint32_t write_lo; 86 uint32_t length; 87 uint32_t control; 88 }; 89 90 #elif defined(ALTERA_MSGDMA_DESC_EXT) 91 92 /* Extended descriptor format with prefetcher disabled. */ 93 struct msgdma_desc { 94 uint32_t read_lo; 95 uint32_t write_lo; 96 uint32_t length; 97 uint8_t write_burst; 98 uint8_t read_burst; 99 uint16_t seq_num; 100 uint16_t write_stride; 101 uint16_t read_stride; 102 uint32_t read_hi; 103 uint32_t write_hi; 104 uint32_t control; 105 }; 106 107 #elif defined(ALTERA_MSGDMA_DESC_PF_STD) 108 109 /* Standard descriptor format with prefetcher enabled. */ 110 struct msgdma_desc { 111 uint32_t read_lo; 112 uint32_t write_lo; 113 uint32_t length; 114 uint32_t next; 115 uint32_t transferred; 116 uint32_t status; 117 uint32_t reserved; 118 uint32_t control; 119 }; 120 121 #elif defined(ALTERA_MSGDMA_DESC_PF_EXT) 122 123 /* Extended descriptor format with prefetcher enabled. */ 124 struct msgdma_desc { 125 uint32_t read_lo; 126 uint32_t write_lo; 127 uint32_t length; 128 uint32_t next; 129 uint32_t transferred; 130 uint32_t status; 131 uint32_t reserved; 132 uint8_t write_burst; 133 uint8_t read_burst; 134 uint16_t seq_num; 135 uint16_t write_stride; 136 uint16_t read_stride; 137 uint32_t read_hi; 138 uint32_t write_hi; 139 uint32_t next_hi; 140 uint32_t reserved1; 141 uint32_t reserved2; 142 uint32_t reserved3; 143 uint32_t control; 144 }; 145 146 #else 147 148 #error "mSGDMA descriptor format (kernel option) is not set." 149 150 #endif 151