1 /* 2 ******************************************************************************** 3 ** OS : FreeBSD 4 ** FILE NAME : arcmsr.c 5 ** BY : Erich Chen, Ching Huang 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x) 8 ** SATA/SAS RAID HOST Adapter 9 ******************************************************************************** 10 ******************************************************************************** 11 ** 12 ** SPDX-License-Identifier: BSD-3-Clause 13 ** 14 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved. 15 ** 16 ** Redistribution and use in source and binary forms, with or without 17 ** modification, are permitted provided that the following conditions 18 ** are met: 19 ** 1. Redistributions of source code must retain the above copyright 20 ** notice, this list of conditions and the following disclaimer. 21 ** 2. Redistributions in binary form must reproduce the above copyright 22 ** notice, this list of conditions and the following disclaimer in the 23 ** documentation and/or other materials provided with the distribution. 24 ** 3. The name of the author may not be used to endorse or promote products 25 ** derived from this software without specific prior written permission. 26 ** 27 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 29 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 31 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT 32 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 34 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 36 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 ******************************************************************************** 38 ** History 39 ** 40 ** REV# DATE NAME DESCRIPTION 41 ** 1.00.00.00 03/31/2004 Erich Chen First release 42 ** 1.20.00.02 11/29/2004 Erich Chen bug fix with arcmsr_bus_reset when PHY error 43 ** 1.20.00.03 04/19/2005 Erich Chen add SATA 24 Ports adapter type support 44 ** clean unused function 45 ** 1.20.00.12 09/12/2005 Erich Chen bug fix with abort command handling, 46 ** firmware version check 47 ** and firmware update notify for hardware bug fix 48 ** handling if none zero high part physical address 49 ** of srb resource 50 ** 1.20.00.13 08/18/2006 Erich Chen remove pending srb and report busy 51 ** add iop message xfer 52 ** with scsi pass-through command 53 ** add new device id of sas raid adapters 54 ** code fit for SPARC64 & PPC 55 ** 1.20.00.14 02/05/2007 Erich Chen bug fix for incorrect ccb_h.status report 56 ** and cause g_vfs_done() read write error 57 ** 1.20.00.15 10/10/2007 Erich Chen support new RAID adapter type ARC120x 58 ** 1.20.00.16 10/10/2009 Erich Chen Bug fix for RAID adapter type ARC120x 59 ** bus_dmamem_alloc() with BUS_DMA_ZERO 60 ** 1.20.00.17 07/15/2010 Ching Huang Added support ARC1880 61 ** report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed, 62 ** prevent cam_periph_error removing all LUN devices of one Target id 63 ** for any one LUN device failed 64 ** 1.20.00.18 10/14/2010 Ching Huang Fixed "inquiry data fails comparion at DV1 step" 65 ** 10/25/2010 Ching Huang Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B 66 ** 1.20.00.19 11/11/2010 Ching Huang Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0 67 ** 1.20.00.20 12/08/2010 Ching Huang Avoid calling atomic_set_int function 68 ** 1.20.00.21 02/08/2011 Ching Huang Implement I/O request timeout 69 ** 02/14/2011 Ching Huang Modified pktRequestCount 70 ** 1.20.00.21 03/03/2011 Ching Huang if a command timeout, then wait its ccb back before free it 71 ** 1.20.00.22 07/04/2011 Ching Huang Fixed multiple MTX panic 72 ** 1.20.00.23 10/28/2011 Ching Huang Added TIMEOUT_DELAY in case of too many HDDs need to start 73 ** 1.20.00.23 11/08/2011 Ching Huang Added report device transfer speed 74 ** 1.20.00.23 01/30/2012 Ching Huang Fixed Request requeued and Retrying command 75 ** 1.20.00.24 06/11/2012 Ching Huang Fixed return sense data condition 76 ** 1.20.00.25 08/17/2012 Ching Huang Fixed hotplug device no function on type A adapter 77 ** 1.20.00.26 12/14/2012 Ching Huang Added support ARC1214,1224,1264,1284 78 ** 1.20.00.27 05/06/2013 Ching Huang Fixed out standing cmd full on ARC-12x4 79 ** 1.20.00.28 09/13/2013 Ching Huang Removed recursive mutex in arcmsr_abort_dr_ccbs 80 ** 1.20.00.29 12/18/2013 Ching Huang Change simq allocation number, support ARC1883 81 ** 1.30.00.00 11/30/2015 Ching Huang Added support ARC1203 82 ** 1.40.00.00 07/11/2017 Ching Huang Added support ARC1884 83 ** 1.40.00.01 10/30/2017 Ching Huang Fixed release memory resource 84 ** 1.50.00.00 09/30/2020 Ching Huang Added support ARC-1886, NVMe/SAS/SATA controller 85 ** 1.50.00.01 02/26/2021 Ching Huang Fixed no action of hot plugging device on type_F adapter 86 ** 1.50.00.02 04/16/2021 Ching Huang Fixed scsi command timeout on ARC-1886 when 87 ** scatter-gather count large than some number 88 ** 1.50.00.03 05/04/2021 Ching Huang Fixed doorbell status arrived late on ARC-1886 89 ** 1.50.00.04 12/08/2021 Ching Huang Fixed boot up hung under ARC-1886 with no volume created 90 ** 1.50.00.05 03/23/2023 Ching Huang Fixed reading buffer empty length error 91 ****************************************************************************************** 92 */ 93 94 #include <sys/cdefs.h> 95 __FBSDID("$FreeBSD$"); 96 97 #if 0 98 #define ARCMSR_DEBUG1 1 99 #endif 100 #include <sys/param.h> 101 #include <sys/systm.h> 102 #include <sys/malloc.h> 103 #include <sys/kernel.h> 104 #include <sys/bus.h> 105 #include <sys/queue.h> 106 #include <sys/stat.h> 107 #include <sys/devicestat.h> 108 #include <sys/kthread.h> 109 #include <sys/module.h> 110 #include <sys/proc.h> 111 #include <sys/lock.h> 112 #include <sys/sysctl.h> 113 #include <sys/poll.h> 114 #include <sys/ioccom.h> 115 #include <vm/vm.h> 116 #include <vm/vm_param.h> 117 #include <vm/pmap.h> 118 119 #include <isa/rtc.h> 120 121 #include <machine/bus.h> 122 #include <machine/resource.h> 123 #include <machine/atomic.h> 124 #include <sys/conf.h> 125 #include <sys/rman.h> 126 127 #include <cam/cam.h> 128 #include <cam/cam_ccb.h> 129 #include <cam/cam_sim.h> 130 #include <cam/cam_periph.h> 131 #include <cam/cam_xpt_periph.h> 132 #include <cam/cam_xpt_sim.h> 133 #include <cam/cam_debug.h> 134 #include <cam/scsi/scsi_all.h> 135 #include <cam/scsi/scsi_message.h> 136 /* 137 ************************************************************************** 138 ************************************************************************** 139 */ 140 #include <sys/selinfo.h> 141 #include <sys/mutex.h> 142 #include <sys/endian.h> 143 #include <dev/pci/pcivar.h> 144 #include <dev/pci/pcireg.h> 145 146 #define arcmsr_callout_init(a) callout_init(a, /*mpsafe*/1); 147 148 #define ARCMSR_DRIVER_VERSION "arcmsr version 1.50.00.05 2023-03-23" 149 #include <dev/arcmsr/arcmsr.h> 150 /* 151 ************************************************************************** 152 ************************************************************************** 153 */ 154 static void arcmsr_free_srb(struct CommandControlBlock *srb); 155 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb); 156 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb); 157 static int arcmsr_probe(device_t dev); 158 static int arcmsr_attach(device_t dev); 159 static int arcmsr_detach(device_t dev); 160 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg); 161 static void arcmsr_iop_parking(struct AdapterControlBlock *acb); 162 static int arcmsr_shutdown(device_t dev); 163 static void arcmsr_interrupt(struct AdapterControlBlock *acb); 164 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb); 165 static void arcmsr_free_resource(struct AdapterControlBlock *acb); 166 static void arcmsr_bus_reset(struct AdapterControlBlock *acb); 167 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb); 168 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb); 169 static void arcmsr_iop_init(struct AdapterControlBlock *acb); 170 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb); 171 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, struct QBUFFER *prbuffer); 172 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb); 173 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb); 174 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag); 175 static void arcmsr_iop_reset(struct AdapterControlBlock *acb); 176 static void arcmsr_report_sense_info(struct CommandControlBlock *srb); 177 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t *dm_segs, u_int32_t nseg); 178 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb); 179 static int arcmsr_resume(device_t dev); 180 static int arcmsr_suspend(device_t dev); 181 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb); 182 static void arcmsr_polling_devmap(void *arg); 183 static void arcmsr_srb_timeout(void *arg); 184 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb); 185 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb); 186 static void arcmsr_hbf_postqueue_isr(struct AdapterControlBlock *acb); 187 static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb); 188 #ifdef ARCMSR_DEBUG1 189 static void arcmsr_dump_data(struct AdapterControlBlock *acb); 190 #endif 191 /* 192 ************************************************************************** 193 ************************************************************************** 194 */ 195 static void UDELAY(u_int32_t us) { DELAY(us); } 196 /* 197 ************************************************************************** 198 ************************************************************************** 199 */ 200 static bus_dmamap_callback_t arcmsr_map_free_srb; 201 static bus_dmamap_callback_t arcmsr_execute_srb; 202 /* 203 ************************************************************************** 204 ************************************************************************** 205 */ 206 static d_open_t arcmsr_open; 207 static d_close_t arcmsr_close; 208 static d_ioctl_t arcmsr_ioctl; 209 210 static device_method_t arcmsr_methods[]={ 211 DEVMETHOD(device_probe, arcmsr_probe), 212 DEVMETHOD(device_attach, arcmsr_attach), 213 DEVMETHOD(device_detach, arcmsr_detach), 214 DEVMETHOD(device_shutdown, arcmsr_shutdown), 215 DEVMETHOD(device_suspend, arcmsr_suspend), 216 DEVMETHOD(device_resume, arcmsr_resume), 217 DEVMETHOD_END 218 }; 219 220 static driver_t arcmsr_driver={ 221 "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock) 222 }; 223 224 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, 0, 0); 225 MODULE_DEPEND(arcmsr, pci, 1, 1, 1); 226 MODULE_DEPEND(arcmsr, cam, 1, 1, 1); 227 #ifndef BUS_DMA_COHERENT 228 #define BUS_DMA_COHERENT 0x04 /* hint: map memory in a coherent way */ 229 #endif 230 static struct cdevsw arcmsr_cdevsw={ 231 .d_version = D_VERSION, 232 .d_open = arcmsr_open, /* open */ 233 .d_close = arcmsr_close, /* close */ 234 .d_ioctl = arcmsr_ioctl, /* ioctl */ 235 .d_name = "arcmsr", /* name */ 236 }; 237 /* 238 ************************************************************************** 239 ************************************************************************** 240 */ 241 static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc) 242 { 243 return (0); 244 } 245 /* 246 ************************************************************************** 247 ************************************************************************** 248 */ 249 static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc) 250 { 251 return 0; 252 } 253 /* 254 ************************************************************************** 255 ************************************************************************** 256 */ 257 static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc) 258 { 259 struct AdapterControlBlock *acb = dev->si_drv1; 260 261 return (arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg)); 262 } 263 /* 264 ********************************************************************** 265 ********************************************************************** 266 */ 267 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb) 268 { 269 u_int32_t intmask_org = 0; 270 271 switch (acb->adapter_type) { 272 case ACB_ADAPTER_TYPE_A: { 273 /* disable all outbound interrupt */ 274 intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */ 275 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE); 276 } 277 break; 278 case ACB_ADAPTER_TYPE_B: { 279 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 280 /* disable all outbound interrupt */ 281 intmask_org = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask) 282 & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */ 283 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, 0); /* disable all interrupt */ 284 } 285 break; 286 case ACB_ADAPTER_TYPE_C: { 287 /* disable all outbound interrupt */ 288 intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask); /* disable outbound message0 int */ 289 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE); 290 } 291 break; 292 case ACB_ADAPTER_TYPE_D: { 293 /* disable all outbound interrupt */ 294 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); /* disable outbound message0 int */ 295 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 296 } 297 break; 298 case ACB_ADAPTER_TYPE_E: 299 case ACB_ADAPTER_TYPE_F: { 300 /* disable all outbound interrupt */ 301 intmask_org = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_mask); /* disable outbound message0 int */ 302 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE); 303 } 304 break; 305 } 306 return (intmask_org); 307 } 308 /* 309 ********************************************************************** 310 ********************************************************************** 311 */ 312 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org) 313 { 314 u_int32_t mask; 315 316 switch (acb->adapter_type) { 317 case ACB_ADAPTER_TYPE_A: { 318 /* enable outbound Post Queue, outbound doorbell Interrupt */ 319 mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE); 320 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask); 321 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff; 322 } 323 break; 324 case ACB_ADAPTER_TYPE_B: { 325 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 326 /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */ 327 mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); 328 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/ 329 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f; 330 } 331 break; 332 case ACB_ADAPTER_TYPE_C: { 333 /* enable outbound Post Queue, outbound doorbell Interrupt */ 334 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK); 335 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask); 336 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 337 } 338 break; 339 case ACB_ADAPTER_TYPE_D: { 340 /* enable outbound Post Queue, outbound doorbell Interrupt */ 341 mask = ARCMSR_HBDMU_ALL_INT_ENABLE; 342 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask); 343 CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 344 acb->outbound_int_enable = mask; 345 } 346 break; 347 case ACB_ADAPTER_TYPE_E: 348 case ACB_ADAPTER_TYPE_F: { 349 /* enable outbound Post Queue, outbound doorbell Interrupt */ 350 mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR); 351 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org & mask); 352 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 353 } 354 break; 355 } 356 } 357 /* 358 ********************************************************************** 359 ********************************************************************** 360 */ 361 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb) 362 { 363 u_int32_t Index; 364 u_int8_t Retries = 0x00; 365 366 do { 367 for(Index=0; Index < 100; Index++) { 368 if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 369 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/ 370 return TRUE; 371 } 372 UDELAY(10000); 373 }/*max 1 seconds*/ 374 }while(Retries++ < 20);/*max 20 sec*/ 375 return (FALSE); 376 } 377 /* 378 ********************************************************************** 379 ********************************************************************** 380 */ 381 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb) 382 { 383 u_int32_t Index; 384 u_int8_t Retries = 0x00; 385 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 386 387 do { 388 for(Index=0; Index < 100; Index++) { 389 if(READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 390 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/ 391 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 392 return TRUE; 393 } 394 UDELAY(10000); 395 }/*max 1 seconds*/ 396 }while(Retries++ < 20);/*max 20 sec*/ 397 return (FALSE); 398 } 399 /* 400 ********************************************************************** 401 ********************************************************************** 402 */ 403 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb) 404 { 405 u_int32_t Index; 406 u_int8_t Retries = 0x00; 407 408 do { 409 for(Index=0; Index < 100; Index++) { 410 if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 411 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/ 412 return TRUE; 413 } 414 UDELAY(10000); 415 }/*max 1 seconds*/ 416 }while(Retries++ < 20);/*max 20 sec*/ 417 return (FALSE); 418 } 419 /* 420 ********************************************************************** 421 ********************************************************************** 422 */ 423 static u_int8_t arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock *acb) 424 { 425 u_int32_t Index; 426 u_int8_t Retries = 0x00; 427 428 do { 429 for(Index=0; Index < 100; Index++) { 430 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 431 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/ 432 return TRUE; 433 } 434 UDELAY(10000); 435 }/*max 1 seconds*/ 436 }while(Retries++ < 20);/*max 20 sec*/ 437 return (FALSE); 438 } 439 /* 440 ********************************************************************** 441 ********************************************************************** 442 */ 443 static u_int8_t arcmsr_hbe_wait_msgint_ready(struct AdapterControlBlock *acb) 444 { 445 u_int32_t Index, read_doorbell; 446 u_int8_t Retries = 0x00; 447 448 do { 449 for(Index=0; Index < 100; Index++) { 450 read_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 451 if((read_doorbell ^ acb->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 452 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0);/*clear interrupt*/ 453 acb->in_doorbell = read_doorbell; 454 return TRUE; 455 } 456 UDELAY(10000); 457 }/*max 1 seconds*/ 458 }while(Retries++ < 20);/*max 20 sec*/ 459 return (FALSE); 460 } 461 /* 462 ************************************************************************ 463 ************************************************************************ 464 */ 465 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb) 466 { 467 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 468 469 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 470 do { 471 if(arcmsr_hba_wait_msgint_ready(acb)) { 472 break; 473 } else { 474 retry_count--; 475 } 476 }while(retry_count != 0); 477 } 478 /* 479 ************************************************************************ 480 ************************************************************************ 481 */ 482 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb) 483 { 484 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 485 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 486 487 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE); 488 do { 489 if(arcmsr_hbb_wait_msgint_ready(acb)) { 490 break; 491 } else { 492 retry_count--; 493 } 494 }while(retry_count != 0); 495 } 496 /* 497 ************************************************************************ 498 ************************************************************************ 499 */ 500 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb) 501 { 502 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 503 504 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 505 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 506 do { 507 if(arcmsr_hbc_wait_msgint_ready(acb)) { 508 break; 509 } else { 510 retry_count--; 511 } 512 }while(retry_count != 0); 513 } 514 /* 515 ************************************************************************ 516 ************************************************************************ 517 */ 518 static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb) 519 { 520 int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */ 521 522 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 523 do { 524 if(arcmsr_hbd_wait_msgint_ready(acb)) { 525 break; 526 } else { 527 retry_count--; 528 } 529 }while(retry_count != 0); 530 } 531 /* 532 ************************************************************************ 533 ************************************************************************ 534 */ 535 static void arcmsr_flush_hbe_cache(struct AdapterControlBlock *acb) 536 { 537 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 538 539 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 540 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 541 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 542 do { 543 if(arcmsr_hbe_wait_msgint_ready(acb)) { 544 break; 545 } else { 546 retry_count--; 547 } 548 }while(retry_count != 0); 549 } 550 /* 551 ************************************************************************ 552 ************************************************************************ 553 */ 554 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb) 555 { 556 switch (acb->adapter_type) { 557 case ACB_ADAPTER_TYPE_A: { 558 arcmsr_flush_hba_cache(acb); 559 } 560 break; 561 case ACB_ADAPTER_TYPE_B: { 562 arcmsr_flush_hbb_cache(acb); 563 } 564 break; 565 case ACB_ADAPTER_TYPE_C: { 566 arcmsr_flush_hbc_cache(acb); 567 } 568 break; 569 case ACB_ADAPTER_TYPE_D: { 570 arcmsr_flush_hbd_cache(acb); 571 } 572 break; 573 case ACB_ADAPTER_TYPE_E: 574 case ACB_ADAPTER_TYPE_F: { 575 arcmsr_flush_hbe_cache(acb); 576 } 577 break; 578 } 579 } 580 /* 581 ******************************************************************************* 582 ******************************************************************************* 583 */ 584 static int arcmsr_suspend(device_t dev) 585 { 586 struct AdapterControlBlock *acb = device_get_softc(dev); 587 588 /* flush controller */ 589 arcmsr_iop_parking(acb); 590 /* disable all outbound interrupt */ 591 arcmsr_disable_allintr(acb); 592 return(0); 593 } 594 /* 595 ******************************************************************************* 596 ******************************************************************************* 597 */ 598 static int arcmsr_resume(device_t dev) 599 { 600 struct AdapterControlBlock *acb = device_get_softc(dev); 601 602 arcmsr_iop_init(acb); 603 return(0); 604 } 605 /* 606 ********************************************************************************* 607 ********************************************************************************* 608 */ 609 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg) 610 { 611 u_int8_t target_id, target_lun; 612 613 switch (code) { 614 case AC_LOST_DEVICE: 615 target_id = xpt_path_target_id(path); 616 target_lun = xpt_path_lun_id(path); 617 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) { 618 break; 619 } 620 break; 621 default: 622 break; 623 } 624 } 625 /* 626 ********************************************************************** 627 ********************************************************************** 628 */ 629 static void arcmsr_report_sense_info(struct CommandControlBlock *srb) 630 { 631 union ccb *pccb = srb->pccb; 632 633 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 634 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 635 if(pccb->csio.sense_len) { 636 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data)); 637 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData, 638 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data))); 639 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */ 640 pccb->ccb_h.status |= CAM_AUTOSNS_VALID; 641 } 642 } 643 /* 644 ********************************************************************* 645 ********************************************************************* 646 */ 647 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb) 648 { 649 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 650 if(!arcmsr_hba_wait_msgint_ready(acb)) { 651 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 652 } 653 } 654 /* 655 ********************************************************************* 656 ********************************************************************* 657 */ 658 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb) 659 { 660 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 661 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD); 662 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 663 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 664 } 665 } 666 /* 667 ********************************************************************* 668 ********************************************************************* 669 */ 670 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb) 671 { 672 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 673 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 674 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 675 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 676 } 677 } 678 /* 679 ********************************************************************* 680 ********************************************************************* 681 */ 682 static void arcmsr_abort_hbd_allcmd(struct AdapterControlBlock *acb) 683 { 684 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 685 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 686 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 687 } 688 } 689 /* 690 ********************************************************************* 691 ********************************************************************* 692 */ 693 static void arcmsr_abort_hbe_allcmd(struct AdapterControlBlock *acb) 694 { 695 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 696 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 697 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 698 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 699 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 700 } 701 } 702 /* 703 ********************************************************************* 704 ********************************************************************* 705 */ 706 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb) 707 { 708 switch (acb->adapter_type) { 709 case ACB_ADAPTER_TYPE_A: { 710 arcmsr_abort_hba_allcmd(acb); 711 } 712 break; 713 case ACB_ADAPTER_TYPE_B: { 714 arcmsr_abort_hbb_allcmd(acb); 715 } 716 break; 717 case ACB_ADAPTER_TYPE_C: { 718 arcmsr_abort_hbc_allcmd(acb); 719 } 720 break; 721 case ACB_ADAPTER_TYPE_D: { 722 arcmsr_abort_hbd_allcmd(acb); 723 } 724 break; 725 case ACB_ADAPTER_TYPE_E: 726 case ACB_ADAPTER_TYPE_F: { 727 arcmsr_abort_hbe_allcmd(acb); 728 } 729 break; 730 } 731 } 732 /* 733 ********************************************************************** 734 ********************************************************************** 735 */ 736 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag) 737 { 738 struct AdapterControlBlock *acb = srb->acb; 739 union ccb *pccb = srb->pccb; 740 741 if(srb->srb_flags & SRB_FLAG_TIMER_START) 742 callout_stop(&srb->ccb_callout); 743 if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 744 bus_dmasync_op_t op; 745 746 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 747 op = BUS_DMASYNC_POSTREAD; 748 } else { 749 op = BUS_DMASYNC_POSTWRITE; 750 } 751 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 752 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 753 } 754 if(stand_flag == 1) { 755 atomic_subtract_int(&acb->srboutstandingcount, 1); 756 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && ( 757 acb->srboutstandingcount < (acb->maxOutstanding -10))) { 758 acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN; 759 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 760 } 761 } 762 if(srb->srb_state != ARCMSR_SRB_TIMEOUT) 763 arcmsr_free_srb(srb); 764 acb->pktReturnCount++; 765 xpt_done(pccb); 766 } 767 /* 768 ************************************************************************** 769 ************************************************************************** 770 */ 771 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error) 772 { 773 int target, lun; 774 775 target = srb->pccb->ccb_h.target_id; 776 lun = srb->pccb->ccb_h.target_lun; 777 if(error == FALSE) { 778 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 779 acb->devstate[target][lun] = ARECA_RAID_GOOD; 780 } 781 srb->pccb->ccb_h.status |= CAM_REQ_CMP; 782 arcmsr_srb_complete(srb, 1); 783 } else { 784 switch(srb->arcmsr_cdb.DeviceStatus) { 785 case ARCMSR_DEV_SELECT_TIMEOUT: { 786 if(acb->devstate[target][lun] == ARECA_RAID_GOOD) { 787 printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun); 788 } 789 acb->devstate[target][lun] = ARECA_RAID_GONE; 790 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 791 arcmsr_srb_complete(srb, 1); 792 } 793 break; 794 case ARCMSR_DEV_ABORTED: 795 case ARCMSR_DEV_INIT_FAIL: { 796 acb->devstate[target][lun] = ARECA_RAID_GONE; 797 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 798 arcmsr_srb_complete(srb, 1); 799 } 800 break; 801 case SCSISTAT_CHECK_CONDITION: { 802 acb->devstate[target][lun] = ARECA_RAID_GOOD; 803 arcmsr_report_sense_info(srb); 804 arcmsr_srb_complete(srb, 1); 805 } 806 break; 807 default: 808 printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknown DeviceStatus=0x%x \n" 809 , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus); 810 acb->devstate[target][lun] = ARECA_RAID_GONE; 811 srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY; 812 /*unknown error or crc error just for retry*/ 813 arcmsr_srb_complete(srb, 1); 814 break; 815 } 816 } 817 } 818 /* 819 ************************************************************************** 820 ************************************************************************** 821 */ 822 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error) 823 { 824 struct CommandControlBlock *srb; 825 826 /* check if command done with no error*/ 827 switch (acb->adapter_type) { 828 case ACB_ADAPTER_TYPE_A: 829 case ACB_ADAPTER_TYPE_B: 830 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 831 break; 832 case ACB_ADAPTER_TYPE_C: 833 case ACB_ADAPTER_TYPE_D: 834 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/ 835 break; 836 case ACB_ADAPTER_TYPE_E: 837 case ACB_ADAPTER_TYPE_F: 838 srb = acb->psrb_pool[flag_srb]; 839 break; 840 default: 841 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 842 break; 843 } 844 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 845 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) { 846 arcmsr_free_srb(srb); 847 printf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb); 848 return; 849 } 850 printf("arcmsr%d: return srb has been completed\n" 851 "srb='%p' srb_state=0x%x outstanding srb count=%d \n", 852 acb->pci_unit, srb, srb->srb_state, acb->srboutstandingcount); 853 return; 854 } 855 arcmsr_report_srb_state(acb, srb, error); 856 } 857 /* 858 ************************************************************************** 859 ************************************************************************** 860 */ 861 static void arcmsr_srb_timeout(void *arg) 862 { 863 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 864 struct AdapterControlBlock *acb; 865 int target, lun; 866 u_int8_t cmd; 867 868 target = srb->pccb->ccb_h.target_id; 869 lun = srb->pccb->ccb_h.target_lun; 870 acb = srb->acb; 871 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 872 if(srb->srb_state == ARCMSR_SRB_START) 873 { 874 cmd = scsiio_cdb_ptr(&srb->pccb->csio)[0]; 875 srb->srb_state = ARCMSR_SRB_TIMEOUT; 876 srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT; 877 arcmsr_srb_complete(srb, 1); 878 printf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n", 879 acb->pci_unit, target, lun, cmd, srb); 880 } 881 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 882 #ifdef ARCMSR_DEBUG1 883 arcmsr_dump_data(acb); 884 #endif 885 } 886 887 /* 888 ********************************************************************** 889 ********************************************************************** 890 */ 891 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb) 892 { 893 int i=0; 894 u_int32_t flag_srb; 895 u_int16_t error; 896 897 switch (acb->adapter_type) { 898 case ACB_ADAPTER_TYPE_A: { 899 u_int32_t outbound_intstatus; 900 901 /*clear and abort all outbound posted Q*/ 902 outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 903 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/ 904 while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 905 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 906 arcmsr_drain_donequeue(acb, flag_srb, error); 907 } 908 } 909 break; 910 case ACB_ADAPTER_TYPE_B: { 911 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu; 912 913 /*clear all outbound posted Q*/ 914 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 915 for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) { 916 if((flag_srb = phbbmu->done_qbuffer[i]) != 0) { 917 phbbmu->done_qbuffer[i] = 0; 918 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 919 arcmsr_drain_donequeue(acb, flag_srb, error); 920 } 921 phbbmu->post_qbuffer[i] = 0; 922 }/*drain reply FIFO*/ 923 phbbmu->doneq_index = 0; 924 phbbmu->postq_index = 0; 925 } 926 break; 927 case ACB_ADAPTER_TYPE_C: { 928 while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 929 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 930 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 931 arcmsr_drain_donequeue(acb, flag_srb, error); 932 } 933 } 934 break; 935 case ACB_ADAPTER_TYPE_D: 936 arcmsr_hbd_postqueue_isr(acb); 937 break; 938 case ACB_ADAPTER_TYPE_E: 939 arcmsr_hbe_postqueue_isr(acb); 940 break; 941 case ACB_ADAPTER_TYPE_F: 942 arcmsr_hbf_postqueue_isr(acb); 943 break; 944 } 945 } 946 /* 947 **************************************************************************** 948 **************************************************************************** 949 */ 950 static void arcmsr_iop_reset(struct AdapterControlBlock *acb) 951 { 952 struct CommandControlBlock *srb; 953 u_int32_t intmask_org; 954 u_int32_t i=0; 955 956 if(acb->srboutstandingcount>0) { 957 /* disable all outbound interrupt */ 958 intmask_org = arcmsr_disable_allintr(acb); 959 /*clear and abort all outbound posted Q*/ 960 arcmsr_done4abort_postqueue(acb); 961 /* talk to iop 331 outstanding command aborted*/ 962 arcmsr_abort_allcmd(acb); 963 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 964 srb = acb->psrb_pool[i]; 965 if(srb->srb_state == ARCMSR_SRB_START) { 966 srb->srb_state = ARCMSR_SRB_ABORTED; 967 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 968 arcmsr_srb_complete(srb, 1); 969 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p' aborted\n" 970 , acb->pci_unit, srb->pccb->ccb_h.target_id 971 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 972 } 973 } 974 /* enable all outbound interrupt */ 975 arcmsr_enable_allintr(acb, intmask_org); 976 } 977 acb->srboutstandingcount = 0; 978 acb->workingsrb_doneindex = 0; 979 acb->workingsrb_startindex = 0; 980 acb->pktRequestCount = 0; 981 acb->pktReturnCount = 0; 982 } 983 /* 984 ********************************************************************** 985 ********************************************************************** 986 */ 987 static void arcmsr_build_srb(struct CommandControlBlock *srb, 988 bus_dma_segment_t *dm_segs, u_int32_t nseg) 989 { 990 struct ARCMSR_CDB *arcmsr_cdb = &srb->arcmsr_cdb; 991 u_int8_t *psge = (u_int8_t *)&arcmsr_cdb->u; 992 u_int32_t address_lo, address_hi; 993 union ccb *pccb = srb->pccb; 994 struct ccb_scsiio *pcsio = &pccb->csio; 995 u_int32_t arccdbsize = 0x30; 996 997 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB)); 998 arcmsr_cdb->Bus = 0; 999 arcmsr_cdb->TargetID = pccb->ccb_h.target_id; 1000 arcmsr_cdb->LUN = pccb->ccb_h.target_lun; 1001 arcmsr_cdb->Function = 1; 1002 arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len; 1003 bcopy(scsiio_cdb_ptr(pcsio), arcmsr_cdb->Cdb, pcsio->cdb_len); 1004 if(nseg != 0) { 1005 struct AdapterControlBlock *acb = srb->acb; 1006 bus_dmasync_op_t op; 1007 u_int32_t length, i, cdb_sgcount = 0; 1008 1009 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1010 op = BUS_DMASYNC_PREREAD; 1011 } else { 1012 op = BUS_DMASYNC_PREWRITE; 1013 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE; 1014 srb->srb_flags |= SRB_FLAG_WRITE; 1015 } 1016 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 1017 for(i=0; i < nseg; i++) { 1018 /* Get the physical address of the current data pointer */ 1019 length = arcmsr_htole32(dm_segs[i].ds_len); 1020 address_lo = arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr)); 1021 address_hi = arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr)); 1022 if(address_hi == 0) { 1023 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge; 1024 pdma_sg->address = address_lo; 1025 pdma_sg->length = length; 1026 psge += sizeof(struct SG32ENTRY); 1027 arccdbsize += sizeof(struct SG32ENTRY); 1028 } else { 1029 u_int32_t sg64s_size = 0, tmplength = length; 1030 1031 while(1) { 1032 u_int64_t span4G, length0; 1033 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge; 1034 1035 span4G = (u_int64_t)address_lo + tmplength; 1036 pdma_sg->addresshigh = address_hi; 1037 pdma_sg->address = address_lo; 1038 if(span4G > 0x100000000) { 1039 /*see if cross 4G boundary*/ 1040 length0 = 0x100000000-address_lo; 1041 pdma_sg->length = (u_int32_t)length0 | IS_SG64_ADDR; 1042 address_hi = address_hi+1; 1043 address_lo = 0; 1044 tmplength = tmplength - (u_int32_t)length0; 1045 sg64s_size += sizeof(struct SG64ENTRY); 1046 psge += sizeof(struct SG64ENTRY); 1047 cdb_sgcount++; 1048 } else { 1049 pdma_sg->length = tmplength | IS_SG64_ADDR; 1050 sg64s_size += sizeof(struct SG64ENTRY); 1051 psge += sizeof(struct SG64ENTRY); 1052 break; 1053 } 1054 } 1055 arccdbsize += sg64s_size; 1056 } 1057 cdb_sgcount++; 1058 } 1059 arcmsr_cdb->sgcount = (u_int8_t)cdb_sgcount; 1060 arcmsr_cdb->DataLength = pcsio->dxfer_len; 1061 if( arccdbsize > 256) { 1062 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE; 1063 } 1064 } else { 1065 arcmsr_cdb->DataLength = 0; 1066 } 1067 srb->arc_cdb_size = arccdbsize; 1068 arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0); 1069 } 1070 /* 1071 ************************************************************************** 1072 ************************************************************************** 1073 */ 1074 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb) 1075 { 1076 u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low; 1077 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb; 1078 1079 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD); 1080 atomic_add_int(&acb->srboutstandingcount, 1); 1081 srb->srb_state = ARCMSR_SRB_START; 1082 1083 switch (acb->adapter_type) { 1084 case ACB_ADAPTER_TYPE_A: { 1085 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1086 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE); 1087 } else { 1088 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low); 1089 } 1090 } 1091 break; 1092 case ACB_ADAPTER_TYPE_B: { 1093 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1094 int ending_index, index; 1095 1096 index = phbbmu->postq_index; 1097 ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE); 1098 phbbmu->post_qbuffer[ending_index] = 0; 1099 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1100 phbbmu->post_qbuffer[index] = cdb_phyaddr_low | ARCMSR_SRBPOST_FLAG_SGL_BSIZE; 1101 } else { 1102 phbbmu->post_qbuffer[index] = cdb_phyaddr_low; 1103 } 1104 index++; 1105 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 1106 phbbmu->postq_index = index; 1107 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED); 1108 } 1109 break; 1110 case ACB_ADAPTER_TYPE_C: { 1111 u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32; 1112 1113 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size; 1114 ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1); 1115 cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 1116 if(cdb_phyaddr_hi32) 1117 { 1118 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32); 1119 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1120 } 1121 else 1122 { 1123 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1124 } 1125 } 1126 break; 1127 case ACB_ADAPTER_TYPE_D: { 1128 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1129 u_int16_t index_stripped; 1130 u_int16_t postq_index; 1131 struct InBound_SRB *pinbound_srb; 1132 1133 ARCMSR_LOCK_ACQUIRE(&acb->postDone_lock); 1134 postq_index = phbdmu->postq_index; 1135 pinbound_srb = (struct InBound_SRB *)&phbdmu->post_qbuffer[postq_index & 0xFF]; 1136 pinbound_srb->addressHigh = srb->cdb_phyaddr_high; 1137 pinbound_srb->addressLow = srb->cdb_phyaddr_low; 1138 pinbound_srb->length = srb->arc_cdb_size >> 2; 1139 arcmsr_cdb->Context = srb->cdb_phyaddr_low; 1140 if (postq_index & 0x4000) { 1141 index_stripped = postq_index & 0xFF; 1142 index_stripped += 1; 1143 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1144 phbdmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped; 1145 } else { 1146 index_stripped = postq_index; 1147 index_stripped += 1; 1148 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1149 phbdmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000); 1150 } 1151 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index); 1152 ARCMSR_LOCK_RELEASE(&acb->postDone_lock); 1153 } 1154 break; 1155 case ACB_ADAPTER_TYPE_E: { 1156 u_int32_t ccb_post_stamp, arc_cdb_size; 1157 1158 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size; 1159 ccb_post_stamp = (srb->smid | ((arc_cdb_size-1) >> 6)); 1160 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_high, 0); 1161 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp); 1162 } 1163 break; 1164 case ACB_ADAPTER_TYPE_F: { 1165 u_int32_t ccb_post_stamp, arc_cdb_size; 1166 1167 if (srb->arc_cdb_size <= 0x300) 1168 arc_cdb_size = (srb->arc_cdb_size - 1) >> 6 | 1; 1169 else { 1170 arc_cdb_size = ((srb->arc_cdb_size + 0xff) >> 8) + 2; 1171 if (arc_cdb_size > 0xF) 1172 arc_cdb_size = 0xF; 1173 arc_cdb_size = (arc_cdb_size << 1) | 1; 1174 } 1175 ccb_post_stamp = (srb->smid | arc_cdb_size); 1176 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_high, 0); 1177 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp); 1178 } 1179 break; 1180 } 1181 } 1182 /* 1183 ************************************************************************ 1184 ************************************************************************ 1185 */ 1186 static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb) 1187 { 1188 struct QBUFFER *qbuffer=NULL; 1189 1190 switch (acb->adapter_type) { 1191 case ACB_ADAPTER_TYPE_A: { 1192 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1193 1194 qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer; 1195 } 1196 break; 1197 case ACB_ADAPTER_TYPE_B: { 1198 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1199 1200 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer; 1201 } 1202 break; 1203 case ACB_ADAPTER_TYPE_C: { 1204 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1205 1206 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer; 1207 } 1208 break; 1209 case ACB_ADAPTER_TYPE_D: { 1210 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1211 1212 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer; 1213 } 1214 break; 1215 case ACB_ADAPTER_TYPE_E: { 1216 struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu; 1217 1218 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer; 1219 } 1220 break; 1221 case ACB_ADAPTER_TYPE_F: 1222 qbuffer = (struct QBUFFER *)acb->message_rbuffer; 1223 break; 1224 } 1225 return(qbuffer); 1226 } 1227 /* 1228 ************************************************************************ 1229 ************************************************************************ 1230 */ 1231 static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb) 1232 { 1233 struct QBUFFER *qbuffer = NULL; 1234 1235 switch (acb->adapter_type) { 1236 case ACB_ADAPTER_TYPE_A: { 1237 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1238 1239 qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer; 1240 } 1241 break; 1242 case ACB_ADAPTER_TYPE_B: { 1243 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1244 1245 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer; 1246 } 1247 break; 1248 case ACB_ADAPTER_TYPE_C: { 1249 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1250 1251 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer; 1252 } 1253 break; 1254 case ACB_ADAPTER_TYPE_D: { 1255 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1256 1257 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer; 1258 } 1259 break; 1260 case ACB_ADAPTER_TYPE_E: { 1261 struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu; 1262 1263 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer; 1264 } 1265 break; 1266 case ACB_ADAPTER_TYPE_F: 1267 qbuffer = (struct QBUFFER *)acb->message_wbuffer; 1268 break; 1269 } 1270 return(qbuffer); 1271 } 1272 /* 1273 ************************************************************************** 1274 ************************************************************************** 1275 */ 1276 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb) 1277 { 1278 switch (acb->adapter_type) { 1279 case ACB_ADAPTER_TYPE_A: { 1280 /* let IOP know data has been read */ 1281 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 1282 } 1283 break; 1284 case ACB_ADAPTER_TYPE_B: { 1285 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1286 /* let IOP know data has been read */ 1287 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 1288 } 1289 break; 1290 case ACB_ADAPTER_TYPE_C: { 1291 /* let IOP know data has been read */ 1292 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 1293 } 1294 break; 1295 case ACB_ADAPTER_TYPE_D: { 1296 /* let IOP know data has been read */ 1297 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 1298 } 1299 break; 1300 case ACB_ADAPTER_TYPE_E: 1301 case ACB_ADAPTER_TYPE_F: { 1302 /* let IOP know data has been read */ 1303 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 1304 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 1305 } 1306 break; 1307 } 1308 } 1309 /* 1310 ************************************************************************** 1311 ************************************************************************** 1312 */ 1313 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb) 1314 { 1315 switch (acb->adapter_type) { 1316 case ACB_ADAPTER_TYPE_A: { 1317 /* 1318 ** push inbound doorbell tell iop, driver data write ok 1319 ** and wait reply on next hwinterrupt for next Qbuffer post 1320 */ 1321 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK); 1322 } 1323 break; 1324 case ACB_ADAPTER_TYPE_B: { 1325 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1326 /* 1327 ** push inbound doorbell tell iop, driver data write ok 1328 ** and wait reply on next hwinterrupt for next Qbuffer post 1329 */ 1330 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK); 1331 } 1332 break; 1333 case ACB_ADAPTER_TYPE_C: { 1334 /* 1335 ** push inbound doorbell tell iop, driver data write ok 1336 ** and wait reply on next hwinterrupt for next Qbuffer post 1337 */ 1338 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK); 1339 } 1340 break; 1341 case ACB_ADAPTER_TYPE_D: { 1342 /* 1343 ** push inbound doorbell tell iop, driver data write ok 1344 ** and wait reply on next hwinterrupt for next Qbuffer post 1345 */ 1346 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY); 1347 } 1348 break; 1349 case ACB_ADAPTER_TYPE_E: 1350 case ACB_ADAPTER_TYPE_F: { 1351 /* 1352 ** push inbound doorbell tell iop, driver data write ok 1353 ** and wait reply on next hwinterrupt for next Qbuffer post 1354 */ 1355 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK; 1356 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 1357 } 1358 break; 1359 } 1360 } 1361 /* 1362 ************************************************************************ 1363 ************************************************************************ 1364 */ 1365 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb) 1366 { 1367 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1368 CHIP_REG_WRITE32(HBA_MessageUnit, 1369 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1370 if(!arcmsr_hba_wait_msgint_ready(acb)) { 1371 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1372 , acb->pci_unit); 1373 } 1374 } 1375 /* 1376 ************************************************************************ 1377 ************************************************************************ 1378 */ 1379 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb) 1380 { 1381 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1382 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1383 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB); 1384 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 1385 printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1386 , acb->pci_unit); 1387 } 1388 } 1389 /* 1390 ************************************************************************ 1391 ************************************************************************ 1392 */ 1393 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb) 1394 { 1395 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1396 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1397 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 1398 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 1399 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1400 } 1401 } 1402 /* 1403 ************************************************************************ 1404 ************************************************************************ 1405 */ 1406 static void arcmsr_stop_hbd_bgrb(struct AdapterControlBlock *acb) 1407 { 1408 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1409 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1410 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 1411 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1412 } 1413 } 1414 /* 1415 ************************************************************************ 1416 ************************************************************************ 1417 */ 1418 static void arcmsr_stop_hbe_bgrb(struct AdapterControlBlock *acb) 1419 { 1420 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1421 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1422 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 1423 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 1424 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 1425 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1426 } 1427 } 1428 /* 1429 ************************************************************************ 1430 ************************************************************************ 1431 */ 1432 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb) 1433 { 1434 switch (acb->adapter_type) { 1435 case ACB_ADAPTER_TYPE_A: { 1436 arcmsr_stop_hba_bgrb(acb); 1437 } 1438 break; 1439 case ACB_ADAPTER_TYPE_B: { 1440 arcmsr_stop_hbb_bgrb(acb); 1441 } 1442 break; 1443 case ACB_ADAPTER_TYPE_C: { 1444 arcmsr_stop_hbc_bgrb(acb); 1445 } 1446 break; 1447 case ACB_ADAPTER_TYPE_D: { 1448 arcmsr_stop_hbd_bgrb(acb); 1449 } 1450 break; 1451 case ACB_ADAPTER_TYPE_E: 1452 case ACB_ADAPTER_TYPE_F: { 1453 arcmsr_stop_hbe_bgrb(acb); 1454 } 1455 break; 1456 } 1457 } 1458 /* 1459 ************************************************************************ 1460 ************************************************************************ 1461 */ 1462 static void arcmsr_poll(struct cam_sim *psim) 1463 { 1464 struct AdapterControlBlock *acb; 1465 int mutex; 1466 1467 acb = (struct AdapterControlBlock *)cam_sim_softc(psim); 1468 mutex = mtx_owned(&acb->isr_lock); 1469 if( mutex == 0 ) 1470 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 1471 arcmsr_interrupt(acb); 1472 if( mutex == 0 ) 1473 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 1474 } 1475 /* 1476 ************************************************************************** 1477 ************************************************************************** 1478 */ 1479 static u_int32_t arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock *acb, 1480 struct QBUFFER *prbuffer) { 1481 u_int8_t *pQbuffer; 1482 u_int8_t *buf1 = NULL; 1483 u_int32_t *iop_data, *buf2 = NULL; 1484 u_int32_t iop_len, data_len; 1485 1486 iop_data = (u_int32_t *)prbuffer->data; 1487 iop_len = (u_int32_t)prbuffer->data_len; 1488 if ( iop_len > 0 ) 1489 { 1490 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO); 1491 buf2 = (u_int32_t *)buf1; 1492 if( buf1 == NULL) 1493 return (0); 1494 data_len = iop_len; 1495 while(data_len >= 4) 1496 { 1497 *buf2++ = *iop_data++; 1498 data_len -= 4; 1499 } 1500 if(data_len) 1501 *buf2 = *iop_data; 1502 buf2 = (u_int32_t *)buf1; 1503 } 1504 while (iop_len > 0) { 1505 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1506 *pQbuffer = *buf1; 1507 acb->rqbuf_lastindex++; 1508 /* if last, index number set it to 0 */ 1509 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1510 buf1++; 1511 iop_len--; 1512 } 1513 if(buf2) 1514 free( (u_int8_t *)buf2, M_DEVBUF); 1515 /* let IOP know data has been read */ 1516 arcmsr_iop_message_read(acb); 1517 return (1); 1518 } 1519 /* 1520 ************************************************************************** 1521 ************************************************************************** 1522 */ 1523 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, 1524 struct QBUFFER *prbuffer) { 1525 u_int8_t *pQbuffer; 1526 u_int8_t *iop_data; 1527 u_int32_t iop_len; 1528 1529 if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) { 1530 return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer)); 1531 } 1532 iop_data = (u_int8_t *)prbuffer->data; 1533 iop_len = (u_int32_t)prbuffer->data_len; 1534 while (iop_len > 0) { 1535 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1536 *pQbuffer = *iop_data; 1537 acb->rqbuf_lastindex++; 1538 /* if last, index number set it to 0 */ 1539 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1540 iop_data++; 1541 iop_len--; 1542 } 1543 /* let IOP know data has been read */ 1544 arcmsr_iop_message_read(acb); 1545 return (1); 1546 } 1547 /* 1548 ************************************************************************** 1549 ************************************************************************** 1550 */ 1551 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb) 1552 { 1553 struct QBUFFER *prbuffer; 1554 int my_empty_len; 1555 1556 /*check this iop data if overflow my rqbuffer*/ 1557 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1558 prbuffer = arcmsr_get_iop_rqbuffer(acb); 1559 if (acb->rqbuf_lastindex >= acb->rqbuf_firstindex) 1560 my_empty_len = (ARCMSR_MAX_QBUFFER - 1) - (acb->rqbuf_lastindex - acb->rqbuf_firstindex); 1561 else 1562 my_empty_len = acb->rqbuf_firstindex - acb->rqbuf_lastindex - 1; 1563 if(my_empty_len >= prbuffer->data_len) { 1564 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 1565 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1566 } else { 1567 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1568 } 1569 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1570 } 1571 /* 1572 ********************************************************************** 1573 ********************************************************************** 1574 */ 1575 static void arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock *acb) 1576 { 1577 u_int8_t *pQbuffer; 1578 struct QBUFFER *pwbuffer; 1579 u_int8_t *buf1 = NULL; 1580 u_int32_t *iop_data, *buf2 = NULL; 1581 u_int32_t allxfer_len = 0, data_len; 1582 1583 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1584 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO); 1585 buf2 = (u_int32_t *)buf1; 1586 if( buf1 == NULL) 1587 return; 1588 1589 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1590 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1591 iop_data = (u_int32_t *)pwbuffer->data; 1592 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1593 && (allxfer_len < 124)) { 1594 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1595 *buf1 = *pQbuffer; 1596 acb->wqbuf_firstindex++; 1597 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1598 buf1++; 1599 allxfer_len++; 1600 } 1601 pwbuffer->data_len = allxfer_len; 1602 data_len = allxfer_len; 1603 buf1 = (u_int8_t *)buf2; 1604 while(data_len >= 4) 1605 { 1606 *iop_data++ = *buf2++; 1607 data_len -= 4; 1608 } 1609 if(data_len) 1610 *iop_data = *buf2; 1611 free( buf1, M_DEVBUF); 1612 arcmsr_iop_message_wrote(acb); 1613 } 1614 } 1615 /* 1616 ********************************************************************** 1617 ********************************************************************** 1618 */ 1619 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb) 1620 { 1621 u_int8_t *pQbuffer; 1622 struct QBUFFER *pwbuffer; 1623 u_int8_t *iop_data; 1624 int32_t allxfer_len=0; 1625 1626 if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) { 1627 arcmsr_Write_data_2iop_wqbuffer_D(acb); 1628 return; 1629 } 1630 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1631 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1632 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1633 iop_data = (u_int8_t *)pwbuffer->data; 1634 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1635 && (allxfer_len < 124)) { 1636 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1637 *iop_data = *pQbuffer; 1638 acb->wqbuf_firstindex++; 1639 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1640 iop_data++; 1641 allxfer_len++; 1642 } 1643 pwbuffer->data_len = allxfer_len; 1644 arcmsr_iop_message_wrote(acb); 1645 } 1646 } 1647 /* 1648 ************************************************************************** 1649 ************************************************************************** 1650 */ 1651 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb) 1652 { 1653 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1654 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ; 1655 /* 1656 ***************************************************************** 1657 ** check if there are any mail packages from user space program 1658 ** in my post bag, now is the time to send them into Areca's firmware 1659 ***************************************************************** 1660 */ 1661 if(acb->wqbuf_firstindex != acb->wqbuf_lastindex) { 1662 arcmsr_Write_data_2iop_wqbuffer(acb); 1663 } 1664 if(acb->wqbuf_firstindex == acb->wqbuf_lastindex) { 1665 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED; 1666 } 1667 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1668 } 1669 /* 1670 ************************************************************************** 1671 ************************************************************************** 1672 */ 1673 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb) 1674 { 1675 /* 1676 if (ccb->ccb_h.status != CAM_REQ_CMP) 1677 printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x," 1678 "failure status=%x\n", ccb->ccb_h.target_id, 1679 ccb->ccb_h.target_lun, ccb->ccb_h.status); 1680 else 1681 printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n"); 1682 */ 1683 xpt_free_path(ccb->ccb_h.path); 1684 xpt_free_ccb(ccb); 1685 } 1686 1687 static void arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun) 1688 { 1689 struct cam_path *path; 1690 union ccb *ccb; 1691 1692 if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL) 1693 return; 1694 if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP) 1695 { 1696 xpt_free_ccb(ccb); 1697 return; 1698 } 1699 /* printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */ 1700 xpt_setup_ccb(&ccb->ccb_h, path, 5); 1701 ccb->ccb_h.func_code = XPT_SCAN_LUN; 1702 ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb; 1703 ccb->crcn.flags = CAM_FLAG_NONE; 1704 xpt_action(ccb); 1705 } 1706 1707 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun) 1708 { 1709 struct CommandControlBlock *srb; 1710 u_int32_t intmask_org; 1711 int i; 1712 1713 /* disable all outbound interrupts */ 1714 intmask_org = arcmsr_disable_allintr(acb); 1715 for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++) 1716 { 1717 srb = acb->psrb_pool[i]; 1718 if (srb->srb_state == ARCMSR_SRB_START) 1719 { 1720 if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun)) 1721 { 1722 srb->srb_state = ARCMSR_SRB_ABORTED; 1723 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 1724 arcmsr_srb_complete(srb, 1); 1725 printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb); 1726 } 1727 } 1728 } 1729 /* enable outbound Post Queue, outbound doorbell Interrupt */ 1730 arcmsr_enable_allintr(acb, intmask_org); 1731 } 1732 /* 1733 ************************************************************************** 1734 ************************************************************************** 1735 */ 1736 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) { 1737 u_int32_t devicemap; 1738 u_int32_t target, lun; 1739 u_int32_t deviceMapCurrent[4]={0}; 1740 u_int8_t *pDevMap; 1741 1742 switch (acb->adapter_type) { 1743 case ACB_ADAPTER_TYPE_A: 1744 devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1745 for (target = 0; target < 4; target++) 1746 { 1747 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1748 devicemap += 4; 1749 } 1750 break; 1751 1752 case ACB_ADAPTER_TYPE_B: 1753 devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1754 for (target = 0; target < 4; target++) 1755 { 1756 deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1], devicemap); 1757 devicemap += 4; 1758 } 1759 break; 1760 1761 case ACB_ADAPTER_TYPE_C: 1762 devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1763 for (target = 0; target < 4; target++) 1764 { 1765 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1766 devicemap += 4; 1767 } 1768 break; 1769 case ACB_ADAPTER_TYPE_D: 1770 devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1771 for (target = 0; target < 4; target++) 1772 { 1773 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1774 devicemap += 4; 1775 } 1776 break; 1777 case ACB_ADAPTER_TYPE_E: 1778 devicemap = offsetof(struct HBE_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1779 for (target = 0; target < 4; target++) 1780 { 1781 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1782 devicemap += 4; 1783 } 1784 break; 1785 case ACB_ADAPTER_TYPE_F: 1786 devicemap = ARCMSR_FW_DEVMAP_OFFSET; 1787 for (target = 0; target < 4; target++) 1788 { 1789 deviceMapCurrent[target] = acb->msgcode_rwbuffer[devicemap]; 1790 devicemap += 1; 1791 } 1792 break; 1793 } 1794 1795 if(acb->acb_flags & ACB_F_BUS_HANG_ON) 1796 { 1797 acb->acb_flags &= ~ACB_F_BUS_HANG_ON; 1798 } 1799 /* 1800 ** adapter posted CONFIG message 1801 ** copy the new map, note if there are differences with the current map 1802 */ 1803 pDevMap = (u_int8_t *)&deviceMapCurrent[0]; 1804 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++) 1805 { 1806 if (*pDevMap != acb->device_map[target]) 1807 { 1808 u_int8_t difference, bit_check; 1809 1810 difference = *pDevMap ^ acb->device_map[target]; 1811 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++) 1812 { 1813 bit_check = (1 << lun); /*check bit from 0....31*/ 1814 if(difference & bit_check) 1815 { 1816 if(acb->device_map[target] & bit_check) 1817 {/* unit departed */ 1818 printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun); 1819 arcmsr_abort_dr_ccbs(acb, target, lun); 1820 arcmsr_rescan_lun(acb, target, lun); 1821 acb->devstate[target][lun] = ARECA_RAID_GONE; 1822 } 1823 else 1824 {/* unit arrived */ 1825 printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun); 1826 arcmsr_rescan_lun(acb, target, lun); 1827 acb->devstate[target][lun] = ARECA_RAID_GOOD; 1828 } 1829 } 1830 } 1831 /* printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */ 1832 acb->device_map[target] = *pDevMap; 1833 } 1834 pDevMap++; 1835 } 1836 } 1837 /* 1838 ************************************************************************** 1839 ************************************************************************** 1840 */ 1841 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) { 1842 u_int32_t outbound_message; 1843 1844 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT); 1845 outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]); 1846 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1847 arcmsr_dr_handle( acb ); 1848 } 1849 /* 1850 ************************************************************************** 1851 ************************************************************************** 1852 */ 1853 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) { 1854 u_int32_t outbound_message; 1855 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1856 1857 /* clear interrupts */ 1858 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN); 1859 outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]); 1860 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1861 arcmsr_dr_handle( acb ); 1862 } 1863 /* 1864 ************************************************************************** 1865 ************************************************************************** 1866 */ 1867 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) { 1868 u_int32_t outbound_message; 1869 1870 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR); 1871 outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]); 1872 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1873 arcmsr_dr_handle( acb ); 1874 } 1875 /* 1876 ************************************************************************** 1877 ************************************************************************** 1878 */ 1879 static void arcmsr_hbd_message_isr(struct AdapterControlBlock *acb) { 1880 u_int32_t outbound_message; 1881 1882 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 1883 outbound_message = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[0]); 1884 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1885 arcmsr_dr_handle( acb ); 1886 } 1887 /* 1888 ************************************************************************** 1889 ************************************************************************** 1890 */ 1891 static void arcmsr_hbe_message_isr(struct AdapterControlBlock *acb) { 1892 u_int32_t outbound_message; 1893 1894 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); 1895 if (acb->adapter_type == ACB_ADAPTER_TYPE_E) 1896 outbound_message = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[0]); 1897 else 1898 outbound_message = acb->msgcode_rwbuffer[0]; 1899 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1900 arcmsr_dr_handle( acb ); 1901 } 1902 /* 1903 ************************************************************************** 1904 ************************************************************************** 1905 */ 1906 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb) 1907 { 1908 u_int32_t doorbell_status; 1909 1910 /* 1911 ******************************************************************* 1912 ** Maybe here we need to check wrqbuffer_lock is lock or not 1913 ** DOORBELL: din! don! 1914 ** check if there are any mail need to pack from firmware 1915 ******************************************************************* 1916 */ 1917 doorbell_status = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell); 1918 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1919 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) { 1920 arcmsr_iop2drv_data_wrote_handle(acb); 1921 } 1922 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) { 1923 arcmsr_iop2drv_data_read_handle(acb); 1924 } 1925 } 1926 /* 1927 ************************************************************************** 1928 ************************************************************************** 1929 */ 1930 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb) 1931 { 1932 u_int32_t doorbell_status; 1933 1934 /* 1935 ******************************************************************* 1936 ** Maybe here we need to check wrqbuffer_lock is lock or not 1937 ** DOORBELL: din! don! 1938 ** check if there are any mail need to pack from firmware 1939 ******************************************************************* 1940 */ 1941 doorbell_status = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 1942 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, doorbell_status); /* clear doorbell interrupt */ 1943 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) { 1944 arcmsr_iop2drv_data_wrote_handle(acb); 1945 } 1946 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) { 1947 arcmsr_iop2drv_data_read_handle(acb); 1948 } 1949 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 1950 arcmsr_hbc_message_isr(acb); /* messenger of "driver to iop commands" */ 1951 } 1952 } 1953 /* 1954 ************************************************************************** 1955 ************************************************************************** 1956 */ 1957 static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb) 1958 { 1959 u_int32_t doorbell_status; 1960 1961 /* 1962 ******************************************************************* 1963 ** Maybe here we need to check wrqbuffer_lock is lock or not 1964 ** DOORBELL: din! don! 1965 ** check if there are any mail need to pack from firmware 1966 ******************************************************************* 1967 */ 1968 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 1969 if(doorbell_status) 1970 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1971 while( doorbell_status & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) { 1972 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) { 1973 arcmsr_iop2drv_data_wrote_handle(acb); 1974 } 1975 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) { 1976 arcmsr_iop2drv_data_read_handle(acb); 1977 } 1978 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 1979 arcmsr_hbd_message_isr(acb); /* messenger of "driver to iop commands" */ 1980 } 1981 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 1982 if(doorbell_status) 1983 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1984 } 1985 } 1986 /* 1987 ************************************************************************** 1988 ************************************************************************** 1989 */ 1990 static void arcmsr_hbe_doorbell_isr(struct AdapterControlBlock *acb) 1991 { 1992 u_int32_t doorbell_status, in_doorbell; 1993 1994 /* 1995 ******************************************************************* 1996 ** Maybe here we need to check wrqbuffer_lock is lock or not 1997 ** DOORBELL: din! don! 1998 ** check if there are any mail need to pack from firmware 1999 ******************************************************************* 2000 */ 2001 in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 2002 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /* clear doorbell interrupt */ 2003 doorbell_status = in_doorbell ^ acb->in_doorbell; 2004 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) { 2005 arcmsr_iop2drv_data_wrote_handle(acb); 2006 } 2007 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) { 2008 arcmsr_iop2drv_data_read_handle(acb); 2009 } 2010 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 2011 arcmsr_hbe_message_isr(acb); /* messenger of "driver to iop commands" */ 2012 } 2013 acb->in_doorbell = in_doorbell; 2014 } 2015 /* 2016 ************************************************************************** 2017 ************************************************************************** 2018 */ 2019 static void arcmsr_hbf_doorbell_isr(struct AdapterControlBlock *acb) 2020 { 2021 u_int32_t doorbell_status, in_doorbell; 2022 2023 /* 2024 ******************************************************************* 2025 ** Maybe here we need to check wrqbuffer_lock is lock or not 2026 ** DOORBELL: din! don! 2027 ** check if there are any mail need to pack from firmware 2028 ******************************************************************* 2029 */ 2030 while(1) { 2031 in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 2032 if ((in_doorbell != 0) && (in_doorbell != 0xFFFFFFFF)) 2033 break; 2034 } 2035 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /* clear doorbell interrupt */ 2036 doorbell_status = in_doorbell ^ acb->in_doorbell; 2037 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) { 2038 arcmsr_iop2drv_data_wrote_handle(acb); 2039 } 2040 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) { 2041 arcmsr_iop2drv_data_read_handle(acb); 2042 } 2043 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 2044 arcmsr_hbe_message_isr(acb); /* messenger of "driver to iop commands" */ 2045 } 2046 acb->in_doorbell = in_doorbell; 2047 } 2048 /* 2049 ************************************************************************** 2050 ************************************************************************** 2051 */ 2052 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb) 2053 { 2054 u_int32_t flag_srb; 2055 u_int16_t error; 2056 2057 /* 2058 ***************************************************************************** 2059 ** areca cdb command done 2060 ***************************************************************************** 2061 */ 2062 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 2063 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2064 while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 2065 0, outbound_queueport)) != 0xFFFFFFFF) { 2066 /* check if command done with no error*/ 2067 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE; 2068 arcmsr_drain_donequeue(acb, flag_srb, error); 2069 } /*drain reply FIFO*/ 2070 } 2071 /* 2072 ************************************************************************** 2073 ************************************************************************** 2074 */ 2075 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb) 2076 { 2077 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2078 u_int32_t flag_srb; 2079 int index; 2080 u_int16_t error; 2081 2082 /* 2083 ***************************************************************************** 2084 ** areca cdb command done 2085 ***************************************************************************** 2086 */ 2087 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 2088 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2089 index = phbbmu->doneq_index; 2090 while((flag_srb = phbbmu->done_qbuffer[index]) != 0) { 2091 phbbmu->done_qbuffer[index] = 0; 2092 index++; 2093 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 2094 phbbmu->doneq_index = index; 2095 /* check if command done with no error*/ 2096 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 2097 arcmsr_drain_donequeue(acb, flag_srb, error); 2098 } /*drain reply FIFO*/ 2099 } 2100 /* 2101 ************************************************************************** 2102 ************************************************************************** 2103 */ 2104 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb) 2105 { 2106 u_int32_t flag_srb,throttling = 0; 2107 u_int16_t error; 2108 2109 /* 2110 ***************************************************************************** 2111 ** areca cdb command done 2112 ***************************************************************************** 2113 */ 2114 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2115 do { 2116 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 2117 if (flag_srb == 0xFFFFFFFF) 2118 break; 2119 /* check if command done with no error*/ 2120 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 2121 arcmsr_drain_donequeue(acb, flag_srb, error); 2122 throttling++; 2123 if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) { 2124 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING); 2125 throttling = 0; 2126 } 2127 } while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR); 2128 } 2129 /* 2130 ********************************************************************** 2131 ** 2132 ********************************************************************** 2133 */ 2134 static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu) 2135 { 2136 uint16_t doneq_index, index_stripped; 2137 2138 doneq_index = phbdmu->doneq_index; 2139 if (doneq_index & 0x4000) { 2140 index_stripped = doneq_index & 0xFF; 2141 index_stripped += 1; 2142 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 2143 phbdmu->doneq_index = index_stripped ? 2144 (index_stripped | 0x4000) : index_stripped; 2145 } else { 2146 index_stripped = doneq_index; 2147 index_stripped += 1; 2148 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 2149 phbdmu->doneq_index = index_stripped ? 2150 index_stripped : (index_stripped | 0x4000); 2151 } 2152 return (phbdmu->doneq_index); 2153 } 2154 /* 2155 ************************************************************************** 2156 ************************************************************************** 2157 */ 2158 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb) 2159 { 2160 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 2161 u_int32_t outbound_write_pointer; 2162 u_int32_t addressLow; 2163 uint16_t doneq_index; 2164 u_int16_t error; 2165 /* 2166 ***************************************************************************** 2167 ** areca cdb command done 2168 ***************************************************************************** 2169 */ 2170 if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) & 2171 ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0) 2172 return; 2173 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 2174 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2175 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 2176 doneq_index = phbdmu->doneq_index; 2177 while ((doneq_index & 0xFF) != (outbound_write_pointer & 0xFF)) { 2178 doneq_index = arcmsr_get_doneq_index(phbdmu); 2179 addressLow = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 2180 error = (addressLow & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2181 arcmsr_drain_donequeue(acb, addressLow, error); /*Check if command done with no error */ 2182 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 2183 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 2184 } 2185 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR); 2186 CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */ 2187 } 2188 /* 2189 ************************************************************************** 2190 ************************************************************************** 2191 */ 2192 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb) 2193 { 2194 u_int16_t error; 2195 uint32_t doneq_index; 2196 uint16_t cmdSMID; 2197 2198 /* 2199 ***************************************************************************** 2200 ** areca cdb command done 2201 ***************************************************************************** 2202 */ 2203 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2204 doneq_index = acb->doneq_index; 2205 while ((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) != doneq_index) { 2206 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 2207 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2208 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error); 2209 doneq_index++; 2210 if (doneq_index >= acb->completionQ_entry) 2211 doneq_index = 0; 2212 } 2213 acb->doneq_index = doneq_index; 2214 CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_consumer_index, doneq_index); 2215 } 2216 2217 static void arcmsr_hbf_postqueue_isr(struct AdapterControlBlock *acb) 2218 { 2219 uint16_t error; 2220 uint32_t doneq_index; 2221 uint16_t cmdSMID; 2222 2223 /* 2224 ***************************************************************************** 2225 ** areca cdb command done 2226 ***************************************************************************** 2227 */ 2228 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2229 doneq_index = acb->doneq_index; 2230 while (1) { 2231 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 2232 if (cmdSMID == 0xffff) 2233 break; 2234 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2235 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error); 2236 acb->pCompletionQ[doneq_index].cmdSMID = 0xffff; 2237 doneq_index++; 2238 if (doneq_index >= acb->completionQ_entry) 2239 doneq_index = 0; 2240 } 2241 acb->doneq_index = doneq_index; 2242 CHIP_REG_WRITE32(HBF_MessageUnit, 0, reply_post_consumer_index, doneq_index); 2243 } 2244 2245 /* 2246 ********************************************************************** 2247 ********************************************************************** 2248 */ 2249 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb) 2250 { 2251 u_int32_t outbound_intStatus; 2252 /* 2253 ********************************************* 2254 ** check outbound intstatus 2255 ********************************************* 2256 */ 2257 outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 2258 if(!outbound_intStatus) { 2259 /*it must be share irq*/ 2260 return; 2261 } 2262 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/ 2263 /* MU doorbell interrupts*/ 2264 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) { 2265 arcmsr_hba_doorbell_isr(acb); 2266 } 2267 /* MU post queue interrupts*/ 2268 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) { 2269 arcmsr_hba_postqueue_isr(acb); 2270 } 2271 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 2272 arcmsr_hba_message_isr(acb); 2273 } 2274 } 2275 /* 2276 ********************************************************************** 2277 ********************************************************************** 2278 */ 2279 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb) 2280 { 2281 u_int32_t outbound_doorbell; 2282 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2283 /* 2284 ********************************************* 2285 ** check outbound intstatus 2286 ********************************************* 2287 */ 2288 outbound_doorbell = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & acb->outbound_int_enable; 2289 if(!outbound_doorbell) { 2290 /*it must be share irq*/ 2291 return; 2292 } 2293 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */ 2294 READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell); 2295 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 2296 /* MU ioctl transfer doorbell interrupts*/ 2297 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) { 2298 arcmsr_iop2drv_data_wrote_handle(acb); 2299 } 2300 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) { 2301 arcmsr_iop2drv_data_read_handle(acb); 2302 } 2303 /* MU post queue interrupts*/ 2304 if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) { 2305 arcmsr_hbb_postqueue_isr(acb); 2306 } 2307 if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 2308 arcmsr_hbb_message_isr(acb); 2309 } 2310 } 2311 /* 2312 ********************************************************************** 2313 ********************************************************************** 2314 */ 2315 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb) 2316 { 2317 u_int32_t host_interrupt_status; 2318 /* 2319 ********************************************* 2320 ** check outbound intstatus 2321 ********************************************* 2322 */ 2323 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & 2324 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | 2325 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR); 2326 if(!host_interrupt_status) { 2327 /*it must be share irq*/ 2328 return; 2329 } 2330 do { 2331 /* MU doorbell interrupts*/ 2332 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) { 2333 arcmsr_hbc_doorbell_isr(acb); 2334 } 2335 /* MU post queue interrupts*/ 2336 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) { 2337 arcmsr_hbc_postqueue_isr(acb); 2338 } 2339 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status); 2340 } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR)); 2341 } 2342 /* 2343 ********************************************************************** 2344 ********************************************************************** 2345 */ 2346 static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb) 2347 { 2348 u_int32_t host_interrupt_status; 2349 u_int32_t intmask_org; 2350 /* 2351 ********************************************* 2352 ** check outbound intstatus 2353 ********************************************* 2354 */ 2355 host_interrupt_status = CHIP_REG_READ32(HBD_MessageUnit, 0, host_int_status) & acb->outbound_int_enable; 2356 if(!(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_INT)) { 2357 /*it must be share irq*/ 2358 return; 2359 } 2360 /* disable outbound interrupt */ 2361 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */ 2362 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 2363 /* MU doorbell interrupts*/ 2364 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT) { 2365 arcmsr_hbd_doorbell_isr(acb); 2366 } 2367 /* MU post queue interrupts*/ 2368 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT) { 2369 arcmsr_hbd_postqueue_isr(acb); 2370 } 2371 /* enable all outbound interrupt */ 2372 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE); 2373 // CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 2374 } 2375 /* 2376 ********************************************************************** 2377 ********************************************************************** 2378 */ 2379 static void arcmsr_handle_hbe_isr( struct AdapterControlBlock *acb) 2380 { 2381 u_int32_t host_interrupt_status; 2382 /* 2383 ********************************************* 2384 ** check outbound intstatus 2385 ********************************************* 2386 */ 2387 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status) & 2388 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | 2389 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR); 2390 if(!host_interrupt_status) { 2391 /*it must be share irq*/ 2392 return; 2393 } 2394 do { 2395 /* MU doorbell interrupts*/ 2396 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) { 2397 arcmsr_hbe_doorbell_isr(acb); 2398 } 2399 /* MU post queue interrupts*/ 2400 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) { 2401 arcmsr_hbe_postqueue_isr(acb); 2402 } 2403 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status); 2404 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR)); 2405 } 2406 2407 static void arcmsr_handle_hbf_isr( struct AdapterControlBlock *acb) 2408 { 2409 u_int32_t host_interrupt_status; 2410 /* 2411 ********************************************* 2412 ** check outbound intstatus 2413 ********************************************* 2414 */ 2415 host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status) & 2416 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | 2417 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR); 2418 if(!host_interrupt_status) { 2419 /*it must be share irq*/ 2420 return; 2421 } 2422 do { 2423 /* MU doorbell interrupts*/ 2424 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) { 2425 arcmsr_hbf_doorbell_isr(acb); 2426 } 2427 /* MU post queue interrupts*/ 2428 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) { 2429 arcmsr_hbf_postqueue_isr(acb); 2430 } 2431 host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status); 2432 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR)); 2433 } 2434 /* 2435 ****************************************************************************** 2436 ****************************************************************************** 2437 */ 2438 static void arcmsr_interrupt(struct AdapterControlBlock *acb) 2439 { 2440 switch (acb->adapter_type) { 2441 case ACB_ADAPTER_TYPE_A: 2442 arcmsr_handle_hba_isr(acb); 2443 break; 2444 case ACB_ADAPTER_TYPE_B: 2445 arcmsr_handle_hbb_isr(acb); 2446 break; 2447 case ACB_ADAPTER_TYPE_C: 2448 arcmsr_handle_hbc_isr(acb); 2449 break; 2450 case ACB_ADAPTER_TYPE_D: 2451 arcmsr_handle_hbd_isr(acb); 2452 break; 2453 case ACB_ADAPTER_TYPE_E: 2454 arcmsr_handle_hbe_isr(acb); 2455 break; 2456 case ACB_ADAPTER_TYPE_F: 2457 arcmsr_handle_hbf_isr(acb); 2458 break; 2459 default: 2460 printf("arcmsr%d: interrupt service," 2461 " unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type); 2462 break; 2463 } 2464 } 2465 /* 2466 ********************************************************************** 2467 ********************************************************************** 2468 */ 2469 static void arcmsr_intr_handler(void *arg) 2470 { 2471 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2472 2473 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 2474 arcmsr_interrupt(acb); 2475 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 2476 } 2477 /* 2478 ****************************************************************************** 2479 ****************************************************************************** 2480 */ 2481 static void arcmsr_polling_devmap(void *arg) 2482 { 2483 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2484 switch (acb->adapter_type) { 2485 case ACB_ADAPTER_TYPE_A: 2486 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2487 break; 2488 2489 case ACB_ADAPTER_TYPE_B: { 2490 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2491 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 2492 } 2493 break; 2494 2495 case ACB_ADAPTER_TYPE_C: 2496 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2497 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 2498 break; 2499 2500 case ACB_ADAPTER_TYPE_D: 2501 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2502 break; 2503 2504 case ACB_ADAPTER_TYPE_E: 2505 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2506 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 2507 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 2508 break; 2509 2510 case ACB_ADAPTER_TYPE_F: { 2511 u_int32_t outMsg1 = CHIP_REG_READ32(HBF_MessageUnit, 0, outbound_msgaddr1); 2512 if (!(outMsg1 & ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK) || 2513 (outMsg1 & ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE)) 2514 goto nxt6s; 2515 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2516 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 2517 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 2518 break; 2519 } 2520 } 2521 nxt6s: 2522 if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0) 2523 { 2524 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb); /* polling per 5 seconds */ 2525 } 2526 } 2527 2528 /* 2529 ******************************************************************************* 2530 ** 2531 ******************************************************************************* 2532 */ 2533 static void arcmsr_iop_parking(struct AdapterControlBlock *acb) 2534 { 2535 u_int32_t intmask_org; 2536 2537 if(acb != NULL) { 2538 /* stop adapter background rebuild */ 2539 if(acb->acb_flags & ACB_F_MSG_START_BGRB) { 2540 intmask_org = arcmsr_disable_allintr(acb); 2541 arcmsr_stop_adapter_bgrb(acb); 2542 arcmsr_flush_adapter_cache(acb); 2543 arcmsr_enable_allintr(acb, intmask_org); 2544 } 2545 } 2546 } 2547 /* 2548 *********************************************************************** 2549 ** 2550 ************************************************************************ 2551 */ 2552 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg) 2553 { 2554 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2555 u_int32_t retvalue = EINVAL; 2556 2557 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg; 2558 if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) { 2559 return retvalue; 2560 } 2561 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2562 switch(ioctl_cmd) { 2563 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2564 u_int8_t *pQbuffer; 2565 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2566 u_int32_t allxfer_len=0; 2567 2568 while((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2569 && (allxfer_len < 1031)) { 2570 /*copy READ QBUFFER to srb*/ 2571 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2572 *ptmpQbuffer = *pQbuffer; 2573 acb->rqbuf_firstindex++; 2574 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2575 /*if last index number set it to 0 */ 2576 ptmpQbuffer++; 2577 allxfer_len++; 2578 } 2579 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2580 struct QBUFFER *prbuffer; 2581 2582 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2583 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2584 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2585 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2586 } 2587 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2588 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2589 retvalue = ARCMSR_MESSAGE_SUCCESS; 2590 } 2591 break; 2592 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2593 u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2594 u_int8_t *pQbuffer; 2595 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2596 2597 user_len = pcmdmessagefld->cmdmessage.Length; 2598 /*check if data xfer length of this request will overflow my array qbuffer */ 2599 wqbuf_lastindex = acb->wqbuf_lastindex; 2600 wqbuf_firstindex = acb->wqbuf_firstindex; 2601 if(wqbuf_lastindex != wqbuf_firstindex) { 2602 arcmsr_Write_data_2iop_wqbuffer(acb); 2603 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2604 } else { 2605 my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) & 2606 (ARCMSR_MAX_QBUFFER - 1); 2607 if(my_empty_len >= user_len) { 2608 while(user_len > 0) { 2609 /*copy srb data to wqbuffer*/ 2610 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2611 *pQbuffer = *ptmpuserbuffer; 2612 acb->wqbuf_lastindex++; 2613 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2614 /*if last index number set it to 0 */ 2615 ptmpuserbuffer++; 2616 user_len--; 2617 } 2618 /*post fist Qbuffer*/ 2619 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2620 acb->acb_flags &= ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2621 arcmsr_Write_data_2iop_wqbuffer(acb); 2622 } 2623 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2624 } else { 2625 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2626 } 2627 } 2628 retvalue = ARCMSR_MESSAGE_SUCCESS; 2629 } 2630 break; 2631 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2632 u_int8_t *pQbuffer = acb->rqbuffer; 2633 2634 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2635 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2636 arcmsr_iop_message_read(acb); 2637 /*signature, let IOP know data has been readed */ 2638 } 2639 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2640 acb->rqbuf_firstindex = 0; 2641 acb->rqbuf_lastindex = 0; 2642 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2643 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2644 retvalue = ARCMSR_MESSAGE_SUCCESS; 2645 } 2646 break; 2647 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: 2648 { 2649 u_int8_t *pQbuffer = acb->wqbuffer; 2650 2651 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2652 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2653 arcmsr_iop_message_read(acb); 2654 /*signature, let IOP know data has been readed */ 2655 } 2656 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 2657 acb->wqbuf_firstindex = 0; 2658 acb->wqbuf_lastindex = 0; 2659 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2660 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2661 retvalue = ARCMSR_MESSAGE_SUCCESS; 2662 } 2663 break; 2664 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2665 u_int8_t *pQbuffer; 2666 2667 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2668 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2669 arcmsr_iop_message_read(acb); 2670 /*signature, let IOP know data has been readed */ 2671 } 2672 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED 2673 |ACB_F_MESSAGE_RQBUFFER_CLEARED 2674 |ACB_F_MESSAGE_WQBUFFER_READ); 2675 acb->rqbuf_firstindex = 0; 2676 acb->rqbuf_lastindex = 0; 2677 acb->wqbuf_firstindex = 0; 2678 acb->wqbuf_lastindex = 0; 2679 pQbuffer = acb->rqbuffer; 2680 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2681 pQbuffer = acb->wqbuffer; 2682 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2683 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2684 retvalue = ARCMSR_MESSAGE_SUCCESS; 2685 } 2686 break; 2687 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2688 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2689 retvalue = ARCMSR_MESSAGE_SUCCESS; 2690 } 2691 break; 2692 case ARCMSR_MESSAGE_SAY_HELLO: { 2693 u_int8_t *hello_string = "Hello! I am ARCMSR"; 2694 u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer; 2695 2696 if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) { 2697 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2698 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2699 return ENOIOCTL; 2700 } 2701 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2702 retvalue = ARCMSR_MESSAGE_SUCCESS; 2703 } 2704 break; 2705 case ARCMSR_MESSAGE_SAY_GOODBYE: { 2706 arcmsr_iop_parking(acb); 2707 retvalue = ARCMSR_MESSAGE_SUCCESS; 2708 } 2709 break; 2710 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: { 2711 arcmsr_flush_adapter_cache(acb); 2712 retvalue = ARCMSR_MESSAGE_SUCCESS; 2713 } 2714 break; 2715 } 2716 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2717 return (retvalue); 2718 } 2719 /* 2720 ************************************************************************** 2721 ************************************************************************** 2722 */ 2723 static void arcmsr_free_srb(struct CommandControlBlock *srb) 2724 { 2725 struct AdapterControlBlock *acb; 2726 2727 acb = srb->acb; 2728 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2729 srb->srb_state = ARCMSR_SRB_DONE; 2730 srb->srb_flags = 0; 2731 acb->srbworkingQ[acb->workingsrb_doneindex] = srb; 2732 acb->workingsrb_doneindex++; 2733 acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM; 2734 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2735 } 2736 /* 2737 ************************************************************************** 2738 ************************************************************************** 2739 */ 2740 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb) 2741 { 2742 struct CommandControlBlock *srb = NULL; 2743 u_int32_t workingsrb_startindex, workingsrb_doneindex; 2744 2745 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2746 workingsrb_doneindex = acb->workingsrb_doneindex; 2747 workingsrb_startindex = acb->workingsrb_startindex; 2748 srb = acb->srbworkingQ[workingsrb_startindex]; 2749 workingsrb_startindex++; 2750 workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM; 2751 if(workingsrb_doneindex != workingsrb_startindex) { 2752 acb->workingsrb_startindex = workingsrb_startindex; 2753 } else { 2754 srb = NULL; 2755 } 2756 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2757 return(srb); 2758 } 2759 /* 2760 ************************************************************************** 2761 ************************************************************************** 2762 */ 2763 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb) 2764 { 2765 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2766 int retvalue = 0, transfer_len = 0; 2767 char *buffer; 2768 uint8_t *ptr = scsiio_cdb_ptr(&pccb->csio); 2769 u_int32_t controlcode = (u_int32_t ) ptr[5] << 24 | 2770 (u_int32_t ) ptr[6] << 16 | 2771 (u_int32_t ) ptr[7] << 8 | 2772 (u_int32_t ) ptr[8]; 2773 /* 4 bytes: Areca io control code */ 2774 if ((pccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) { 2775 buffer = pccb->csio.data_ptr; 2776 transfer_len = pccb->csio.dxfer_len; 2777 } else { 2778 retvalue = ARCMSR_MESSAGE_FAIL; 2779 goto message_out; 2780 } 2781 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) { 2782 retvalue = ARCMSR_MESSAGE_FAIL; 2783 goto message_out; 2784 } 2785 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer; 2786 switch(controlcode) { 2787 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2788 u_int8_t *pQbuffer; 2789 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2790 int32_t allxfer_len = 0; 2791 2792 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2793 while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2794 && (allxfer_len < 1031)) { 2795 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2796 *ptmpQbuffer = *pQbuffer; 2797 acb->rqbuf_firstindex++; 2798 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2799 ptmpQbuffer++; 2800 allxfer_len++; 2801 } 2802 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2803 struct QBUFFER *prbuffer; 2804 2805 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2806 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2807 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2808 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2809 } 2810 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2811 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2812 retvalue = ARCMSR_MESSAGE_SUCCESS; 2813 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2814 } 2815 break; 2816 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2817 int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2818 u_int8_t *pQbuffer; 2819 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2820 2821 user_len = pcmdmessagefld->cmdmessage.Length; 2822 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2823 wqbuf_lastindex = acb->wqbuf_lastindex; 2824 wqbuf_firstindex = acb->wqbuf_firstindex; 2825 if (wqbuf_lastindex != wqbuf_firstindex) { 2826 arcmsr_Write_data_2iop_wqbuffer(acb); 2827 /* has error report sensedata */ 2828 if(pccb->csio.sense_len) { 2829 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2830 /* Valid,ErrorCode */ 2831 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2832 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2833 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2834 /* AdditionalSenseLength */ 2835 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2836 /* AdditionalSenseCode */ 2837 } 2838 retvalue = ARCMSR_MESSAGE_FAIL; 2839 } else { 2840 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1) 2841 &(ARCMSR_MAX_QBUFFER - 1); 2842 if (my_empty_len >= user_len) { 2843 while (user_len > 0) { 2844 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2845 *pQbuffer = *ptmpuserbuffer; 2846 acb->wqbuf_lastindex++; 2847 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2848 ptmpuserbuffer++; 2849 user_len--; 2850 } 2851 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2852 acb->acb_flags &= 2853 ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2854 arcmsr_Write_data_2iop_wqbuffer(acb); 2855 } 2856 } else { 2857 /* has error report sensedata */ 2858 if(pccb->csio.sense_len) { 2859 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2860 /* Valid,ErrorCode */ 2861 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2862 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2863 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2864 /* AdditionalSenseLength */ 2865 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2866 /* AdditionalSenseCode */ 2867 } 2868 retvalue = ARCMSR_MESSAGE_FAIL; 2869 } 2870 } 2871 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2872 } 2873 break; 2874 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2875 u_int8_t *pQbuffer = acb->rqbuffer; 2876 2877 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2878 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2879 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2880 arcmsr_iop_message_read(acb); 2881 } 2882 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2883 acb->rqbuf_firstindex = 0; 2884 acb->rqbuf_lastindex = 0; 2885 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2886 pcmdmessagefld->cmdmessage.ReturnCode = 2887 ARCMSR_MESSAGE_RETURNCODE_OK; 2888 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2889 } 2890 break; 2891 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: { 2892 u_int8_t *pQbuffer = acb->wqbuffer; 2893 2894 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2895 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2896 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2897 arcmsr_iop_message_read(acb); 2898 } 2899 acb->acb_flags |= 2900 (ACB_F_MESSAGE_WQBUFFER_CLEARED | 2901 ACB_F_MESSAGE_WQBUFFER_READ); 2902 acb->wqbuf_firstindex = 0; 2903 acb->wqbuf_lastindex = 0; 2904 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2905 pcmdmessagefld->cmdmessage.ReturnCode = 2906 ARCMSR_MESSAGE_RETURNCODE_OK; 2907 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2908 } 2909 break; 2910 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2911 u_int8_t *pQbuffer; 2912 2913 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2914 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2915 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2916 arcmsr_iop_message_read(acb); 2917 } 2918 acb->acb_flags |= 2919 (ACB_F_MESSAGE_WQBUFFER_CLEARED 2920 | ACB_F_MESSAGE_RQBUFFER_CLEARED 2921 | ACB_F_MESSAGE_WQBUFFER_READ); 2922 acb->rqbuf_firstindex = 0; 2923 acb->rqbuf_lastindex = 0; 2924 acb->wqbuf_firstindex = 0; 2925 acb->wqbuf_lastindex = 0; 2926 pQbuffer = acb->rqbuffer; 2927 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2928 pQbuffer = acb->wqbuffer; 2929 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2930 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2931 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2932 } 2933 break; 2934 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2935 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2936 } 2937 break; 2938 case ARCMSR_MESSAGE_SAY_HELLO: { 2939 int8_t *hello_string = "Hello! I am ARCMSR"; 2940 2941 memcpy(pcmdmessagefld->messagedatabuffer, hello_string 2942 , (int16_t)strlen(hello_string)); 2943 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2944 } 2945 break; 2946 case ARCMSR_MESSAGE_SAY_GOODBYE: 2947 arcmsr_iop_parking(acb); 2948 break; 2949 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: 2950 arcmsr_flush_adapter_cache(acb); 2951 break; 2952 default: 2953 retvalue = ARCMSR_MESSAGE_FAIL; 2954 } 2955 message_out: 2956 return (retvalue); 2957 } 2958 /* 2959 ********************************************************************* 2960 ********************************************************************* 2961 */ 2962 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 2963 { 2964 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 2965 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb; 2966 union ccb *pccb; 2967 int target, lun; 2968 2969 pccb = srb->pccb; 2970 target = pccb->ccb_h.target_id; 2971 lun = pccb->ccb_h.target_lun; 2972 acb->pktRequestCount++; 2973 if(error != 0) { 2974 if(error != EFBIG) { 2975 printf("arcmsr%d: unexpected error %x" 2976 " returned from 'bus_dmamap_load' \n" 2977 , acb->pci_unit, error); 2978 } 2979 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) { 2980 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2981 } 2982 arcmsr_srb_complete(srb, 0); 2983 return; 2984 } 2985 if(nseg > ARCMSR_MAX_SG_ENTRIES) { 2986 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2987 arcmsr_srb_complete(srb, 0); 2988 return; 2989 } 2990 if(acb->acb_flags & ACB_F_BUS_RESET) { 2991 printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit); 2992 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET; 2993 arcmsr_srb_complete(srb, 0); 2994 return; 2995 } 2996 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 2997 u_int8_t block_cmd, cmd; 2998 2999 cmd = scsiio_cdb_ptr(&pccb->csio)[0]; 3000 block_cmd = cmd & 0x0f; 3001 if(block_cmd == 0x08 || block_cmd == 0x0a) { 3002 printf("arcmsr%d:block 'read/write' command " 3003 "with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n" 3004 , acb->pci_unit, cmd, target, lun); 3005 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 3006 arcmsr_srb_complete(srb, 0); 3007 return; 3008 } 3009 } 3010 if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 3011 if(nseg != 0) { 3012 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 3013 } 3014 arcmsr_srb_complete(srb, 0); 3015 return; 3016 } 3017 if(acb->srboutstandingcount >= acb->maxOutstanding) { 3018 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0) 3019 { 3020 xpt_freeze_simq(acb->psim, 1); 3021 acb->acb_flags |= ACB_F_CAM_DEV_QFRZN; 3022 } 3023 pccb->ccb_h.status &= ~CAM_SIM_QUEUED; 3024 pccb->ccb_h.status |= CAM_REQUEUE_REQ; 3025 arcmsr_srb_complete(srb, 0); 3026 return; 3027 } 3028 pccb->ccb_h.status |= CAM_SIM_QUEUED; 3029 arcmsr_build_srb(srb, dm_segs, nseg); 3030 arcmsr_post_srb(acb, srb); 3031 if (pccb->ccb_h.timeout != CAM_TIME_INFINITY) 3032 { 3033 arcmsr_callout_init(&srb->ccb_callout); 3034 callout_reset_sbt(&srb->ccb_callout, SBT_1MS * 3035 (pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)), 0, 3036 arcmsr_srb_timeout, srb, 0); 3037 srb->srb_flags |= SRB_FLAG_TIMER_START; 3038 } 3039 } 3040 /* 3041 ***************************************************************************************** 3042 ***************************************************************************************** 3043 */ 3044 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb) 3045 { 3046 struct CommandControlBlock *srb; 3047 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr; 3048 u_int32_t intmask_org; 3049 int i = 0; 3050 3051 acb->num_aborts++; 3052 /* 3053 *************************************************************************** 3054 ** It is the upper layer do abort command this lock just prior to calling us. 3055 ** First determine if we currently own this command. 3056 ** Start by searching the device queue. If not found 3057 ** at all, and the system wanted us to just abort the 3058 ** command return success. 3059 *************************************************************************** 3060 */ 3061 if(acb->srboutstandingcount != 0) { 3062 /* disable all outbound interrupt */ 3063 intmask_org = arcmsr_disable_allintr(acb); 3064 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 3065 srb = acb->psrb_pool[i]; 3066 if(srb->srb_state == ARCMSR_SRB_START) { 3067 if(srb->pccb == abortccb) { 3068 srb->srb_state = ARCMSR_SRB_ABORTED; 3069 printf("arcmsr%d:scsi id=%d lun=%jx abort srb '%p'" 3070 "outstanding command \n" 3071 , acb->pci_unit, abortccb->ccb_h.target_id 3072 , (uintmax_t)abortccb->ccb_h.target_lun, srb); 3073 arcmsr_polling_srbdone(acb, srb); 3074 /* enable outbound Post Queue, outbound doorbell Interrupt */ 3075 arcmsr_enable_allintr(acb, intmask_org); 3076 return (TRUE); 3077 } 3078 } 3079 } 3080 /* enable outbound Post Queue, outbound doorbell Interrupt */ 3081 arcmsr_enable_allintr(acb, intmask_org); 3082 } 3083 return(FALSE); 3084 } 3085 /* 3086 **************************************************************************** 3087 **************************************************************************** 3088 */ 3089 static void arcmsr_bus_reset(struct AdapterControlBlock *acb) 3090 { 3091 int retry = 0; 3092 3093 acb->num_resets++; 3094 acb->acb_flags |= ACB_F_BUS_RESET; 3095 while(acb->srboutstandingcount != 0 && retry < 400) { 3096 arcmsr_interrupt(acb); 3097 UDELAY(25000); 3098 retry++; 3099 } 3100 arcmsr_iop_reset(acb); 3101 acb->acb_flags &= ~ACB_F_BUS_RESET; 3102 } 3103 /* 3104 ************************************************************************** 3105 ************************************************************************** 3106 */ 3107 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb, 3108 union ccb *pccb) 3109 { 3110 if (pccb->ccb_h.target_lun) { 3111 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 3112 xpt_done(pccb); 3113 return; 3114 } 3115 pccb->ccb_h.status |= CAM_REQ_CMP; 3116 switch (scsiio_cdb_ptr(&pccb->csio)[0]) { 3117 case INQUIRY: { 3118 unsigned char inqdata[36]; 3119 char *buffer = pccb->csio.data_ptr; 3120 3121 inqdata[0] = T_PROCESSOR; /* Periph Qualifier & Periph Dev Type */ 3122 inqdata[1] = 0; /* rem media bit & Dev Type Modifier */ 3123 inqdata[2] = 0; /* ISO, ECMA, & ANSI versions */ 3124 inqdata[3] = 0; 3125 inqdata[4] = 31; /* length of additional data */ 3126 inqdata[5] = 0; 3127 inqdata[6] = 0; 3128 inqdata[7] = 0; 3129 strncpy(&inqdata[8], "Areca ", 8); /* Vendor Identification */ 3130 strncpy(&inqdata[16], "RAID controller ", 16); /* Product Identification */ 3131 strncpy(&inqdata[32], "R001", 4); /* Product Revision */ 3132 memcpy(buffer, inqdata, sizeof(inqdata)); 3133 xpt_done(pccb); 3134 } 3135 break; 3136 case WRITE_BUFFER: 3137 case READ_BUFFER: { 3138 if (arcmsr_iop_message_xfer(acb, pccb)) { 3139 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 3140 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 3141 } 3142 xpt_done(pccb); 3143 } 3144 break; 3145 default: 3146 xpt_done(pccb); 3147 } 3148 } 3149 /* 3150 ********************************************************************* 3151 ********************************************************************* 3152 */ 3153 static void arcmsr_action(struct cam_sim *psim, union ccb *pccb) 3154 { 3155 struct AdapterControlBlock *acb; 3156 3157 acb = (struct AdapterControlBlock *) cam_sim_softc(psim); 3158 if(acb == NULL) { 3159 pccb->ccb_h.status |= CAM_REQ_INVALID; 3160 xpt_done(pccb); 3161 return; 3162 } 3163 switch (pccb->ccb_h.func_code) { 3164 case XPT_SCSI_IO: { 3165 struct CommandControlBlock *srb; 3166 int target = pccb->ccb_h.target_id; 3167 int error; 3168 3169 if (pccb->ccb_h.flags & CAM_CDB_PHYS) { 3170 pccb->ccb_h.status = CAM_REQ_INVALID; 3171 xpt_done(pccb); 3172 return; 3173 } 3174 3175 if(target == 16) { 3176 /* virtual device for iop message transfer */ 3177 arcmsr_handle_virtual_command(acb, pccb); 3178 return; 3179 } 3180 if((srb = arcmsr_get_freesrb(acb)) == NULL) { 3181 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL; 3182 xpt_done(pccb); 3183 return; 3184 } 3185 pccb->ccb_h.arcmsr_ccbsrb_ptr = srb; 3186 pccb->ccb_h.arcmsr_ccbacb_ptr = acb; 3187 srb->pccb = pccb; 3188 error = bus_dmamap_load_ccb(acb->dm_segs_dmat 3189 , srb->dm_segs_dmamap 3190 , pccb 3191 , arcmsr_execute_srb, srb, /*flags*/0); 3192 if(error == EINPROGRESS) { 3193 xpt_freeze_simq(acb->psim, 1); 3194 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 3195 } 3196 break; 3197 } 3198 case XPT_PATH_INQ: { 3199 struct ccb_pathinq *cpi = &pccb->cpi; 3200 3201 cpi->version_num = 1; 3202 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE; 3203 cpi->target_sprt = 0; 3204 cpi->hba_misc = 0; 3205 cpi->hba_eng_cnt = 0; 3206 cpi->max_target = ARCMSR_MAX_TARGETID; /* 0-16 */ 3207 cpi->max_lun = ARCMSR_MAX_TARGETLUN; /* 0-7 */ 3208 cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */ 3209 cpi->bus_id = cam_sim_bus(psim); 3210 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 3211 strlcpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN); 3212 strlcpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 3213 cpi->unit_number = cam_sim_unit(psim); 3214 if(acb->adapter_bus_speed == ACB_BUS_SPEED_12G) 3215 cpi->base_transfer_speed = 1200000; 3216 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3217 cpi->base_transfer_speed = 600000; 3218 else 3219 cpi->base_transfer_speed = 300000; 3220 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 3221 (acb->vendor_device_id == PCIDevVenIDARC1884) || 3222 (acb->vendor_device_id == PCIDevVenIDARC1680) || 3223 (acb->vendor_device_id == PCIDevVenIDARC1214)) 3224 { 3225 cpi->transport = XPORT_SAS; 3226 cpi->transport_version = 0; 3227 cpi->protocol_version = SCSI_REV_SPC2; 3228 } 3229 else 3230 { 3231 cpi->transport = XPORT_SPI; 3232 cpi->transport_version = 2; 3233 cpi->protocol_version = SCSI_REV_2; 3234 } 3235 cpi->protocol = PROTO_SCSI; 3236 cpi->ccb_h.status |= CAM_REQ_CMP; 3237 xpt_done(pccb); 3238 break; 3239 } 3240 case XPT_ABORT: { 3241 union ccb *pabort_ccb; 3242 3243 pabort_ccb = pccb->cab.abort_ccb; 3244 switch (pabort_ccb->ccb_h.func_code) { 3245 case XPT_ACCEPT_TARGET_IO: 3246 case XPT_CONT_TARGET_IO: 3247 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) { 3248 pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED; 3249 xpt_done(pabort_ccb); 3250 pccb->ccb_h.status |= CAM_REQ_CMP; 3251 } else { 3252 xpt_print_path(pabort_ccb->ccb_h.path); 3253 printf("Not found\n"); 3254 pccb->ccb_h.status |= CAM_PATH_INVALID; 3255 } 3256 break; 3257 case XPT_SCSI_IO: 3258 pccb->ccb_h.status |= CAM_UA_ABORT; 3259 break; 3260 default: 3261 pccb->ccb_h.status |= CAM_REQ_INVALID; 3262 break; 3263 } 3264 xpt_done(pccb); 3265 break; 3266 } 3267 case XPT_RESET_BUS: 3268 case XPT_RESET_DEV: { 3269 u_int32_t i; 3270 3271 arcmsr_bus_reset(acb); 3272 for (i=0; i < 500; i++) { 3273 DELAY(1000); 3274 } 3275 pccb->ccb_h.status |= CAM_REQ_CMP; 3276 xpt_done(pccb); 3277 break; 3278 } 3279 case XPT_TERM_IO: { 3280 pccb->ccb_h.status |= CAM_REQ_INVALID; 3281 xpt_done(pccb); 3282 break; 3283 } 3284 case XPT_GET_TRAN_SETTINGS: { 3285 struct ccb_trans_settings *cts; 3286 3287 if(pccb->ccb_h.target_id == 16) { 3288 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3289 xpt_done(pccb); 3290 break; 3291 } 3292 cts = &pccb->cts; 3293 { 3294 struct ccb_trans_settings_scsi *scsi; 3295 struct ccb_trans_settings_spi *spi; 3296 struct ccb_trans_settings_sas *sas; 3297 3298 scsi = &cts->proto_specific.scsi; 3299 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB; 3300 scsi->valid = CTS_SCSI_VALID_TQ; 3301 cts->protocol = PROTO_SCSI; 3302 3303 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 3304 (acb->vendor_device_id == PCIDevVenIDARC1884) || 3305 (acb->vendor_device_id == PCIDevVenIDARC1680) || 3306 (acb->vendor_device_id == PCIDevVenIDARC1214)) 3307 { 3308 cts->protocol_version = SCSI_REV_SPC2; 3309 cts->transport_version = 0; 3310 cts->transport = XPORT_SAS; 3311 sas = &cts->xport_specific.sas; 3312 sas->valid = CTS_SAS_VALID_SPEED; 3313 if (acb->adapter_bus_speed == ACB_BUS_SPEED_12G) 3314 sas->bitrate = 1200000; 3315 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3316 sas->bitrate = 600000; 3317 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_3G) 3318 sas->bitrate = 300000; 3319 } 3320 else 3321 { 3322 cts->protocol_version = SCSI_REV_2; 3323 cts->transport_version = 2; 3324 cts->transport = XPORT_SPI; 3325 spi = &cts->xport_specific.spi; 3326 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 3327 if (acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3328 spi->sync_period = 1; 3329 else 3330 spi->sync_period = 2; 3331 spi->sync_offset = 32; 3332 spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT; 3333 spi->valid = CTS_SPI_VALID_DISC 3334 | CTS_SPI_VALID_SYNC_RATE 3335 | CTS_SPI_VALID_SYNC_OFFSET 3336 | CTS_SPI_VALID_BUS_WIDTH; 3337 } 3338 } 3339 pccb->ccb_h.status |= CAM_REQ_CMP; 3340 xpt_done(pccb); 3341 break; 3342 } 3343 case XPT_SET_TRAN_SETTINGS: { 3344 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3345 xpt_done(pccb); 3346 break; 3347 } 3348 case XPT_CALC_GEOMETRY: 3349 if(pccb->ccb_h.target_id == 16) { 3350 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3351 xpt_done(pccb); 3352 break; 3353 } 3354 cam_calc_geometry(&pccb->ccg, 1); 3355 xpt_done(pccb); 3356 break; 3357 default: 3358 pccb->ccb_h.status |= CAM_REQ_INVALID; 3359 xpt_done(pccb); 3360 break; 3361 } 3362 } 3363 /* 3364 ********************************************************************** 3365 ********************************************************************** 3366 */ 3367 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb) 3368 { 3369 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3370 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3371 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3372 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3373 } 3374 } 3375 /* 3376 ********************************************************************** 3377 ********************************************************************** 3378 */ 3379 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb) 3380 { 3381 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3382 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3383 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_BGRB); 3384 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3385 printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3386 } 3387 } 3388 /* 3389 ********************************************************************** 3390 ********************************************************************** 3391 */ 3392 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb) 3393 { 3394 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3395 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3396 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3397 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3398 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3399 } 3400 } 3401 /* 3402 ********************************************************************** 3403 ********************************************************************** 3404 */ 3405 static void arcmsr_start_hbd_bgrb(struct AdapterControlBlock *acb) 3406 { 3407 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3408 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3409 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3410 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3411 } 3412 } 3413 /* 3414 ********************************************************************** 3415 ********************************************************************** 3416 */ 3417 static void arcmsr_start_hbe_bgrb(struct AdapterControlBlock *acb) 3418 { 3419 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3420 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3421 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3422 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 3423 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 3424 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3425 } 3426 } 3427 /* 3428 ********************************************************************** 3429 ********************************************************************** 3430 */ 3431 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb) 3432 { 3433 switch (acb->adapter_type) { 3434 case ACB_ADAPTER_TYPE_A: 3435 arcmsr_start_hba_bgrb(acb); 3436 break; 3437 case ACB_ADAPTER_TYPE_B: 3438 arcmsr_start_hbb_bgrb(acb); 3439 break; 3440 case ACB_ADAPTER_TYPE_C: 3441 arcmsr_start_hbc_bgrb(acb); 3442 break; 3443 case ACB_ADAPTER_TYPE_D: 3444 arcmsr_start_hbd_bgrb(acb); 3445 break; 3446 case ACB_ADAPTER_TYPE_E: 3447 case ACB_ADAPTER_TYPE_F: 3448 arcmsr_start_hbe_bgrb(acb); 3449 break; 3450 } 3451 } 3452 /* 3453 ********************************************************************** 3454 ** 3455 ********************************************************************** 3456 */ 3457 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3458 { 3459 struct CommandControlBlock *srb; 3460 u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0; 3461 u_int16_t error; 3462 3463 polling_ccb_retry: 3464 poll_count++; 3465 outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 3466 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus); /*clear interrupt*/ 3467 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3468 while(1) { 3469 if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 3470 0, outbound_queueport)) == 0xFFFFFFFF) { 3471 if(poll_srb_done) { 3472 break;/*chip FIFO no ccb for completion already*/ 3473 } else { 3474 UDELAY(25000); 3475 if ((poll_count > 100) && (poll_srb != NULL)) { 3476 break; 3477 } 3478 goto polling_ccb_retry; 3479 } 3480 } 3481 /* check if command done with no error*/ 3482 srb = (struct CommandControlBlock *) 3483 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3484 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3485 poll_srb_done = (srb == poll_srb) ? 1:0; 3486 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3487 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3488 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'" 3489 "poll command abort successfully \n" 3490 , acb->pci_unit 3491 , srb->pccb->ccb_h.target_id 3492 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3493 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3494 arcmsr_srb_complete(srb, 1); 3495 continue; 3496 } 3497 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3498 "srboutstandingcount=%d \n" 3499 , acb->pci_unit 3500 , srb, acb->srboutstandingcount); 3501 continue; 3502 } 3503 arcmsr_report_srb_state(acb, srb, error); 3504 } /*drain reply FIFO*/ 3505 } 3506 /* 3507 ********************************************************************** 3508 ** 3509 ********************************************************************** 3510 */ 3511 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3512 { 3513 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3514 struct CommandControlBlock *srb; 3515 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3516 int index; 3517 u_int16_t error; 3518 3519 polling_ccb_retry: 3520 poll_count++; 3521 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 3522 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3523 while(1) { 3524 index = phbbmu->doneq_index; 3525 if((flag_srb = phbbmu->done_qbuffer[index]) == 0) { 3526 if(poll_srb_done) { 3527 break;/*chip FIFO no ccb for completion already*/ 3528 } else { 3529 UDELAY(25000); 3530 if ((poll_count > 100) && (poll_srb != NULL)) { 3531 break; 3532 } 3533 goto polling_ccb_retry; 3534 } 3535 } 3536 phbbmu->done_qbuffer[index] = 0; 3537 index++; 3538 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 3539 phbbmu->doneq_index = index; 3540 /* check if command done with no error*/ 3541 srb = (struct CommandControlBlock *) 3542 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3543 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3544 poll_srb_done = (srb == poll_srb) ? 1:0; 3545 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3546 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3547 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'" 3548 "poll command abort successfully \n" 3549 , acb->pci_unit 3550 , srb->pccb->ccb_h.target_id 3551 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3552 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3553 arcmsr_srb_complete(srb, 1); 3554 continue; 3555 } 3556 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3557 "srboutstandingcount=%d \n" 3558 , acb->pci_unit 3559 , srb, acb->srboutstandingcount); 3560 continue; 3561 } 3562 arcmsr_report_srb_state(acb, srb, error); 3563 } /*drain reply FIFO*/ 3564 } 3565 /* 3566 ********************************************************************** 3567 ** 3568 ********************************************************************** 3569 */ 3570 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3571 { 3572 struct CommandControlBlock *srb; 3573 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3574 u_int16_t error; 3575 3576 polling_ccb_retry: 3577 poll_count++; 3578 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3579 while(1) { 3580 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) { 3581 if(poll_srb_done) { 3582 break;/*chip FIFO no ccb for completion already*/ 3583 } else { 3584 UDELAY(25000); 3585 if ((poll_count > 100) && (poll_srb != NULL)) { 3586 break; 3587 } 3588 if (acb->srboutstandingcount == 0) { 3589 break; 3590 } 3591 goto polling_ccb_retry; 3592 } 3593 } 3594 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 3595 /* check if command done with no error*/ 3596 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3597 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 3598 if (poll_srb != NULL) 3599 poll_srb_done = (srb == poll_srb) ? 1:0; 3600 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3601 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3602 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3603 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3604 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3605 arcmsr_srb_complete(srb, 1); 3606 continue; 3607 } 3608 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3609 , acb->pci_unit, srb, acb->srboutstandingcount); 3610 continue; 3611 } 3612 arcmsr_report_srb_state(acb, srb, error); 3613 } /*drain reply FIFO*/ 3614 } 3615 /* 3616 ********************************************************************** 3617 ** 3618 ********************************************************************** 3619 */ 3620 static void arcmsr_polling_hbd_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3621 { 3622 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 3623 struct CommandControlBlock *srb; 3624 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3625 u_int32_t outbound_write_pointer; 3626 u_int16_t error, doneq_index; 3627 3628 polling_ccb_retry: 3629 poll_count++; 3630 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3631 while(1) { 3632 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 3633 doneq_index = phbdmu->doneq_index; 3634 if ((outbound_write_pointer & 0xFF) == (doneq_index & 0xFF)) { 3635 if(poll_srb_done) { 3636 break;/*chip FIFO no ccb for completion already*/ 3637 } else { 3638 UDELAY(25000); 3639 if ((poll_count > 100) && (poll_srb != NULL)) { 3640 break; 3641 } 3642 if (acb->srboutstandingcount == 0) { 3643 break; 3644 } 3645 goto polling_ccb_retry; 3646 } 3647 } 3648 doneq_index = arcmsr_get_doneq_index(phbdmu); 3649 flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 3650 /* check if command done with no error*/ 3651 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3652 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 3653 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 3654 if (poll_srb != NULL) 3655 poll_srb_done = (srb == poll_srb) ? 1:0; 3656 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3657 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3658 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3659 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3660 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3661 arcmsr_srb_complete(srb, 1); 3662 continue; 3663 } 3664 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3665 , acb->pci_unit, srb, acb->srboutstandingcount); 3666 continue; 3667 } 3668 arcmsr_report_srb_state(acb, srb, error); 3669 } /*drain reply FIFO*/ 3670 } 3671 /* 3672 ********************************************************************** 3673 ** 3674 ********************************************************************** 3675 */ 3676 static void arcmsr_polling_hbe_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3677 { 3678 struct CommandControlBlock *srb; 3679 u_int32_t poll_srb_done=0, poll_count=0, doneq_index; 3680 u_int16_t error, cmdSMID; 3681 3682 polling_ccb_retry: 3683 poll_count++; 3684 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3685 while(1) { 3686 doneq_index = acb->doneq_index; 3687 if((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) == doneq_index) { 3688 if(poll_srb_done) { 3689 break;/*chip FIFO no ccb for completion already*/ 3690 } else { 3691 UDELAY(25000); 3692 if ((poll_count > 100) && (poll_srb != NULL)) { 3693 break; 3694 } 3695 if (acb->srboutstandingcount == 0) { 3696 break; 3697 } 3698 goto polling_ccb_retry; 3699 } 3700 } 3701 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 3702 doneq_index++; 3703 if (doneq_index >= acb->completionQ_entry) 3704 doneq_index = 0; 3705 acb->doneq_index = doneq_index; 3706 srb = acb->psrb_pool[cmdSMID]; 3707 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 3708 if (poll_srb != NULL) 3709 poll_srb_done = (srb == poll_srb) ? 1:0; 3710 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3711 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3712 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3713 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3714 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3715 arcmsr_srb_complete(srb, 1); 3716 continue; 3717 } 3718 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3719 , acb->pci_unit, srb, acb->srboutstandingcount); 3720 continue; 3721 } 3722 arcmsr_report_srb_state(acb, srb, error); 3723 } /*drain reply FIFO*/ 3724 CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_producer_index, doneq_index); 3725 } 3726 /* 3727 ********************************************************************** 3728 ********************************************************************** 3729 */ 3730 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3731 { 3732 switch (acb->adapter_type) { 3733 case ACB_ADAPTER_TYPE_A: 3734 arcmsr_polling_hba_srbdone(acb, poll_srb); 3735 break; 3736 case ACB_ADAPTER_TYPE_B: 3737 arcmsr_polling_hbb_srbdone(acb, poll_srb); 3738 break; 3739 case ACB_ADAPTER_TYPE_C: 3740 arcmsr_polling_hbc_srbdone(acb, poll_srb); 3741 break; 3742 case ACB_ADAPTER_TYPE_D: 3743 arcmsr_polling_hbd_srbdone(acb, poll_srb); 3744 break; 3745 case ACB_ADAPTER_TYPE_E: 3746 case ACB_ADAPTER_TYPE_F: 3747 arcmsr_polling_hbe_srbdone(acb, poll_srb); 3748 break; 3749 } 3750 } 3751 /* 3752 ********************************************************************** 3753 ********************************************************************** 3754 */ 3755 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb) 3756 { 3757 char *acb_firm_model = acb->firm_model; 3758 char *acb_firm_version = acb->firm_version; 3759 char *acb_device_map = acb->device_map; 3760 size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3761 size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3762 size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3763 int i; 3764 3765 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3766 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3767 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3768 } 3769 i = 0; 3770 while(i < 8) { 3771 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3772 /* 8 bytes firm_model, 15, 60-67*/ 3773 acb_firm_model++; 3774 i++; 3775 } 3776 i=0; 3777 while(i < 16) { 3778 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3779 /* 16 bytes firm_version, 17, 68-83*/ 3780 acb_firm_version++; 3781 i++; 3782 } 3783 i=0; 3784 while(i < 16) { 3785 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3786 acb_device_map++; 3787 i++; 3788 } 3789 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3790 acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3791 acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3792 acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3793 acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3794 acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3795 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3796 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3797 else 3798 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3799 } 3800 /* 3801 ********************************************************************** 3802 ********************************************************************** 3803 */ 3804 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb) 3805 { 3806 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3807 char *acb_firm_model = acb->firm_model; 3808 char *acb_firm_version = acb->firm_version; 3809 char *acb_device_map = acb->device_map; 3810 size_t iop_firm_model = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3811 size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3812 size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3813 int i; 3814 3815 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 3816 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3817 printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3818 } 3819 i = 0; 3820 while(i < 8) { 3821 *acb_firm_model = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i); 3822 /* 8 bytes firm_model, 15, 60-67*/ 3823 acb_firm_model++; 3824 i++; 3825 } 3826 i = 0; 3827 while(i < 16) { 3828 *acb_firm_version = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i); 3829 /* 16 bytes firm_version, 17, 68-83*/ 3830 acb_firm_version++; 3831 i++; 3832 } 3833 i = 0; 3834 while(i < 16) { 3835 *acb_device_map = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i); 3836 acb_device_map++; 3837 i++; 3838 } 3839 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3840 acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3841 acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3842 acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3843 acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3844 acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3845 if(acb->firm_numbers_queue > ARCMSR_MAX_HBB_POSTQUEUE) 3846 acb->maxOutstanding = ARCMSR_MAX_HBB_POSTQUEUE - 1; 3847 else 3848 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3849 } 3850 /* 3851 ********************************************************************** 3852 ********************************************************************** 3853 */ 3854 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb) 3855 { 3856 char *acb_firm_model = acb->firm_model; 3857 char *acb_firm_version = acb->firm_version; 3858 char *acb_device_map = acb->device_map; 3859 size_t iop_firm_model = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3860 size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3861 size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3862 int i; 3863 3864 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3865 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3866 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3867 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3868 } 3869 i = 0; 3870 while(i < 8) { 3871 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3872 /* 8 bytes firm_model, 15, 60-67*/ 3873 acb_firm_model++; 3874 i++; 3875 } 3876 i = 0; 3877 while(i < 16) { 3878 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3879 /* 16 bytes firm_version, 17, 68-83*/ 3880 acb_firm_version++; 3881 i++; 3882 } 3883 i = 0; 3884 while(i < 16) { 3885 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3886 acb_device_map++; 3887 i++; 3888 } 3889 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3890 acb->firm_request_len = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3891 acb->firm_numbers_queue = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3892 acb->firm_sdram_size = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3893 acb->firm_ide_channels = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3894 acb->firm_cfg_version = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3895 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3896 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3897 else 3898 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3899 } 3900 /* 3901 ********************************************************************** 3902 ********************************************************************** 3903 */ 3904 static void arcmsr_get_hbd_config(struct AdapterControlBlock *acb) 3905 { 3906 char *acb_firm_model = acb->firm_model; 3907 char *acb_firm_version = acb->firm_version; 3908 char *acb_device_map = acb->device_map; 3909 size_t iop_firm_model = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3910 size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3911 size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3912 int i; 3913 3914 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) 3915 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 3916 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3917 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3918 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3919 } 3920 i = 0; 3921 while(i < 8) { 3922 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3923 /* 8 bytes firm_model, 15, 60-67*/ 3924 acb_firm_model++; 3925 i++; 3926 } 3927 i = 0; 3928 while(i < 16) { 3929 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3930 /* 16 bytes firm_version, 17, 68-83*/ 3931 acb_firm_version++; 3932 i++; 3933 } 3934 i = 0; 3935 while(i < 16) { 3936 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3937 acb_device_map++; 3938 i++; 3939 } 3940 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3941 acb->firm_request_len = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3942 acb->firm_numbers_queue = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3943 acb->firm_sdram_size = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3944 acb->firm_ide_channels = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3945 acb->firm_cfg_version = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3946 if(acb->firm_numbers_queue > ARCMSR_MAX_HBD_POSTQUEUE) 3947 acb->maxOutstanding = ARCMSR_MAX_HBD_POSTQUEUE - 1; 3948 else 3949 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3950 } 3951 /* 3952 ********************************************************************** 3953 ********************************************************************** 3954 */ 3955 static void arcmsr_get_hbe_config(struct AdapterControlBlock *acb) 3956 { 3957 char *acb_firm_model = acb->firm_model; 3958 char *acb_firm_version = acb->firm_version; 3959 char *acb_device_map = acb->device_map; 3960 size_t iop_firm_model = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3961 size_t iop_firm_version = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3962 size_t iop_device_map = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3963 int i; 3964 3965 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3966 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3967 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 3968 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 3969 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3970 } 3971 3972 i = 0; 3973 while(i < 8) { 3974 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3975 /* 8 bytes firm_model, 15, 60-67*/ 3976 acb_firm_model++; 3977 i++; 3978 } 3979 i = 0; 3980 while(i < 16) { 3981 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3982 /* 16 bytes firm_version, 17, 68-83*/ 3983 acb_firm_version++; 3984 i++; 3985 } 3986 i = 0; 3987 while(i < 16) { 3988 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3989 acb_device_map++; 3990 i++; 3991 } 3992 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3993 acb->firm_request_len = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3994 acb->firm_numbers_queue = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3995 acb->firm_sdram_size = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3996 acb->firm_ide_channels = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3997 acb->firm_cfg_version = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3998 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3999 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 4000 else 4001 acb->maxOutstanding = acb->firm_numbers_queue - 1; 4002 } 4003 /* 4004 ********************************************************************** 4005 ********************************************************************** 4006 */ 4007 static void arcmsr_get_hbf_config(struct AdapterControlBlock *acb) 4008 { 4009 u_int32_t *acb_firm_model = (u_int32_t *)acb->firm_model; 4010 u_int32_t *acb_firm_version = (u_int32_t *)acb->firm_version; 4011 u_int32_t *acb_device_map = (u_int32_t *)acb->device_map; 4012 size_t iop_firm_model = ARCMSR_FW_MODEL_OFFSET; /*firm_model,15,60-67*/ 4013 size_t iop_firm_version = ARCMSR_FW_VERS_OFFSET; /*firm_version,17,68-83*/ 4014 size_t iop_device_map = ARCMSR_FW_DEVMAP_OFFSET; 4015 int i; 4016 4017 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 4018 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 4019 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4020 if(!arcmsr_hbe_wait_msgint_ready(acb)) 4021 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 4022 4023 i = 0; 4024 while(i < 2) { 4025 *acb_firm_model = acb->msgcode_rwbuffer[iop_firm_model]; 4026 /* 8 bytes firm_model, 15, 60-67*/ 4027 acb_firm_model++; 4028 iop_firm_model++; 4029 i++; 4030 } 4031 i = 0; 4032 while(i < 4) { 4033 *acb_firm_version = acb->msgcode_rwbuffer[iop_firm_version]; 4034 /* 16 bytes firm_version, 17, 68-83*/ 4035 acb_firm_version++; 4036 iop_firm_version++; 4037 i++; 4038 } 4039 i = 0; 4040 while(i < 4) { 4041 *acb_device_map = acb->msgcode_rwbuffer[iop_device_map]; 4042 acb_device_map++; 4043 iop_device_map++; 4044 i++; 4045 } 4046 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 4047 acb->firm_request_len = acb->msgcode_rwbuffer[1]; /*firm_request_len, 1, 04-07*/ 4048 acb->firm_numbers_queue = acb->msgcode_rwbuffer[2]; /*firm_numbers_queue, 2, 08-11*/ 4049 acb->firm_sdram_size = acb->msgcode_rwbuffer[3]; /*firm_sdram_size, 3, 12-15*/ 4050 acb->firm_ide_channels = acb->msgcode_rwbuffer[4]; /*firm_ide_channels, 4, 16-19*/ 4051 acb->firm_cfg_version = acb->msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]; /*firm_cfg_version, 25*/ 4052 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 4053 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 4054 else 4055 acb->maxOutstanding = acb->firm_numbers_queue - 1; 4056 } 4057 /* 4058 ********************************************************************** 4059 ********************************************************************** 4060 */ 4061 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb) 4062 { 4063 switch (acb->adapter_type) { 4064 case ACB_ADAPTER_TYPE_A: 4065 arcmsr_get_hba_config(acb); 4066 break; 4067 case ACB_ADAPTER_TYPE_B: 4068 arcmsr_get_hbb_config(acb); 4069 break; 4070 case ACB_ADAPTER_TYPE_C: 4071 arcmsr_get_hbc_config(acb); 4072 break; 4073 case ACB_ADAPTER_TYPE_D: 4074 arcmsr_get_hbd_config(acb); 4075 break; 4076 case ACB_ADAPTER_TYPE_E: 4077 arcmsr_get_hbe_config(acb); 4078 break; 4079 case ACB_ADAPTER_TYPE_F: 4080 arcmsr_get_hbf_config(acb); 4081 break; 4082 } 4083 } 4084 /* 4085 ********************************************************************** 4086 ********************************************************************** 4087 */ 4088 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb) 4089 { 4090 int timeout=0; 4091 4092 switch (acb->adapter_type) { 4093 case ACB_ADAPTER_TYPE_A: { 4094 while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) 4095 { 4096 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4097 { 4098 printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit); 4099 return; 4100 } 4101 UDELAY(15000); /* wait 15 milli-seconds */ 4102 } 4103 } 4104 break; 4105 case ACB_ADAPTER_TYPE_B: { 4106 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4107 while ((READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0) 4108 { 4109 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4110 { 4111 printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit); 4112 return; 4113 } 4114 UDELAY(15000); /* wait 15 milli-seconds */ 4115 } 4116 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 4117 } 4118 break; 4119 case ACB_ADAPTER_TYPE_C: { 4120 while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0) 4121 { 4122 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4123 { 4124 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 4125 return; 4126 } 4127 UDELAY(15000); /* wait 15 milli-seconds */ 4128 } 4129 } 4130 break; 4131 case ACB_ADAPTER_TYPE_D: { 4132 while ((CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK) == 0) 4133 { 4134 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4135 { 4136 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 4137 return; 4138 } 4139 UDELAY(15000); /* wait 15 milli-seconds */ 4140 } 4141 } 4142 break; 4143 case ACB_ADAPTER_TYPE_E: 4144 case ACB_ADAPTER_TYPE_F: { 4145 while ((CHIP_REG_READ32(HBE_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0) 4146 { 4147 if (timeout++ > 4000) /* (4000*15)/1000 = 60 sec */ 4148 { 4149 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 4150 return; 4151 } 4152 UDELAY(15000); /* wait 15 milli-seconds */ 4153 } 4154 } 4155 break; 4156 } 4157 } 4158 /* 4159 ********************************************************************** 4160 ********************************************************************** 4161 */ 4162 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb) 4163 { 4164 u_int32_t outbound_doorbell; 4165 4166 switch (acb->adapter_type) { 4167 case ACB_ADAPTER_TYPE_A: { 4168 /* empty doorbell Qbuffer if door bell ringed */ 4169 outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell); 4170 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 4171 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 4172 } 4173 break; 4174 case ACB_ADAPTER_TYPE_B: { 4175 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4176 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN);/*clear interrupt and message state*/ 4177 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 4178 /* let IOP know data has been read */ 4179 } 4180 break; 4181 case ACB_ADAPTER_TYPE_C: { 4182 /* empty doorbell Qbuffer if door bell ringed */ 4183 outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 4184 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /*clear doorbell interrupt */ 4185 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 4186 CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell_clear); /* Dummy read to force pci flush */ 4187 CHIP_REG_READ32(HBC_MessageUnit, 0, inbound_doorbell); /* Dummy read to force pci flush */ 4188 } 4189 break; 4190 case ACB_ADAPTER_TYPE_D: { 4191 /* empty doorbell Qbuffer if door bell ringed */ 4192 outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell); 4193 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 4194 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 4195 } 4196 break; 4197 case ACB_ADAPTER_TYPE_E: 4198 case ACB_ADAPTER_TYPE_F: { 4199 /* empty doorbell Qbuffer if door bell ringed */ 4200 acb->in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 4201 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear doorbell interrupt */ 4202 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 4203 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4204 } 4205 break; 4206 } 4207 } 4208 /* 4209 ************************************************************************ 4210 ************************************************************************ 4211 */ 4212 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb) 4213 { 4214 unsigned long srb_phyaddr; 4215 u_int32_t srb_phyaddr_hi32; 4216 u_int32_t srb_phyaddr_lo32; 4217 4218 /* 4219 ******************************************************************** 4220 ** here we need to tell iop 331 our freesrb.HighPart 4221 ** if freesrb.HighPart is not zero 4222 ******************************************************************** 4223 */ 4224 srb_phyaddr = (unsigned long) acb->srb_phyaddr.phyaddr; 4225 srb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 4226 srb_phyaddr_lo32 = acb->srb_phyaddr.B.phyadd_low; 4227 switch (acb->adapter_type) { 4228 case ACB_ADAPTER_TYPE_A: { 4229 if(srb_phyaddr_hi32 != 0) { 4230 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 4231 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 4232 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4233 if(!arcmsr_hba_wait_msgint_ready(acb)) { 4234 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4235 return FALSE; 4236 } 4237 } 4238 } 4239 break; 4240 /* 4241 *********************************************************************** 4242 ** if adapter type B, set window of "post command Q" 4243 *********************************************************************** 4244 */ 4245 case ACB_ADAPTER_TYPE_B: { 4246 u_int32_t post_queue_phyaddr; 4247 struct HBB_MessageUnit *phbbmu; 4248 4249 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4250 phbbmu->postq_index = 0; 4251 phbbmu->doneq_index = 0; 4252 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW); 4253 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4254 printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit); 4255 return FALSE; 4256 } 4257 post_queue_phyaddr = srb_phyaddr + ARCMSR_SRBS_POOL_SIZE 4258 + offsetof(struct HBB_MessageUnit, post_qbuffer); 4259 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 4260 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */ 4261 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */ 4262 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */ 4263 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */ 4264 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG); 4265 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4266 printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit); 4267 return FALSE; 4268 } 4269 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE); 4270 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4271 printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit); 4272 return FALSE; 4273 } 4274 } 4275 break; 4276 case ACB_ADAPTER_TYPE_C: { 4277 if(srb_phyaddr_hi32 != 0) { 4278 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 4279 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 4280 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4281 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 4282 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 4283 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4284 return FALSE; 4285 } 4286 } 4287 } 4288 break; 4289 case ACB_ADAPTER_TYPE_D: { 4290 u_int32_t post_queue_phyaddr, done_queue_phyaddr; 4291 struct HBD_MessageUnit0 *phbdmu; 4292 4293 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 4294 phbdmu->postq_index = 0; 4295 phbdmu->doneq_index = 0x40FF; 4296 post_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 4297 + offsetof(struct HBD_MessageUnit0, post_qbuffer); 4298 done_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 4299 + offsetof(struct HBD_MessageUnit0, done_qbuffer); 4300 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 4301 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 4302 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */ 4303 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */ 4304 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100); 4305 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4306 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 4307 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4308 return FALSE; 4309 } 4310 } 4311 break; 4312 case ACB_ADAPTER_TYPE_E: { 4313 u_int32_t cdb_phyaddr_lo32; 4314 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb); 4315 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 4316 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[1], ARCMSR_SIGNATURE_1884); 4317 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[2], cdb_phyaddr_lo32); 4318 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[3], srb_phyaddr_hi32); 4319 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[4], SRB_SIZE); 4320 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE; 4321 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[5], cdb_phyaddr_lo32); 4322 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[6], srb_phyaddr_hi32); 4323 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[7], COMPLETION_Q_POOL_SIZE); 4324 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4325 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 4326 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4327 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 4328 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4329 return FALSE; 4330 } 4331 } 4332 break; 4333 case ACB_ADAPTER_TYPE_F: { 4334 u_int32_t cdb_phyaddr_lo32; 4335 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb); 4336 acb->msgcode_rwbuffer[0] = ARCMSR_SIGNATURE_SET_CONFIG; 4337 acb->msgcode_rwbuffer[1] = ARCMSR_SIGNATURE_1886; 4338 acb->msgcode_rwbuffer[2] = cdb_phyaddr_lo32; 4339 acb->msgcode_rwbuffer[3] = srb_phyaddr_hi32; 4340 acb->msgcode_rwbuffer[4] = SRB_SIZE; 4341 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE; 4342 acb->msgcode_rwbuffer[5] = cdb_phyaddr_lo32; 4343 acb->msgcode_rwbuffer[6] = srb_phyaddr_hi32; 4344 acb->msgcode_rwbuffer[7] = COMPLETION_Q_POOL_SIZE; 4345 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4346 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 4347 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4348 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 4349 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4350 return FALSE; 4351 } 4352 } 4353 break; 4354 } 4355 return (TRUE); 4356 } 4357 /* 4358 ************************************************************************ 4359 ************************************************************************ 4360 */ 4361 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb) 4362 { 4363 if (acb->adapter_type == ACB_ADAPTER_TYPE_B) 4364 { 4365 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4366 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ACTIVE_EOI_MODE); 4367 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4368 printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit); 4369 return; 4370 } 4371 } 4372 } 4373 /* 4374 ********************************************************************** 4375 ********************************************************************** 4376 */ 4377 static void arcmsr_iop_init(struct AdapterControlBlock *acb) 4378 { 4379 u_int32_t intmask_org; 4380 4381 /* disable all outbound interrupt */ 4382 intmask_org = arcmsr_disable_allintr(acb); 4383 arcmsr_wait_firmware_ready(acb); 4384 arcmsr_iop_confirm(acb); 4385 arcmsr_get_firmware_spec(acb); 4386 /*start background rebuild*/ 4387 arcmsr_start_adapter_bgrb(acb); 4388 /* empty doorbell Qbuffer if door bell ringed */ 4389 arcmsr_clear_doorbell_queue_buffer(acb); 4390 arcmsr_enable_eoi_mode(acb); 4391 /* enable outbound Post Queue, outbound doorbell Interrupt */ 4392 arcmsr_enable_allintr(acb, intmask_org); 4393 acb->acb_flags |= ACB_F_IOP_INITED; 4394 } 4395 /* 4396 ********************************************************************** 4397 ********************************************************************** 4398 */ 4399 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4400 { 4401 struct AdapterControlBlock *acb = arg; 4402 struct CommandControlBlock *srb_tmp; 4403 u_int32_t i; 4404 unsigned long srb_phyaddr = (unsigned long)segs->ds_addr; 4405 4406 acb->srb_phyaddr.phyaddr = srb_phyaddr; 4407 srb_tmp = (struct CommandControlBlock *)acb->uncacheptr; 4408 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 4409 if(bus_dmamap_create(acb->dm_segs_dmat, 4410 /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) { 4411 acb->acb_flags |= ACB_F_MAPFREESRB_FAILD; 4412 printf("arcmsr%d:" 4413 " srb dmamap bus_dmamap_create error\n", acb->pci_unit); 4414 return; 4415 } 4416 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D) 4417 || (acb->adapter_type == ACB_ADAPTER_TYPE_E) || (acb->adapter_type == ACB_ADAPTER_TYPE_F)) 4418 { 4419 srb_tmp->cdb_phyaddr_low = srb_phyaddr; 4420 srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16); 4421 } 4422 else 4423 srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5; 4424 srb_tmp->acb = acb; 4425 srb_tmp->smid = i << 16; 4426 acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp; 4427 srb_phyaddr = srb_phyaddr + SRB_SIZE; 4428 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE); 4429 } 4430 if (acb->adapter_type == ACB_ADAPTER_TYPE_E) 4431 acb->pCompletionQ = (pCompletion_Q)srb_tmp; 4432 else if (acb->adapter_type == ACB_ADAPTER_TYPE_F) { 4433 acb->pCompletionQ = (pCompletion_Q)srb_tmp; 4434 acb->completeQ_phys = srb_phyaddr; 4435 memset(acb->pCompletionQ, 0xff, COMPLETION_Q_POOL_SIZE); 4436 acb->message_wbuffer = (u_int32_t *)((unsigned long)acb->pCompletionQ + COMPLETION_Q_POOL_SIZE); 4437 acb->message_rbuffer = (u_int32_t *)((unsigned long)acb->message_wbuffer + 0x100); 4438 acb->msgcode_rwbuffer = (u_int32_t *)((unsigned long)acb->message_wbuffer + 0x200); 4439 memset((void *)acb->message_wbuffer, 0, MESG_RW_BUFFER_SIZE); 4440 } 4441 acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr; 4442 } 4443 /* 4444 ************************************************************************ 4445 ************************************************************************ 4446 */ 4447 static void arcmsr_free_resource(struct AdapterControlBlock *acb) 4448 { 4449 /* remove the control device */ 4450 if(acb->ioctl_dev != NULL) { 4451 destroy_dev(acb->ioctl_dev); 4452 } 4453 bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap); 4454 bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap); 4455 bus_dma_tag_destroy(acb->srb_dmat); 4456 bus_dma_tag_destroy(acb->dm_segs_dmat); 4457 bus_dma_tag_destroy(acb->parent_dmat); 4458 } 4459 /* 4460 ************************************************************************ 4461 ************************************************************************ 4462 */ 4463 static void arcmsr_mutex_init(struct AdapterControlBlock *acb) 4464 { 4465 ARCMSR_LOCK_INIT(&acb->isr_lock, "arcmsr isr lock"); 4466 ARCMSR_LOCK_INIT(&acb->srb_lock, "arcmsr srb lock"); 4467 ARCMSR_LOCK_INIT(&acb->postDone_lock, "arcmsr postQ lock"); 4468 ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr RW buffer lock"); 4469 } 4470 /* 4471 ************************************************************************ 4472 ************************************************************************ 4473 */ 4474 static void arcmsr_mutex_destroy(struct AdapterControlBlock *acb) 4475 { 4476 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 4477 ARCMSR_LOCK_DESTROY(&acb->postDone_lock); 4478 ARCMSR_LOCK_DESTROY(&acb->srb_lock); 4479 ARCMSR_LOCK_DESTROY(&acb->isr_lock); 4480 } 4481 /* 4482 ************************************************************************ 4483 ************************************************************************ 4484 */ 4485 static u_int32_t arcmsr_initialize(device_t dev) 4486 { 4487 struct AdapterControlBlock *acb = device_get_softc(dev); 4488 u_int16_t pci_command; 4489 int i, j,max_coherent_size; 4490 u_int32_t vendor_dev_id; 4491 4492 vendor_dev_id = pci_get_devid(dev); 4493 acb->vendor_device_id = vendor_dev_id; 4494 acb->sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 4495 switch (vendor_dev_id) { 4496 case PCIDevVenIDARC1880: 4497 case PCIDevVenIDARC1882: 4498 case PCIDevVenIDARC1213: 4499 case PCIDevVenIDARC1223: { 4500 acb->adapter_type = ACB_ADAPTER_TYPE_C; 4501 if ((acb->sub_device_id == ARECA_SUB_DEV_ID_1883) || 4502 (acb->sub_device_id == ARECA_SUB_DEV_ID_1216) || 4503 (acb->sub_device_id == ARECA_SUB_DEV_ID_1226)) 4504 acb->adapter_bus_speed = ACB_BUS_SPEED_12G; 4505 else 4506 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4507 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 4508 } 4509 break; 4510 case PCIDevVenIDARC1884: 4511 acb->adapter_type = ACB_ADAPTER_TYPE_E; 4512 acb->adapter_bus_speed = ACB_BUS_SPEED_12G; 4513 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE; 4514 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ); 4515 break; 4516 case PCIDevVenIDARC1886_: 4517 case PCIDevVenIDARC1886: 4518 acb->adapter_type = ACB_ADAPTER_TYPE_F; 4519 acb->adapter_bus_speed = ACB_BUS_SPEED_12G; 4520 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE + MESG_RW_BUFFER_SIZE; 4521 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ); 4522 break; 4523 case PCIDevVenIDARC1214: { 4524 acb->adapter_type = ACB_ADAPTER_TYPE_D; 4525 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4526 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0)); 4527 } 4528 break; 4529 case PCIDevVenIDARC1200: 4530 case PCIDevVenIDARC1201: { 4531 acb->adapter_type = ACB_ADAPTER_TYPE_B; 4532 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 4533 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit)); 4534 } 4535 break; 4536 case PCIDevVenIDARC1203: { 4537 acb->adapter_type = ACB_ADAPTER_TYPE_B; 4538 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4539 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit)); 4540 } 4541 break; 4542 case PCIDevVenIDARC1110: 4543 case PCIDevVenIDARC1120: 4544 case PCIDevVenIDARC1130: 4545 case PCIDevVenIDARC1160: 4546 case PCIDevVenIDARC1170: 4547 case PCIDevVenIDARC1210: 4548 case PCIDevVenIDARC1220: 4549 case PCIDevVenIDARC1230: 4550 case PCIDevVenIDARC1231: 4551 case PCIDevVenIDARC1260: 4552 case PCIDevVenIDARC1261: 4553 case PCIDevVenIDARC1270: 4554 case PCIDevVenIDARC1280: 4555 case PCIDevVenIDARC1212: 4556 case PCIDevVenIDARC1222: 4557 case PCIDevVenIDARC1380: 4558 case PCIDevVenIDARC1381: 4559 case PCIDevVenIDARC1680: 4560 case PCIDevVenIDARC1681: { 4561 acb->adapter_type = ACB_ADAPTER_TYPE_A; 4562 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 4563 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 4564 } 4565 break; 4566 default: { 4567 printf("arcmsr%d:" 4568 " unknown RAID adapter type \n", device_get_unit(dev)); 4569 return ENOMEM; 4570 } 4571 } 4572 if(bus_dma_tag_create( /*PCI parent*/ bus_get_dma_tag(dev), 4573 /*alignemnt*/ 1, 4574 /*boundary*/ 0, 4575 /*lowaddr*/ BUS_SPACE_MAXADDR, 4576 /*highaddr*/ BUS_SPACE_MAXADDR, 4577 /*filter*/ NULL, 4578 /*filterarg*/ NULL, 4579 /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT, 4580 /*nsegments*/ BUS_SPACE_UNRESTRICTED, 4581 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4582 /*flags*/ 0, 4583 /*lockfunc*/ NULL, 4584 /*lockarg*/ NULL, 4585 &acb->parent_dmat) != 0) 4586 { 4587 printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4588 return ENOMEM; 4589 } 4590 4591 /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */ 4592 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 4593 /*alignment*/ 1, 4594 /*boundary*/ 0, 4595 #ifdef PAE 4596 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 4597 #else 4598 /*lowaddr*/ BUS_SPACE_MAXADDR, 4599 #endif 4600 /*highaddr*/ BUS_SPACE_MAXADDR, 4601 /*filter*/ NULL, 4602 /*filterarg*/ NULL, 4603 /*maxsize*/ ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM, 4604 /*nsegments*/ ARCMSR_MAX_SG_ENTRIES, 4605 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4606 /*flags*/ 0, 4607 /*lockfunc*/ busdma_lock_mutex, 4608 /*lockarg*/ &acb->isr_lock, 4609 &acb->dm_segs_dmat) != 0) 4610 { 4611 bus_dma_tag_destroy(acb->parent_dmat); 4612 printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4613 return ENOMEM; 4614 } 4615 4616 /* DMA tag for our srb structures.... Allocate the freesrb memory */ 4617 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 4618 /*alignment*/ 0x20, 4619 /*boundary*/ 0, 4620 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 4621 /*highaddr*/ BUS_SPACE_MAXADDR, 4622 /*filter*/ NULL, 4623 /*filterarg*/ NULL, 4624 /*maxsize*/ max_coherent_size, 4625 /*nsegments*/ 1, 4626 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4627 /*flags*/ 0, 4628 /*lockfunc*/ NULL, 4629 /*lockarg*/ NULL, 4630 &acb->srb_dmat) != 0) 4631 { 4632 bus_dma_tag_destroy(acb->dm_segs_dmat); 4633 bus_dma_tag_destroy(acb->parent_dmat); 4634 printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4635 return ENXIO; 4636 } 4637 /* Allocation for our srbs */ 4638 if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) { 4639 bus_dma_tag_destroy(acb->srb_dmat); 4640 bus_dma_tag_destroy(acb->dm_segs_dmat); 4641 bus_dma_tag_destroy(acb->parent_dmat); 4642 printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev)); 4643 return ENXIO; 4644 } 4645 /* And permanently map them */ 4646 if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) { 4647 bus_dma_tag_destroy(acb->srb_dmat); 4648 bus_dma_tag_destroy(acb->dm_segs_dmat); 4649 bus_dma_tag_destroy(acb->parent_dmat); 4650 printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev)); 4651 return ENXIO; 4652 } 4653 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 4654 pci_command |= PCIM_CMD_BUSMASTEREN; 4655 pci_command |= PCIM_CMD_PERRESPEN; 4656 pci_command |= PCIM_CMD_MWRICEN; 4657 /* Enable Busmaster */ 4658 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 4659 switch(acb->adapter_type) { 4660 case ACB_ADAPTER_TYPE_A: { 4661 u_int32_t rid0 = PCIR_BAR(0); 4662 vm_offset_t mem_base0; 4663 4664 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4665 if(acb->sys_res_arcmsr[0] == NULL) { 4666 arcmsr_free_resource(acb); 4667 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4668 return ENOMEM; 4669 } 4670 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4671 arcmsr_free_resource(acb); 4672 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4673 return ENXIO; 4674 } 4675 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4676 if(mem_base0 == 0) { 4677 arcmsr_free_resource(acb); 4678 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4679 return ENXIO; 4680 } 4681 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4682 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4683 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4684 acb->rid[0] = rid0; 4685 } 4686 break; 4687 case ACB_ADAPTER_TYPE_B: { 4688 struct HBB_MessageUnit *phbbmu; 4689 struct CommandControlBlock *freesrb; 4690 u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) }; 4691 vm_offset_t mem_base[]={0,0}; 4692 for(i=0; i < 2; i++) { 4693 acb->sys_res_arcmsr[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid[i], RF_ACTIVE); 4694 if(acb->sys_res_arcmsr[i] == NULL) { 4695 arcmsr_free_resource(acb); 4696 printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i); 4697 return ENOMEM; 4698 } 4699 if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) { 4700 arcmsr_free_resource(acb); 4701 printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i); 4702 return ENXIO; 4703 } 4704 mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]); 4705 if(mem_base[i] == 0) { 4706 arcmsr_free_resource(acb); 4707 printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i); 4708 return ENXIO; 4709 } 4710 acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]); 4711 acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]); 4712 } 4713 freesrb = (struct CommandControlBlock *)acb->uncacheptr; 4714 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE); 4715 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4716 phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0]; 4717 phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1]; 4718 if (vendor_dev_id == PCIDevVenIDARC1203) { 4719 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell); 4720 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell_mask); 4721 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell); 4722 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell_mask); 4723 } else { 4724 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL, drv2iop_doorbell); 4725 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL, drv2iop_doorbell_mask); 4726 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL, iop2drv_doorbell); 4727 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL, iop2drv_doorbell_mask); 4728 } 4729 acb->rid[0] = rid[0]; 4730 acb->rid[1] = rid[1]; 4731 } 4732 break; 4733 case ACB_ADAPTER_TYPE_C: { 4734 u_int32_t rid0 = PCIR_BAR(1); 4735 vm_offset_t mem_base0; 4736 4737 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4738 if(acb->sys_res_arcmsr[0] == NULL) { 4739 arcmsr_free_resource(acb); 4740 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4741 return ENOMEM; 4742 } 4743 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4744 arcmsr_free_resource(acb); 4745 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4746 return ENXIO; 4747 } 4748 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4749 if(mem_base0 == 0) { 4750 arcmsr_free_resource(acb); 4751 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4752 return ENXIO; 4753 } 4754 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4755 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4756 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4757 acb->rid[0] = rid0; 4758 } 4759 break; 4760 case ACB_ADAPTER_TYPE_D: { 4761 struct HBD_MessageUnit0 *phbdmu; 4762 u_int32_t rid0 = PCIR_BAR(0); 4763 vm_offset_t mem_base0; 4764 4765 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4766 if(acb->sys_res_arcmsr[0] == NULL) { 4767 arcmsr_free_resource(acb); 4768 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4769 return ENOMEM; 4770 } 4771 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4772 arcmsr_free_resource(acb); 4773 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4774 return ENXIO; 4775 } 4776 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4777 if(mem_base0 == 0) { 4778 arcmsr_free_resource(acb); 4779 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4780 return ENXIO; 4781 } 4782 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4783 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4784 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE); 4785 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 4786 phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0; 4787 acb->rid[0] = rid0; 4788 } 4789 break; 4790 case ACB_ADAPTER_TYPE_E: { 4791 u_int32_t rid0 = PCIR_BAR(1); 4792 vm_offset_t mem_base0; 4793 4794 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4795 if(acb->sys_res_arcmsr[0] == NULL) { 4796 arcmsr_free_resource(acb); 4797 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4798 return ENOMEM; 4799 } 4800 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4801 arcmsr_free_resource(acb); 4802 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4803 return ENXIO; 4804 } 4805 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4806 if(mem_base0 == 0) { 4807 arcmsr_free_resource(acb); 4808 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4809 return ENXIO; 4810 } 4811 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4812 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4813 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4814 acb->doneq_index = 0; 4815 acb->in_doorbell = 0; 4816 acb->out_doorbell = 0; 4817 acb->rid[0] = rid0; 4818 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/ 4819 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */ 4820 } 4821 break; 4822 case ACB_ADAPTER_TYPE_F: { 4823 u_int32_t rid0 = PCIR_BAR(0); 4824 vm_offset_t mem_base0; 4825 unsigned long host_buffer_dma; 4826 4827 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4828 if(acb->sys_res_arcmsr[0] == NULL) { 4829 arcmsr_free_resource(acb); 4830 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4831 return ENOMEM; 4832 } 4833 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4834 arcmsr_free_resource(acb); 4835 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4836 return ENXIO; 4837 } 4838 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4839 if(mem_base0 == 0) { 4840 arcmsr_free_resource(acb); 4841 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4842 return ENXIO; 4843 } 4844 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4845 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4846 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4847 acb->doneq_index = 0; 4848 acb->in_doorbell = 0; 4849 acb->out_doorbell = 0; 4850 acb->rid[0] = rid0; 4851 CHIP_REG_WRITE32(HBF_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/ 4852 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */ 4853 arcmsr_wait_firmware_ready(acb); 4854 host_buffer_dma = acb->completeQ_phys + COMPLETION_Q_POOL_SIZE; 4855 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, (u_int32_t)(host_buffer_dma | 1)); /* host buffer low addr, bit0:1 all buffer active */ 4856 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr1, (u_int32_t)((host_buffer_dma >> 16) >> 16));/* host buffer high addr */ 4857 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBFMU_DOORBELL_SYNC1); /* set host buffer physical address */ 4858 } 4859 break; 4860 } 4861 if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) { 4862 arcmsr_free_resource(acb); 4863 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev)); 4864 return ENXIO; 4865 } 4866 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 4867 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER; 4868 /* 4869 ******************************************************************** 4870 ** init raid volume state 4871 ******************************************************************** 4872 */ 4873 for(i=0; i < ARCMSR_MAX_TARGETID; i++) { 4874 for(j=0; j < ARCMSR_MAX_TARGETLUN; j++) { 4875 acb->devstate[i][j] = ARECA_RAID_GONE; 4876 } 4877 } 4878 arcmsr_iop_init(acb); 4879 return(0); 4880 } 4881 4882 static int arcmsr_setup_msix(struct AdapterControlBlock *acb) 4883 { 4884 int i; 4885 4886 for (i = 0; i < acb->msix_vectors; i++) { 4887 acb->irq_id[i] = 1 + i; 4888 acb->irqres[i] = bus_alloc_resource_any(acb->pci_dev, 4889 SYS_RES_IRQ, &acb->irq_id[i], RF_ACTIVE); 4890 if (acb->irqres[i] == NULL) { 4891 printf("arcmsr: Can't allocate MSI-X resource\n"); 4892 goto irq_alloc_failed; 4893 } 4894 if (bus_setup_intr(acb->pci_dev, acb->irqres[i], 4895 INTR_MPSAFE | INTR_TYPE_CAM, NULL, arcmsr_intr_handler, 4896 acb, &acb->ih[i])) { 4897 printf("arcmsr: Cannot set up MSI-X interrupt handler\n"); 4898 goto irq_alloc_failed; 4899 } 4900 } 4901 printf("arcmsr: MSI-X INT enabled\n"); 4902 acb->acb_flags |= ACB_F_MSIX_ENABLED; 4903 return TRUE; 4904 4905 irq_alloc_failed: 4906 arcmsr_teardown_intr(acb->pci_dev, acb); 4907 return FALSE; 4908 } 4909 4910 /* 4911 ************************************************************************ 4912 ************************************************************************ 4913 */ 4914 static int arcmsr_attach(device_t dev) 4915 { 4916 struct make_dev_args args; 4917 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 4918 u_int32_t unit=device_get_unit(dev); 4919 struct ccb_setasync csa; 4920 struct cam_devq *devq; /* Device Queue to use for this SIM */ 4921 struct resource *irqres; 4922 4923 if(acb == NULL) { 4924 printf("arcmsr%d: cannot allocate softc\n", unit); 4925 return (ENOMEM); 4926 } 4927 arcmsr_mutex_init(acb); 4928 acb->pci_dev = dev; 4929 acb->pci_unit = unit; 4930 if(arcmsr_initialize(dev)) { 4931 printf("arcmsr%d: initialize failure!\n", unit); 4932 goto initialize_failed; 4933 } 4934 /* After setting up the adapter, map our interrupt */ 4935 acb->msix_vectors = ARCMSR_NUM_MSIX_VECTORS; 4936 if (pci_alloc_msix(dev, &acb->msix_vectors) == 0) { 4937 if (arcmsr_setup_msix(acb) == TRUE) 4938 goto irqx; 4939 } 4940 acb->irq_id[0] = 0; 4941 irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &acb->irq_id[0], RF_SHAREABLE | RF_ACTIVE); 4942 if(irqres == NULL || 4943 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih[0])) { 4944 printf("arcmsr%d: unable to register interrupt handler!\n", unit); 4945 goto setup_intr_failed; 4946 } 4947 acb->irqres[0] = irqres; 4948 irqx: 4949 /* 4950 * Now let the CAM generic SCSI layer find the SCSI devices on 4951 * the bus * start queue to reset to the idle loop. * 4952 * Create device queue of SIM(s) * (MAX_START_JOB - 1) : 4953 * max_sim_transactions 4954 */ 4955 devq = cam_simq_alloc(acb->maxOutstanding); 4956 if(devq == NULL) { 4957 printf("arcmsr%d: cam_simq_alloc failure!\n", unit); 4958 goto simq_alloc_failed; 4959 } 4960 acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq); 4961 if(acb->psim == NULL) { 4962 printf("arcmsr%d: cam_sim_alloc failure!\n", unit); 4963 goto sim_alloc_failed; 4964 } 4965 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 4966 if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) { 4967 printf("arcmsr%d: xpt_bus_register failure!\n", unit); 4968 goto xpt_bus_failed; 4969 } 4970 if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 4971 printf("arcmsr%d: xpt_create_path failure!\n", unit); 4972 goto xpt_path_failed; 4973 } 4974 /* 4975 **************************************************** 4976 */ 4977 memset(&csa, 0, sizeof(csa)); 4978 xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5); 4979 csa.ccb_h.func_code = XPT_SASYNC_CB; 4980 csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE; 4981 csa.callback = arcmsr_async; 4982 csa.callback_arg = acb->psim; 4983 xpt_action((union ccb *)&csa); 4984 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 4985 /* Create the control device. */ 4986 make_dev_args_init(&args); 4987 args.mda_devsw = &arcmsr_cdevsw; 4988 args.mda_uid = UID_ROOT; 4989 args.mda_gid = GID_WHEEL /* GID_OPERATOR */; 4990 args.mda_mode = S_IRUSR | S_IWUSR; 4991 args.mda_si_drv1 = acb; 4992 (void)make_dev_s(&args, &acb->ioctl_dev, "arcmsr%d", unit); 4993 4994 (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit); 4995 arcmsr_callout_init(&acb->devmap_callout); 4996 callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb); 4997 return (0); 4998 xpt_path_failed: 4999 xpt_bus_deregister(cam_sim_path(acb->psim)); 5000 xpt_bus_failed: 5001 cam_sim_free(acb->psim, /* free_simq */ TRUE); 5002 sim_alloc_failed: 5003 cam_simq_free(devq); 5004 simq_alloc_failed: 5005 arcmsr_teardown_intr(dev, acb); 5006 setup_intr_failed: 5007 arcmsr_free_resource(acb); 5008 initialize_failed: 5009 arcmsr_mutex_destroy(acb); 5010 return ENXIO; 5011 } 5012 5013 /* 5014 ************************************************************************ 5015 ************************************************************************ 5016 */ 5017 static int arcmsr_probe(device_t dev) 5018 { 5019 u_int32_t id; 5020 u_int16_t sub_device_id; 5021 static char buf[256]; 5022 char x_type[]={"unknown"}; 5023 char *type; 5024 int raid6 = 1; 5025 5026 if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) { 5027 return (ENXIO); 5028 } 5029 sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 5030 switch(id = pci_get_devid(dev)) { 5031 case PCIDevVenIDARC1110: 5032 case PCIDevVenIDARC1200: 5033 case PCIDevVenIDARC1201: 5034 case PCIDevVenIDARC1210: 5035 raid6 = 0; 5036 /*FALLTHRU*/ 5037 case PCIDevVenIDARC1120: 5038 case PCIDevVenIDARC1130: 5039 case PCIDevVenIDARC1160: 5040 case PCIDevVenIDARC1170: 5041 case PCIDevVenIDARC1220: 5042 case PCIDevVenIDARC1230: 5043 case PCIDevVenIDARC1231: 5044 case PCIDevVenIDARC1260: 5045 case PCIDevVenIDARC1261: 5046 case PCIDevVenIDARC1270: 5047 case PCIDevVenIDARC1280: 5048 type = "SATA 3G"; 5049 break; 5050 case PCIDevVenIDARC1212: 5051 case PCIDevVenIDARC1222: 5052 case PCIDevVenIDARC1380: 5053 case PCIDevVenIDARC1381: 5054 case PCIDevVenIDARC1680: 5055 case PCIDevVenIDARC1681: 5056 type = "SAS 3G"; 5057 break; 5058 case PCIDevVenIDARC1880: 5059 case PCIDevVenIDARC1882: 5060 case PCIDevVenIDARC1213: 5061 case PCIDevVenIDARC1223: 5062 if ((sub_device_id == ARECA_SUB_DEV_ID_1883) || 5063 (sub_device_id == ARECA_SUB_DEV_ID_1216) || 5064 (sub_device_id == ARECA_SUB_DEV_ID_1226)) 5065 type = "SAS 12G"; 5066 else 5067 type = "SAS 6G"; 5068 break; 5069 case PCIDevVenIDARC1884: 5070 type = "SAS 12G"; 5071 break; 5072 case PCIDevVenIDARC1886_: 5073 case PCIDevVenIDARC1886: 5074 type = "NVME,SAS-12G,SATA-6G"; 5075 break; 5076 case PCIDevVenIDARC1214: 5077 case PCIDevVenIDARC1203: 5078 type = "SATA 6G"; 5079 break; 5080 default: 5081 type = x_type; 5082 raid6 = 0; 5083 break; 5084 } 5085 if(type == x_type) 5086 return(ENXIO); 5087 sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n%s\n", 5088 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION); 5089 device_set_desc_copy(dev, buf); 5090 return (BUS_PROBE_DEFAULT); 5091 } 5092 /* 5093 ************************************************************************ 5094 ************************************************************************ 5095 */ 5096 static int arcmsr_shutdown(device_t dev) 5097 { 5098 u_int32_t i; 5099 struct CommandControlBlock *srb; 5100 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 5101 5102 /* stop adapter background rebuild */ 5103 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 5104 /* disable all outbound interrupt */ 5105 arcmsr_disable_allintr(acb); 5106 arcmsr_stop_adapter_bgrb(acb); 5107 arcmsr_flush_adapter_cache(acb); 5108 /* abort all outstanding command */ 5109 acb->acb_flags |= ACB_F_SCSISTOPADAPTER; 5110 acb->acb_flags &= ~ACB_F_IOP_INITED; 5111 if(acb->srboutstandingcount != 0) { 5112 /*clear and abort all outbound posted Q*/ 5113 arcmsr_done4abort_postqueue(acb); 5114 /* talk to iop 331 outstanding command aborted*/ 5115 arcmsr_abort_allcmd(acb); 5116 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 5117 srb = acb->psrb_pool[i]; 5118 if(srb->srb_state == ARCMSR_SRB_START) { 5119 srb->srb_state = ARCMSR_SRB_ABORTED; 5120 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 5121 arcmsr_srb_complete(srb, 1); 5122 } 5123 } 5124 } 5125 acb->srboutstandingcount = 0; 5126 acb->workingsrb_doneindex = 0; 5127 acb->workingsrb_startindex = 0; 5128 acb->pktRequestCount = 0; 5129 acb->pktReturnCount = 0; 5130 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 5131 return (0); 5132 } 5133 /* 5134 ************************************************************************ 5135 ************************************************************************ 5136 */ 5137 static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb) 5138 { 5139 int i; 5140 5141 if (acb->acb_flags & ACB_F_MSIX_ENABLED) { 5142 for (i = 0; i < acb->msix_vectors; i++) { 5143 if (acb->ih[i]) 5144 bus_teardown_intr(dev, acb->irqres[i], acb->ih[i]); 5145 if (acb->irqres[i] != NULL) 5146 bus_release_resource(dev, SYS_RES_IRQ, 5147 acb->irq_id[i], acb->irqres[i]); 5148 5149 acb->ih[i] = NULL; 5150 } 5151 pci_release_msi(dev); 5152 } else { 5153 if (acb->ih[0]) 5154 bus_teardown_intr(dev, acb->irqres[0], acb->ih[0]); 5155 if (acb->irqres[0] != NULL) 5156 bus_release_resource(dev, SYS_RES_IRQ, 5157 acb->irq_id[0], acb->irqres[0]); 5158 acb->ih[0] = NULL; 5159 } 5160 5161 } 5162 /* 5163 ************************************************************************ 5164 ************************************************************************ 5165 */ 5166 static int arcmsr_detach(device_t dev) 5167 { 5168 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 5169 int i; 5170 5171 callout_stop(&acb->devmap_callout); 5172 arcmsr_teardown_intr(dev, acb); 5173 arcmsr_shutdown(dev); 5174 arcmsr_free_resource(acb); 5175 for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) { 5176 bus_release_resource(dev, SYS_RES_MEMORY, acb->rid[i], acb->sys_res_arcmsr[i]); 5177 } 5178 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 5179 xpt_async(AC_LOST_DEVICE, acb->ppath, NULL); 5180 xpt_free_path(acb->ppath); 5181 xpt_bus_deregister(cam_sim_path(acb->psim)); 5182 cam_sim_free(acb->psim, TRUE); 5183 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 5184 arcmsr_mutex_destroy(acb); 5185 return (0); 5186 } 5187 5188 #ifdef ARCMSR_DEBUG1 5189 static void arcmsr_dump_data(struct AdapterControlBlock *acb) 5190 { 5191 if((acb->pktRequestCount - acb->pktReturnCount) == 0) 5192 return; 5193 printf("Command Request Count =0x%x\n",acb->pktRequestCount); 5194 printf("Command Return Count =0x%x\n",acb->pktReturnCount); 5195 printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount)); 5196 printf("Queued Command Count =0x%x\n",acb->srboutstandingcount); 5197 } 5198 #endif 5199