1 /* 2 ***************************************************************************************** 3 ** O.S : FreeBSD 4 ** FILE NAME : arcmsr.c 5 ** BY : Erich Chen, Ching Huang 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x) SATA/SAS RAID HOST Adapter 8 ** ARCMSR RAID Host adapter 9 ** [RAID controller:INTEL 331(PCI-X) 341(PCI-EXPRESS) chip set] 10 ****************************************************************************************** 11 ************************************************************************ 12 ** 13 ** Copyright (c) 2004-2010 ARECA Co. Ltd. 14 ** Erich Chen, Taipei Taiwan All rights reserved. 15 ** 16 ** Redistribution and use in source and binary forms, with or without 17 ** modification, are permitted provided that the following conditions 18 ** are met: 19 ** 1. Redistributions of source code must retain the above copyright 20 ** notice, this list of conditions and the following disclaimer. 21 ** 2. Redistributions in binary form must reproduce the above copyright 22 ** notice, this list of conditions and the following disclaimer in the 23 ** documentation and/or other materials provided with the distribution. 24 ** 3. The name of the author may not be used to endorse or promote products 25 ** derived from this software without specific prior written permission. 26 ** 27 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 29 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 31 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT 32 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 34 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 36 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 ************************************************************************** 38 ** History 39 ** 40 ** REV# DATE NAME DESCRIPTION 41 ** 1.00.00.00 3/31/2004 Erich Chen First release 42 ** 1.20.00.02 11/29/2004 Erich Chen bug fix with arcmsr_bus_reset when PHY error 43 ** 1.20.00.03 4/19/2005 Erich Chen add SATA 24 Ports adapter type support 44 ** clean unused function 45 ** 1.20.00.12 9/12/2005 Erich Chen bug fix with abort command handling, 46 ** firmware version check 47 ** and firmware update notify for hardware bug fix 48 ** handling if none zero high part physical address 49 ** of srb resource 50 ** 1.20.00.13 8/18/2006 Erich Chen remove pending srb and report busy 51 ** add iop message xfer 52 ** with scsi pass-through command 53 ** add new device id of sas raid adapters 54 ** code fit for SPARC64 & PPC 55 ** 1.20.00.14 02/05/2007 Erich Chen bug fix for incorrect ccb_h.status report 56 ** and cause g_vfs_done() read write error 57 ** 1.20.00.15 10/10/2007 Erich Chen support new RAID adapter type ARC120x 58 ** 1.20.00.16 10/10/2009 Erich Chen Bug fix for RAID adapter type ARC120x 59 ** bus_dmamem_alloc() with BUS_DMA_ZERO 60 ** 1.20.00.17 07/15/2010 Ching Huang Added support ARC1880 61 ** report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed, 62 ** prevent cam_periph_error removing all LUN devices of one Target id 63 ** for any one LUN device failed 64 ****************************************************************************************** 65 * $FreeBSD$ 66 */ 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/malloc.h> 70 #include <sys/kernel.h> 71 #include <sys/bus.h> 72 #include <sys/queue.h> 73 #include <sys/stat.h> 74 #include <sys/devicestat.h> 75 #include <sys/kthread.h> 76 #include <sys/module.h> 77 #include <sys/proc.h> 78 #include <sys/lock.h> 79 #include <sys/sysctl.h> 80 #include <sys/poll.h> 81 #include <sys/ioccom.h> 82 #include <vm/vm.h> 83 #include <vm/vm_param.h> 84 #include <vm/pmap.h> 85 86 #include <isa/rtc.h> 87 88 #include <machine/bus.h> 89 #include <machine/resource.h> 90 #include <machine/atomic.h> 91 #include <sys/conf.h> 92 #include <sys/rman.h> 93 94 #include <cam/cam.h> 95 #include <cam/cam_ccb.h> 96 #include <cam/cam_sim.h> 97 #include <cam/cam_periph.h> 98 #include <cam/cam_xpt_periph.h> 99 #include <cam/cam_xpt_sim.h> 100 #include <cam/cam_debug.h> 101 #include <cam/scsi/scsi_all.h> 102 #include <cam/scsi/scsi_message.h> 103 /* 104 ************************************************************************** 105 ************************************************************************** 106 */ 107 #if __FreeBSD_version >= 500005 108 #include <sys/selinfo.h> 109 #include <sys/mutex.h> 110 #include <sys/endian.h> 111 #include <dev/pci/pcivar.h> 112 #include <dev/pci/pcireg.h> 113 #define ARCMSR_LOCK_INIT(l, s) mtx_init(l, s, NULL, MTX_DEF) 114 #define ARCMSR_LOCK_DESTROY(l) mtx_destroy(l) 115 #define ARCMSR_LOCK_ACQUIRE(l) mtx_lock(l) 116 #define ARCMSR_LOCK_RELEASE(l) mtx_unlock(l) 117 #define ARCMSR_LOCK_TRY(l) mtx_trylock(l) 118 #define arcmsr_htole32(x) htole32(x) 119 typedef struct mtx arcmsr_lock_t; 120 #else 121 #include <sys/select.h> 122 #include <pci/pcivar.h> 123 #include <pci/pcireg.h> 124 #define ARCMSR_LOCK_INIT(l, s) simple_lock_init(l) 125 #define ARCMSR_LOCK_DESTROY(l) 126 #define ARCMSR_LOCK_ACQUIRE(l) simple_lock(l) 127 #define ARCMSR_LOCK_RELEASE(l) simple_unlock(l) 128 #define ARCMSR_LOCK_TRY(l) simple_lock_try(l) 129 #define arcmsr_htole32(x) (x) 130 typedef struct simplelock arcmsr_lock_t; 131 #endif 132 133 #if !defined(CAM_NEW_TRAN_CODE) && __FreeBSD_version >= 700025 134 #define CAM_NEW_TRAN_CODE 1 135 #endif 136 137 #include <dev/arcmsr/arcmsr.h> 138 #define ARCMSR_SRBS_POOL_SIZE ((sizeof(struct CommandControlBlock) * ARCMSR_MAX_FREESRB_NUM)) 139 /* 140 ************************************************************************** 141 ************************************************************************** 142 */ 143 #define CHIP_REG_READ32(s, b, r) bus_space_read_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r)) 144 #define CHIP_REG_WRITE32(s, b, r, d) bus_space_write_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r), d) 145 /* 146 ************************************************************************** 147 ************************************************************************** 148 */ 149 static struct CommandControlBlock * arcmsr_get_freesrb(struct AdapterControlBlock *acb); 150 static u_int8_t arcmsr_seek_cmd2abort(union ccb * abortccb); 151 static int arcmsr_probe(device_t dev); 152 static int arcmsr_attach(device_t dev); 153 static int arcmsr_detach(device_t dev); 154 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg); 155 static void arcmsr_iop_parking(struct AdapterControlBlock *acb); 156 static int arcmsr_shutdown(device_t dev); 157 static void arcmsr_interrupt(struct AdapterControlBlock *acb); 158 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb); 159 static void arcmsr_free_resource(struct AdapterControlBlock *acb); 160 static void arcmsr_bus_reset(struct AdapterControlBlock *acb); 161 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb); 162 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb); 163 static void arcmsr_iop_init(struct AdapterControlBlock *acb); 164 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb); 165 static void arcmsr_post_ioctldata2iop(struct AdapterControlBlock *acb); 166 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb); 167 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag); 168 static void arcmsr_iop_reset(struct AdapterControlBlock *acb); 169 static void arcmsr_report_sense_info(struct CommandControlBlock *srb); 170 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t * dm_segs, u_int32_t nseg); 171 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb * pccb); 172 static int arcmsr_resume(device_t dev); 173 static int arcmsr_suspend(device_t dev); 174 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb); 175 static void arcmsr_polling_devmap(void* arg); 176 /* 177 ************************************************************************** 178 ************************************************************************** 179 */ 180 static void UDELAY(u_int32_t us) { DELAY(us); } 181 /* 182 ************************************************************************** 183 ************************************************************************** 184 */ 185 static bus_dmamap_callback_t arcmsr_map_freesrb; 186 static bus_dmamap_callback_t arcmsr_executesrb; 187 /* 188 ************************************************************************** 189 ************************************************************************** 190 */ 191 static d_open_t arcmsr_open; 192 static d_close_t arcmsr_close; 193 static d_ioctl_t arcmsr_ioctl; 194 195 static device_method_t arcmsr_methods[]={ 196 DEVMETHOD(device_probe, arcmsr_probe), 197 DEVMETHOD(device_attach, arcmsr_attach), 198 DEVMETHOD(device_detach, arcmsr_detach), 199 DEVMETHOD(device_shutdown, arcmsr_shutdown), 200 DEVMETHOD(device_suspend, arcmsr_suspend), 201 DEVMETHOD(device_resume, arcmsr_resume), 202 DEVMETHOD(bus_print_child, bus_generic_print_child), 203 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 204 { 0, 0 } 205 }; 206 207 static driver_t arcmsr_driver={ 208 "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock) 209 }; 210 211 static devclass_t arcmsr_devclass; 212 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, arcmsr_devclass, 0, 0); 213 MODULE_DEPEND(arcmsr, pci, 1, 1, 1); 214 MODULE_DEPEND(arcmsr, cam, 1, 1, 1); 215 #ifndef BUS_DMA_COHERENT 216 #define BUS_DMA_COHERENT 0x04 /* hint: map memory in a coherent way */ 217 #endif 218 #if __FreeBSD_version >= 501000 219 #ifndef D_NEEDGIANT 220 #define D_NEEDGIANT 0x00400000 /* driver want Giant */ 221 #endif 222 #ifndef D_VERSION 223 #define D_VERSION 0x20011966 224 #endif 225 static struct cdevsw arcmsr_cdevsw={ 226 #if __FreeBSD_version > 502010 227 .d_version = D_VERSION, 228 #endif 229 .d_flags = D_NEEDGIANT, 230 .d_open = arcmsr_open, /* open */ 231 .d_close = arcmsr_close, /* close */ 232 .d_ioctl = arcmsr_ioctl, /* ioctl */ 233 .d_name = "arcmsr", /* name */ 234 }; 235 #else 236 #define ARCMSR_CDEV_MAJOR 180 237 238 static struct cdevsw arcmsr_cdevsw = { 239 arcmsr_open, /* open */ 240 arcmsr_close, /* close */ 241 noread, /* read */ 242 nowrite, /* write */ 243 arcmsr_ioctl, /* ioctl */ 244 nopoll, /* poll */ 245 nommap, /* mmap */ 246 nostrategy, /* strategy */ 247 "arcmsr", /* name */ 248 ARCMSR_CDEV_MAJOR, /* major */ 249 nodump, /* dump */ 250 nopsize, /* psize */ 251 0 /* flags */ 252 }; 253 #endif 254 /* 255 ************************************************************************** 256 ************************************************************************** 257 */ 258 #if __FreeBSD_version < 500005 259 static int arcmsr_open(dev_t dev, int flags, int fmt, struct proc *proc) 260 #else 261 #if __FreeBSD_version < 503000 262 static int arcmsr_open(dev_t dev, int flags, int fmt, struct thread *proc) 263 #else 264 static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc) 265 #endif 266 #endif 267 { 268 #if __FreeBSD_version < 503000 269 struct AdapterControlBlock *acb=dev->si_drv1; 270 #else 271 int unit = dev2unit(dev); 272 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 273 #endif 274 if(acb==NULL) { 275 return ENXIO; 276 } 277 return 0; 278 } 279 /* 280 ************************************************************************** 281 ************************************************************************** 282 */ 283 #if __FreeBSD_version < 500005 284 static int arcmsr_close(dev_t dev, int flags, int fmt, struct proc *proc) 285 #else 286 #if __FreeBSD_version < 503000 287 static int arcmsr_close(dev_t dev, int flags, int fmt, struct thread *proc) 288 #else 289 static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc) 290 #endif 291 #endif 292 { 293 #if __FreeBSD_version < 503000 294 struct AdapterControlBlock *acb=dev->si_drv1; 295 #else 296 int unit = dev2unit(dev); 297 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 298 #endif 299 if(acb==NULL) { 300 return ENXIO; 301 } 302 return 0; 303 } 304 /* 305 ************************************************************************** 306 ************************************************************************** 307 */ 308 #if __FreeBSD_version < 500005 309 static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct proc *proc) 310 #else 311 #if __FreeBSD_version < 503000 312 static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc) 313 #else 314 static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc) 315 #endif 316 #endif 317 { 318 #if __FreeBSD_version < 503000 319 struct AdapterControlBlock *acb=dev->si_drv1; 320 #else 321 int unit = dev2unit(dev); 322 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 323 #endif 324 325 if(acb==NULL) { 326 return ENXIO; 327 } 328 return(arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg)); 329 } 330 /* 331 ********************************************************************** 332 ********************************************************************** 333 */ 334 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb) 335 { 336 u_int32_t intmask_org=0; 337 338 switch (acb->adapter_type) { 339 case ACB_ADAPTER_TYPE_A: { 340 /* disable all outbound interrupt */ 341 intmask_org=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */ 342 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE); 343 } 344 break; 345 case ACB_ADAPTER_TYPE_B: { 346 /* disable all outbound interrupt */ 347 intmask_org=CHIP_REG_READ32(HBB_DOORBELL, 348 0, iop2drv_doorbell_mask) & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */ 349 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell_mask, 0); /* disable all interrupt */ 350 } 351 break; 352 case ACB_ADAPTER_TYPE_C: { 353 /* disable all outbound interrupt */ 354 intmask_org=CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask) ; /* disable outbound message0 int */ 355 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE); 356 } 357 break; 358 } 359 return(intmask_org); 360 } 361 /* 362 ********************************************************************** 363 ********************************************************************** 364 */ 365 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org) 366 { 367 u_int32_t mask; 368 369 switch (acb->adapter_type) { 370 case ACB_ADAPTER_TYPE_A: { 371 /* enable outbound Post Queue, outbound doorbell Interrupt */ 372 mask=~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE); 373 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask); 374 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff; 375 } 376 break; 377 case ACB_ADAPTER_TYPE_B: { 378 /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */ 379 mask=(ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); 380 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/ 381 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f; 382 } 383 break; 384 case ACB_ADAPTER_TYPE_C: { 385 /* enable outbound Post Queue, outbound doorbell Interrupt */ 386 mask=~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK); 387 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask); 388 acb->outbound_int_enable= ~(intmask_org & mask) & 0x0000000f; 389 } 390 break; 391 } 392 return; 393 } 394 /* 395 ********************************************************************** 396 ********************************************************************** 397 */ 398 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb) 399 { 400 u_int32_t Index; 401 u_int8_t Retries=0x00; 402 403 do { 404 for(Index=0; Index < 100; Index++) { 405 if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 406 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/ 407 return TRUE; 408 } 409 UDELAY(10000); 410 }/*max 1 seconds*/ 411 }while(Retries++ < 20);/*max 20 sec*/ 412 return FALSE; 413 } 414 /* 415 ********************************************************************** 416 ********************************************************************** 417 */ 418 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb) 419 { 420 u_int32_t Index; 421 u_int8_t Retries=0x00; 422 423 do { 424 for(Index=0; Index < 100; Index++) { 425 if(CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 426 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/ 427 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 428 return TRUE; 429 } 430 UDELAY(10000); 431 }/*max 1 seconds*/ 432 }while(Retries++ < 20);/*max 20 sec*/ 433 return FALSE; 434 } 435 /* 436 ********************************************************************** 437 ********************************************************************** 438 */ 439 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb) 440 { 441 u_int32_t Index; 442 u_int8_t Retries=0x00; 443 444 do { 445 for(Index=0; Index < 100; Index++) { 446 if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 447 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/ 448 return TRUE; 449 } 450 UDELAY(10000); 451 }/*max 1 seconds*/ 452 }while(Retries++ < 20);/*max 20 sec*/ 453 return FALSE; 454 } 455 /* 456 ************************************************************************ 457 ************************************************************************ 458 */ 459 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb) 460 { 461 int retry_count=30;/* enlarge wait flush adapter cache time: 10 minute */ 462 463 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 464 do { 465 if(arcmsr_hba_wait_msgint_ready(acb)) { 466 break; 467 } else { 468 retry_count--; 469 } 470 }while(retry_count!=0); 471 return; 472 } 473 /* 474 ************************************************************************ 475 ************************************************************************ 476 */ 477 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb) 478 { 479 int retry_count=30;/* enlarge wait flush adapter cache time: 10 minute */ 480 481 CHIP_REG_WRITE32(HBB_DOORBELL, 482 0, drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE); 483 do { 484 if(arcmsr_hbb_wait_msgint_ready(acb)) { 485 break; 486 } else { 487 retry_count--; 488 } 489 }while(retry_count!=0); 490 return; 491 } 492 /* 493 ************************************************************************ 494 ************************************************************************ 495 */ 496 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb) 497 { 498 int retry_count=30;/* enlarge wait flush adapter cache time: 10 minute */ 499 500 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 501 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 502 do { 503 if(arcmsr_hbc_wait_msgint_ready(acb)) { 504 break; 505 } else { 506 retry_count--; 507 } 508 }while(retry_count!=0); 509 return; 510 } 511 /* 512 ************************************************************************ 513 ************************************************************************ 514 */ 515 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb) 516 { 517 switch (acb->adapter_type) { 518 case ACB_ADAPTER_TYPE_A: { 519 arcmsr_flush_hba_cache(acb); 520 } 521 break; 522 case ACB_ADAPTER_TYPE_B: { 523 arcmsr_flush_hbb_cache(acb); 524 } 525 break; 526 case ACB_ADAPTER_TYPE_C: { 527 arcmsr_flush_hbc_cache(acb); 528 } 529 break; 530 } 531 return; 532 } 533 /* 534 ******************************************************************************* 535 ******************************************************************************* 536 */ 537 static int arcmsr_suspend(device_t dev) 538 { 539 struct AdapterControlBlock *acb = device_get_softc(dev); 540 541 /* flush controller */ 542 arcmsr_iop_parking(acb); 543 /* disable all outbound interrupt */ 544 arcmsr_disable_allintr(acb); 545 return(0); 546 } 547 /* 548 ******************************************************************************* 549 ******************************************************************************* 550 */ 551 static int arcmsr_resume(device_t dev) 552 { 553 struct AdapterControlBlock *acb = device_get_softc(dev); 554 555 arcmsr_iop_init(acb); 556 return(0); 557 } 558 /* 559 ********************************************************************************* 560 ********************************************************************************* 561 */ 562 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg) 563 { 564 struct AdapterControlBlock *acb; 565 u_int8_t target_id, target_lun; 566 struct cam_sim * sim; 567 568 sim=(struct cam_sim *) cb_arg; 569 acb =(struct AdapterControlBlock *) cam_sim_softc(sim); 570 switch (code) { 571 case AC_LOST_DEVICE: 572 target_id=xpt_path_target_id(path); 573 target_lun=xpt_path_lun_id(path); 574 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) { 575 break; 576 } 577 printf("%s:scsi id=%d lun=%d device lost \n", device_get_name(acb->pci_dev), target_id, target_lun); 578 break; 579 default: 580 break; 581 } 582 } 583 /* 584 ********************************************************************** 585 ********************************************************************** 586 */ 587 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag) 588 { 589 struct AdapterControlBlock *acb=srb->acb; 590 union ccb * pccb=srb->pccb; 591 592 if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 593 bus_dmasync_op_t op; 594 595 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 596 op = BUS_DMASYNC_POSTREAD; 597 } else { 598 op = BUS_DMASYNC_POSTWRITE; 599 } 600 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 601 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 602 } 603 if(stand_flag==1) { 604 atomic_subtract_int(&acb->srboutstandingcount, 1); 605 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && ( 606 acb->srboutstandingcount < ARCMSR_RELEASE_SIMQ_LEVEL)) { 607 acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN; 608 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 609 } 610 } 611 srb->startdone=ARCMSR_SRB_DONE; 612 srb->srb_flags=0; 613 acb->srbworkingQ[acb->workingsrb_doneindex]=srb; 614 acb->workingsrb_doneindex++; 615 acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM; 616 xpt_done(pccb); 617 return; 618 } 619 /* 620 ********************************************************************** 621 ********************************************************************** 622 */ 623 static void arcmsr_report_sense_info(struct CommandControlBlock *srb) 624 { 625 union ccb * pccb=srb->pccb; 626 627 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 628 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 629 if(&pccb->csio.sense_data) { 630 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data)); 631 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData, 632 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data))); 633 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */ 634 pccb->ccb_h.status |= CAM_AUTOSNS_VALID; 635 } 636 return; 637 } 638 /* 639 ********************************************************************* 640 ********************************************************************* 641 */ 642 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb) 643 { 644 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 645 if(!arcmsr_hba_wait_msgint_ready(acb)) { 646 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 647 } 648 return; 649 } 650 /* 651 ********************************************************************* 652 ********************************************************************* 653 */ 654 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb) 655 { 656 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD); 657 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 658 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 659 } 660 return; 661 } 662 /* 663 ********************************************************************* 664 ********************************************************************* 665 */ 666 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb) 667 { 668 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 669 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 670 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 671 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 672 } 673 return; 674 } 675 /* 676 ********************************************************************* 677 ********************************************************************* 678 */ 679 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb) 680 { 681 switch (acb->adapter_type) { 682 case ACB_ADAPTER_TYPE_A: { 683 arcmsr_abort_hba_allcmd(acb); 684 } 685 break; 686 case ACB_ADAPTER_TYPE_B: { 687 arcmsr_abort_hbb_allcmd(acb); 688 } 689 break; 690 case ACB_ADAPTER_TYPE_C: { 691 arcmsr_abort_hbc_allcmd(acb); 692 } 693 break; 694 } 695 return; 696 } 697 /* 698 ************************************************************************** 699 ************************************************************************** 700 */ 701 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error) 702 { 703 int target, lun; 704 705 target=srb->pccb->ccb_h.target_id; 706 lun=srb->pccb->ccb_h.target_lun; 707 if(error == FALSE) { 708 if(acb->devstate[target][lun]==ARECA_RAID_GONE) { 709 acb->devstate[target][lun]=ARECA_RAID_GOOD; 710 } 711 srb->pccb->ccb_h.status |= CAM_REQ_CMP; 712 arcmsr_srb_complete(srb, 1); 713 } else { 714 switch(srb->arcmsr_cdb.DeviceStatus) { 715 case ARCMSR_DEV_SELECT_TIMEOUT: { 716 if(acb->devstate[target][lun]==ARECA_RAID_GOOD) { 717 printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun); 718 } 719 acb->devstate[target][lun]=ARECA_RAID_GONE; 720 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 721 arcmsr_srb_complete(srb, 1); 722 } 723 break; 724 case ARCMSR_DEV_ABORTED: 725 case ARCMSR_DEV_INIT_FAIL: { 726 acb->devstate[target][lun]=ARECA_RAID_GONE; 727 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 728 arcmsr_srb_complete(srb, 1); 729 } 730 break; 731 case SCSISTAT_CHECK_CONDITION: { 732 acb->devstate[target][lun]=ARECA_RAID_GOOD; 733 arcmsr_report_sense_info(srb); 734 arcmsr_srb_complete(srb, 1); 735 } 736 break; 737 default: 738 printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknow DeviceStatus=0x%x \n" 739 , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus); 740 acb->devstate[target][lun]=ARECA_RAID_GONE; 741 srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY; 742 /*unknow error or crc error just for retry*/ 743 arcmsr_srb_complete(srb, 1); 744 break; 745 } 746 } 747 return; 748 } 749 /* 750 ************************************************************************** 751 ************************************************************************** 752 */ 753 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error) 754 { 755 struct CommandControlBlock *srb; 756 757 /* check if command done with no error*/ 758 switch (acb->adapter_type) { 759 case ACB_ADAPTER_TYPE_C: 760 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFF0));/*frame must be 32 bytes aligned*/ 761 break; 762 case ACB_ADAPTER_TYPE_A: 763 case ACB_ADAPTER_TYPE_B: 764 default: 765 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 766 break; 767 } 768 if((srb->acb!=acb) || (srb->startdone!=ARCMSR_SRB_START)) { 769 if(srb->startdone==ARCMSR_SRB_ABORTED) { 770 printf("arcmsr%d: srb='%p' isr got aborted command \n", acb->pci_unit, srb); 771 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 772 arcmsr_srb_complete(srb, 1); 773 return; 774 } 775 printf("arcmsr%d: isr get an illegal srb command done" 776 "acb='%p' srb='%p' srbacb='%p' startdone=0x%xsrboutstandingcount=%d \n", 777 acb->pci_unit, acb, srb, srb->acb,srb->startdone, acb->srboutstandingcount); 778 return; 779 } 780 arcmsr_report_srb_state(acb, srb, error); 781 return; 782 } 783 /* 784 ********************************************************************** 785 ********************************************************************** 786 */ 787 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb) 788 { 789 int i=0; 790 u_int32_t flag_srb; 791 u_int16_t error; 792 793 switch (acb->adapter_type) { 794 case ACB_ADAPTER_TYPE_A: { 795 u_int32_t outbound_intstatus; 796 797 /*clear and abort all outbound posted Q*/ 798 outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 799 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/ 800 while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 801 error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 802 arcmsr_drain_donequeue(acb, flag_srb, error); 803 } 804 } 805 break; 806 case ACB_ADAPTER_TYPE_B: { 807 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu; 808 809 /*clear all outbound posted Q*/ 810 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 811 for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) { 812 if((flag_srb=phbbmu->done_qbuffer[i])!=0) { 813 phbbmu->done_qbuffer[i]=0; 814 error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 815 arcmsr_drain_donequeue(acb, flag_srb, error); 816 } 817 phbbmu->post_qbuffer[i]=0; 818 }/*drain reply FIFO*/ 819 phbbmu->doneq_index=0; 820 phbbmu->postq_index=0; 821 } 822 break; 823 case ACB_ADAPTER_TYPE_C: { 824 825 while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 826 flag_srb=CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 827 error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 828 arcmsr_drain_donequeue(acb, flag_srb, error); 829 } 830 } 831 break; 832 } 833 return; 834 } 835 /* 836 **************************************************************************** 837 **************************************************************************** 838 */ 839 static void arcmsr_iop_reset(struct AdapterControlBlock *acb) 840 { 841 struct CommandControlBlock *srb; 842 u_int32_t intmask_org; 843 u_int32_t i=0; 844 845 if(acb->srboutstandingcount>0) { 846 /* disable all outbound interrupt */ 847 intmask_org=arcmsr_disable_allintr(acb); 848 /*clear and abort all outbound posted Q*/ 849 arcmsr_done4abort_postqueue(acb); 850 /* talk to iop 331 outstanding command aborted*/ 851 arcmsr_abort_allcmd(acb); 852 for(i=0;i<ARCMSR_MAX_FREESRB_NUM;i++) { 853 srb=acb->psrb_pool[i]; 854 if(srb->startdone==ARCMSR_SRB_START) { 855 srb->startdone=ARCMSR_SRB_ABORTED; 856 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 857 arcmsr_srb_complete(srb, 1); 858 } 859 } 860 /* enable all outbound interrupt */ 861 arcmsr_enable_allintr(acb, intmask_org); 862 } 863 atomic_set_int(&acb->srboutstandingcount, 0); 864 acb->workingsrb_doneindex=0; 865 acb->workingsrb_startindex=0; 866 return; 867 } 868 /* 869 ********************************************************************** 870 ********************************************************************** 871 */ 872 static void arcmsr_build_srb(struct CommandControlBlock *srb, 873 bus_dma_segment_t *dm_segs, u_int32_t nseg) 874 { 875 struct ARCMSR_CDB * arcmsr_cdb= &srb->arcmsr_cdb; 876 u_int8_t * psge=(u_int8_t *)&arcmsr_cdb->u; 877 u_int32_t address_lo, address_hi; 878 union ccb * pccb=srb->pccb; 879 struct ccb_scsiio * pcsio= &pccb->csio; 880 u_int32_t arccdbsize=0x30; 881 882 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB)); 883 arcmsr_cdb->Bus=0; 884 arcmsr_cdb->TargetID=pccb->ccb_h.target_id; 885 arcmsr_cdb->LUN=pccb->ccb_h.target_lun; 886 arcmsr_cdb->Function=1; 887 arcmsr_cdb->CdbLength=(u_int8_t)pcsio->cdb_len; 888 arcmsr_cdb->Context=0; 889 bcopy(pcsio->cdb_io.cdb_bytes, arcmsr_cdb->Cdb, pcsio->cdb_len); 890 if(nseg != 0) { 891 struct AdapterControlBlock *acb=srb->acb; 892 bus_dmasync_op_t op; 893 u_int32_t length, i, cdb_sgcount=0; 894 895 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 896 op=BUS_DMASYNC_PREREAD; 897 } else { 898 op=BUS_DMASYNC_PREWRITE; 899 arcmsr_cdb->Flags|=ARCMSR_CDB_FLAG_WRITE; 900 srb->srb_flags|=SRB_FLAG_WRITE; 901 } 902 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 903 for(i=0;i<nseg;i++) { 904 /* Get the physical address of the current data pointer */ 905 length=arcmsr_htole32(dm_segs[i].ds_len); 906 address_lo=arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr)); 907 address_hi=arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr)); 908 if(address_hi==0) { 909 struct SG32ENTRY * pdma_sg=(struct SG32ENTRY *)psge; 910 pdma_sg->address=address_lo; 911 pdma_sg->length=length; 912 psge += sizeof(struct SG32ENTRY); 913 arccdbsize += sizeof(struct SG32ENTRY); 914 } else { 915 u_int32_t sg64s_size=0, tmplength=length; 916 917 while(1) { 918 u_int64_t span4G, length0; 919 struct SG64ENTRY * pdma_sg=(struct SG64ENTRY *)psge; 920 921 span4G=(u_int64_t)address_lo + tmplength; 922 pdma_sg->addresshigh=address_hi; 923 pdma_sg->address=address_lo; 924 if(span4G > 0x100000000) { 925 /*see if cross 4G boundary*/ 926 length0=0x100000000-address_lo; 927 pdma_sg->length=(u_int32_t)length0|IS_SG64_ADDR; 928 address_hi=address_hi+1; 929 address_lo=0; 930 tmplength=tmplength-(u_int32_t)length0; 931 sg64s_size += sizeof(struct SG64ENTRY); 932 psge += sizeof(struct SG64ENTRY); 933 cdb_sgcount++; 934 } else { 935 pdma_sg->length=tmplength|IS_SG64_ADDR; 936 sg64s_size += sizeof(struct SG64ENTRY); 937 psge += sizeof(struct SG64ENTRY); 938 break; 939 } 940 } 941 arccdbsize += sg64s_size; 942 } 943 cdb_sgcount++; 944 } 945 arcmsr_cdb->sgcount=(u_int8_t)cdb_sgcount; 946 arcmsr_cdb->DataLength=pcsio->dxfer_len; 947 if( arccdbsize > 256) { 948 arcmsr_cdb->Flags|=ARCMSR_CDB_FLAG_SGL_BSIZE; 949 } 950 } else { 951 arcmsr_cdb->DataLength = 0; 952 } 953 srb->arc_cdb_size=arccdbsize; 954 return; 955 } 956 /* 957 ************************************************************************** 958 ************************************************************************** 959 */ 960 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb) 961 { 962 u_int32_t cdb_shifted_phyaddr=(u_int32_t) srb->cdb_shifted_phyaddr; 963 struct ARCMSR_CDB * arcmsr_cdb=(struct ARCMSR_CDB *)&srb->arcmsr_cdb; 964 965 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD); 966 atomic_add_int(&acb->srboutstandingcount, 1); 967 srb->startdone=ARCMSR_SRB_START; 968 969 switch (acb->adapter_type) { 970 case ACB_ADAPTER_TYPE_A: { 971 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 972 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_shifted_phyaddr|ARCMSR_SRBPOST_FLAG_SGL_BSIZE); 973 } else { 974 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_shifted_phyaddr); 975 } 976 } 977 break; 978 case ACB_ADAPTER_TYPE_B: { 979 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu; 980 int ending_index, index; 981 982 index=phbbmu->postq_index; 983 ending_index=((index+1)%ARCMSR_MAX_HBB_POSTQUEUE); 984 phbbmu->post_qbuffer[ending_index]=0; 985 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 986 phbbmu->post_qbuffer[index]= cdb_shifted_phyaddr|ARCMSR_SRBPOST_FLAG_SGL_BSIZE; 987 } else { 988 phbbmu->post_qbuffer[index]= cdb_shifted_phyaddr; 989 } 990 index++; 991 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 992 phbbmu->postq_index=index; 993 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED); 994 } 995 break; 996 case ACB_ADAPTER_TYPE_C: 997 { 998 u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32; 999 1000 arc_cdb_size=(srb->arc_cdb_size>0x300)?0x300:srb->arc_cdb_size; 1001 ccb_post_stamp=(cdb_shifted_phyaddr | ((arc_cdb_size-1) >> 6) | 1); 1002 cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 1003 if(cdb_phyaddr_hi32) 1004 { 1005 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32); 1006 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1007 } 1008 else 1009 { 1010 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1011 } 1012 } 1013 break; 1014 } 1015 return; 1016 } 1017 /* 1018 ************************************************************************ 1019 ************************************************************************ 1020 */ 1021 static struct QBUFFER * arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb) 1022 { 1023 struct QBUFFER *qbuffer=NULL; 1024 1025 switch (acb->adapter_type) { 1026 case ACB_ADAPTER_TYPE_A: { 1027 struct HBA_MessageUnit *phbamu=(struct HBA_MessageUnit *)acb->pmu; 1028 1029 qbuffer=(struct QBUFFER *)&phbamu->message_rbuffer; 1030 } 1031 break; 1032 case ACB_ADAPTER_TYPE_B: { 1033 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu; 1034 1035 qbuffer=(struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer; 1036 } 1037 break; 1038 case ACB_ADAPTER_TYPE_C: { 1039 struct HBC_MessageUnit *phbcmu=(struct HBC_MessageUnit *)acb->pmu; 1040 1041 qbuffer=(struct QBUFFER *)&phbcmu->message_rbuffer; 1042 } 1043 break; 1044 } 1045 return(qbuffer); 1046 } 1047 /* 1048 ************************************************************************ 1049 ************************************************************************ 1050 */ 1051 static struct QBUFFER * arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb) 1052 { 1053 struct QBUFFER *qbuffer=NULL; 1054 1055 switch (acb->adapter_type) { 1056 case ACB_ADAPTER_TYPE_A: { 1057 struct HBA_MessageUnit *phbamu=(struct HBA_MessageUnit *)acb->pmu; 1058 1059 qbuffer=(struct QBUFFER *)&phbamu->message_wbuffer; 1060 } 1061 break; 1062 case ACB_ADAPTER_TYPE_B: { 1063 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu; 1064 1065 qbuffer=(struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer; 1066 } 1067 break; 1068 case ACB_ADAPTER_TYPE_C: { 1069 struct HBC_MessageUnit *phbcmu=(struct HBC_MessageUnit *)acb->pmu; 1070 1071 qbuffer=(struct QBUFFER *)&phbcmu->message_wbuffer; 1072 } 1073 break; 1074 } 1075 return(qbuffer); 1076 } 1077 /* 1078 ************************************************************************** 1079 ************************************************************************** 1080 */ 1081 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb) 1082 { 1083 switch (acb->adapter_type) { 1084 case ACB_ADAPTER_TYPE_A: { 1085 /* let IOP know data has been read */ 1086 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 1087 } 1088 break; 1089 case ACB_ADAPTER_TYPE_B: { 1090 /* let IOP know data has been read */ 1091 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 1092 } 1093 break; 1094 case ACB_ADAPTER_TYPE_C: { 1095 /* let IOP know data has been read */ 1096 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 1097 } 1098 } 1099 return; 1100 } 1101 /* 1102 ************************************************************************** 1103 ************************************************************************** 1104 */ 1105 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb) 1106 { 1107 switch (acb->adapter_type) { 1108 case ACB_ADAPTER_TYPE_A: { 1109 /* 1110 ** push inbound doorbell tell iop, driver data write ok 1111 ** and wait reply on next hwinterrupt for next Qbuffer post 1112 */ 1113 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK); 1114 } 1115 break; 1116 case ACB_ADAPTER_TYPE_B: { 1117 /* 1118 ** push inbound doorbell tell iop, driver data write ok 1119 ** and wait reply on next hwinterrupt for next Qbuffer post 1120 */ 1121 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK); 1122 } 1123 break; 1124 case ACB_ADAPTER_TYPE_C: { 1125 /* 1126 ** push inbound doorbell tell iop, driver data write ok 1127 ** and wait reply on next hwinterrupt for next Qbuffer post 1128 */ 1129 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK); 1130 } 1131 break; 1132 } 1133 } 1134 /* 1135 ********************************************************************** 1136 ********************************************************************** 1137 */ 1138 static void arcmsr_post_ioctldata2iop(struct AdapterControlBlock *acb) 1139 { 1140 u_int8_t *pQbuffer; 1141 struct QBUFFER *pwbuffer; 1142 u_int8_t * iop_data; 1143 int32_t allxfer_len=0; 1144 1145 pwbuffer=arcmsr_get_iop_wqbuffer(acb); 1146 iop_data=(u_int8_t *)pwbuffer->data; 1147 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1148 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1149 while((acb->wqbuf_firstindex!=acb->wqbuf_lastindex) 1150 && (allxfer_len<124)) { 1151 pQbuffer=&acb->wqbuffer[acb->wqbuf_firstindex]; 1152 memcpy(iop_data, pQbuffer, 1); 1153 acb->wqbuf_firstindex++; 1154 acb->wqbuf_firstindex %=ARCMSR_MAX_QBUFFER; /*if last index number set it to 0 */ 1155 iop_data++; 1156 allxfer_len++; 1157 } 1158 pwbuffer->data_len=allxfer_len; 1159 /* 1160 ** push inbound doorbell and wait reply at hwinterrupt routine for next Qbuffer post 1161 */ 1162 arcmsr_iop_message_wrote(acb); 1163 } 1164 return; 1165 } 1166 /* 1167 ************************************************************************ 1168 ************************************************************************ 1169 */ 1170 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb) 1171 { 1172 acb->acb_flags &=~ACB_F_MSG_START_BGRB; 1173 CHIP_REG_WRITE32(HBA_MessageUnit, 1174 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1175 if(!arcmsr_hba_wait_msgint_ready(acb)) { 1176 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1177 , acb->pci_unit); 1178 } 1179 return; 1180 } 1181 /* 1182 ************************************************************************ 1183 ************************************************************************ 1184 */ 1185 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb) 1186 { 1187 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1188 CHIP_REG_WRITE32(HBB_DOORBELL, 1189 0, drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB); 1190 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 1191 printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1192 , acb->pci_unit); 1193 } 1194 return; 1195 } 1196 /* 1197 ************************************************************************ 1198 ************************************************************************ 1199 */ 1200 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb) 1201 { 1202 acb->acb_flags &=~ACB_F_MSG_START_BGRB; 1203 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1204 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 1205 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 1206 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1207 } 1208 return; 1209 } 1210 /* 1211 ************************************************************************ 1212 ************************************************************************ 1213 */ 1214 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb) 1215 { 1216 switch (acb->adapter_type) { 1217 case ACB_ADAPTER_TYPE_A: { 1218 arcmsr_stop_hba_bgrb(acb); 1219 } 1220 break; 1221 case ACB_ADAPTER_TYPE_B: { 1222 arcmsr_stop_hbb_bgrb(acb); 1223 } 1224 break; 1225 case ACB_ADAPTER_TYPE_C: { 1226 arcmsr_stop_hbc_bgrb(acb); 1227 } 1228 break; 1229 } 1230 return; 1231 } 1232 /* 1233 ************************************************************************ 1234 ************************************************************************ 1235 */ 1236 static void arcmsr_poll(struct cam_sim * psim) 1237 { 1238 struct AdapterControlBlock *acb; 1239 1240 acb = (struct AdapterControlBlock *)cam_sim_softc(psim); 1241 #if __FreeBSD_version < 700025 1242 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1243 #endif 1244 arcmsr_interrupt(acb); 1245 #if __FreeBSD_version < 700025 1246 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1247 #endif 1248 return; 1249 } 1250 /* 1251 ************************************************************************** 1252 ************************************************************************** 1253 */ 1254 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb) 1255 { 1256 struct QBUFFER *prbuffer; 1257 u_int8_t *pQbuffer; 1258 u_int8_t *iop_data; 1259 int my_empty_len, iop_len, rqbuf_firstindex, rqbuf_lastindex; 1260 1261 /*check this iop data if overflow my rqbuffer*/ 1262 rqbuf_lastindex=acb->rqbuf_lastindex; 1263 rqbuf_firstindex=acb->rqbuf_firstindex; 1264 prbuffer=arcmsr_get_iop_rqbuffer(acb); 1265 iop_data=(u_int8_t *)prbuffer->data; 1266 iop_len=prbuffer->data_len; 1267 my_empty_len=(rqbuf_firstindex-rqbuf_lastindex-1)&(ARCMSR_MAX_QBUFFER-1); 1268 if(my_empty_len>=iop_len) { 1269 while(iop_len > 0) { 1270 pQbuffer=&acb->rqbuffer[rqbuf_lastindex]; 1271 memcpy(pQbuffer, iop_data, 1); 1272 rqbuf_lastindex++; 1273 rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;/*if last index number set it to 0 */ 1274 iop_data++; 1275 iop_len--; 1276 } 1277 acb->rqbuf_lastindex=rqbuf_lastindex; 1278 arcmsr_iop_message_read(acb); 1279 /*signature, let IOP know data has been read */ 1280 } else { 1281 acb->acb_flags|=ACB_F_IOPDATA_OVERFLOW; 1282 } 1283 return; 1284 } 1285 /* 1286 ************************************************************************** 1287 ************************************************************************** 1288 */ 1289 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb) 1290 { 1291 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ; 1292 /* 1293 ***************************************************************** 1294 ** check if there are any mail packages from user space program 1295 ** in my post bag, now is the time to send them into Areca's firmware 1296 ***************************************************************** 1297 */ 1298 if(acb->wqbuf_firstindex!=acb->wqbuf_lastindex) { 1299 u_int8_t *pQbuffer; 1300 struct QBUFFER *pwbuffer; 1301 u_int8_t *iop_data; 1302 int allxfer_len=0; 1303 1304 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1305 pwbuffer=arcmsr_get_iop_wqbuffer(acb); 1306 iop_data=(u_int8_t *)pwbuffer->data; 1307 while((acb->wqbuf_firstindex!=acb->wqbuf_lastindex) 1308 && (allxfer_len<124)) { 1309 pQbuffer=&acb->wqbuffer[acb->wqbuf_firstindex]; 1310 memcpy(iop_data, pQbuffer, 1); 1311 acb->wqbuf_firstindex++; 1312 acb->wqbuf_firstindex %=ARCMSR_MAX_QBUFFER; /*if last index number set it to 0 */ 1313 iop_data++; 1314 allxfer_len++; 1315 } 1316 pwbuffer->data_len=allxfer_len; 1317 /* 1318 ** push inbound doorbell tell iop driver data write ok 1319 ** and wait reply on next hwinterrupt for next Qbuffer post 1320 */ 1321 arcmsr_iop_message_wrote(acb); 1322 } 1323 if(acb->wqbuf_firstindex==acb->wqbuf_lastindex) { 1324 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED; 1325 } 1326 return; 1327 } 1328 1329 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb) 1330 { 1331 /* 1332 if (ccb->ccb_h.status != CAM_REQ_CMP) 1333 printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x, failure status=%x\n",ccb->ccb_h.target_id,ccb->ccb_h.target_lun,ccb->ccb_h.status); 1334 else 1335 printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n"); 1336 */ 1337 xpt_free_path(ccb->ccb_h.path); 1338 xpt_free_ccb(ccb); 1339 } 1340 1341 static void arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun) 1342 { 1343 struct cam_path *path; 1344 union ccb *ccb; 1345 1346 if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL) 1347 return; 1348 if (xpt_create_path(&path, xpt_periph, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP) 1349 { 1350 xpt_free_ccb(ccb); 1351 return; 1352 } 1353 /* printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */ 1354 bzero(ccb, sizeof(union ccb)); 1355 xpt_setup_ccb(&ccb->ccb_h, path, 5); 1356 ccb->ccb_h.func_code = XPT_SCAN_LUN; 1357 ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb; 1358 ccb->crcn.flags = CAM_FLAG_NONE; 1359 xpt_action(ccb); 1360 return; 1361 } 1362 1363 1364 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun) 1365 { 1366 struct CommandControlBlock *srb; 1367 u_int32_t intmask_org; 1368 int i; 1369 1370 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1371 /* disable all outbound interrupts */ 1372 intmask_org = arcmsr_disable_allintr(acb); 1373 for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++) 1374 { 1375 srb = acb->psrb_pool[i]; 1376 if (srb->startdone == ARCMSR_SRB_START) 1377 { 1378 if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun)) 1379 { 1380 srb->startdone = ARCMSR_SRB_ABORTED; 1381 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 1382 arcmsr_srb_complete(srb, 1); 1383 } 1384 } 1385 } 1386 /* enable outbound Post Queue, outbound doorbell Interrupt */ 1387 arcmsr_enable_allintr(acb, intmask_org); 1388 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1389 } 1390 1391 1392 /* 1393 ************************************************************************** 1394 ************************************************************************** 1395 */ 1396 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) { 1397 u_int32_t devicemap; 1398 u_int32_t target, lun; 1399 u_int32_t deviceMapCurrent[4]={0}; 1400 u_int8_t *pDevMap; 1401 1402 switch (acb->adapter_type) { 1403 case ACB_ADAPTER_TYPE_A: 1404 devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1405 for (target= 0; target < 4; target++) 1406 { 1407 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1408 devicemap += 4; 1409 } 1410 break; 1411 1412 case ACB_ADAPTER_TYPE_B: 1413 devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1414 for (target= 0; target < 4; target++) 1415 { 1416 deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1], devicemap); 1417 devicemap += 4; 1418 } 1419 break; 1420 1421 case ACB_ADAPTER_TYPE_C: 1422 devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1423 for (target= 0; target < 4; target++) 1424 { 1425 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1426 devicemap += 4; 1427 } 1428 break; 1429 } 1430 if(acb->acb_flags & ACB_F_BUS_HANG_ON) 1431 { 1432 acb->acb_flags &= ~ACB_F_BUS_HANG_ON; 1433 } 1434 /* 1435 ** adapter posted CONFIG message 1436 ** copy the new map, note if there are differences with the current map 1437 */ 1438 pDevMap = (u_int8_t *)&deviceMapCurrent[0]; 1439 for (target= 0; target < ARCMSR_MAX_TARGETID - 1; target++) 1440 { 1441 if (*pDevMap != acb->device_map[target]) 1442 { 1443 u_int8_t difference, bit_check; 1444 1445 difference= *pDevMap ^ acb->device_map[target]; 1446 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++) 1447 { 1448 bit_check=(1 << lun); /*check bit from 0....31*/ 1449 if(difference & bit_check) 1450 { 1451 if(acb->device_map[target] & bit_check) 1452 {/* unit departed */ 1453 printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun); 1454 arcmsr_abort_dr_ccbs(acb, target, lun); 1455 arcmsr_rescan_lun(acb, target, lun); 1456 acb->devstate[target][lun] = ARECA_RAID_GONE; 1457 } 1458 else 1459 {/* unit arrived */ 1460 printf("arcmsr_dr_handle: Target=%x, lun=%x, ARRIVING!!!\n",target,lun); 1461 arcmsr_rescan_lun(acb, target, lun); 1462 acb->devstate[target][lun] = ARECA_RAID_GOOD; 1463 } 1464 } 1465 } 1466 /* printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */ 1467 acb->device_map[target]= *pDevMap; 1468 } 1469 pDevMap++; 1470 } 1471 } 1472 /* 1473 ************************************************************************** 1474 ************************************************************************** 1475 */ 1476 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) { 1477 u_int32_t outbound_message; 1478 1479 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT); 1480 outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]); 1481 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1482 arcmsr_dr_handle( acb ); 1483 } 1484 /* 1485 ************************************************************************** 1486 ************************************************************************** 1487 */ 1488 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) { 1489 u_int32_t outbound_message; 1490 1491 /* clear interrupts */ 1492 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN); 1493 outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]); 1494 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1495 arcmsr_dr_handle( acb ); 1496 } 1497 /* 1498 ************************************************************************** 1499 ************************************************************************** 1500 */ 1501 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) { 1502 u_int32_t outbound_message; 1503 1504 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR); 1505 outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]); 1506 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1507 arcmsr_dr_handle( acb ); 1508 } 1509 /* 1510 ************************************************************************** 1511 ************************************************************************** 1512 */ 1513 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb) 1514 { 1515 u_int32_t outbound_doorbell; 1516 1517 /* 1518 ******************************************************************* 1519 ** Maybe here we need to check wrqbuffer_lock is lock or not 1520 ** DOORBELL: din! don! 1521 ** check if there are any mail need to pack from firmware 1522 ******************************************************************* 1523 */ 1524 outbound_doorbell=CHIP_REG_READ32(HBA_MessageUnit, 1525 0, outbound_doorbell); 1526 CHIP_REG_WRITE32(HBA_MessageUnit, 1527 0, outbound_doorbell, outbound_doorbell); /* clear doorbell interrupt */ 1528 if(outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) { 1529 arcmsr_iop2drv_data_wrote_handle(acb); 1530 } 1531 if(outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) { 1532 arcmsr_iop2drv_data_read_handle(acb); 1533 } 1534 return; 1535 } 1536 /* 1537 ************************************************************************** 1538 ************************************************************************** 1539 */ 1540 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb) 1541 { 1542 u_int32_t outbound_doorbell; 1543 1544 /* 1545 ******************************************************************* 1546 ** Maybe here we need to check wrqbuffer_lock is lock or not 1547 ** DOORBELL: din! don! 1548 ** check if there are any mail need to pack from firmware 1549 ******************************************************************* 1550 */ 1551 outbound_doorbell=CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 1552 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /* clear doorbell interrupt */ 1553 if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) { 1554 arcmsr_iop2drv_data_wrote_handle(acb); 1555 } 1556 if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) { 1557 arcmsr_iop2drv_data_read_handle(acb); 1558 } 1559 if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 1560 arcmsr_hbc_message_isr(acb); /* messenger of "driver to iop commands" */ 1561 } 1562 return; 1563 } 1564 /* 1565 ************************************************************************** 1566 ************************************************************************** 1567 */ 1568 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb) 1569 { 1570 u_int32_t flag_srb; 1571 u_int16_t error; 1572 1573 /* 1574 ***************************************************************************** 1575 ** areca cdb command done 1576 ***************************************************************************** 1577 */ 1578 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 1579 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1580 while((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 1581 0, outbound_queueport)) != 0xFFFFFFFF) { 1582 /* check if command done with no error*/ 1583 error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 1584 arcmsr_drain_donequeue(acb, flag_srb, error); 1585 } /*drain reply FIFO*/ 1586 return; 1587 } 1588 /* 1589 ************************************************************************** 1590 ************************************************************************** 1591 */ 1592 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb) 1593 { 1594 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu; 1595 u_int32_t flag_srb; 1596 int index; 1597 u_int16_t error; 1598 1599 /* 1600 ***************************************************************************** 1601 ** areca cdb command done 1602 ***************************************************************************** 1603 */ 1604 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 1605 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1606 index=phbbmu->doneq_index; 1607 while((flag_srb=phbbmu->done_qbuffer[index]) != 0) { 1608 phbbmu->done_qbuffer[index]=0; 1609 index++; 1610 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 1611 phbbmu->doneq_index=index; 1612 /* check if command done with no error*/ 1613 error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 1614 arcmsr_drain_donequeue(acb, flag_srb, error); 1615 } /*drain reply FIFO*/ 1616 return; 1617 } 1618 /* 1619 ************************************************************************** 1620 ************************************************************************** 1621 */ 1622 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb) 1623 { 1624 u_int32_t flag_srb,throttling=0; 1625 u_int16_t error; 1626 1627 /* 1628 ***************************************************************************** 1629 ** areca cdb command done 1630 ***************************************************************************** 1631 */ 1632 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1633 1634 while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) { 1635 1636 flag_srb=CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 1637 /* check if command done with no error*/ 1638 error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 1639 arcmsr_drain_donequeue(acb, flag_srb, error); 1640 if(throttling==ARCMSR_HBC_ISR_THROTTLING_LEVEL) { 1641 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING); 1642 break; 1643 } 1644 throttling++; 1645 } /*drain reply FIFO*/ 1646 return; 1647 } 1648 /* 1649 ********************************************************************** 1650 ********************************************************************** 1651 */ 1652 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb) 1653 { 1654 u_int32_t outbound_intstatus; 1655 /* 1656 ********************************************* 1657 ** check outbound intstatus 1658 ********************************************* 1659 */ 1660 outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 1661 if(!outbound_intstatus) { 1662 /*it must be share irq*/ 1663 return; 1664 } 1665 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/ 1666 /* MU doorbell interrupts*/ 1667 if(outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) { 1668 arcmsr_hba_doorbell_isr(acb); 1669 } 1670 /* MU post queue interrupts*/ 1671 if(outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) { 1672 arcmsr_hba_postqueue_isr(acb); 1673 } 1674 if(outbound_intstatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 1675 arcmsr_hba_message_isr(acb); 1676 } 1677 return; 1678 } 1679 /* 1680 ********************************************************************** 1681 ********************************************************************** 1682 */ 1683 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb) 1684 { 1685 u_int32_t outbound_doorbell; 1686 /* 1687 ********************************************* 1688 ** check outbound intstatus 1689 ********************************************* 1690 */ 1691 outbound_doorbell=CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & acb->outbound_int_enable; 1692 if(!outbound_doorbell) { 1693 /*it must be share irq*/ 1694 return; 1695 } 1696 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */ 1697 CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell); 1698 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 1699 /* MU ioctl transfer doorbell interrupts*/ 1700 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) { 1701 arcmsr_iop2drv_data_wrote_handle(acb); 1702 } 1703 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) { 1704 arcmsr_iop2drv_data_read_handle(acb); 1705 } 1706 /* MU post queue interrupts*/ 1707 if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) { 1708 arcmsr_hbb_postqueue_isr(acb); 1709 } 1710 if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 1711 arcmsr_hbb_message_isr(acb); 1712 } 1713 return; 1714 } 1715 /* 1716 ********************************************************************** 1717 ********************************************************************** 1718 */ 1719 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb) 1720 { 1721 u_int32_t host_interrupt_status; 1722 /* 1723 ********************************************* 1724 ** check outbound intstatus 1725 ********************************************* 1726 */ 1727 host_interrupt_status=CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status); 1728 if(!host_interrupt_status) { 1729 /*it must be share irq*/ 1730 return; 1731 } 1732 /* MU doorbell interrupts*/ 1733 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) { 1734 arcmsr_hbc_doorbell_isr(acb); 1735 } 1736 /* MU post queue interrupts*/ 1737 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) { 1738 arcmsr_hbc_postqueue_isr(acb); 1739 } 1740 return; 1741 } 1742 /* 1743 ****************************************************************************** 1744 ****************************************************************************** 1745 */ 1746 static void arcmsr_interrupt(struct AdapterControlBlock *acb) 1747 { 1748 switch (acb->adapter_type) { 1749 case ACB_ADAPTER_TYPE_A: 1750 arcmsr_handle_hba_isr(acb); 1751 break; 1752 case ACB_ADAPTER_TYPE_B: 1753 arcmsr_handle_hbb_isr(acb); 1754 break; 1755 case ACB_ADAPTER_TYPE_C: 1756 arcmsr_handle_hbc_isr(acb); 1757 break; 1758 default: 1759 printf("arcmsr%d: interrupt service," 1760 " unknow adapter type =%d\n", acb->pci_unit, acb->adapter_type); 1761 break; 1762 } 1763 return; 1764 } 1765 /* 1766 ********************************************************************** 1767 ********************************************************************** 1768 */ 1769 static void arcmsr_intr_handler(void *arg) 1770 { 1771 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)arg; 1772 1773 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1774 arcmsr_interrupt(acb); 1775 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1776 } 1777 /* 1778 ****************************************************************************** 1779 ****************************************************************************** 1780 */ 1781 static void arcmsr_polling_devmap(void* arg) 1782 { 1783 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 1784 switch (acb->adapter_type) { 1785 case ACB_ADAPTER_TYPE_A: 1786 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 1787 break; 1788 1789 case ACB_ADAPTER_TYPE_B: 1790 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 1791 break; 1792 1793 case ACB_ADAPTER_TYPE_C: 1794 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 1795 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 1796 break; 1797 } 1798 1799 if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0) 1800 { 1801 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb); /* polling per 5 seconds */ 1802 } 1803 } 1804 1805 /* 1806 ******************************************************************************* 1807 ** 1808 ******************************************************************************* 1809 */ 1810 static void arcmsr_iop_parking(struct AdapterControlBlock *acb) 1811 { 1812 u_int32_t intmask_org; 1813 1814 if(acb!=NULL) { 1815 /* stop adapter background rebuild */ 1816 if(acb->acb_flags & ACB_F_MSG_START_BGRB) { 1817 intmask_org = arcmsr_disable_allintr(acb); 1818 arcmsr_stop_adapter_bgrb(acb); 1819 arcmsr_flush_adapter_cache(acb); 1820 arcmsr_enable_allintr(acb, intmask_org); 1821 } 1822 } 1823 } 1824 /* 1825 *********************************************************************** 1826 ** 1827 ************************************************************************ 1828 */ 1829 u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg) 1830 { 1831 struct CMD_MESSAGE_FIELD * pcmdmessagefld; 1832 u_int32_t retvalue=EINVAL; 1833 1834 pcmdmessagefld=(struct CMD_MESSAGE_FIELD *) arg; 1835 if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) { 1836 return retvalue; 1837 } 1838 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1839 switch(ioctl_cmd) { 1840 case ARCMSR_MESSAGE_READ_RQBUFFER: { 1841 u_int8_t * pQbuffer; 1842 u_int8_t * ptmpQbuffer=pcmdmessagefld->messagedatabuffer; 1843 u_int32_t allxfer_len=0; 1844 1845 while((acb->rqbuf_firstindex!=acb->rqbuf_lastindex) 1846 && (allxfer_len<1031)) { 1847 /*copy READ QBUFFER to srb*/ 1848 pQbuffer= &acb->rqbuffer[acb->rqbuf_firstindex]; 1849 memcpy(ptmpQbuffer, pQbuffer, 1); 1850 acb->rqbuf_firstindex++; 1851 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1852 /*if last index number set it to 0 */ 1853 ptmpQbuffer++; 1854 allxfer_len++; 1855 } 1856 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 1857 struct QBUFFER * prbuffer; 1858 u_int8_t * iop_data; 1859 u_int32_t iop_len; 1860 1861 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 1862 prbuffer=arcmsr_get_iop_rqbuffer(acb); 1863 iop_data=(u_int8_t *)prbuffer->data; 1864 iop_len=(u_int32_t)prbuffer->data_len; 1865 /*this iop data does no chance to make me overflow again here, so just do it*/ 1866 while(iop_len>0) { 1867 pQbuffer= &acb->rqbuffer[acb->rqbuf_lastindex]; 1868 memcpy(pQbuffer, iop_data, 1); 1869 acb->rqbuf_lastindex++; 1870 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1871 /*if last index number set it to 0 */ 1872 iop_data++; 1873 iop_len--; 1874 } 1875 arcmsr_iop_message_read(acb); 1876 /*signature, let IOP know data has been readed */ 1877 } 1878 pcmdmessagefld->cmdmessage.Length=allxfer_len; 1879 pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_OK; 1880 retvalue=ARCMSR_MESSAGE_SUCCESS; 1881 } 1882 break; 1883 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 1884 u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 1885 u_int8_t * pQbuffer; 1886 u_int8_t * ptmpuserbuffer=pcmdmessagefld->messagedatabuffer; 1887 1888 user_len=pcmdmessagefld->cmdmessage.Length; 1889 /*check if data xfer length of this request will overflow my array qbuffer */ 1890 wqbuf_lastindex=acb->wqbuf_lastindex; 1891 wqbuf_firstindex=acb->wqbuf_firstindex; 1892 if(wqbuf_lastindex!=wqbuf_firstindex) { 1893 arcmsr_post_ioctldata2iop(acb); 1894 pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_ERROR; 1895 } else { 1896 my_empty_len=(wqbuf_firstindex-wqbuf_lastindex-1)&(ARCMSR_MAX_QBUFFER-1); 1897 if(my_empty_len>=user_len) { 1898 while(user_len>0) { 1899 /*copy srb data to wqbuffer*/ 1900 pQbuffer= &acb->wqbuffer[acb->wqbuf_lastindex]; 1901 memcpy(pQbuffer, ptmpuserbuffer, 1); 1902 acb->wqbuf_lastindex++; 1903 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1904 /*if last index number set it to 0 */ 1905 ptmpuserbuffer++; 1906 user_len--; 1907 } 1908 /*post fist Qbuffer*/ 1909 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 1910 acb->acb_flags &=~ACB_F_MESSAGE_WQBUFFER_CLEARED; 1911 arcmsr_post_ioctldata2iop(acb); 1912 } 1913 pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_OK; 1914 } else { 1915 pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_ERROR; 1916 } 1917 } 1918 retvalue=ARCMSR_MESSAGE_SUCCESS; 1919 } 1920 break; 1921 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 1922 u_int8_t * pQbuffer=acb->rqbuffer; 1923 1924 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 1925 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 1926 arcmsr_iop_message_read(acb); 1927 /*signature, let IOP know data has been readed */ 1928 } 1929 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 1930 acb->rqbuf_firstindex=0; 1931 acb->rqbuf_lastindex=0; 1932 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 1933 pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_OK; 1934 retvalue=ARCMSR_MESSAGE_SUCCESS; 1935 } 1936 break; 1937 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: 1938 { 1939 u_int8_t * pQbuffer=acb->wqbuffer; 1940 1941 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 1942 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 1943 arcmsr_iop_message_read(acb); 1944 /*signature, let IOP know data has been readed */ 1945 } 1946 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 1947 acb->wqbuf_firstindex=0; 1948 acb->wqbuf_lastindex=0; 1949 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 1950 pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_OK; 1951 retvalue=ARCMSR_MESSAGE_SUCCESS; 1952 } 1953 break; 1954 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 1955 u_int8_t * pQbuffer; 1956 1957 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 1958 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 1959 arcmsr_iop_message_read(acb); 1960 /*signature, let IOP know data has been readed */ 1961 } 1962 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED 1963 |ACB_F_MESSAGE_RQBUFFER_CLEARED 1964 |ACB_F_MESSAGE_WQBUFFER_READ); 1965 acb->rqbuf_firstindex=0; 1966 acb->rqbuf_lastindex=0; 1967 acb->wqbuf_firstindex=0; 1968 acb->wqbuf_lastindex=0; 1969 pQbuffer=acb->rqbuffer; 1970 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 1971 pQbuffer=acb->wqbuffer; 1972 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 1973 pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_OK; 1974 retvalue=ARCMSR_MESSAGE_SUCCESS; 1975 } 1976 break; 1977 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 1978 pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_3F; 1979 retvalue=ARCMSR_MESSAGE_SUCCESS; 1980 } 1981 break; 1982 case ARCMSR_MESSAGE_SAY_HELLO: { 1983 u_int8_t * hello_string="Hello! I am ARCMSR"; 1984 u_int8_t * puserbuffer=(u_int8_t *)pcmdmessagefld->messagedatabuffer; 1985 1986 if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) { 1987 pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_ERROR; 1988 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1989 return ENOIOCTL; 1990 } 1991 pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_OK; 1992 retvalue=ARCMSR_MESSAGE_SUCCESS; 1993 } 1994 break; 1995 case ARCMSR_MESSAGE_SAY_GOODBYE: { 1996 arcmsr_iop_parking(acb); 1997 retvalue=ARCMSR_MESSAGE_SUCCESS; 1998 } 1999 break; 2000 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: { 2001 arcmsr_flush_adapter_cache(acb); 2002 retvalue=ARCMSR_MESSAGE_SUCCESS; 2003 } 2004 break; 2005 } 2006 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2007 return retvalue; 2008 } 2009 /* 2010 ************************************************************************** 2011 ************************************************************************** 2012 */ 2013 struct CommandControlBlock * arcmsr_get_freesrb(struct AdapterControlBlock *acb) 2014 { 2015 struct CommandControlBlock *srb=NULL; 2016 u_int32_t workingsrb_startindex, workingsrb_doneindex; 2017 2018 #if __FreeBSD_version < 700025 2019 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2020 #endif 2021 workingsrb_doneindex=acb->workingsrb_doneindex; 2022 workingsrb_startindex=acb->workingsrb_startindex; 2023 srb=acb->srbworkingQ[workingsrb_startindex]; 2024 workingsrb_startindex++; 2025 workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM; 2026 if(workingsrb_doneindex!=workingsrb_startindex) { 2027 acb->workingsrb_startindex=workingsrb_startindex; 2028 } else { 2029 srb=NULL; 2030 } 2031 #if __FreeBSD_version < 700025 2032 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2033 #endif 2034 return(srb); 2035 } 2036 /* 2037 ************************************************************************** 2038 ************************************************************************** 2039 */ 2040 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb * pccb) 2041 { 2042 struct CMD_MESSAGE_FIELD * pcmdmessagefld; 2043 int retvalue = 0, transfer_len = 0; 2044 char *buffer; 2045 u_int32_t controlcode = (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[5] << 24 | 2046 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[6] << 16 | 2047 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[7] << 8 | 2048 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[8]; 2049 /* 4 bytes: Areca io control code */ 2050 if((pccb->ccb_h.flags & CAM_SCATTER_VALID) == 0) { 2051 buffer = pccb->csio.data_ptr; 2052 transfer_len = pccb->csio.dxfer_len; 2053 } else { 2054 retvalue = ARCMSR_MESSAGE_FAIL; 2055 goto message_out; 2056 } 2057 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) { 2058 retvalue = ARCMSR_MESSAGE_FAIL; 2059 goto message_out; 2060 } 2061 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer; 2062 switch(controlcode) { 2063 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2064 u_int8_t *pQbuffer; 2065 u_int8_t *ptmpQbuffer=pcmdmessagefld->messagedatabuffer; 2066 int32_t allxfer_len = 0; 2067 2068 while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2069 && (allxfer_len < 1031)) { 2070 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2071 memcpy(ptmpQbuffer, pQbuffer, 1); 2072 acb->rqbuf_firstindex++; 2073 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2074 ptmpQbuffer++; 2075 allxfer_len++; 2076 } 2077 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2078 struct QBUFFER *prbuffer; 2079 u_int8_t *iop_data; 2080 int32_t iop_len; 2081 2082 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2083 prbuffer=arcmsr_get_iop_rqbuffer(acb); 2084 iop_data = (u_int8_t *)prbuffer->data; 2085 iop_len =(u_int32_t)prbuffer->data_len; 2086 while (iop_len > 0) { 2087 pQbuffer= &acb->rqbuffer[acb->rqbuf_lastindex]; 2088 memcpy(pQbuffer, iop_data, 1); 2089 acb->rqbuf_lastindex++; 2090 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2091 iop_data++; 2092 iop_len--; 2093 } 2094 arcmsr_iop_message_read(acb); 2095 } 2096 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2097 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2098 retvalue=ARCMSR_MESSAGE_SUCCESS; 2099 } 2100 break; 2101 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2102 int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2103 u_int8_t *pQbuffer; 2104 u_int8_t *ptmpuserbuffer=pcmdmessagefld->messagedatabuffer; 2105 2106 user_len = pcmdmessagefld->cmdmessage.Length; 2107 wqbuf_lastindex = acb->wqbuf_lastindex; 2108 wqbuf_firstindex = acb->wqbuf_firstindex; 2109 if (wqbuf_lastindex != wqbuf_firstindex) { 2110 arcmsr_post_ioctldata2iop(acb); 2111 /* has error report sensedata */ 2112 if(&pccb->csio.sense_data) { 2113 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2114 /* Valid,ErrorCode */ 2115 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2116 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2117 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2118 /* AdditionalSenseLength */ 2119 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2120 /* AdditionalSenseCode */ 2121 } 2122 retvalue = ARCMSR_MESSAGE_FAIL; 2123 } else { 2124 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1) 2125 &(ARCMSR_MAX_QBUFFER - 1); 2126 if (my_empty_len >= user_len) { 2127 while (user_len > 0) { 2128 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2129 memcpy(pQbuffer, ptmpuserbuffer, 1); 2130 acb->wqbuf_lastindex++; 2131 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2132 ptmpuserbuffer++; 2133 user_len--; 2134 } 2135 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2136 acb->acb_flags &= 2137 ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2138 arcmsr_post_ioctldata2iop(acb); 2139 } 2140 } else { 2141 /* has error report sensedata */ 2142 if(&pccb->csio.sense_data) { 2143 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2144 /* Valid,ErrorCode */ 2145 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2146 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2147 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2148 /* AdditionalSenseLength */ 2149 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2150 /* AdditionalSenseCode */ 2151 } 2152 retvalue = ARCMSR_MESSAGE_FAIL; 2153 } 2154 } 2155 } 2156 break; 2157 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2158 u_int8_t *pQbuffer = acb->rqbuffer; 2159 2160 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2161 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2162 arcmsr_iop_message_read(acb); 2163 } 2164 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2165 acb->rqbuf_firstindex = 0; 2166 acb->rqbuf_lastindex = 0; 2167 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2168 pcmdmessagefld->cmdmessage.ReturnCode = 2169 ARCMSR_MESSAGE_RETURNCODE_OK; 2170 } 2171 break; 2172 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: { 2173 u_int8_t *pQbuffer = acb->wqbuffer; 2174 2175 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2176 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2177 arcmsr_iop_message_read(acb); 2178 } 2179 acb->acb_flags |= 2180 (ACB_F_MESSAGE_WQBUFFER_CLEARED | 2181 ACB_F_MESSAGE_WQBUFFER_READ); 2182 acb->wqbuf_firstindex = 0; 2183 acb->wqbuf_lastindex = 0; 2184 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2185 pcmdmessagefld->cmdmessage.ReturnCode = 2186 ARCMSR_MESSAGE_RETURNCODE_OK; 2187 } 2188 break; 2189 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2190 u_int8_t *pQbuffer; 2191 2192 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2193 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2194 arcmsr_iop_message_read(acb); 2195 } 2196 acb->acb_flags |= 2197 (ACB_F_MESSAGE_WQBUFFER_CLEARED 2198 | ACB_F_MESSAGE_RQBUFFER_CLEARED 2199 | ACB_F_MESSAGE_WQBUFFER_READ); 2200 acb->rqbuf_firstindex = 0; 2201 acb->rqbuf_lastindex = 0; 2202 acb->wqbuf_firstindex = 0; 2203 acb->wqbuf_lastindex = 0; 2204 pQbuffer = acb->rqbuffer; 2205 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2206 pQbuffer = acb->wqbuffer; 2207 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2208 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2209 } 2210 break; 2211 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2212 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2213 } 2214 break; 2215 case ARCMSR_MESSAGE_SAY_HELLO: { 2216 int8_t * hello_string = "Hello! I am ARCMSR"; 2217 2218 memcpy(pcmdmessagefld->messagedatabuffer, hello_string 2219 , (int16_t)strlen(hello_string)); 2220 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2221 } 2222 break; 2223 case ARCMSR_MESSAGE_SAY_GOODBYE: 2224 arcmsr_iop_parking(acb); 2225 break; 2226 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: 2227 arcmsr_flush_adapter_cache(acb); 2228 break; 2229 default: 2230 retvalue = ARCMSR_MESSAGE_FAIL; 2231 } 2232 message_out: 2233 return retvalue; 2234 } 2235 /* 2236 ********************************************************************* 2237 ********************************************************************* 2238 */ 2239 static void arcmsr_executesrb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 2240 { 2241 struct CommandControlBlock *srb=(struct CommandControlBlock *)arg; 2242 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)srb->acb; 2243 union ccb * pccb; 2244 int target, lun; 2245 2246 pccb=srb->pccb; 2247 target=pccb->ccb_h.target_id; 2248 lun=pccb->ccb_h.target_lun; 2249 if(error != 0) { 2250 if(error != EFBIG) { 2251 printf("arcmsr%d: unexpected error %x" 2252 " returned from 'bus_dmamap_load' \n" 2253 , acb->pci_unit, error); 2254 } 2255 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) { 2256 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2257 } 2258 arcmsr_srb_complete(srb, 0); 2259 return; 2260 } 2261 if(nseg > ARCMSR_MAX_SG_ENTRIES) { 2262 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2263 arcmsr_srb_complete(srb, 0); 2264 return; 2265 } 2266 if(acb->acb_flags & ACB_F_BUS_RESET) { 2267 printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit); 2268 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET; 2269 arcmsr_srb_complete(srb, 0); 2270 return; 2271 } 2272 if(acb->devstate[target][lun]==ARECA_RAID_GONE) { 2273 u_int8_t block_cmd; 2274 2275 block_cmd=pccb->csio.cdb_io.cdb_bytes[0] & 0x0f; 2276 if(block_cmd==0x08 || block_cmd==0x0a) { 2277 printf("arcmsr%d:block 'read/write' command " 2278 "with gone raid volume Cmd=%2x, TargetId=%d, Lun=%d \n" 2279 , acb->pci_unit, block_cmd, target, lun); 2280 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 2281 arcmsr_srb_complete(srb, 0); 2282 return; 2283 } 2284 } 2285 if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 2286 if(nseg != 0) { 2287 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 2288 } 2289 arcmsr_srb_complete(srb, 0); 2290 return; 2291 } 2292 if(acb->srboutstandingcount >= ARCMSR_MAX_OUTSTANDING_CMD) { 2293 xpt_freeze_simq(acb->psim, 1); 2294 pccb->ccb_h.status = CAM_REQUEUE_REQ; 2295 acb->acb_flags |= ACB_F_CAM_DEV_QFRZN; 2296 arcmsr_srb_complete(srb, 0); 2297 return; 2298 } 2299 pccb->ccb_h.status |= CAM_SIM_QUEUED; 2300 arcmsr_build_srb(srb, dm_segs, nseg); 2301 /* if (pccb->ccb_h.timeout != CAM_TIME_INFINITY) 2302 callout_reset(&srb->ccb_callout, (pccb->ccb_h.timeout * hz) / 1000, arcmsr_srb_timeout, srb); 2303 */ 2304 arcmsr_post_srb(acb, srb); 2305 return; 2306 } 2307 /* 2308 ***************************************************************************************** 2309 ***************************************************************************************** 2310 */ 2311 static u_int8_t arcmsr_seek_cmd2abort(union ccb * abortccb) 2312 { 2313 struct CommandControlBlock *srb; 2314 struct AdapterControlBlock *acb=(struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr; 2315 u_int32_t intmask_org; 2316 int i=0; 2317 2318 acb->num_aborts++; 2319 /* 2320 *************************************************************************** 2321 ** It is the upper layer do abort command this lock just prior to calling us. 2322 ** First determine if we currently own this command. 2323 ** Start by searching the device queue. If not found 2324 ** at all, and the system wanted us to just abort the 2325 ** command return success. 2326 *************************************************************************** 2327 */ 2328 if(acb->srboutstandingcount!=0) { 2329 for(i=0;i<ARCMSR_MAX_FREESRB_NUM;i++) { 2330 srb=acb->psrb_pool[i]; 2331 if(srb->startdone==ARCMSR_SRB_START) { 2332 if(srb->pccb==abortccb) { 2333 srb->startdone=ARCMSR_SRB_ABORTED; 2334 printf("arcmsr%d:scsi id=%d lun=%d abort srb '%p'" 2335 "outstanding command \n" 2336 , acb->pci_unit, abortccb->ccb_h.target_id 2337 , abortccb->ccb_h.target_lun, srb); 2338 goto abort_outstanding_cmd; 2339 } 2340 } 2341 } 2342 } 2343 return(FALSE); 2344 abort_outstanding_cmd: 2345 /* disable all outbound interrupt */ 2346 intmask_org=arcmsr_disable_allintr(acb); 2347 arcmsr_polling_srbdone(acb, srb); 2348 /* enable outbound Post Queue, outbound doorbell Interrupt */ 2349 arcmsr_enable_allintr(acb, intmask_org); 2350 return (TRUE); 2351 } 2352 /* 2353 **************************************************************************** 2354 **************************************************************************** 2355 */ 2356 static void arcmsr_bus_reset(struct AdapterControlBlock *acb) 2357 { 2358 int retry=0; 2359 2360 acb->num_resets++; 2361 acb->acb_flags |=ACB_F_BUS_RESET; 2362 while(acb->srboutstandingcount!=0 && retry < 400) { 2363 arcmsr_interrupt(acb); 2364 UDELAY(25000); 2365 retry++; 2366 } 2367 arcmsr_iop_reset(acb); 2368 acb->acb_flags &= ~ACB_F_BUS_RESET; 2369 return; 2370 } 2371 /* 2372 ************************************************************************** 2373 ************************************************************************** 2374 */ 2375 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb, 2376 union ccb * pccb) 2377 { 2378 pccb->ccb_h.status |= CAM_REQ_CMP; 2379 switch (pccb->csio.cdb_io.cdb_bytes[0]) { 2380 case INQUIRY: { 2381 unsigned char inqdata[36]; 2382 char *buffer=pccb->csio.data_ptr; 2383 2384 if (pccb->ccb_h.target_lun) { 2385 pccb->ccb_h.status |= CAM_SEL_TIMEOUT; 2386 xpt_done(pccb); 2387 return; 2388 } 2389 inqdata[0] = T_PROCESSOR; 2390 /* Periph Qualifier & Periph Dev Type */ 2391 inqdata[1] = 0; 2392 /* rem media bit & Dev Type Modifier */ 2393 inqdata[2] = 0; 2394 /* ISO, ECMA, & ANSI versions */ 2395 inqdata[4] = 31; 2396 /* length of additional data */ 2397 strncpy(&inqdata[8], "Areca ", 8); 2398 /* Vendor Identification */ 2399 strncpy(&inqdata[16], "RAID controller ", 16); 2400 /* Product Identification */ 2401 strncpy(&inqdata[32], "R001", 4); /* Product Revision */ 2402 memcpy(buffer, inqdata, sizeof(inqdata)); 2403 xpt_done(pccb); 2404 } 2405 break; 2406 case WRITE_BUFFER: 2407 case READ_BUFFER: { 2408 if (arcmsr_iop_message_xfer(acb, pccb)) { 2409 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 2410 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 2411 } 2412 xpt_done(pccb); 2413 } 2414 break; 2415 default: 2416 xpt_done(pccb); 2417 } 2418 } 2419 /* 2420 ********************************************************************* 2421 ********************************************************************* 2422 */ 2423 static void arcmsr_action(struct cam_sim * psim, union ccb * pccb) 2424 { 2425 struct AdapterControlBlock * acb; 2426 2427 acb=(struct AdapterControlBlock *) cam_sim_softc(psim); 2428 if(acb==NULL) { 2429 pccb->ccb_h.status |= CAM_REQ_INVALID; 2430 xpt_done(pccb); 2431 return; 2432 } 2433 switch (pccb->ccb_h.func_code) { 2434 case XPT_SCSI_IO: { 2435 struct CommandControlBlock *srb; 2436 int target=pccb->ccb_h.target_id; 2437 2438 if(target == 16) { 2439 /* virtual device for iop message transfer */ 2440 arcmsr_handle_virtual_command(acb, pccb); 2441 return; 2442 } 2443 if((srb=arcmsr_get_freesrb(acb)) == NULL) { 2444 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL; 2445 xpt_done(pccb); 2446 return; 2447 } 2448 pccb->ccb_h.arcmsr_ccbsrb_ptr=srb; 2449 pccb->ccb_h.arcmsr_ccbacb_ptr=acb; 2450 srb->pccb=pccb; 2451 if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2452 if(!(pccb->ccb_h.flags & CAM_SCATTER_VALID)) { 2453 /* Single buffer */ 2454 if(!(pccb->ccb_h.flags & CAM_DATA_PHYS)) { 2455 /* Buffer is virtual */ 2456 u_int32_t error, s; 2457 2458 s=splsoftvm(); 2459 error = bus_dmamap_load(acb->dm_segs_dmat 2460 , srb->dm_segs_dmamap 2461 , pccb->csio.data_ptr 2462 , pccb->csio.dxfer_len 2463 , arcmsr_executesrb, srb, /*flags*/0); 2464 if(error == EINPROGRESS) { 2465 xpt_freeze_simq(acb->psim, 1); 2466 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2467 } 2468 splx(s); 2469 } else { 2470 /* Buffer is physical */ 2471 panic("arcmsr: CAM_DATA_PHYS not supported"); 2472 } 2473 } else { 2474 /* Scatter/gather list */ 2475 struct bus_dma_segment *segs; 2476 2477 if((pccb->ccb_h.flags & CAM_SG_LIST_PHYS) == 0 2478 || (pccb->ccb_h.flags & CAM_DATA_PHYS) != 0) { 2479 pccb->ccb_h.status |= CAM_PROVIDE_FAIL; 2480 xpt_done(pccb); 2481 free(srb, M_DEVBUF); 2482 return; 2483 } 2484 segs=(struct bus_dma_segment *)pccb->csio.data_ptr; 2485 arcmsr_executesrb(srb, segs, pccb->csio.sglist_cnt, 0); 2486 } 2487 } else { 2488 arcmsr_executesrb(srb, NULL, 0, 0); 2489 } 2490 break; 2491 } 2492 case XPT_TARGET_IO: { 2493 /* target mode not yet support vendor specific commands. */ 2494 pccb->ccb_h.status |= CAM_REQ_CMP; 2495 xpt_done(pccb); 2496 break; 2497 } 2498 case XPT_PATH_INQ: { 2499 struct ccb_pathinq *cpi= &pccb->cpi; 2500 2501 cpi->version_num=1; 2502 cpi->hba_inquiry=PI_SDTR_ABLE | PI_TAG_ABLE; 2503 cpi->target_sprt=0; 2504 cpi->hba_misc=0; 2505 cpi->hba_eng_cnt=0; 2506 cpi->max_target=ARCMSR_MAX_TARGETID; /* 0-16 */ 2507 cpi->max_lun=ARCMSR_MAX_TARGETLUN; /* 0-7 */ 2508 cpi->initiator_id=ARCMSR_SCSI_INITIATOR_ID; /* 255 */ 2509 cpi->bus_id=cam_sim_bus(psim); 2510 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2511 strncpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN); 2512 strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 2513 cpi->unit_number=cam_sim_unit(psim); 2514 #ifdef CAM_NEW_TRAN_CODE 2515 cpi->transport = XPORT_SPI; 2516 cpi->transport_version = 2; 2517 cpi->protocol = PROTO_SCSI; 2518 cpi->protocol_version = SCSI_REV_2; 2519 #endif 2520 cpi->ccb_h.status |= CAM_REQ_CMP; 2521 xpt_done(pccb); 2522 break; 2523 } 2524 case XPT_ABORT: { 2525 union ccb *pabort_ccb; 2526 2527 pabort_ccb=pccb->cab.abort_ccb; 2528 switch (pabort_ccb->ccb_h.func_code) { 2529 case XPT_ACCEPT_TARGET_IO: 2530 case XPT_IMMED_NOTIFY: 2531 case XPT_CONT_TARGET_IO: 2532 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) { 2533 pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED; 2534 xpt_done(pabort_ccb); 2535 pccb->ccb_h.status |= CAM_REQ_CMP; 2536 } else { 2537 xpt_print_path(pabort_ccb->ccb_h.path); 2538 printf("Not found\n"); 2539 pccb->ccb_h.status |= CAM_PATH_INVALID; 2540 } 2541 break; 2542 case XPT_SCSI_IO: 2543 pccb->ccb_h.status |= CAM_UA_ABORT; 2544 break; 2545 default: 2546 pccb->ccb_h.status |= CAM_REQ_INVALID; 2547 break; 2548 } 2549 xpt_done(pccb); 2550 break; 2551 } 2552 case XPT_RESET_BUS: 2553 case XPT_RESET_DEV: { 2554 u_int32_t i; 2555 2556 arcmsr_bus_reset(acb); 2557 for (i=0; i < 500; i++) { 2558 DELAY(1000); 2559 } 2560 pccb->ccb_h.status |= CAM_REQ_CMP; 2561 xpt_done(pccb); 2562 break; 2563 } 2564 case XPT_TERM_IO: { 2565 pccb->ccb_h.status |= CAM_REQ_INVALID; 2566 xpt_done(pccb); 2567 break; 2568 } 2569 case XPT_GET_TRAN_SETTINGS: { 2570 struct ccb_trans_settings *cts; 2571 2572 if(pccb->ccb_h.target_id == 16) { 2573 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 2574 xpt_done(pccb); 2575 break; 2576 } 2577 cts= &pccb->cts; 2578 #ifdef CAM_NEW_TRAN_CODE 2579 { 2580 struct ccb_trans_settings_scsi *scsi; 2581 struct ccb_trans_settings_spi *spi; 2582 2583 scsi = &cts->proto_specific.scsi; 2584 spi = &cts->xport_specific.spi; 2585 cts->protocol = PROTO_SCSI; 2586 cts->protocol_version = SCSI_REV_2; 2587 cts->transport = XPORT_SPI; 2588 cts->transport_version = 2; 2589 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 2590 spi->sync_period=3; 2591 spi->sync_offset=32; 2592 spi->bus_width=MSG_EXT_WDTR_BUS_16_BIT; 2593 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB; 2594 spi->valid = CTS_SPI_VALID_DISC 2595 | CTS_SPI_VALID_SYNC_RATE 2596 | CTS_SPI_VALID_SYNC_OFFSET 2597 | CTS_SPI_VALID_BUS_WIDTH; 2598 scsi->valid = CTS_SCSI_VALID_TQ; 2599 } 2600 #else 2601 { 2602 cts->flags=(CCB_TRANS_DISC_ENB | CCB_TRANS_TAG_ENB); 2603 cts->sync_period=3; 2604 cts->sync_offset=32; 2605 cts->bus_width=MSG_EXT_WDTR_BUS_16_BIT; 2606 cts->valid=CCB_TRANS_SYNC_RATE_VALID | 2607 CCB_TRANS_SYNC_OFFSET_VALID | 2608 CCB_TRANS_BUS_WIDTH_VALID | 2609 CCB_TRANS_DISC_VALID | 2610 CCB_TRANS_TQ_VALID; 2611 } 2612 #endif 2613 pccb->ccb_h.status |= CAM_REQ_CMP; 2614 xpt_done(pccb); 2615 break; 2616 } 2617 case XPT_SET_TRAN_SETTINGS: { 2618 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 2619 xpt_done(pccb); 2620 break; 2621 } 2622 case XPT_CALC_GEOMETRY: { 2623 struct ccb_calc_geometry *ccg; 2624 u_int32_t size_mb; 2625 u_int32_t secs_per_cylinder; 2626 2627 if(pccb->ccb_h.target_id == 16) { 2628 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 2629 xpt_done(pccb); 2630 break; 2631 } 2632 ccg= &pccb->ccg; 2633 if (ccg->block_size == 0) { 2634 pccb->ccb_h.status = CAM_REQ_INVALID; 2635 xpt_done(pccb); 2636 break; 2637 } 2638 if(((1024L * 1024L)/ccg->block_size) < 0) { 2639 pccb->ccb_h.status = CAM_REQ_INVALID; 2640 xpt_done(pccb); 2641 break; 2642 } 2643 size_mb=ccg->volume_size/((1024L * 1024L)/ccg->block_size); 2644 if(size_mb > 1024 ) { 2645 ccg->heads=255; 2646 ccg->secs_per_track=63; 2647 } else { 2648 ccg->heads=64; 2649 ccg->secs_per_track=32; 2650 } 2651 secs_per_cylinder=ccg->heads * ccg->secs_per_track; 2652 ccg->cylinders=ccg->volume_size / secs_per_cylinder; 2653 pccb->ccb_h.status |= CAM_REQ_CMP; 2654 xpt_done(pccb); 2655 break; 2656 } 2657 default: 2658 pccb->ccb_h.status |= CAM_REQ_INVALID; 2659 xpt_done(pccb); 2660 break; 2661 } 2662 return; 2663 } 2664 /* 2665 ********************************************************************** 2666 ********************************************************************** 2667 */ 2668 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb) 2669 { 2670 acb->acb_flags |= ACB_F_MSG_START_BGRB; 2671 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 2672 if(!arcmsr_hba_wait_msgint_ready(acb)) { 2673 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 2674 } 2675 return; 2676 } 2677 /* 2678 ********************************************************************** 2679 ********************************************************************** 2680 */ 2681 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb) 2682 { 2683 acb->acb_flags |= ACB_F_MSG_START_BGRB; 2684 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_START_BGRB); 2685 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 2686 printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 2687 } 2688 return; 2689 } 2690 /* 2691 ********************************************************************** 2692 ********************************************************************** 2693 */ 2694 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb) 2695 { 2696 acb->acb_flags |= ACB_F_MSG_START_BGRB; 2697 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 2698 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 2699 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 2700 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 2701 } 2702 return; 2703 } 2704 /* 2705 ********************************************************************** 2706 ********************************************************************** 2707 */ 2708 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb) 2709 { 2710 switch (acb->adapter_type) { 2711 case ACB_ADAPTER_TYPE_A: 2712 arcmsr_start_hba_bgrb(acb); 2713 break; 2714 case ACB_ADAPTER_TYPE_B: 2715 arcmsr_start_hbb_bgrb(acb); 2716 break; 2717 case ACB_ADAPTER_TYPE_C: 2718 arcmsr_start_hbc_bgrb(acb); 2719 break; 2720 } 2721 return; 2722 } 2723 /* 2724 ********************************************************************** 2725 ** 2726 ********************************************************************** 2727 */ 2728 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 2729 { 2730 struct CommandControlBlock *srb; 2731 u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0; 2732 u_int16_t error; 2733 2734 polling_ccb_retry: 2735 poll_count++; 2736 outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 2737 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus); /*clear interrupt*/ 2738 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2739 while(1) { 2740 if((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 2741 0, outbound_queueport))==0xFFFFFFFF) { 2742 if(poll_srb_done) { 2743 break;/*chip FIFO no ccb for completion already*/ 2744 } else { 2745 UDELAY(25000); 2746 if ((poll_count > 100) && (poll_srb != NULL)) { 2747 break; 2748 } 2749 goto polling_ccb_retry; 2750 } 2751 } 2752 /* check if command done with no error*/ 2753 srb=(struct CommandControlBlock *) 2754 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 2755 error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 2756 poll_srb_done = (srb==poll_srb) ? 1:0; 2757 if((srb->acb!=acb) || (srb->startdone!=ARCMSR_SRB_START)) { 2758 if(srb->startdone==ARCMSR_SRB_ABORTED) { 2759 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'" 2760 "poll command abort successfully \n" 2761 , acb->pci_unit 2762 , srb->pccb->ccb_h.target_id 2763 , srb->pccb->ccb_h.target_lun, srb); 2764 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 2765 arcmsr_srb_complete(srb, 1); 2766 continue; 2767 } 2768 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 2769 "srboutstandingcount=%d \n" 2770 , acb->pci_unit 2771 , srb, acb->srboutstandingcount); 2772 continue; 2773 } 2774 arcmsr_report_srb_state(acb, srb, error); 2775 } /*drain reply FIFO*/ 2776 return; 2777 } 2778 /* 2779 ********************************************************************** 2780 ** 2781 ********************************************************************** 2782 */ 2783 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 2784 { 2785 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu; 2786 struct CommandControlBlock *srb; 2787 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 2788 int index; 2789 u_int16_t error; 2790 2791 polling_ccb_retry: 2792 poll_count++; 2793 CHIP_REG_WRITE32(HBB_DOORBELL, 2794 0, iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 2795 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2796 while(1) { 2797 index=phbbmu->doneq_index; 2798 if((flag_srb=phbbmu->done_qbuffer[index]) == 0) { 2799 if(poll_srb_done) { 2800 break;/*chip FIFO no ccb for completion already*/ 2801 } else { 2802 UDELAY(25000); 2803 if ((poll_count > 100) && (poll_srb != NULL)) { 2804 break; 2805 } 2806 goto polling_ccb_retry; 2807 } 2808 } 2809 phbbmu->done_qbuffer[index]=0; 2810 index++; 2811 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 2812 phbbmu->doneq_index=index; 2813 /* check if command done with no error*/ 2814 srb=(struct CommandControlBlock *) 2815 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 2816 error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 2817 poll_srb_done = (srb==poll_srb) ? 1:0; 2818 if((srb->acb!=acb) || (srb->startdone!=ARCMSR_SRB_START)) { 2819 if(srb->startdone==ARCMSR_SRB_ABORTED) { 2820 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'" 2821 "poll command abort successfully \n" 2822 , acb->pci_unit 2823 , srb->pccb->ccb_h.target_id 2824 , srb->pccb->ccb_h.target_lun, srb); 2825 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 2826 arcmsr_srb_complete(srb, 1); 2827 continue; 2828 } 2829 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 2830 "srboutstandingcount=%d \n" 2831 , acb->pci_unit 2832 , srb, acb->srboutstandingcount); 2833 continue; 2834 } 2835 arcmsr_report_srb_state(acb, srb, error); 2836 } /*drain reply FIFO*/ 2837 return; 2838 } 2839 /* 2840 ********************************************************************** 2841 ** 2842 ********************************************************************** 2843 */ 2844 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 2845 { 2846 struct CommandControlBlock *srb; 2847 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 2848 u_int16_t error; 2849 2850 polling_ccb_retry: 2851 poll_count++; 2852 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2853 while(1) { 2854 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) { 2855 if(poll_srb_done) { 2856 break;/*chip FIFO no ccb for completion already*/ 2857 } else { 2858 UDELAY(25000); 2859 if ((poll_count > 100) && (poll_srb != NULL)) { 2860 break; 2861 } 2862 if (acb->srboutstandingcount == 0) { 2863 break; 2864 } 2865 goto polling_ccb_retry; 2866 } 2867 } 2868 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 2869 /* check if command done with no error*/ 2870 srb=(struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFF0));/*frame must be 32 bytes aligned*/ 2871 error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 2872 if (poll_srb != NULL) 2873 poll_srb_done = (srb==poll_srb) ? 1:0; 2874 if((srb->acb!=acb) || (srb->startdone!=ARCMSR_SRB_START)) { 2875 if(srb->startdone==ARCMSR_SRB_ABORTED) { 2876 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'poll command abort successfully \n" 2877 , acb->pci_unit, srb->pccb->ccb_h.target_id, srb->pccb->ccb_h.target_lun, srb); 2878 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 2879 arcmsr_srb_complete(srb, 1); 2880 continue; 2881 } 2882 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 2883 , acb->pci_unit, srb, acb->srboutstandingcount); 2884 continue; 2885 } 2886 arcmsr_report_srb_state(acb, srb, error); 2887 } /*drain reply FIFO*/ 2888 return; 2889 } 2890 /* 2891 ********************************************************************** 2892 ********************************************************************** 2893 */ 2894 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 2895 { 2896 switch (acb->adapter_type) { 2897 case ACB_ADAPTER_TYPE_A: { 2898 arcmsr_polling_hba_srbdone(acb, poll_srb); 2899 } 2900 break; 2901 case ACB_ADAPTER_TYPE_B: { 2902 arcmsr_polling_hbb_srbdone(acb, poll_srb); 2903 } 2904 break; 2905 case ACB_ADAPTER_TYPE_C: { 2906 arcmsr_polling_hbc_srbdone(acb, poll_srb); 2907 } 2908 break; 2909 } 2910 } 2911 /* 2912 ********************************************************************** 2913 ********************************************************************** 2914 */ 2915 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb) 2916 { 2917 char *acb_firm_model=acb->firm_model; 2918 char *acb_firm_version=acb->firm_version; 2919 char *acb_device_map = acb->device_map; 2920 size_t iop_firm_model=offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 2921 size_t iop_firm_version=offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 2922 size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 2923 int i; 2924 2925 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2926 if(!arcmsr_hba_wait_msgint_ready(acb)) { 2927 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 2928 } 2929 i=0; 2930 while(i<8) { 2931 *acb_firm_model=bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 2932 /* 8 bytes firm_model, 15, 60-67*/ 2933 acb_firm_model++; 2934 i++; 2935 } 2936 i=0; 2937 while(i<16) { 2938 *acb_firm_version=bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 2939 /* 16 bytes firm_version, 17, 68-83*/ 2940 acb_firm_version++; 2941 i++; 2942 } 2943 i=0; 2944 while(i<16) { 2945 *acb_device_map=bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 2946 acb_device_map++; 2947 i++; 2948 } 2949 printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION); 2950 printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version); 2951 acb->firm_request_len=CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 2952 acb->firm_numbers_queue=CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 2953 acb->firm_sdram_size=CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 2954 acb->firm_ide_channels=CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 2955 acb->firm_cfg_version=CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 2956 return; 2957 } 2958 /* 2959 ********************************************************************** 2960 ********************************************************************** 2961 */ 2962 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb) 2963 { 2964 char *acb_firm_model=acb->firm_model; 2965 char *acb_firm_version=acb->firm_version; 2966 char *acb_device_map = acb->device_map; 2967 size_t iop_firm_model=offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 2968 size_t iop_firm_version=offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 2969 size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 2970 int i; 2971 2972 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 2973 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 2974 printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 2975 } 2976 i=0; 2977 while(i<8) { 2978 *acb_firm_model=bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i); 2979 /* 8 bytes firm_model, 15, 60-67*/ 2980 acb_firm_model++; 2981 i++; 2982 } 2983 i=0; 2984 while(i<16) { 2985 *acb_firm_version=bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i); 2986 /* 16 bytes firm_version, 17, 68-83*/ 2987 acb_firm_version++; 2988 i++; 2989 } 2990 i=0; 2991 while(i<16) { 2992 *acb_device_map=bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i); 2993 acb_device_map++; 2994 i++; 2995 } 2996 printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION); 2997 printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version); 2998 acb->firm_request_len=CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 2999 acb->firm_numbers_queue=CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3000 acb->firm_sdram_size=CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3001 acb->firm_ide_channels=CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3002 acb->firm_cfg_version=CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3003 return; 3004 } 3005 /* 3006 ********************************************************************** 3007 ********************************************************************** 3008 */ 3009 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb) 3010 { 3011 char *acb_firm_model=acb->firm_model; 3012 char *acb_firm_version=acb->firm_version; 3013 char *acb_device_map = acb->device_map; 3014 size_t iop_firm_model=offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3015 size_t iop_firm_version=offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3016 size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3017 int i; 3018 3019 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3020 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3021 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3022 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3023 } 3024 i=0; 3025 while(i<8) { 3026 *acb_firm_model=bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3027 /* 8 bytes firm_model, 15, 60-67*/ 3028 acb_firm_model++; 3029 i++; 3030 } 3031 i=0; 3032 while(i<16) { 3033 *acb_firm_version=bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3034 /* 16 bytes firm_version, 17, 68-83*/ 3035 acb_firm_version++; 3036 i++; 3037 } 3038 i=0; 3039 while(i<16) { 3040 *acb_device_map=bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3041 acb_device_map++; 3042 i++; 3043 } 3044 printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION); 3045 printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version); 3046 acb->firm_request_len =CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3047 acb->firm_numbers_queue =CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3048 acb->firm_sdram_size =CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3049 acb->firm_ide_channels =CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3050 acb->firm_cfg_version =CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3051 return; 3052 } 3053 /* 3054 ********************************************************************** 3055 ********************************************************************** 3056 */ 3057 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb) 3058 { 3059 switch (acb->adapter_type) { 3060 case ACB_ADAPTER_TYPE_A: { 3061 arcmsr_get_hba_config(acb); 3062 } 3063 break; 3064 case ACB_ADAPTER_TYPE_B: { 3065 arcmsr_get_hbb_config(acb); 3066 } 3067 break; 3068 case ACB_ADAPTER_TYPE_C: { 3069 arcmsr_get_hbc_config(acb); 3070 } 3071 break; 3072 } 3073 return; 3074 } 3075 /* 3076 ********************************************************************** 3077 ********************************************************************** 3078 */ 3079 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb) 3080 { 3081 int timeout=0; 3082 3083 switch (acb->adapter_type) { 3084 case ACB_ADAPTER_TYPE_A: { 3085 while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) 3086 { 3087 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3088 { 3089 printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit); 3090 return; 3091 } 3092 UDELAY(15000); /* wait 15 milli-seconds */ 3093 } 3094 } 3095 break; 3096 case ACB_ADAPTER_TYPE_B: { 3097 while ((CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0) 3098 { 3099 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3100 { 3101 printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit); 3102 return; 3103 } 3104 UDELAY(15000); /* wait 15 milli-seconds */ 3105 } 3106 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 3107 } 3108 break; 3109 case ACB_ADAPTER_TYPE_C: { 3110 while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0) 3111 { 3112 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3113 { 3114 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 3115 return; 3116 } 3117 UDELAY(15000); /* wait 15 milli-seconds */ 3118 } 3119 } 3120 break; 3121 } 3122 return; 3123 } 3124 /* 3125 ********************************************************************** 3126 ********************************************************************** 3127 */ 3128 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb) 3129 { 3130 u_int32_t outbound_doorbell; 3131 3132 switch (acb->adapter_type) { 3133 case ACB_ADAPTER_TYPE_A: { 3134 /* empty doorbell Qbuffer if door bell ringed */ 3135 outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell); 3136 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 3137 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 3138 3139 } 3140 break; 3141 case ACB_ADAPTER_TYPE_B: { 3142 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt and message state*/ 3143 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 3144 /* let IOP know data has been read */ 3145 } 3146 break; 3147 case ACB_ADAPTER_TYPE_C: { 3148 /* empty doorbell Qbuffer if door bell ringed */ 3149 outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 3150 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /*clear doorbell interrupt */ 3151 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 3152 3153 } 3154 break; 3155 } 3156 return; 3157 } 3158 /* 3159 ************************************************************************ 3160 ************************************************************************ 3161 */ 3162 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb) 3163 { 3164 unsigned long srb_phyaddr; 3165 u_int32_t srb_phyaddr_hi32; 3166 3167 /* 3168 ******************************************************************** 3169 ** here we need to tell iop 331 our freesrb.HighPart 3170 ** if freesrb.HighPart is not zero 3171 ******************************************************************** 3172 */ 3173 srb_phyaddr= (unsigned long) acb->srb_phyaddr.phyaddr; 3174 // srb_phyaddr_hi32=(u_int32_t) ((srb_phyaddr>>16)>>16); 3175 srb_phyaddr_hi32=acb->srb_phyaddr.B.phyadd_high; 3176 switch (acb->adapter_type) { 3177 case ACB_ADAPTER_TYPE_A: { 3178 if(srb_phyaddr_hi32!=0) { 3179 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 3180 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 3181 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 3182 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3183 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 3184 return FALSE; 3185 } 3186 } 3187 } 3188 break; 3189 /* 3190 *********************************************************************** 3191 ** if adapter type B, set window of "post command Q" 3192 *********************************************************************** 3193 */ 3194 case ACB_ADAPTER_TYPE_B: { 3195 u_int32_t post_queue_phyaddr; 3196 struct HBB_MessageUnit *phbbmu; 3197 3198 phbbmu=(struct HBB_MessageUnit *)acb->pmu; 3199 phbbmu->postq_index=0; 3200 phbbmu->doneq_index=0; 3201 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW); 3202 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3203 printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit); 3204 return FALSE; 3205 } 3206 post_queue_phyaddr = srb_phyaddr + ARCMSR_MAX_FREESRB_NUM*sizeof(struct CommandControlBlock) 3207 + offsetof(struct HBB_MessageUnit, post_qbuffer); 3208 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 3209 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */ 3210 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */ 3211 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */ 3212 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */ 3213 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG); 3214 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3215 printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit); 3216 return FALSE; 3217 } 3218 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE); 3219 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3220 printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit); 3221 return FALSE; 3222 } 3223 } 3224 break; 3225 case ACB_ADAPTER_TYPE_C: { 3226 if(srb_phyaddr_hi32!=0) { 3227 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 3228 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 3229 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 3230 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3231 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3232 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 3233 return FALSE; 3234 } 3235 } 3236 } 3237 break; 3238 } 3239 return TRUE; 3240 } 3241 /* 3242 ************************************************************************ 3243 ************************************************************************ 3244 */ 3245 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb) 3246 { 3247 switch (acb->adapter_type) 3248 { 3249 case ACB_ADAPTER_TYPE_A: 3250 case ACB_ADAPTER_TYPE_C: 3251 break; 3252 case ACB_ADAPTER_TYPE_B: { 3253 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell,ARCMSR_MESSAGE_ACTIVE_EOI_MODE); 3254 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3255 printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit); 3256 3257 return; 3258 } 3259 } 3260 break; 3261 } 3262 return; 3263 } 3264 /* 3265 ********************************************************************** 3266 ********************************************************************** 3267 */ 3268 static void arcmsr_iop_init(struct AdapterControlBlock *acb) 3269 { 3270 u_int32_t intmask_org; 3271 3272 /* disable all outbound interrupt */ 3273 intmask_org=arcmsr_disable_allintr(acb); 3274 arcmsr_wait_firmware_ready(acb); 3275 arcmsr_iop_confirm(acb); 3276 arcmsr_get_firmware_spec(acb); 3277 /*start background rebuild*/ 3278 arcmsr_start_adapter_bgrb(acb); 3279 /* empty doorbell Qbuffer if door bell ringed */ 3280 arcmsr_clear_doorbell_queue_buffer(acb); 3281 arcmsr_enable_eoi_mode(acb); 3282 /* enable outbound Post Queue, outbound doorbell Interrupt */ 3283 arcmsr_enable_allintr(acb, intmask_org); 3284 acb->acb_flags |=ACB_F_IOP_INITED; 3285 return; 3286 } 3287 /* 3288 ********************************************************************** 3289 ********************************************************************** 3290 */ 3291 static void arcmsr_map_freesrb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3292 { 3293 struct AdapterControlBlock *acb=arg; 3294 struct CommandControlBlock *srb_tmp; 3295 u_int8_t * dma_memptr; 3296 u_int32_t i; 3297 unsigned long srb_phyaddr=(unsigned long)segs->ds_addr; 3298 3299 dma_memptr=acb->uncacheptr; 3300 acb->srb_phyaddr.phyaddr=srb_phyaddr; 3301 srb_tmp=(struct CommandControlBlock *)dma_memptr; 3302 for(i=0;i<ARCMSR_MAX_FREESRB_NUM;i++) { 3303 if(bus_dmamap_create(acb->dm_segs_dmat, 3304 /*flags*/0, &srb_tmp->dm_segs_dmamap)!=0) { 3305 acb->acb_flags |= ACB_F_MAPFREESRB_FAILD; 3306 printf("arcmsr%d:" 3307 " srb dmamap bus_dmamap_create error\n", acb->pci_unit); 3308 return; 3309 } 3310 srb_tmp->cdb_shifted_phyaddr=(acb->adapter_type==ACB_ADAPTER_TYPE_C)?srb_phyaddr:(srb_phyaddr >> 5); 3311 srb_tmp->acb=acb; 3312 acb->srbworkingQ[i]=acb->psrb_pool[i]=srb_tmp; 3313 srb_phyaddr=srb_phyaddr+sizeof(struct CommandControlBlock); 3314 srb_tmp++; 3315 } 3316 acb->vir2phy_offset=(unsigned long)srb_tmp-(unsigned long)srb_phyaddr; 3317 return; 3318 } 3319 /* 3320 ************************************************************************ 3321 ** 3322 ** 3323 ************************************************************************ 3324 */ 3325 static void arcmsr_free_resource(struct AdapterControlBlock *acb) 3326 { 3327 /* remove the control device */ 3328 if(acb->ioctl_dev != NULL) { 3329 destroy_dev(acb->ioctl_dev); 3330 } 3331 bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap); 3332 bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap); 3333 bus_dma_tag_destroy(acb->srb_dmat); 3334 bus_dma_tag_destroy(acb->dm_segs_dmat); 3335 bus_dma_tag_destroy(acb->parent_dmat); 3336 return; 3337 } 3338 /* 3339 ************************************************************************ 3340 ************************************************************************ 3341 */ 3342 static u_int32_t arcmsr_initialize(device_t dev) 3343 { 3344 struct AdapterControlBlock *acb=device_get_softc(dev); 3345 u_int16_t pci_command; 3346 int i, j,max_coherent_size; 3347 3348 switch (pci_get_devid(dev)) { 3349 case PCIDevVenIDARC1880: { 3350 acb->adapter_type=ACB_ADAPTER_TYPE_C; 3351 max_coherent_size=ARCMSR_SRBS_POOL_SIZE; 3352 } 3353 break; 3354 case PCIDevVenIDARC1201: { 3355 acb->adapter_type=ACB_ADAPTER_TYPE_B; 3356 max_coherent_size=ARCMSR_SRBS_POOL_SIZE+(sizeof(struct HBB_MessageUnit)); 3357 } 3358 break; 3359 case PCIDevVenIDARC1110: 3360 case PCIDevVenIDARC1120: 3361 case PCIDevVenIDARC1130: 3362 case PCIDevVenIDARC1160: 3363 case PCIDevVenIDARC1170: 3364 case PCIDevVenIDARC1210: 3365 case PCIDevVenIDARC1220: 3366 case PCIDevVenIDARC1230: 3367 case PCIDevVenIDARC1260: 3368 case PCIDevVenIDARC1270: 3369 case PCIDevVenIDARC1280: 3370 case PCIDevVenIDARC1212: 3371 case PCIDevVenIDARC1222: 3372 case PCIDevVenIDARC1380: 3373 case PCIDevVenIDARC1381: 3374 case PCIDevVenIDARC1680: 3375 case PCIDevVenIDARC1681: { 3376 acb->adapter_type=ACB_ADAPTER_TYPE_A; 3377 max_coherent_size=ARCMSR_SRBS_POOL_SIZE; 3378 } 3379 break; 3380 default: { 3381 printf("arcmsr%d:" 3382 " unknown RAID adapter type \n", device_get_unit(dev)); 3383 return ENOMEM; 3384 } 3385 } 3386 #if __FreeBSD_version >= 502010 3387 if(bus_dma_tag_create( /*parent*/ NULL, 3388 /*alignemnt*/ 1, 3389 /*boundary*/ 0, 3390 /*lowaddr*/ BUS_SPACE_MAXADDR, 3391 /*highaddr*/ BUS_SPACE_MAXADDR, 3392 /*filter*/ NULL, 3393 /*filterarg*/ NULL, 3394 /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT, 3395 /*nsegments*/ BUS_SPACE_UNRESTRICTED, 3396 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 3397 /*flags*/ 0, 3398 /*lockfunc*/ NULL, 3399 /*lockarg*/ NULL, 3400 &acb->parent_dmat) != 0) 3401 #else 3402 if(bus_dma_tag_create( /*parent*/ NULL, 3403 /*alignemnt*/ 1, 3404 /*boundary*/ 0, 3405 /*lowaddr*/ BUS_SPACE_MAXADDR, 3406 /*highaddr*/ BUS_SPACE_MAXADDR, 3407 /*filter*/ NULL, 3408 /*filterarg*/ NULL, 3409 /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT, 3410 /*nsegments*/ BUS_SPACE_UNRESTRICTED, 3411 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 3412 /*flags*/ 0, 3413 &acb->parent_dmat) != 0) 3414 #endif 3415 { 3416 printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 3417 return ENOMEM; 3418 } 3419 /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */ 3420 #if __FreeBSD_version >= 502010 3421 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 3422 /*alignment*/ 1, 3423 /*boundary*/ 0, 3424 /*lowaddr*/ BUS_SPACE_MAXADDR, 3425 /*highaddr*/ BUS_SPACE_MAXADDR, 3426 /*filter*/ NULL, 3427 /*filterarg*/ NULL, 3428 /*maxsize*/ MAXBSIZE, 3429 /*nsegments*/ ARCMSR_MAX_SG_ENTRIES, 3430 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 3431 /*flags*/ 0, 3432 /*lockfunc*/ busdma_lock_mutex, 3433 #if __FreeBSD_version >= 700025 3434 /*lockarg*/ &acb->qbuffer_lock, 3435 #else 3436 /*lockarg*/ &Giant, 3437 #endif 3438 &acb->dm_segs_dmat) != 0) 3439 #else 3440 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 3441 /*alignment*/ 1, 3442 /*boundary*/ 0, 3443 /*lowaddr*/ BUS_SPACE_MAXADDR, 3444 /*highaddr*/ BUS_SPACE_MAXADDR, 3445 /*filter*/ NULL, 3446 /*filterarg*/ NULL, 3447 /*maxsize*/ MAXBSIZE, 3448 /*nsegments*/ ARCMSR_MAX_SG_ENTRIES, 3449 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 3450 /*flags*/ 0, 3451 &acb->dm_segs_dmat) != 0) 3452 #endif 3453 { 3454 bus_dma_tag_destroy(acb->parent_dmat); 3455 printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 3456 return ENOMEM; 3457 } 3458 /* DMA tag for our srb structures.... Allocate the freesrb memory */ 3459 #if __FreeBSD_version >= 502010 3460 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 3461 /*alignment*/ 0x20, 3462 /*boundary*/ 0, 3463 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 3464 /*highaddr*/ BUS_SPACE_MAXADDR, 3465 /*filter*/ NULL, 3466 /*filterarg*/ NULL, 3467 /*maxsize*/ max_coherent_size, 3468 /*nsegments*/ 1, 3469 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 3470 /*flags*/ 0, 3471 /*lockfunc*/ NULL, 3472 /*lockarg*/ NULL, 3473 &acb->srb_dmat) != 0) 3474 #else 3475 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 3476 /*alignment*/ 0x20, 3477 /*boundary*/ 0, 3478 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 3479 /*highaddr*/ BUS_SPACE_MAXADDR, 3480 /*filter*/ NULL, 3481 /*filterarg*/ NULL, 3482 /*maxsize*/ max_coherent_size, 3483 /*nsegments*/ 1, 3484 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 3485 /*flags*/ 0, 3486 &acb->srb_dmat) != 0) 3487 #endif 3488 { 3489 bus_dma_tag_destroy(acb->dm_segs_dmat); 3490 bus_dma_tag_destroy(acb->parent_dmat); 3491 printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 3492 return ENXIO; 3493 } 3494 /* Allocation for our srbs */ 3495 if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) { 3496 bus_dma_tag_destroy(acb->srb_dmat); 3497 bus_dma_tag_destroy(acb->dm_segs_dmat); 3498 bus_dma_tag_destroy(acb->parent_dmat); 3499 printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev)); 3500 return ENXIO; 3501 } 3502 /* And permanently map them */ 3503 if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_freesrb, acb, /*flags*/0)) { 3504 bus_dma_tag_destroy(acb->srb_dmat); 3505 bus_dma_tag_destroy(acb->dm_segs_dmat); 3506 bus_dma_tag_destroy(acb->parent_dmat); 3507 printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev)); 3508 return ENXIO; 3509 } 3510 pci_command=pci_read_config(dev, PCIR_COMMAND, 2); 3511 pci_command |= PCIM_CMD_BUSMASTEREN; 3512 pci_command |= PCIM_CMD_PERRESPEN; 3513 pci_command |= PCIM_CMD_MWRICEN; 3514 /* Enable Busmaster/Mem */ 3515 pci_command |= PCIM_CMD_MEMEN; 3516 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 3517 switch(acb->adapter_type) { 3518 case ACB_ADAPTER_TYPE_A: { 3519 u_int32_t rid0=PCIR_BAR(0); 3520 vm_offset_t mem_base0; 3521 3522 acb->sys_res_arcmsr[0]=bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, 0x1000, RF_ACTIVE); 3523 if(acb->sys_res_arcmsr[0] == NULL) { 3524 arcmsr_free_resource(acb); 3525 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 3526 return ENOMEM; 3527 } 3528 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 3529 arcmsr_free_resource(acb); 3530 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 3531 return ENXIO; 3532 } 3533 mem_base0=(vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 3534 if(mem_base0==0) { 3535 arcmsr_free_resource(acb); 3536 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 3537 return ENXIO; 3538 } 3539 acb->btag[0]=rman_get_bustag(acb->sys_res_arcmsr[0]); 3540 acb->bhandle[0]=rman_get_bushandle(acb->sys_res_arcmsr[0]); 3541 acb->pmu=(struct MessageUnit_UNION *)mem_base0; 3542 } 3543 break; 3544 case ACB_ADAPTER_TYPE_B: { 3545 struct HBB_MessageUnit *phbbmu; 3546 struct CommandControlBlock *freesrb; 3547 u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) }; 3548 vm_offset_t mem_base[]={0,0}; 3549 for(i=0; i<2; i++) { 3550 if(i==0) { 3551 acb->sys_res_arcmsr[i]=bus_alloc_resource(dev,SYS_RES_MEMORY, &rid[i], 3552 0x20400, 0x20400+sizeof(struct HBB_DOORBELL), sizeof(struct HBB_DOORBELL), RF_ACTIVE); 3553 } else { 3554 acb->sys_res_arcmsr[i]=bus_alloc_resource(dev, SYS_RES_MEMORY, &rid[i], 3555 0x0fa00, 0x0fa00+sizeof(struct HBB_RWBUFFER), sizeof(struct HBB_RWBUFFER), RF_ACTIVE); 3556 } 3557 if(acb->sys_res_arcmsr[i] == NULL) { 3558 arcmsr_free_resource(acb); 3559 printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i); 3560 return ENOMEM; 3561 } 3562 if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) { 3563 arcmsr_free_resource(acb); 3564 printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i); 3565 return ENXIO; 3566 } 3567 mem_base[i]=(vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]); 3568 if(mem_base[i]==0) { 3569 arcmsr_free_resource(acb); 3570 printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i); 3571 return ENXIO; 3572 } 3573 acb->btag[i]=rman_get_bustag(acb->sys_res_arcmsr[i]); 3574 acb->bhandle[i]=rman_get_bushandle(acb->sys_res_arcmsr[i]); 3575 } 3576 freesrb=(struct CommandControlBlock *)acb->uncacheptr; 3577 acb->pmu=(struct MessageUnit_UNION *)&freesrb[ARCMSR_MAX_FREESRB_NUM]; 3578 phbbmu=(struct HBB_MessageUnit *)acb->pmu; 3579 phbbmu->hbb_doorbell=(struct HBB_DOORBELL *)mem_base[0]; 3580 phbbmu->hbb_rwbuffer=(struct HBB_RWBUFFER *)mem_base[1]; 3581 } 3582 break; 3583 case ACB_ADAPTER_TYPE_C: { 3584 u_int32_t rid0=PCIR_BAR(1); 3585 vm_offset_t mem_base0; 3586 3587 acb->sys_res_arcmsr[0]=bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBC_MessageUnit), RF_ACTIVE); 3588 if(acb->sys_res_arcmsr[0] == NULL) { 3589 arcmsr_free_resource(acb); 3590 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 3591 return ENOMEM; 3592 } 3593 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 3594 arcmsr_free_resource(acb); 3595 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 3596 return ENXIO; 3597 } 3598 mem_base0=(vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 3599 if(mem_base0==0) { 3600 arcmsr_free_resource(acb); 3601 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 3602 return ENXIO; 3603 } 3604 acb->btag[0]=rman_get_bustag(acb->sys_res_arcmsr[0]); 3605 acb->bhandle[0]=rman_get_bushandle(acb->sys_res_arcmsr[0]); 3606 acb->pmu=(struct MessageUnit_UNION *)mem_base0; 3607 } 3608 break; 3609 } 3610 if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) { 3611 arcmsr_free_resource(acb); 3612 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev)); 3613 return ENXIO; 3614 } 3615 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 3616 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER; 3617 /* 3618 ******************************************************************** 3619 ** init raid volume state 3620 ******************************************************************** 3621 */ 3622 for(i=0;i<ARCMSR_MAX_TARGETID;i++) { 3623 for(j=0;j<ARCMSR_MAX_TARGETLUN;j++) { 3624 acb->devstate[i][j]=ARECA_RAID_GONE; 3625 } 3626 } 3627 arcmsr_iop_init(acb); 3628 return(0); 3629 } 3630 /* 3631 ************************************************************************ 3632 ************************************************************************ 3633 */ 3634 static int arcmsr_attach(device_t dev) 3635 { 3636 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 3637 u_int32_t unit=device_get_unit(dev); 3638 struct ccb_setasync csa; 3639 struct cam_devq *devq; /* Device Queue to use for this SIM */ 3640 struct resource *irqres; 3641 int rid; 3642 3643 if(acb == NULL) { 3644 printf("arcmsr%d: cannot allocate softc\n", unit); 3645 return (ENOMEM); 3646 } 3647 ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr Q buffer lock"); 3648 if(arcmsr_initialize(dev)) { 3649 printf("arcmsr%d: initialize failure!\n", unit); 3650 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 3651 return ENXIO; 3652 } 3653 /* After setting up the adapter, map our interrupt */ 3654 rid=0; 3655 irqres=bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1, RF_SHAREABLE | RF_ACTIVE); 3656 if(irqres == NULL || 3657 #if __FreeBSD_version >= 700025 3658 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih)) { 3659 #else 3660 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, arcmsr_intr_handler, acb, &acb->ih)) { 3661 #endif 3662 arcmsr_free_resource(acb); 3663 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 3664 printf("arcmsr%d: unable to register interrupt handler!\n", unit); 3665 return ENXIO; 3666 } 3667 acb->irqres=irqres; 3668 acb->pci_dev=dev; 3669 acb->pci_unit=unit; 3670 /* 3671 * Now let the CAM generic SCSI layer find the SCSI devices on 3672 * the bus * start queue to reset to the idle loop. * 3673 * Create device queue of SIM(s) * (MAX_START_JOB - 1) : 3674 * max_sim_transactions 3675 */ 3676 devq=cam_simq_alloc(ARCMSR_MAX_START_JOB); 3677 if(devq == NULL) { 3678 arcmsr_free_resource(acb); 3679 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 3680 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 3681 printf("arcmsr%d: cam_simq_alloc failure!\n", unit); 3682 return ENXIO; 3683 } 3684 #if __FreeBSD_version >= 700025 3685 acb->psim=cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->qbuffer_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq); 3686 #else 3687 acb->psim=cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq); 3688 #endif 3689 if(acb->psim == NULL) { 3690 arcmsr_free_resource(acb); 3691 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 3692 cam_simq_free(devq); 3693 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 3694 printf("arcmsr%d: cam_sim_alloc failure!\n", unit); 3695 return ENXIO; 3696 } 3697 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 3698 #if __FreeBSD_version >= 700044 3699 if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) { 3700 #else 3701 if(xpt_bus_register(acb->psim, 0) != CAM_SUCCESS) { 3702 #endif 3703 arcmsr_free_resource(acb); 3704 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 3705 cam_sim_free(acb->psim, /*free_devq*/TRUE); 3706 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 3707 printf("arcmsr%d: xpt_bus_register failure!\n", unit); 3708 return ENXIO; 3709 } 3710 if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 3711 arcmsr_free_resource(acb); 3712 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 3713 xpt_bus_deregister(cam_sim_path(acb->psim)); 3714 cam_sim_free(acb->psim, /* free_simq */ TRUE); 3715 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 3716 printf("arcmsr%d: xpt_create_path failure!\n", unit); 3717 return ENXIO; 3718 } 3719 /* 3720 **************************************************** 3721 */ 3722 xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5); 3723 csa.ccb_h.func_code=XPT_SASYNC_CB; 3724 csa.event_enable=AC_FOUND_DEVICE|AC_LOST_DEVICE; 3725 csa.callback=arcmsr_async; 3726 csa.callback_arg=acb->psim; 3727 xpt_action((union ccb *)&csa); 3728 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 3729 /* Create the control device. */ 3730 acb->ioctl_dev=make_dev(&arcmsr_cdevsw, unit, UID_ROOT, GID_WHEEL /* GID_OPERATOR */, S_IRUSR | S_IWUSR, "arcmsr%d", unit); 3731 3732 #if __FreeBSD_version < 503000 3733 acb->ioctl_dev->si_drv1=acb; 3734 #endif 3735 #if __FreeBSD_version > 500005 3736 (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit); 3737 #endif 3738 #if __FreeBSD_version > 500000 3739 callout_init(&acb->devmap_callout, /*mpsafe*/1); 3740 #else 3741 callout_init(&acb->devmap_callout); 3742 #endif 3743 callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb); 3744 return 0; 3745 } 3746 /* 3747 ************************************************************************ 3748 ************************************************************************ 3749 */ 3750 static int arcmsr_probe(device_t dev) 3751 { 3752 u_int32_t id; 3753 static char buf[256]; 3754 char *type; 3755 int raid6 = 1; 3756 3757 if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) { 3758 return (ENXIO); 3759 } 3760 switch(id=pci_get_devid(dev)) { 3761 case PCIDevVenIDARC1110: 3762 case PCIDevVenIDARC1210: 3763 case PCIDevVenIDARC1201: 3764 raid6 = 0; 3765 /*FALLTHRU*/ 3766 case PCIDevVenIDARC1120: 3767 case PCIDevVenIDARC1130: 3768 case PCIDevVenIDARC1160: 3769 case PCIDevVenIDARC1170: 3770 case PCIDevVenIDARC1220: 3771 case PCIDevVenIDARC1230: 3772 case PCIDevVenIDARC1260: 3773 case PCIDevVenIDARC1270: 3774 case PCIDevVenIDARC1280: 3775 type = "SATA"; 3776 break; 3777 case PCIDevVenIDARC1212: 3778 case PCIDevVenIDARC1222: 3779 case PCIDevVenIDARC1380: 3780 case PCIDevVenIDARC1381: 3781 case PCIDevVenIDARC1680: 3782 case PCIDevVenIDARC1681: 3783 type = "SAS 3G"; 3784 break; 3785 case PCIDevVenIDARC1880: 3786 type = "SAS 6G"; 3787 break; 3788 default: 3789 type = "X-TYPE"; 3790 break; 3791 } 3792 sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n", type, raid6 ? "(RAID6 capable)" : ""); 3793 device_set_desc_copy(dev, buf); 3794 return 0; 3795 } 3796 /* 3797 ************************************************************************ 3798 ************************************************************************ 3799 */ 3800 static int arcmsr_shutdown(device_t dev) 3801 { 3802 u_int32_t i; 3803 u_int32_t intmask_org; 3804 struct CommandControlBlock *srb; 3805 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 3806 3807 /* stop adapter background rebuild */ 3808 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 3809 /* disable all outbound interrupt */ 3810 intmask_org=arcmsr_disable_allintr(acb); 3811 arcmsr_stop_adapter_bgrb(acb); 3812 arcmsr_flush_adapter_cache(acb); 3813 /* abort all outstanding command */ 3814 acb->acb_flags |= ACB_F_SCSISTOPADAPTER; 3815 acb->acb_flags &= ~ACB_F_IOP_INITED; 3816 if(acb->srboutstandingcount!=0) { 3817 /*clear and abort all outbound posted Q*/ 3818 arcmsr_done4abort_postqueue(acb); 3819 /* talk to iop 331 outstanding command aborted*/ 3820 arcmsr_abort_allcmd(acb); 3821 for(i=0;i<ARCMSR_MAX_FREESRB_NUM;i++) { 3822 srb=acb->psrb_pool[i]; 3823 if(srb->startdone==ARCMSR_SRB_START) { 3824 srb->startdone=ARCMSR_SRB_ABORTED; 3825 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3826 arcmsr_srb_complete(srb, 1); 3827 } 3828 } 3829 } 3830 atomic_set_int(&acb->srboutstandingcount, 0); 3831 acb->workingsrb_doneindex=0; 3832 acb->workingsrb_startindex=0; 3833 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 3834 return (0); 3835 } 3836 /* 3837 ************************************************************************ 3838 ************************************************************************ 3839 */ 3840 static int arcmsr_detach(device_t dev) 3841 { 3842 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 3843 int i; 3844 3845 callout_stop(&acb->devmap_callout); 3846 bus_teardown_intr(dev, acb->irqres, acb->ih); 3847 arcmsr_shutdown(dev); 3848 arcmsr_free_resource(acb); 3849 for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) { 3850 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(i), acb->sys_res_arcmsr[i]); 3851 } 3852 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 3853 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 3854 xpt_async(AC_LOST_DEVICE, acb->ppath, NULL); 3855 xpt_free_path(acb->ppath); 3856 xpt_bus_deregister(cam_sim_path(acb->psim)); 3857 cam_sim_free(acb->psim, TRUE); 3858 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 3859 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 3860 return (0); 3861 } 3862 3863 3864