1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 * 30 */ 31 32 #define ASMC_MAXFANS 6 33 34 struct asmc_softc { 35 device_t sc_dev; 36 struct mtx sc_mtx; 37 int sc_nfan; 38 int16_t sms_rest_x; 39 int16_t sms_rest_y; 40 int16_t sms_rest_z; 41 struct sysctl_oid *sc_fan_tree[ASMC_MAXFANS+1]; 42 struct sysctl_oid *sc_temp_tree; 43 struct sysctl_oid *sc_sms_tree; 44 struct sysctl_oid *sc_light_tree; 45 struct asmc_model *sc_model; 46 int sc_rid_port; 47 int sc_rid_irq; 48 struct resource *sc_ioport; 49 struct resource *sc_irq; 50 void *sc_cookie; 51 int sc_sms_intrtype; 52 struct taskqueue *sc_sms_tq; 53 struct task sc_sms_task; 54 uint8_t sc_sms_intr_works; 55 }; 56 57 /* 58 * Data port. 59 */ 60 #define ASMC_DATAPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x00) 61 #define ASMC_DATAPORT_WRITE(sc, val) \ 62 bus_write_1(sc->sc_ioport, 0x00, val) 63 #define ASMC_STATUS_MASK 0x0f 64 65 /* 66 * Command port. 67 */ 68 #define ASMC_CMDPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x04) 69 #define ASMC_CMDPORT_WRITE(sc, val) \ 70 bus_write_1(sc->sc_ioport, 0x04, val) 71 #define ASMC_CMDREAD 0x10 72 #define ASMC_CMDWRITE 0x11 73 74 /* 75 * Interrupt port. 76 */ 77 #define ASMC_INTPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x1f) 78 79 80 /* Number of keys */ 81 #define ASMC_NKEYS "#KEY" /* RO; 4 bytes */ 82 83 /* 84 * Fan control via SMC. 85 */ 86 #define ASMC_KEY_FANCOUNT "FNum" /* RO; 1 byte */ 87 #define ASMC_KEY_FANMANUAL "FS! " /* RW; 2 bytes */ 88 #define ASMC_KEY_FANID "F%dID" /* RO; 16 bytes */ 89 #define ASMC_KEY_FANSPEED "F%dAc" /* RO; 2 bytes */ 90 #define ASMC_KEY_FANMINSPEED "F%dMn" /* RO; 2 bytes */ 91 #define ASMC_KEY_FANMAXSPEED "F%dMx" /* RO; 2 bytes */ 92 #define ASMC_KEY_FANSAFESPEED "F%dSf" /* RO; 2 bytes */ 93 #define ASMC_KEY_FANTARGETSPEED "F%dTg" /* RW; 2 bytes */ 94 95 /* 96 * Sudden Motion Sensor (SMS). 97 */ 98 #define ASMC_SMS_INIT1 0xe0 99 #define ASMC_SMS_INIT2 0xf8 100 #define ASMC_KEY_SMS "MOCN" /* RW; 2 bytes */ 101 #define ASMC_KEY_SMS_X "MO_X" /* RO; 2 bytes */ 102 #define ASMC_KEY_SMS_Y "MO_Y" /* RO; 2 bytes */ 103 #define ASMC_KEY_SMS_Z "MO_Z" /* RO; 2 bytes */ 104 #define ASMC_KEY_SMS_LOW "MOLT" /* RW; 2 bytes */ 105 #define ASMC_KEY_SMS_HIGH "MOHT" /* RW; 2 bytes */ 106 #define ASMC_KEY_SMS_LOW_INT "MOLD" /* RW; 1 byte */ 107 #define ASMC_KEY_SMS_HIGH_INT "MOHD" /* RW; 1 byte */ 108 #define ASMC_KEY_SMS_FLAG "MSDW" /* RW; 1 byte */ 109 #define ASMC_SMS_INTFF 0x60 /* Free fall Interrupt */ 110 #define ASMC_SMS_INTHA 0x6f /* High Acceleration Interrupt */ 111 #define ASMC_SMS_INTSH 0x80 /* Shock Interrupt */ 112 113 /* 114 * Keyboard backlight. 115 */ 116 #define ASMC_KEY_LIGHTLEFT "ALV0" /* RO; 6 bytes */ 117 #define ASMC_KEY_LIGHTRIGHT "ALV1" /* RO; 6 bytes */ 118 #define ASMC_KEY_LIGHTVALUE "LKSB" /* WO; 2 bytes */ 119 120 /* 121 * Clamshell. 122 */ 123 #define ASMC_KEY_CLAMSHELL "MSLD" /* RO; 1 byte */ 124 125 /* 126 * Interrupt keys. 127 */ 128 #define ASMC_KEY_INTOK "NTOK" /* WO; 1 byte */ 129 130 /* 131 * Temperatures. 132 * 133 * First for MacBook, second for MacBook Pro, third for Intel Mac Mini, 134 * fourth the Mac Pro 8-core and finally the MacBook Air. 135 * 136 */ 137 /* maximum array size for temperatures including the last NULL */ 138 #define ASMC_TEMP_MAX 80 139 #define ASMC_MB_TEMPS { "TB0T", "TN0P", "TN1P", "Th0H", "Th1H", \ 140 "TM0P", NULL } 141 #define ASMC_MB_TEMPNAMES { "enclosure", "northbridge1", \ 142 "northbridge2", "heatsink1", \ 143 "heatsink2", "memory", } 144 #define ASMC_MB_TEMPDESCS { "Enclosure Bottomside", \ 145 "Northbridge Point 1", \ 146 "Northbridge Point 2", "Heatsink 1", \ 147 "Heatsink 2", "Memory Bank A", } 148 149 #define ASMC_MB31_TEMPS { "TB0T", "TN0P", "Th0H", "Th1H", \ 150 "TM0P", NULL } 151 152 #define ASMC_MB31_TEMPNAMES { "enclosure", "northbridge1", \ 153 "heatsink1", "heatsink2", \ 154 "memory", } 155 156 #define ASMC_MB31_TEMPDESCS { "Enclosure Bottomside", \ 157 "Northbridge Point 1", \ 158 "Heatsink 1","Heatsink 2" \ 159 "Memory Bank A", } 160 161 #define ASMC_MBP_TEMPS { "TB0T", "Th0H", "Th1H", "Tm0P", \ 162 "TG0H", "TG0P", "TG0T", NULL } 163 164 #define ASMC_MBP_TEMPNAMES { "enclosure", "heatsink1", \ 165 "heatsink2", "memory", "graphics", \ 166 "graphicssink", "unknown", } 167 168 #define ASMC_MBP_TEMPDESCS { "Enclosure Bottomside", \ 169 "Heatsink 1", "Heatsink 2", \ 170 "Memory Controller", \ 171 "Graphics Chip", "Graphics Heatsink", \ 172 "Unknown", } 173 174 #define ASMC_MBP4_TEMPS { "TB0T", "Th0H", "Th1H", "Th2H", "Tm0P", \ 175 "TG0H", "TG0D", "TC0D", "TC0P", "Ts0P", \ 176 "TTF0", "TW0P", NULL } 177 178 #define ASMC_MBP4_TEMPNAMES { "enclosure", "heatsink1", "heatsink2", \ 179 "heatsink3", "memory", "graphicssink", \ 180 "graphics", "cpu", "cpu2", "unknown1", \ 181 "unknown2", "wireless", } 182 183 #define ASMC_MBP4_TEMPDESCS { "Enclosure Bottomside", \ 184 "Main Heatsink 1", "Main Heatsink 2", \ 185 "Main Heatsink 3", \ 186 "Memory Controller", \ 187 "Graphics Chip Heatsink", \ 188 "Graphics Chip Diode", \ 189 "CPU Temperature Diode", "CPU Point 2", \ 190 "Unknown", "Unknown", \ 191 "Wireless Module", } 192 193 #define ASMC_MBP5_TEMPS { "TB0T", "TB1T", "TB2T", "TB3T", "TC0D", \ 194 "TC0F", "TC0P", "TG0D", "TG0F", "TG0H", \ 195 "TG0P", "TG0T", "TG1H", "TN0D", "TN0P", \ 196 "TTF0", "Th2H", "Tm0P", "Ts0P", "Ts0S", \ 197 NULL } 198 199 #define ASMC_MBP5_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \ 200 "enclosure_bottom_2", "enclosure_bottom_3", \ 201 "cpu_diode", "cpu", \ 202 "cpu_pin", "gpu_diode", \ 203 "gpu", "gpu_heatsink", \ 204 "gpu_pin", "gpu_transistor", \ 205 "gpu_2_heatsink", "northbridge_diode", \ 206 "northbridge_pin", "unknown", \ 207 "heatsink_2", "memory_controller", \ 208 "pci_express_slot_pin", "pci_express_slot_unk" } 209 210 #define ASMC_MBP5_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \ 211 "Enclosure Bottom 2", "Enclosure Bottom 3", \ 212 "CPU Diode", "CPU ???", \ 213 "CPU Pin", "GPU Diode", \ 214 "GPU ???", "GPU Heatsink", \ 215 "GPU Pin", "GPU Transistor", \ 216 "GPU 2 Heatsink", "Northbridge Diode", \ 217 "Northbridge Pin", "Unknown", \ 218 "Heatsink 2", "Memory Controller", \ 219 "PCI Express Slot Pin", "PCI Express Slot (unk)" } 220 221 #define ASMC_MBP81_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \ 222 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 223 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \ 224 "TP0P", "TPCD", "TW0P", "Th1H", "Ts0P", \ 225 "Ts0S", NULL } 226 227 #define ASMC_MBP81_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \ 228 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 229 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \ 230 "TP0P", "TPCD", "wireless", "Th1H", "Ts0P", \ 231 "Ts0S" } 232 233 #define ASMC_MBP81_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \ 234 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 235 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \ 236 "TP0P", "TPCD", "TW0P", "Th1H", "Ts0P", \ 237 "Ts0S" } 238 239 #define ASMC_MBP82_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \ 240 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 241 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 242 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \ 243 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \ 244 "Th2H", "Tm0P", "Ts0P", "Ts0S", NULL } 245 246 #define ASMC_MBP82_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \ 247 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 248 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 249 "TCTD", "graphics", "TG0P", "THSP", "TM0S", \ 250 "TMBS", "TP0P", "TPCD", "wireless", "Th1H", \ 251 "Th2H", "memory", "Ts0P", "Ts0S" } 252 253 #define ASMC_MBP82_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \ 254 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 255 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 256 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \ 257 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \ 258 "Th2H", "Tm0P", "Ts0P", "Ts0S" } 259 260 #define ASMC_MBP9_TEMPS { "Ts0P", "Ts0S", "TA0P", "TB1T", "TB2T", \ 261 "TB0T", "TC1C", "TC2C", "TC0E", "TC0F", \ 262 "TC0J", "TC0P", "TCFC", "TCGC", "TCSA", \ 263 "TCTD", "TCXC", "TG1D", "TM0P", "TM0S", \ 264 "TPCD", NULL } 265 266 #define ASMC_MBP9_TEMPNAMES { "Ts0P", "Ts0S", "TA0P", "TB1T", "TB2T", \ 267 "TB0T", "TC1C", "TC2C", "TC0E", "TC0F", \ 268 "TC0J", "TC0P", "TCFC", "TCGC", "TCSA", \ 269 "TCTD", "TCXC", "TG1D", "TM0P", "TM0S", \ 270 "TPCD" } 271 272 #define ASMC_MBP9_TEMPDESCS { "Palm Rest", "Memory Proximity", "Airflow 1", \ 273 "Battery 1", "Battery 2", "Battery TS_MAX", \ 274 "CPU Core 1", "CPU Core 2", "CPU1", "CPU1", \ 275 "TC0J", "CPU 1 Proximity", "TCFC", \ 276 "PECI GPU", "PECI SA", "TCTD", "PECI CPU", \ 277 "GPU Die", "Memory Bank A1", "Memory Module A1", \ 278 "PCH Die" } 279 280 281 #define ASMC_MBP112_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 282 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 283 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 284 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 285 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 286 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 287 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 288 "Ts1S", NULL } 289 290 #define ASMC_MBP112_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 291 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 292 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 293 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 294 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 295 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 296 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 297 "Ts1S" } 298 299 #define ASMC_MBP112_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 300 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 301 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 302 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \ 303 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 304 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 305 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 306 "Ts1S" } 307 308 #define ASMC_MBP113_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 309 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 310 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 311 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 312 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 313 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 314 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 315 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 316 "Ts1S", NULL } 317 318 #define ASMC_MBP113_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 319 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 320 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 321 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 322 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 323 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 324 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 325 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 326 "Ts1S" } 327 328 #define ASMC_MBP113_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 329 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 330 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 331 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 332 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 333 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 334 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 335 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 336 "Ts1S" } 337 338 339 #define ASMC_MM_TEMPS { "TN0P", "TN1P", NULL } 340 #define ASMC_MM_TEMPNAMES { "northbridge1", "northbridge2" } 341 #define ASMC_MM_TEMPDESCS { "Northbridge Point 1", \ 342 "Northbridge Point 2" } 343 344 #define ASMC_MM21_TEMPS { "TA0P", "TC0D", \ 345 "TC0H", "TC0P", \ 346 "TC1P", "TN0P", \ 347 "TN1P", NULL } 348 349 #define ASMC_MM21_TEMPNAMES { "ambient_air", "cpu_die", \ 350 "cpu_heatsink", "cpu_proximity1", \ 351 "cpu_proximity2", "northbridge_proximity1", \ 352 "northbridge_proximity2", } 353 354 #define ASMC_MM21_TEMPDESCS { "Ambient Air Temperature" \ 355 "CPU Die Core Temperature", \ 356 "CPU Heatsink Temperature", \ 357 "CPU Proximity 1 Temperature", \ 358 "CPU Proximity 2 Temperature", \ 359 "Northbridge Proximity 1 Temperature", \ 360 "Northbridge Proximity 2 Temperature", } 361 362 #define ASMC_MM31_TEMPS { "TC0D", "TC0H", \ 363 "TC0P", "TH0P", \ 364 "TN0D", "TN0P", \ 365 "TW0P", NULL } 366 367 #define ASMC_MM31_TEMPNAMES { "cpu0_die", "cpu0_heatsink", \ 368 "cpu0_proximity", "hdd_bay", \ 369 "northbridge_die", \ 370 "northbridge_proximity", \ 371 "wireless_proximity", } 372 373 #define ASMC_MM31_TEMPDESCS { "CPU0 Die Core Temperature", \ 374 "CPU0 Heatsink Temperature", \ 375 "CPU0 Proximity Temperature", \ 376 "HDD Bay Temperature", \ 377 "Northbridge Die Core Temperature", \ 378 "Northbridge Proximity Temperature", \ 379 "Wireless Module Proximity Temperature", } 380 381 #define ASMC_MM41_TEMPS { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \ 382 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \ 383 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \ 384 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \ 385 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \ 386 "TW0P", "Tm0P", "Tp0C", NULL } 387 388 #define ASMC_MM41_TEMPNAMES { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \ 389 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \ 390 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \ 391 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \ 392 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \ 393 "TW0P", "Tm0P", "Tp0C", NULL } 394 395 #define ASMC_MM41_TEMPDESCS { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \ 396 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \ 397 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \ 398 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \ 399 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \ 400 "TW0P", "Tm0P", "Tp0C", NULL } 401 402 #define ASMC_MM52_TEMPS { "TA0P", "TA1P", \ 403 "TC0D", "TC0P", \ 404 "TG0D", "TG1D", \ 405 "TG0P", "TG0M", \ 406 "TI0P", \ 407 "TM0S", "TMBS", \ 408 "TM0P", "TP0P", \ 409 "TPCD", "Tp0C", \ 410 "TW0P", NULL } 411 412 #define ASMC_MM52_TEMPNAMES { "ambient_air_proximity", "ambient_cpu_pch_wireless_dimm", \ 413 "cpu_die", "cpu_proximity", \ 414 "gpu_diode1", "gpu_diode2", \ 415 "gpu_proximity", "gpu_integrated_switcher", \ 416 "thunderbolt_proximity", \ 417 "memory_slot1", "memory_slot2", \ 418 "memory_proximity", "pch_controller_proximity", \ 419 "pch_controller_die", "pwr_supply", \ 420 "wireless_proximity", } 421 422 #define ASMC_MM52_TEMPDESCS { "Ambient Air Proximity Temperature", \ 423 "Combo Ambient CPU PCH Wireless DIMM Temperature", \ 424 "CPU Die Temperature", "CPU Proximity Temperature", \ 425 "GPU Diode 1 Temperature" , "GPU Diode 2 Temperature", \ 426 "GPU Proximity Temperature", \ 427 "Integrated Graphics/GPU Switcher Temperature", \ 428 "Thunderbolt Proximity Temperature", \ 429 "Memory Slot 1 Temperature", \ 430 "Memory Slot 2 Temperature", \ 431 "Memory Slots Proximity Temperature", \ 432 "Platform Controller Hub Proximity Temperature", \ 433 "Platform Controller Hub Die Temperature", \ 434 "Power Supply Temperature", \ 435 "Wireless Module Proximity Temperature", } 436 437 #define ASMC_MP1_TEMPS { "TA0P", \ 438 "TCAH", "TCBH", \ 439 "TC0P", "TC0C", "TC1C", \ 440 "TC2C", "TC3C", "THTG", \ 441 "TH0P", "TH1P", \ 442 "TH2P", "TH3P", \ 443 "TM0P", "TM1P", "TM2P", \ 444 "TM8P", "TM9P", "TMAP", \ 445 "TM0S", "TM1S", "TM2P", "TM3S", \ 446 "TM8S", "TM9S", "TMAS", "TMBS", \ 447 "TN0H", "TS0C", \ 448 "Tp0C", "Tp1C", "Tv0S", "Tv1S", NULL } 449 450 #define ASMC_MP1_TEMPNAMES { "ambient", \ 451 "cpu_a_heatsink", "cpu_b_heatsink", \ 452 "cpu_a_proximity", "cpu_core0", "cpu_core1", \ 453 "cpu_core2", "cpu_core3", "THTG", \ 454 "hdd_bay0", "hdd_bay1", \ 455 "hdd_bay2", "hdd_bay3", \ 456 "memory_card_a_proximity0", \ 457 "memory_card_a_proximity1", \ 458 "memory_card_a_proximity2", \ 459 "memory_card_b_proximity0", \ 460 "memory_card_b_proximity1", \ 461 "memory_card_b_proximity2", \ 462 "memory_card_a_slot0", \ 463 "memory_card_a_slot1", \ 464 "memory_card_a_slot2", \ 465 "memory_card_a_slot3", \ 466 "memory_card_b_slot0", \ 467 "memory_card_b_slot1", \ 468 "memory_card_b_slot2", \ 469 "memory_card_b_slot3", \ 470 "mch_heatsink", "expansion_slots", \ 471 "power_supply_loc0", "power_supply_loc1", \ 472 "Tv0S", "Tv1S", } 473 474 #define ASMC_MP1_TEMPDESCS { "Ambient Air", \ 475 "CPU A Heatsink", "CPU B Heatsink", \ 476 "CPU A Proximity", \ 477 "CPU Core 1", "CPU Core 2", \ 478 "CPU Core 3", "CPU Core 4", "THTG", \ 479 "Hard Drive Bay 1", "Hard Drive Bay 2", \ 480 "Hard Drive Bay 3", "Hard Drive Bay 4", \ 481 "Memory Riser A, Proximity 1", \ 482 "Memory Riser A, Proximity 2", \ 483 "Memory Riser A, Proximity 3", \ 484 "Memory Riser B, Proximity 1", \ 485 "Memory Riser B, Proximity 2", \ 486 "Memory Riser B, Proximity 3", \ 487 "Memory Riser A, Slot 1", \ 488 "Memory Riser A, Slot 2", \ 489 "Memory Riser A, Slot 3", \ 490 "Memory Riser A, Slot 4", \ 491 "Memory Riser B, Slot 1", \ 492 "Memory Riser B, Slot 2", \ 493 "Memory Riser B, Slot 3", \ 494 "Memory Riser B, Slot 4", \ 495 "MCH Heatsink", "Expansion Slots", \ 496 "Power Supply, Location 1", \ 497 "Power Supply, Location 2", \ 498 "Tv0S", "Tv1S", } 499 500 #define ASMC_MP2_TEMPS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 501 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 502 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 503 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 504 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 505 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 506 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", \ 507 NULL } 508 509 #define ASMC_MP2_TEMPNAMES { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 510 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 511 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 512 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 513 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 514 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 515 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", } 516 517 #define ASMC_MP2_TEMPDESCS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 518 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 519 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 520 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 521 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 522 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 523 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", } 524 525 #define ASMC_MP5_TEMPS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \ 526 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 527 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 528 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 529 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 530 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 531 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 532 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \ 533 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \ 534 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \ 535 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 536 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 537 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 538 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 539 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", \ 540 NULL } 541 542 #define ASMC_MP5_TEMPNAMES { "ambient", "TCAC", "TCAD", "TCAG", "TCAH", \ 543 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 544 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 545 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 546 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 547 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 548 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 549 "TM7V", "TM8P", "TM8V", "TM9V", "ram_a1", \ 550 "ram_a2", "ram_a3", "ram_a4", "ram_b1", "ram_b2", \ 551 "ram_b3", "ram_b4", "TMHS", "TMLS", "TMPS", \ 552 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 553 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 554 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 555 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 556 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", } 557 558 #define ASMC_MP5_TEMPDESCS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \ 559 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 560 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 561 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 562 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 563 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 564 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 565 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \ 566 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \ 567 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \ 568 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 569 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 570 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 571 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 572 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", } 573 574 #define ASMC_MBA_TEMPS { "TB0T", NULL } 575 #define ASMC_MBA_TEMPNAMES { "enclosure" } 576 #define ASMC_MBA_TEMPDESCS { "Enclosure Bottom" } 577 578 #define ASMC_MBA3_TEMPS { "TB0T", "TB1T", "TB2T", \ 579 "TC0D", "TC0E", "TC0P", NULL } 580 581 #define ASMC_MBA3_TEMPNAMES { "enclosure", "TB1T", "TB2T", \ 582 "TC0D", "TC0E", "TC0P" } 583 584 #define ASMC_MBA3_TEMPDESCS { "Enclosure Bottom", "TB1T", "TB2T", \ 585 "TC0D", "TC0E", "TC0P" } 586 587 #define ASMC_MBA5_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", \ 588 "TC0D", "TC0E", "TC0F", "TC0P", \ 589 "TC1C", "TC2C", "TCGC", "TCSA", \ 590 "TCXC", "THSP", "TM0P", "TPCD", \ 591 "Ta0P", "Th1H", "Tm0P", "Tm1P", \ 592 "Ts0P", "Ts0S", NULL } 593 594 #define ASMC_MBA5_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", "TC0C", \ 595 "cpudiode", "cputemp1", "cputemp2", "cpuproximity", \ 596 "cpucore1", "cpucore2", "cpupeci", "pecisa", \ 597 "TCXC", "THSP", "memorybank", "pchdie", \ 598 "Ta0P", "heatpipe", "mainboardproximity1", "mainboardproximity2", \ 599 "palmrest", "memoryproximity" } 600 601 #define ASMC_MBA5_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", "TC0C",\ 602 "CPU Diode", "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \ 603 "CPU Core 1", "CPU Core 2", "CPU Peci Core", "PECI SA", \ 604 "TCXC", "THSP", "Memory Bank A", "PCH Die", \ 605 "Ta0P", "Heatpipe", "Mainboard Proximity 1", "Mainboard Proximity 2", \ 606 "Palm Rest", "Memory Proximity" } 607 608 #define ASMC_MBA7_TEMPS { "TB0T", "TB1T", "TB2T", \ 609 "TC0E", "TC0F", "TC0P", \ 610 "TC1C", "TC2C", \ 611 "TCGC", "TCSA", "TCXC", \ 612 "THSP", "TM0P", "TPCD", \ 613 "TW0P" "Ta0P", "Th1H", \ 614 "Tm0P", "Ts0P", "Ts0S", NULL } 615 616 #define ASMC_MBA7_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", \ 617 "cputemp1", "cputemp2", "cpuproximity", \ 618 "cpucore1", "cpucore2", \ 619 "pecigpu", "pecisa", "pecicpu", \ 620 "thunderboltproximity", "memorybank", "pchdie", \ 621 "wirelessproximity", "airflowproximity", "heatpipe", \ 622 "mainboardproximity", "palmrest", "memoryproximity" } 623 624 #define ASMC_MBA7_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", \ 625 "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \ 626 "CPU Core 1", "CPU Core 2", \ 627 "PECI GPU", "PECI SA", "PECI CPU", \ 628 "Thunderbolt Proximity", "Memory Bank A", "PCH Die", \ 629 "Wireless Proximity", "Airflow Proxmity", "Heatpipe", \ 630 "Mainboard Proximity", "Palm Rest", "Memory Proximity" } 631