1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/ata.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/malloc.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/sema.h> 41 #include <sys/taskqueue.h> 42 #include <vm/uma.h> 43 #include <machine/stdarg.h> 44 #include <machine/resource.h> 45 #include <machine/bus.h> 46 #include <sys/rman.h> 47 #include <dev/ata/ata-all.h> 48 #include <ata_if.h> 49 50 void 51 ata_sata_phy_check_events(device_t dev, int port) 52 { 53 struct ata_channel *ch = device_get_softc(dev); 54 u_int32_t error, status; 55 56 ata_sata_scr_read(ch, port, ATA_SERROR, &error); 57 /* Clear set error bits/interrupt. */ 58 if (error) 59 ata_sata_scr_write(ch, port, ATA_SERROR, error); 60 61 /* if we have a connection event deal with it */ 62 if ((error & ATA_SE_PHY_CHANGED) && (ch->pm_level == 0)) { 63 if (bootverbose) { 64 ata_sata_scr_read(ch, port, ATA_SSTATUS, &status); 65 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 66 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 67 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) { 68 device_printf(dev, "CONNECT requested\n"); 69 } else 70 device_printf(dev, "DISCONNECT requested\n"); 71 } 72 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 73 } 74 } 75 76 int 77 ata_sata_scr_read(struct ata_channel *ch, int port, int reg, uint32_t *val) 78 { 79 80 if (ch->hw.pm_read != NULL) 81 return (ch->hw.pm_read(ch->dev, port, reg, val)); 82 if (ch->r_io[reg].res) { 83 *val = ATA_IDX_INL(ch, reg); 84 return (0); 85 } 86 return (-1); 87 } 88 89 int 90 ata_sata_scr_write(struct ata_channel *ch, int port, int reg, uint32_t val) 91 { 92 93 if (ch->hw.pm_write != NULL) 94 return (ch->hw.pm_write(ch->dev, port, reg, val)); 95 if (ch->r_io[reg].res) { 96 ATA_IDX_OUTL(ch, reg, val); 97 return (0); 98 } 99 return (-1); 100 } 101 102 static int 103 ata_sata_connect(struct ata_channel *ch, int port, int quick) 104 { 105 u_int32_t status; 106 int timeout, t; 107 108 /* wait up to 1 second for "connect well" */ 109 timeout = (quick == 2) ? 0 : 100; 110 t = 0; 111 while (1) { 112 if (ata_sata_scr_read(ch, port, ATA_SSTATUS, &status)) 113 return (0); 114 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 115 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 116 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 117 break; 118 if (++t > timeout) 119 break; 120 ata_udelay(10000); 121 } 122 if (bootverbose) { 123 if (t > timeout) { 124 if (port < 0) { 125 device_printf(ch->dev, "SATA connect timeout status=%08x\n", 126 status); 127 } else { 128 device_printf(ch->dev, "p%d: SATA connect timeout status=%08x\n", 129 port, status); 130 } 131 } else if (port < 0) { 132 device_printf(ch->dev, "SATA connect time=%dms status=%08x\n", 133 t * 10, status); 134 } else { 135 device_printf(ch->dev, "p%d: SATA connect time=%dms status=%08x\n", 136 port, t * 10, status); 137 } 138 } 139 140 /* clear SATA error register */ 141 ata_sata_scr_write(ch, port, ATA_SERROR, 0xffffffff); 142 143 return ((t > timeout) ? 0 : 1); 144 } 145 146 int 147 ata_sata_phy_reset(device_t dev, int port, int quick) 148 { 149 struct ata_channel *ch = device_get_softc(dev); 150 int loop, retry; 151 uint32_t val; 152 153 if (quick) { 154 if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val)) 155 return (0); 156 if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE) 157 return ata_sata_connect(ch, port, quick); 158 } 159 160 if (bootverbose) { 161 if (port < 0) { 162 device_printf(dev, "hardware reset ...\n"); 163 } else { 164 device_printf(dev, "p%d: hardware reset ...\n", port); 165 } 166 } 167 for (retry = 0; retry < 10; retry++) { 168 for (loop = 0; loop < 10; loop++) { 169 if (ata_sata_scr_write(ch, port, ATA_SCONTROL, ATA_SC_DET_RESET)) 170 return (0); 171 ata_udelay(100); 172 if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val)) 173 return (0); 174 if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_RESET) 175 break; 176 } 177 ata_udelay(5000); 178 for (loop = 0; loop < 10; loop++) { 179 if (ata_sata_scr_write(ch, port, ATA_SCONTROL, 180 ATA_SC_DET_IDLE | ((ch->pm_level > 0) ? 0 : 181 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))) 182 return (0); 183 ata_udelay(100); 184 if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val)) 185 return (0); 186 if ((val & ATA_SC_DET_MASK) == 0) 187 return ata_sata_connect(ch, port, 0); 188 } 189 } 190 return 0; 191 } 192 193 int 194 ata_sata_setmode(device_t dev, int target, int mode) 195 { 196 197 return (min(mode, ATA_UDMA5)); 198 } 199 200 int 201 ata_sata_getrev(device_t dev, int target) 202 { 203 struct ata_channel *ch = device_get_softc(dev); 204 205 if (ch->r_io[ATA_SSTATUS].res) 206 return ((ATA_IDX_INL(ch, ATA_SSTATUS) & 0x0f0) >> 4); 207 return (0xff); 208 } 209 210 int 211 ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis) 212 { 213 214 if (request->flags & ATA_R_ATAPI) { 215 fis[0] = 0x27; /* host to device */ 216 fis[1] = 0x80 | (request->unit & 0x0f); 217 fis[2] = ATA_PACKET_CMD; 218 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) 219 fis[3] = ATA_F_DMA; 220 else { 221 fis[5] = request->transfersize; 222 fis[6] = request->transfersize >> 8; 223 } 224 fis[7] = ATA_D_LBA; 225 fis[15] = ATA_A_4BIT; 226 return 20; 227 } 228 else { 229 fis[0] = 0x27; /* host to device */ 230 fis[1] = 0x80 | (request->unit & 0x0f); 231 fis[2] = request->u.ata.command; 232 fis[3] = request->u.ata.feature; 233 fis[4] = request->u.ata.lba; 234 fis[5] = request->u.ata.lba >> 8; 235 fis[6] = request->u.ata.lba >> 16; 236 fis[7] = ATA_D_LBA; 237 if (!(request->flags & ATA_R_48BIT)) 238 fis[7] |= (ATA_D_IBM | (request->u.ata.lba >> 24 & 0x0f)); 239 fis[8] = request->u.ata.lba >> 24; 240 fis[9] = request->u.ata.lba >> 32; 241 fis[10] = request->u.ata.lba >> 40; 242 fis[11] = request->u.ata.feature >> 8; 243 fis[12] = request->u.ata.count; 244 fis[13] = request->u.ata.count >> 8; 245 fis[15] = ATA_A_4BIT; 246 return 20; 247 } 248 return 0; 249 } 250 251 void 252 ata_pm_identify(device_t dev) 253 { 254 struct ata_channel *ch = device_get_softc(dev); 255 u_int32_t pm_chipid, pm_revision, pm_ports; 256 int port; 257 258 /* get PM vendor & product data */ 259 if (ch->hw.pm_read(dev, ATA_PM, 0, &pm_chipid)) { 260 device_printf(dev, "error getting PM vendor data\n"); 261 return; 262 } 263 264 /* get PM revision data */ 265 if (ch->hw.pm_read(dev, ATA_PM, 1, &pm_revision)) { 266 device_printf(dev, "error getting PM revison data\n"); 267 return; 268 } 269 270 /* get number of HW ports on the PM */ 271 if (ch->hw.pm_read(dev, ATA_PM, 2, &pm_ports)) { 272 device_printf(dev, "error getting PM port info\n"); 273 return; 274 } 275 pm_ports &= 0x0000000f; 276 277 /* chip specific quirks */ 278 switch (pm_chipid) { 279 case 0x37261095: 280 /* This PM declares 6 ports, while only 5 of them are real. 281 * Port 5 is enclosure management bridge port, which has implementation 282 * problems, causing probe faults. Hide it for now. */ 283 device_printf(dev, "SiI 3726 (rev=%x) Port Multiplier with %d (5) ports\n", 284 pm_revision, pm_ports); 285 pm_ports = 5; 286 break; 287 288 case 0x47261095: 289 /* This PM declares 7 ports, while only 5 of them are real. 290 * Port 5 is some fake "Config Disk" with 640 sectors size, 291 * port 6 is enclosure management bridge port. 292 * Both fake ports has implementation problems, causing 293 * probe faults. Hide them for now. */ 294 device_printf(dev, "SiI 4726 (rev=%x) Port Multiplier with %d (5) ports\n", 295 pm_revision, pm_ports); 296 pm_ports = 5; 297 break; 298 299 default: 300 device_printf(dev, "Port Multiplier (id=%08x rev=%x) with %d ports\n", 301 pm_chipid, pm_revision, pm_ports); 302 } 303 304 /* reset all ports and register if anything connected */ 305 for (port=0; port < pm_ports; port++) { 306 u_int32_t signature; 307 308 if (!ata_sata_phy_reset(dev, port, 1)) 309 continue; 310 311 /* 312 * XXX: I have no idea how to properly wait for PMP port hardreset 313 * completion. Without this delay soft reset does not completes 314 * successfully. 315 */ 316 DELAY(1000000); 317 318 signature = ch->hw.softreset(dev, port); 319 320 if (bootverbose) 321 device_printf(dev, "p%d: SIGNATURE=%08x\n", port, signature); 322 323 /* figure out whats there */ 324 switch (signature >> 16) { 325 case 0x0000: 326 ch->devices |= (ATA_ATA_MASTER << port); 327 continue; 328 case 0xeb14: 329 ch->devices |= (ATA_ATAPI_MASTER << port); 330 continue; 331 } 332 } 333 } 334