1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_intel_chipinit(device_t dev); 56 static int ata_intel_ch_attach(device_t dev); 57 static void ata_intel_reset(device_t dev); 58 static void ata_intel_old_setmode(device_t dev, int mode); 59 static void ata_intel_new_setmode(device_t dev, int mode); 60 static void ata_intel_sata_setmode(device_t dev, int mode); 61 static int ata_intel_31244_ch_attach(device_t dev); 62 static int ata_intel_31244_ch_detach(device_t dev); 63 static int ata_intel_31244_status(device_t dev); 64 static void ata_intel_31244_tf_write(struct ata_request *request); 65 static void ata_intel_31244_reset(device_t dev); 66 67 /* misc defines */ 68 #define INTEL_AHCI 1 69 70 71 /* 72 * Intel chipset support functions 73 */ 74 static int 75 ata_intel_probe(device_t dev) 76 { 77 struct ata_pci_controller *ctlr = device_get_softc(dev); 78 static struct ata_chip_id ids[] = 79 {{ ATA_I82371FB, 0, 0, 2, ATA_WDMA2, "PIIX" }, 80 { ATA_I82371SB, 0, 0, 2, ATA_WDMA2, "PIIX3" }, 81 { ATA_I82371AB, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 82 { ATA_I82443MX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 83 { ATA_I82451NX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 84 { ATA_I82801AB, 0, 0, 2, ATA_UDMA2, "ICH0" }, 85 { ATA_I82801AA, 0, 0, 2, ATA_UDMA4, "ICH" }, 86 { ATA_I82372FB, 0, 0, 2, ATA_UDMA4, "ICH" }, 87 { ATA_I82801BA, 0, 0, 2, ATA_UDMA5, "ICH2" }, 88 { ATA_I82801BA_1, 0, 0, 2, ATA_UDMA5, "ICH2" }, 89 { ATA_I82801CA, 0, 0, 2, ATA_UDMA5, "ICH3" }, 90 { ATA_I82801CA_1, 0, 0, 2, ATA_UDMA5, "ICH3" }, 91 { ATA_I82801DB, 0, 0, 2, ATA_UDMA5, "ICH4" }, 92 { ATA_I82801DB_1, 0, 0, 2, ATA_UDMA5, "ICH4" }, 93 { ATA_I82801EB, 0, 0, 2, ATA_UDMA5, "ICH5" }, 94 { ATA_I82801EB_S1, 0, 0, 2, ATA_SA150, "ICH5" }, 95 { ATA_I82801EB_R1, 0, 0, 2, ATA_SA150, "ICH5" }, 96 { ATA_I6300ESB, 0, 0, 2, ATA_UDMA5, "6300ESB" }, 97 { ATA_I6300ESB_S1, 0, 0, 2, ATA_SA150, "6300ESB" }, 98 { ATA_I6300ESB_R1, 0, 0, 2, ATA_SA150, "6300ESB" }, 99 { ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" }, 100 { ATA_I82801FB_S1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 101 { ATA_I82801FB_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 102 { ATA_I82801FBM, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6M" }, 103 { ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" }, 104 { ATA_I82801GB_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 105 { ATA_I82801GB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 106 { ATA_I82801GB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 107 { ATA_I82801GBM_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7M" }, 108 { ATA_I82801GBM_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7M" }, 109 { ATA_I82801GBM_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7M" }, 110 { ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" }, 111 { ATA_I63XXESB2_S1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 112 { ATA_I63XXESB2_S2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 113 { ATA_I63XXESB2_R1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 114 { ATA_I63XXESB2_R2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 115 { ATA_I82801HB_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 116 { ATA_I82801HB_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 117 { ATA_I82801HB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 118 { ATA_I82801HB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 119 { ATA_I82801HB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 120 { ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" }, 121 { ATA_I82801HBM_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 122 { ATA_I82801HBM_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 123 { ATA_I82801HBM_S3, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 124 { ATA_I82801IB_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 125 { ATA_I82801IB_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 126 { ATA_I82801IB_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 127 { ATA_I82801IB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 128 { ATA_I82801IB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 129 { ATA_I82801IB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 130 { ATA_I82801JIB_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 131 { ATA_I82801JIB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 132 { ATA_I82801JIB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 133 { ATA_I82801JIB_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 134 { ATA_I82801JD_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 135 { ATA_I82801JD_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 136 { ATA_I82801JD_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 137 { ATA_I82801JD_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 138 { ATA_I31244, 0, 0, 2, ATA_SA150, "31244" }, 139 { 0, 0, 0, 0, 0, 0}}; 140 141 if (pci_get_vendor(dev) != ATA_INTEL_ID) 142 return ENXIO; 143 144 if (!(ctlr->chip = ata_match_chip(dev, ids))) 145 return ENXIO; 146 147 ata_set_desc(dev); 148 ctlr->chipinit = ata_intel_chipinit; 149 return 0; 150 } 151 152 static int 153 ata_intel_chipinit(device_t dev) 154 { 155 struct ata_pci_controller *ctlr = device_get_softc(dev); 156 157 if (ata_setup_interrupt(dev, ata_generic_intr)) 158 return ENXIO; 159 160 /* good old PIIX needs special treatment (not implemented) */ 161 if (ctlr->chip->chipid == ATA_I82371FB) { 162 ctlr->setmode = ata_intel_old_setmode; 163 } 164 165 /* the intel 31244 needs special care if in DPA mode */ 166 else if (ctlr->chip->chipid == ATA_I31244) { 167 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) { 168 ctlr->r_type2 = SYS_RES_MEMORY; 169 ctlr->r_rid2 = PCIR_BAR(0); 170 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 171 &ctlr->r_rid2, 172 RF_ACTIVE))) 173 return ENXIO; 174 ctlr->channels = 4; 175 ctlr->ch_attach = ata_intel_31244_ch_attach; 176 ctlr->ch_detach = ata_intel_31244_ch_detach; 177 ctlr->reset = ata_intel_31244_reset; 178 } 179 ctlr->setmode = ata_sata_setmode; 180 } 181 182 /* non SATA intel chips goes here */ 183 else if (ctlr->chip->max_dma < ATA_SA150) { 184 ctlr->channels = ctlr->chip->cfg2; 185 ctlr->ch_attach = ata_intel_ch_attach; 186 ctlr->ch_detach = ata_pci_ch_detach; 187 ctlr->setmode = ata_intel_new_setmode; 188 } 189 190 /* SATA parts can be either compat or AHCI */ 191 else { 192 /* force all ports active "the legacy way" */ 193 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f, 2); 194 195 ctlr->ch_attach = ata_intel_ch_attach; 196 ctlr->ch_detach = ata_pci_ch_detach; 197 ctlr->reset = ata_intel_reset; 198 199 /* 200 * if we have AHCI capability and AHCI or RAID mode enabled 201 * in BIOS we try for AHCI mode 202 */ 203 if ((ctlr->chip->cfg1 == INTEL_AHCI) && 204 (pci_read_config(dev, 0x90, 1) & 0xc0) && 205 (ata_ahci_chipinit(dev) != ENXIO)) 206 return 0; 207 208 /* if BAR(5) is IO it should point to SATA interface registers */ 209 ctlr->r_type2 = SYS_RES_IOPORT; 210 ctlr->r_rid2 = PCIR_BAR(5); 211 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 212 &ctlr->r_rid2, RF_ACTIVE))) 213 ctlr->setmode = ata_intel_sata_setmode; 214 else 215 ctlr->setmode = ata_sata_setmode; 216 217 /* enable PCI interrupt */ 218 pci_write_config(dev, PCIR_COMMAND, 219 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 220 } 221 return 0; 222 } 223 224 static int 225 ata_intel_ch_attach(device_t dev) 226 { 227 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 228 struct ata_channel *ch = device_get_softc(dev); 229 230 /* setup the usual register normal pci style */ 231 if (ata_pci_ch_attach(dev)) 232 return ENXIO; 233 234 /* if r_res2 is valid it points to SATA interface registers */ 235 if (ctlr->r_res2) { 236 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 237 ch->r_io[ATA_IDX_ADDR].offset = 0x00; 238 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2; 239 ch->r_io[ATA_IDX_DATA].offset = 0x04; 240 } 241 242 ch->flags |= ATA_ALWAYS_DMASTAT; 243 return 0; 244 } 245 246 static void 247 ata_intel_reset(device_t dev) 248 { 249 device_t parent = device_get_parent(dev); 250 struct ata_pci_controller *ctlr = device_get_softc(parent); 251 struct ata_channel *ch = device_get_softc(dev); 252 int mask, timeout; 253 254 /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */ 255 if (ctlr->chip->cfg1) { 256 mask = (0x0005 << ch->unit); 257 } 258 else { 259 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */ 260 if (pci_read_config(parent, 0x90, 1) & 0x04) 261 mask = 0x0003; 262 else { 263 mask = (0x0001 << ch->unit); 264 /* XXX SOS should be in intel_ch_attach if we grow it */ 265 ch->flags |= ATA_NO_SLAVE; 266 } 267 } 268 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2); 269 DELAY(10); 270 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2); 271 272 /* wait up to 1 sec for "connect well" */ 273 for (timeout = 0; timeout < 100 ; timeout++) { 274 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) && 275 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff)) 276 break; 277 ata_udelay(10000); 278 } 279 ata_generic_reset(dev); 280 } 281 282 static void 283 ata_intel_old_setmode(device_t dev, int mode) 284 { 285 /* NOT YET */ 286 } 287 288 static void 289 ata_intel_new_setmode(device_t dev, int mode) 290 { 291 device_t gparent = GRANDPARENT(dev); 292 struct ata_pci_controller *ctlr = device_get_softc(gparent); 293 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 294 struct ata_device *atadev = device_get_softc(dev); 295 int devno = (ch->unit << 1) + atadev->unit; 296 u_int32_t reg40 = pci_read_config(gparent, 0x40, 4); 297 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1); 298 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1); 299 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2); 300 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2); 301 u_int32_t mask40 = 0, new40 = 0; 302 u_int8_t mask44 = 0, new44 = 0; 303 int error; 304 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23, 305 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 }; 306 307 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 308 309 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) { 310 ata_print_cable(dev, "controller"); 311 mode = ATA_UDMA2; 312 } 313 314 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 315 316 if (bootverbose) 317 device_printf(dev, "%ssetting %s on %s chip\n", 318 (error) ? "FAILURE " : "", 319 ata_mode2str(mode), ctlr->chip->text); 320 if (!error) { 321 if (mode >= ATA_UDMA0) { 322 u_int8_t utimings[] = { 0x00, 0x01, 0x10, 0x01, 0x10, 0x01, 0x10 }; 323 324 pci_write_config(gparent, 0x48, reg48 | (0x0001 << devno), 2); 325 pci_write_config(gparent, 0x4a, 326 (reg4a & ~(0x3 << (devno << 2))) | 327 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2); 328 } 329 else { 330 pci_write_config(gparent, 0x48, reg48 & ~(0x0001 << devno), 2); 331 pci_write_config(gparent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2); 332 } 333 reg54 |= 0x0400; 334 if (mode >= ATA_UDMA2) 335 reg54 |= (0x1 << devno); 336 else 337 reg54 &= ~(0x1 << devno); 338 if (mode >= ATA_UDMA5) 339 reg54 |= (0x1000 << devno); 340 else 341 reg54 &= ~(0x1000 << devno); 342 343 pci_write_config(gparent, 0x54, reg54, 2); 344 345 reg40 &= ~0x00ff00ff; 346 reg40 |= 0x40774077; 347 348 if (atadev->unit == ATA_MASTER) { 349 mask40 = 0x3300; 350 new40 = timings[ata_mode2idx(mode)] << 8; 351 } 352 else { 353 mask44 = 0x0f; 354 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) | 355 (timings[ata_mode2idx(mode)] & 0x03); 356 } 357 if (ch->unit) { 358 mask40 <<= 16; 359 new40 <<= 16; 360 mask44 <<= 4; 361 new44 <<= 4; 362 } 363 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4); 364 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1); 365 366 atadev->mode = mode; 367 } 368 } 369 370 static void 371 ata_intel_sata_setmode(device_t dev, int mode) 372 { 373 struct ata_device *atadev = device_get_softc(dev); 374 375 if (atadev->param.satacapabilities != 0x0000 && 376 atadev->param.satacapabilities != 0xffff) { 377 378 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 379 int devno = (ch->unit << 1) + atadev->unit; 380 381 /* on some drives we need to set the transfer mode */ 382 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, 383 ata_limit_mode(dev, mode, ATA_UDMA6)); 384 385 /* set ATA_SSTATUS register offset */ 386 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, devno * 0x100); 387 388 /* query SATA STATUS for the speed */ 389 if ((ATA_IDX_INL(ch, ATA_IDX_DATA) & ATA_SS_CONWELL_MASK) == 390 ATA_SS_CONWELL_GEN2) 391 atadev->mode = ATA_SA300; 392 else 393 atadev->mode = ATA_SA150; 394 } 395 else { 396 mode = ata_limit_mode(dev, mode, ATA_UDMA5); 397 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 398 atadev->mode = mode; 399 } 400 } 401 402 static int 403 ata_intel_31244_ch_attach(device_t dev) 404 { 405 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 406 struct ata_channel *ch = device_get_softc(dev); 407 int i; 408 int ch_offset; 409 410 ata_pci_dmainit(dev); 411 412 ch_offset = 0x200 + ch->unit * 0x200; 413 414 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 415 ch->r_io[i].res = ctlr->r_res2; 416 417 /* setup ATA registers */ 418 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 419 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06; 420 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 421 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 422 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 423 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 424 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 425 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d; 426 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04; 427 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c; 428 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28; 429 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29; 430 431 /* setup DMA registers */ 432 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100; 433 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104; 434 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108; 435 436 /* setup SATA registers */ 437 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70; 438 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72; 439 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74; 440 441 ch->flags |= ATA_NO_SLAVE; 442 ata_pci_hw(dev); 443 ch->hw.status = ata_intel_31244_status; 444 ch->hw.tf_write = ata_intel_31244_tf_write; 445 446 /* enable PHY state change interrupt */ 447 ATA_OUTL(ctlr->r_res2, 0x4, 448 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); 449 return 0; 450 } 451 452 static int 453 ata_intel_31244_ch_detach(device_t dev) 454 { 455 456 ata_pci_dmafini(dev); 457 return (0); 458 } 459 460 static int 461 ata_intel_31244_status(device_t dev) 462 { 463 /* do we have any PHY events ? */ 464 ata_sata_phy_check_events(dev); 465 466 /* any drive action to take care of ? */ 467 return ata_pci_status(dev); 468 } 469 470 static void 471 ata_intel_31244_tf_write(struct ata_request *request) 472 { 473 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 474 struct ata_device *atadev = device_get_softc(request->dev); 475 476 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 477 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 478 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 479 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) | 480 (request->u.ata.lba & 0x00ff)); 481 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | 482 ((request->u.ata.lba >> 8) & 0x00ff)); 483 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 484 ((request->u.ata.lba >> 16) & 0x00ff)); 485 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(atadev->unit)); 486 } 487 else { 488 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 489 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 490 if (atadev->flags & ATA_D_USE_CHS) { 491 int heads, sectors; 492 493 if (atadev->param.atavalid & ATA_FLAG_54_58) { 494 heads = atadev->param.current_heads; 495 sectors = atadev->param.current_sectors; 496 } 497 else { 498 heads = atadev->param.heads; 499 sectors = atadev->param.sectors; 500 } 501 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1); 502 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 503 (request->u.ata.lba / (sectors * heads))); 504 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 505 (request->u.ata.lba / (sectors * heads)) >> 8); 506 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(atadev->unit) | 507 (((request->u.ata.lba% (sectors * heads)) / 508 sectors) & 0xf)); 509 } 510 else { 511 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 512 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 513 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 514 ATA_IDX_OUTB(ch, ATA_DRIVE, 515 ATA_D_IBM | ATA_D_LBA | ATA_DEV(atadev->unit) | 516 ((request->u.ata.lba >> 24) & 0x0f)); 517 } 518 } 519 } 520 521 static void 522 ata_intel_31244_reset(device_t dev) 523 { 524 if (ata_sata_phy_reset(dev)) 525 ata_generic_reset(dev); 526 } 527 528 ATA_DECLARE_DRIVER(ata_intel); 529 MODULE_DEPEND(ata_intel, ata_ahci, 1, 1, 1); 530