1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/module.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/ata.h> 37 #include <sys/bus.h> 38 #include <sys/endian.h> 39 #include <sys/malloc.h> 40 #include <sys/lock.h> 41 #include <sys/mutex.h> 42 #include <sys/sema.h> 43 #include <sys/taskqueue.h> 44 #include <vm/uma.h> 45 #include <machine/stdarg.h> 46 #include <machine/resource.h> 47 #include <machine/bus.h> 48 #include <sys/rman.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcireg.h> 51 #include <dev/ata/ata-all.h> 52 #include <dev/ata/ata-pci.h> 53 #include <ata_if.h> 54 55 /* local prototypes */ 56 static int ata_promise_chipinit(device_t dev); 57 static int ata_promise_ch_attach(device_t dev); 58 static int ata_promise_status(device_t dev); 59 static int ata_promise_dmastart(struct ata_request *request); 60 static int ata_promise_dmastop(struct ata_request *request); 61 static void ata_promise_dmareset(device_t dev); 62 static int ata_promise_setmode(device_t dev, int target, int mode); 63 static int ata_promise_tx2_ch_attach(device_t dev); 64 static int ata_promise_tx2_status(device_t dev); 65 static int ata_promise_mio_ch_attach(device_t dev); 66 static int ata_promise_mio_ch_detach(device_t dev); 67 static void ata_promise_mio_intr(void *data); 68 static int ata_promise_mio_status(device_t dev); 69 static int ata_promise_mio_command(struct ata_request *request); 70 static void ata_promise_mio_reset(device_t dev); 71 static int ata_promise_mio_pm_read(device_t dev, int port, int reg, u_int32_t *result); 72 static int ata_promise_mio_pm_write(device_t dev, int port, int reg, u_int32_t result); 73 static u_int32_t ata_promise_mio_softreset(device_t dev, int port); 74 static void ata_promise_mio_dmainit(device_t dev); 75 static void ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 76 static int ata_promise_mio_setmode(device_t dev, int target, int mode); 77 static int ata_promise_mio_getrev(device_t dev, int target); 78 static void ata_promise_sx4_intr(void *data); 79 static int ata_promise_sx4_command(struct ata_request *request); 80 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request); 81 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt); 82 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr); 83 84 /* misc defines */ 85 #define PR_OLD 0 86 #define PR_NEW 1 87 #define PR_TX 2 88 #define PR_MIO 3 89 #define PR_TX4 0x01 90 #define PR_SX4X 0x02 91 #define PR_SX6K 0x04 92 #define PR_PATA 0x08 93 #define PR_CMBO 0x10 94 #define PR_CMBO2 0x20 95 #define PR_SATA 0x40 96 #define PR_SATA2 0x80 97 98 /* 99 * Promise chipset support functions 100 */ 101 #define ATA_PDC_APKT_OFFSET 0x00000010 102 #define ATA_PDC_HPKT_OFFSET 0x00000040 103 #define ATA_PDC_ASG_OFFSET 0x00000080 104 #define ATA_PDC_LSG_OFFSET 0x000000c0 105 #define ATA_PDC_HSG_OFFSET 0x00000100 106 #define ATA_PDC_CHN_OFFSET 0x00000400 107 #define ATA_PDC_BUF_BASE 0x00400000 108 #define ATA_PDC_BUF_OFFSET 0x00100000 109 #define ATA_PDC_MAX_HPKT 8 110 #define ATA_PDC_WRITE_REG 0x00 111 #define ATA_PDC_WRITE_CTL 0x0e 112 #define ATA_PDC_WRITE_END 0x08 113 #define ATA_PDC_WAIT_NBUSY 0x10 114 #define ATA_PDC_WAIT_READY 0x18 115 #define ATA_PDC_1B 0x20 116 #define ATA_PDC_2B 0x40 117 118 struct host_packet { 119 u_int32_t addr; 120 TAILQ_ENTRY(host_packet) chain; 121 }; 122 123 struct ata_promise_sx4 { 124 struct mtx mtx; 125 TAILQ_HEAD(, host_packet) queue; 126 int busy; 127 }; 128 129 static int 130 ata_promise_probe(device_t dev) 131 { 132 struct ata_pci_controller *ctlr = device_get_softc(dev); 133 const struct ata_chip_id *idx; 134 static const struct ata_chip_id ids[] = 135 {{ ATA_PDC20246, 0, PR_OLD, 0x00, ATA_UDMA2, "PDC20246" }, 136 { ATA_PDC20262, 0, PR_NEW, 0x00, ATA_UDMA4, "PDC20262" }, 137 { ATA_PDC20263, 0, PR_NEW, 0x00, ATA_UDMA4, "PDC20263" }, 138 { ATA_PDC20265, 0, PR_NEW, 0x00, ATA_UDMA5, "PDC20265" }, 139 { ATA_PDC20267, 0, PR_NEW, 0x00, ATA_UDMA5, "PDC20267" }, 140 { ATA_PDC20268, 0, PR_TX, PR_TX4, ATA_UDMA5, "PDC20268" }, 141 { ATA_PDC20269, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20269" }, 142 { ATA_PDC20270, 0, PR_TX, PR_TX4, ATA_UDMA5, "PDC20270" }, 143 { ATA_PDC20271, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20271" }, 144 { ATA_PDC20275, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20275" }, 145 { ATA_PDC20276, 0, PR_TX, PR_SX6K, ATA_UDMA6, "PDC20276" }, 146 { ATA_PDC20277, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20277" }, 147 { ATA_PDC20318, 0, PR_MIO, PR_SATA, ATA_SA150, "PDC20318" }, 148 { ATA_PDC20319, 0, PR_MIO, PR_SATA, ATA_SA150, "PDC20319" }, 149 { ATA_PDC20371, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20371" }, 150 { ATA_PDC20375, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20375" }, 151 { ATA_PDC20376, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20376" }, 152 { ATA_PDC20377, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20377" }, 153 { ATA_PDC20378, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20378" }, 154 { ATA_PDC20379, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20379" }, 155 { ATA_PDC20571, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20571" }, 156 { ATA_PDC20575, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20575" }, 157 { ATA_PDC20579, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20579" }, 158 { ATA_PDC20771, 0, PR_MIO, PR_CMBO2, ATA_SA300, "PDC20771" }, 159 { ATA_PDC40775, 0, PR_MIO, PR_CMBO2, ATA_SA300, "PDC40775" }, 160 { ATA_PDC20617, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20617" }, 161 { ATA_PDC20618, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20618" }, 162 { ATA_PDC20619, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20619" }, 163 { ATA_PDC20620, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20620" }, 164 { ATA_PDC20621, 0, PR_MIO, PR_SX4X, ATA_UDMA5, "PDC20621" }, 165 { ATA_PDC20622, 0, PR_MIO, PR_SX4X, ATA_SA150, "PDC20622" }, 166 { ATA_PDC40518, 0, PR_MIO, PR_SATA2, ATA_SA150, "PDC40518" }, 167 { ATA_PDC40519, 0, PR_MIO, PR_SATA2, ATA_SA150, "PDC40519" }, 168 { ATA_PDC40718, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40718" }, 169 { ATA_PDC40719, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40719" }, 170 { ATA_PDC40779, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40779" }, 171 { 0, 0, 0, 0, 0, 0}}; 172 char buffer[64]; 173 uintptr_t devid = 0; 174 175 if (pci_get_vendor(dev) != ATA_PROMISE_ID) 176 return ENXIO; 177 178 if (!(idx = ata_match_chip(dev, ids))) 179 return ENXIO; 180 181 /* if we are on a SuperTrak SX6000 dont attach */ 182 if ((idx->cfg2 & PR_SX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 183 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 184 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 185 devid == ATA_I960RM) 186 return ENXIO; 187 188 strcpy(buffer, "Promise "); 189 strcat(buffer, idx->text); 190 191 /* if we are on a FastTrak TX4, adjust the interrupt resource */ 192 if ((idx->cfg2 & PR_TX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 193 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 194 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 195 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) { 196 static rman_res_t start = 0, end = 0; 197 198 if (pci_get_slot(dev) == 1) { 199 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end); 200 strcat(buffer, " (channel 0+1)"); 201 } 202 else if (pci_get_slot(dev) == 2 && start && end) { 203 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end); 204 strcat(buffer, " (channel 2+3)"); 205 } 206 else { 207 start = end = 0; 208 } 209 } 210 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 211 device_set_desc_copy(dev, buffer); 212 ctlr->chip = idx; 213 ctlr->chipinit = ata_promise_chipinit; 214 return (BUS_PROBE_LOW_PRIORITY); 215 } 216 217 static int 218 ata_promise_chipinit(device_t dev) 219 { 220 struct ata_pci_controller *ctlr = device_get_softc(dev); 221 int stat_reg; 222 223 if (ata_setup_interrupt(dev, ata_generic_intr)) 224 return ENXIO; 225 226 switch (ctlr->chip->cfg1) { 227 case PR_NEW: 228 /* setup clocks */ 229 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a); 230 /* FALLTHROUGH */ 231 232 case PR_OLD: 233 /* enable burst mode */ 234 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01); 235 ctlr->ch_attach = ata_promise_ch_attach; 236 ctlr->ch_detach = ata_pci_ch_detach; 237 ctlr->setmode = ata_promise_setmode; 238 return 0; 239 240 case PR_TX: 241 ctlr->ch_attach = ata_promise_tx2_ch_attach; 242 ctlr->ch_detach = ata_pci_ch_detach; 243 ctlr->setmode = ata_promise_setmode; 244 return 0; 245 246 case PR_MIO: 247 ctlr->r_type1 = SYS_RES_MEMORY; 248 ctlr->r_rid1 = PCIR_BAR(4); 249 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 250 &ctlr->r_rid1, RF_ACTIVE))) 251 goto failnfree; 252 253 ctlr->r_type2 = SYS_RES_MEMORY; 254 ctlr->r_rid2 = PCIR_BAR(3); 255 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 256 &ctlr->r_rid2, RF_ACTIVE))) 257 goto failnfree; 258 259 if (ctlr->chip->cfg2 == PR_SX4X) { 260 struct ata_promise_sx4 *hpkt; 261 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080); 262 263 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 264 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL, 265 ata_promise_sx4_intr, ctlr, &ctlr->handle)) { 266 device_printf(dev, "unable to setup interrupt\n"); 267 goto failnfree; 268 } 269 270 /* print info about cache memory */ 271 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n", 272 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4, 273 ((dimm >> 24) & 0xff), 274 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ? 275 " ECC enabled" : "" ); 276 277 /* adjust cache memory parameters */ 278 ATA_OUTL(ctlr->r_res2, 0x000c000c, 279 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000)); 280 281 /* setup host packet controls */ 282 hpkt = malloc(sizeof(struct ata_promise_sx4), 283 M_ATAPCI, M_NOWAIT | M_ZERO); 284 if (hpkt == NULL) { 285 device_printf(dev, "Cannot allocate HPKT\n"); 286 goto failnfree; 287 } 288 mtx_init(&hpkt->mtx, "ATA promise HPKT lock", NULL, MTX_DEF); 289 TAILQ_INIT(&hpkt->queue); 290 hpkt->busy = 0; 291 ctlr->chipset_data = hpkt; 292 ctlr->ch_attach = ata_promise_mio_ch_attach; 293 ctlr->ch_detach = ata_promise_mio_ch_detach; 294 ctlr->reset = ata_promise_mio_reset; 295 ctlr->setmode = ata_promise_setmode; 296 ctlr->channels = 4; 297 return 0; 298 } 299 300 /* mio type controllers need an interrupt intercept */ 301 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 302 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL, 303 ata_promise_mio_intr, ctlr, &ctlr->handle)) { 304 device_printf(dev, "unable to setup interrupt\n"); 305 goto failnfree; 306 } 307 308 switch (ctlr->chip->cfg2) { 309 case PR_PATA: 310 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) + 311 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2; 312 goto sata150; 313 case PR_CMBO: 314 ctlr->channels = 3; 315 goto sata150; 316 case PR_SATA: 317 ctlr->channels = 4; 318 sata150: 319 stat_reg = 0x6c; 320 break; 321 322 case PR_CMBO2: 323 ctlr->channels = 3; 324 goto sataii; 325 case PR_SATA2: 326 default: 327 ctlr->channels = 4; 328 sataii: 329 stat_reg = 0x60; 330 break; 331 } 332 333 /* prime fake interrupt register */ 334 ctlr->chipset_data = (void *)(uintptr_t)0xffffffff; 335 336 /* clear SATA status and unmask interrupts */ 337 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff); 338 339 /* enable "long burst length" on gen2 chips */ 340 if ((ctlr->chip->cfg2 == PR_SATA2) || (ctlr->chip->cfg2 == PR_CMBO2)) 341 ATA_OUTL(ctlr->r_res2, 0x44, ATA_INL(ctlr->r_res2, 0x44) | 0x2000); 342 343 ctlr->ch_attach = ata_promise_mio_ch_attach; 344 ctlr->ch_detach = ata_promise_mio_ch_detach; 345 ctlr->reset = ata_promise_mio_reset; 346 ctlr->setmode = ata_promise_mio_setmode; 347 ctlr->getrev = ata_promise_mio_getrev; 348 349 return 0; 350 } 351 352 failnfree: 353 if (ctlr->r_res2) 354 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 355 if (ctlr->r_res1) 356 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1); 357 return ENXIO; 358 } 359 360 static int 361 ata_promise_ch_attach(device_t dev) 362 { 363 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 364 struct ata_channel *ch = device_get_softc(dev); 365 366 if (ata_pci_ch_attach(dev)) 367 return ENXIO; 368 369 if (ctlr->chip->cfg1 == PR_NEW) { 370 ch->dma.start = ata_promise_dmastart; 371 ch->dma.stop = ata_promise_dmastop; 372 ch->dma.reset = ata_promise_dmareset; 373 } 374 375 ch->hw.status = ata_promise_status; 376 ch->flags |= ATA_NO_ATAPI_DMA; 377 ch->flags |= ATA_CHECKS_CABLE; 378 return 0; 379 } 380 381 static int 382 ata_promise_status(device_t dev) 383 { 384 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 385 struct ata_channel *ch = device_get_softc(dev); 386 387 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) { 388 return ata_pci_status(dev); 389 } 390 return 0; 391 } 392 393 static int 394 ata_promise_dmastart(struct ata_request *request) 395 { 396 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 397 struct ata_channel *ch = device_get_softc(request->parent); 398 399 if (request->flags & ATA_R_48BIT) { 400 ATA_OUTB(ctlr->r_res1, 0x11, 401 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02)); 402 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 403 ((request->flags & ATA_R_READ) ? 0x05000000 : 0x06000000) | 404 (request->bytecount >> 1)); 405 } 406 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) | 407 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 408 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, request->dma->sg_bus); 409 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 410 ((request->flags & ATA_R_READ) ? ATA_BMCMD_WRITE_READ : 0) | 411 ATA_BMCMD_START_STOP); 412 ch->dma.flags |= ATA_DMA_ACTIVE; 413 return 0; 414 } 415 416 static int 417 ata_promise_dmastop(struct ata_request *request) 418 { 419 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 420 struct ata_channel *ch = device_get_softc(request->parent); 421 int error; 422 423 if (request->flags & ATA_R_48BIT) { 424 ATA_OUTB(ctlr->r_res1, 0x11, 425 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02)); 426 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0); 427 } 428 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT); 429 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 430 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 431 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 432 ch->dma.flags &= ~ATA_DMA_ACTIVE; 433 return error; 434 } 435 436 static void 437 ata_promise_dmareset(device_t dev) 438 { 439 struct ata_channel *ch = device_get_softc(dev); 440 441 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 442 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 443 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 444 ch->flags &= ~ATA_DMA_ACTIVE; 445 } 446 447 static int 448 ata_promise_setmode(device_t dev, int target, int mode) 449 { 450 device_t parent = device_get_parent(dev); 451 struct ata_pci_controller *ctlr = device_get_softc(parent); 452 struct ata_channel *ch = device_get_softc(dev); 453 int devno = (ch->unit << 1) + target; 454 static const uint32_t timings[][2] = { 455 /* PR_OLD PR_NEW mode */ 456 { 0x004ff329, 0x004fff2f }, /* PIO 0 */ 457 { 0x004fec25, 0x004ff82a }, /* PIO 1 */ 458 { 0x004fe823, 0x004ff026 }, /* PIO 2 */ 459 { 0x004fe622, 0x004fec24 }, /* PIO 3 */ 460 { 0x004fe421, 0x004fe822 }, /* PIO 4 */ 461 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */ 462 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */ 463 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */ 464 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */ 465 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */ 466 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */ 467 { 0, 0x00424ef6 }, /* UDMA 3 */ 468 { 0, 0x004127f3 }, /* UDMA 4 */ 469 { 0, 0x004127f3 } /* UDMA 5 */ 470 }; 471 472 mode = min(mode, ctlr->chip->max_dma); 473 474 switch (ctlr->chip->cfg1) { 475 case PR_OLD: 476 case PR_NEW: 477 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 478 (pci_read_config(parent, 0x50, 2) & 479 (ch->unit ? 1 << 11 : 1 << 10))) { 480 ata_print_cable(dev, "controller"); 481 mode = ATA_UDMA2; 482 } 483 break; 484 485 case PR_TX: 486 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 487 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 488 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) { 489 ata_print_cable(dev, "controller"); 490 mode = ATA_UDMA2; 491 } 492 break; 493 494 case PR_MIO: 495 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 496 (ATA_INL(ctlr->r_res2, 497 (ctlr->chip->cfg2 & PR_SX4X ? 0x000c0260 : 0x0260) + 498 (ch->unit << 7)) & 0x01000000)) { 499 ata_print_cable(dev, "controller"); 500 mode = ATA_UDMA2; 501 } 502 break; 503 } 504 505 if (ctlr->chip->cfg1 < PR_TX) 506 pci_write_config(parent, 0x60 + (devno << 2), 507 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 508 return (mode); 509 } 510 511 static int 512 ata_promise_tx2_ch_attach(device_t dev) 513 { 514 struct ata_channel *ch = device_get_softc(dev); 515 516 if (ata_pci_ch_attach(dev)) 517 return ENXIO; 518 519 ch->hw.status = ata_promise_tx2_status; 520 ch->flags |= ATA_CHECKS_CABLE; 521 return 0; 522 } 523 524 static int 525 ata_promise_tx2_status(device_t dev) 526 { 527 struct ata_channel *ch = device_get_softc(dev); 528 529 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 530 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) { 531 return ata_pci_status(dev); 532 } 533 return 0; 534 } 535 536 static int 537 ata_promise_mio_ch_attach(device_t dev) 538 { 539 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 540 struct ata_channel *ch = device_get_softc(dev); 541 int offset = (ctlr->chip->cfg2 & PR_SX4X) ? 0x000c0000 : 0; 542 int i; 543 544 ata_promise_mio_dmainit(dev); 545 546 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 547 ch->r_io[i].res = ctlr->r_res2; 548 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7); 549 } 550 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 551 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7); 552 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 553 ata_default_registers(dev); 554 if ((ctlr->chip->cfg2 & (PR_SATA | PR_SATA2)) || 555 ((ctlr->chip->cfg2 & (PR_CMBO | PR_CMBO2)) && ch->unit < 2)) { 556 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 557 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8); 558 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 559 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8); 560 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 561 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8); 562 ch->flags |= ATA_NO_SLAVE; 563 ch->flags |= ATA_SATA; 564 } 565 ch->flags |= ATA_USE_16BIT; 566 ch->flags |= ATA_CHECKS_CABLE; 567 568 ata_generic_hw(dev); 569 if (ctlr->chip->cfg2 & PR_SX4X) { 570 ch->hw.command = ata_promise_sx4_command; 571 } 572 else { 573 ch->hw.command = ata_promise_mio_command; 574 ch->hw.status = ata_promise_mio_status; 575 ch->hw.softreset = ata_promise_mio_softreset; 576 ch->hw.pm_read = ata_promise_mio_pm_read; 577 ch->hw.pm_write = ata_promise_mio_pm_write; 578 } 579 return 0; 580 } 581 582 static int 583 ata_promise_mio_ch_detach(device_t dev) 584 { 585 586 ata_dmafini(dev); 587 return (0); 588 } 589 590 static void 591 ata_promise_mio_intr(void *data) 592 { 593 struct ata_pci_controller *ctlr = data; 594 struct ata_channel *ch; 595 u_int32_t vector; 596 int unit; 597 598 /* 599 * since reading interrupt status register on early "mio" chips 600 * clears the status bits we cannot read it for each channel later on 601 * in the generic interrupt routine. 602 */ 603 vector = ATA_INL(ctlr->r_res2, 0x040); 604 ATA_OUTL(ctlr->r_res2, 0x040, vector); 605 ctlr->chipset_data = (void *)(uintptr_t)vector; 606 607 for (unit = 0; unit < ctlr->channels; unit++) { 608 if ((ch = ctlr->interrupt[unit].argument)) 609 ctlr->interrupt[unit].function(ch); 610 } 611 612 ctlr->chipset_data = (void *)(uintptr_t)0xffffffff; 613 } 614 615 static int 616 ata_promise_mio_status(device_t dev) 617 { 618 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 619 struct ata_channel *ch = device_get_softc(dev); 620 u_int32_t stat_reg, vector, status; 621 622 switch (ctlr->chip->cfg2) { 623 case PR_PATA: 624 case PR_CMBO: 625 case PR_SATA: 626 stat_reg = 0x6c; 627 break; 628 case PR_CMBO2: 629 case PR_SATA2: 630 default: 631 stat_reg = 0x60; 632 break; 633 } 634 635 /* read and acknowledge interrupt */ 636 vector = (uint32_t)(uintptr_t)ctlr->chipset_data; 637 638 /* read and clear interface status */ 639 status = ATA_INL(ctlr->r_res2, stat_reg); 640 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit)); 641 642 /* check for and handle disconnect events */ 643 if (status & (0x00000001 << ch->unit)) { 644 if (bootverbose) 645 device_printf(dev, "DISCONNECT requested\n"); 646 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 647 } 648 649 /* check for and handle connect events */ 650 if (status & (0x00000010 << ch->unit)) { 651 if (bootverbose) 652 device_printf(dev, "CONNECT requested\n"); 653 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 654 } 655 656 /* do we have any device action ? */ 657 return (vector & (1 << (ch->unit + 1))); 658 } 659 660 static int 661 ata_promise_mio_command(struct ata_request *request) 662 { 663 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 664 struct ata_channel *ch = device_get_softc(request->parent); 665 666 u_int32_t *wordp = (u_int32_t *)ch->dma.work; 667 668 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001); 669 670 if ((ctlr->chip->cfg2 == PR_SATA2) || 671 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 672 /* set portmultiplier port */ 673 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), request->unit & 0x0f); 674 } 675 676 /* XXX SOS add ATAPI commands support later */ 677 switch (request->u.ata.command) { 678 default: 679 return ata_generic_command(request); 680 681 case ATA_READ_DMA: 682 case ATA_READ_DMA48: 683 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24)); 684 break; 685 686 case ATA_WRITE_DMA: 687 case ATA_WRITE_DMA48: 688 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24)); 689 break; 690 } 691 wordp[1] = htole32(request->dma->sg_bus); 692 wordp[2] = 0; 693 ata_promise_apkt((u_int8_t*)wordp, request); 694 695 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma.work_bus); 696 return 0; 697 } 698 699 static void 700 ata_promise_mio_reset(device_t dev) 701 { 702 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 703 struct ata_channel *ch = device_get_softc(dev); 704 struct ata_promise_sx4 *hpktp; 705 706 switch (ctlr->chip->cfg2) { 707 case PR_SX4X: 708 709 /* softreset channel ATA module */ 710 hpktp = ctlr->chipset_data; 711 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1); 712 ata_udelay(1000); 713 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), 714 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) & 715 ~0x00003f9f) | (ch->unit + 1)); 716 717 /* softreset HOST module */ /* XXX SOS what about other outstandings */ 718 mtx_lock(&hpktp->mtx); 719 ATA_OUTL(ctlr->r_res2, 0xc012c, 720 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11)); 721 DELAY(10); 722 ATA_OUTL(ctlr->r_res2, 0xc012c, 723 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f)); 724 hpktp->busy = 0; 725 mtx_unlock(&hpktp->mtx); 726 ata_generic_reset(dev); 727 break; 728 729 case PR_PATA: 730 case PR_CMBO: 731 case PR_SATA: 732 if ((ctlr->chip->cfg2 == PR_SATA) || 733 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2))) { 734 /* mask plug/unplug intr */ 735 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit)); 736 } 737 738 /* softreset channels ATA module */ 739 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 740 ata_udelay(10000); 741 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 742 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 743 ~0x00003f9f) | (ch->unit + 1)); 744 745 if ((ctlr->chip->cfg2 == PR_SATA) || 746 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2))) { 747 if (ata_sata_phy_reset(dev, -1, 1)) 748 ata_generic_reset(dev); 749 else 750 ch->devices = 0; 751 752 /* reset and enable plug/unplug intr */ 753 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit)); 754 } 755 else 756 ata_generic_reset(dev); 757 break; 758 759 case PR_CMBO2: 760 case PR_SATA2: 761 if ((ctlr->chip->cfg2 == PR_SATA2) || 762 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 763 /* set portmultiplier port */ 764 //ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 765 766 /* mask plug/unplug intr */ 767 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit)); 768 } 769 770 /* softreset channels ATA module */ 771 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 772 ata_udelay(10000); 773 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 774 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 775 ~0x00003f9f) | (ch->unit + 1)); 776 777 if ((ctlr->chip->cfg2 == PR_SATA2) || 778 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 779 /* set PHY mode to "improved" */ 780 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8), 781 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) & 782 ~0x00000003) | 0x00000001); 783 784 if (ata_sata_phy_reset(dev, -1, 1)) { 785 u_int32_t signature = ch->hw.softreset(dev, ATA_PM); 786 787 if (bootverbose) 788 device_printf(dev, "SIGNATURE: %08x\n", signature); 789 790 switch (signature >> 16) { 791 case 0x0000: 792 ch->devices = ATA_ATA_MASTER; 793 break; 794 case 0x9669: 795 ch->devices = ATA_PORTMULTIPLIER; 796 ata_pm_identify(dev); 797 break; 798 case 0xeb14: 799 ch->devices = ATA_ATAPI_MASTER; 800 break; 801 default: /* SOS XXX */ 802 if (bootverbose) 803 device_printf(dev, 804 "No signature, assuming disk device\n"); 805 ch->devices = ATA_ATA_MASTER; 806 } 807 if (bootverbose) 808 device_printf(dev, "promise_mio_reset devices=%08x\n", 809 ch->devices); 810 811 } else 812 ch->devices = 0; 813 814 /* reset and enable plug/unplug intr */ 815 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit)); 816 817 ///* set portmultiplier port */ 818 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00); 819 } 820 else 821 ata_generic_reset(dev); 822 break; 823 } 824 } 825 826 static int 827 ata_promise_mio_pm_read(device_t dev, int port, int reg, u_int32_t *result) 828 { 829 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 830 struct ata_channel *ch = device_get_softc(dev); 831 int timeout = 0; 832 833 if (port < 0) { 834 *result = ATA_IDX_INL(ch, reg); 835 return (0); 836 } 837 if (port < ATA_PM) { 838 switch (reg) { 839 case ATA_SSTATUS: 840 reg = 0; 841 break; 842 case ATA_SERROR: 843 reg = 1; 844 break; 845 case ATA_SCONTROL: 846 reg = 2; 847 break; 848 default: 849 return (EINVAL); 850 } 851 } 852 /* set portmultiplier port */ 853 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 854 855 ATA_IDX_OUTB(ch, ATA_FEATURE, reg); 856 ATA_IDX_OUTB(ch, ATA_DRIVE, port); 857 858 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_READ_PM); 859 860 while (timeout < 1000000) { 861 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS); 862 if (!(status & ATA_S_BUSY)) 863 break; 864 timeout += 1000; 865 DELAY(1000); 866 } 867 if (timeout >= 1000000) 868 return ATA_E_ABORT; 869 870 *result = ATA_IDX_INB(ch, ATA_COUNT) | 871 (ATA_IDX_INB(ch, ATA_SECTOR) << 8) | 872 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 16) | 873 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 24); 874 return 0; 875 } 876 877 static int 878 ata_promise_mio_pm_write(device_t dev, int port, int reg, u_int32_t value) 879 { 880 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 881 struct ata_channel *ch = device_get_softc(dev); 882 int timeout = 0; 883 884 if (port < 0) { 885 ATA_IDX_OUTL(ch, reg, value); 886 return (0); 887 } 888 if (port < ATA_PM) { 889 switch (reg) { 890 case ATA_SSTATUS: 891 reg = 0; 892 break; 893 case ATA_SERROR: 894 reg = 1; 895 break; 896 case ATA_SCONTROL: 897 reg = 2; 898 break; 899 default: 900 return (EINVAL); 901 } 902 } 903 /* set portmultiplier port */ 904 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 905 906 ATA_IDX_OUTB(ch, ATA_FEATURE, reg); 907 ATA_IDX_OUTB(ch, ATA_DRIVE, port); 908 ATA_IDX_OUTB(ch, ATA_COUNT, value & 0xff); 909 ATA_IDX_OUTB(ch, ATA_SECTOR, (value >> 8) & 0xff); 910 ATA_IDX_OUTB(ch, ATA_CYL_LSB, (value >> 16) & 0xff); 911 ATA_IDX_OUTB(ch, ATA_CYL_MSB, (value >> 24) & 0xff); 912 913 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_WRITE_PM); 914 915 while (timeout < 1000000) { 916 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS); 917 if (!(status & ATA_S_BUSY)) 918 break; 919 timeout += 1000; 920 DELAY(1000); 921 } 922 if (timeout >= 1000000) 923 return ATA_E_ABORT; 924 925 return ATA_IDX_INB(ch, ATA_ERROR); 926 } 927 928 /* must be called with ATA channel locked and state_mtx held */ 929 static u_int32_t 930 ata_promise_mio_softreset(device_t dev, int port) 931 { 932 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 933 struct ata_channel *ch = device_get_softc(dev); 934 int timeout; 935 936 /* set portmultiplier port */ 937 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), port & 0x0f); 938 939 /* softreset device on this channel */ 940 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 941 DELAY(10); 942 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET); 943 ata_udelay(10000); 944 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS); 945 ata_udelay(150000); 946 ATA_IDX_INB(ch, ATA_ERROR); 947 948 /* wait for BUSY to go inactive */ 949 for (timeout = 0; timeout < 100; timeout++) { 950 u_int8_t /* err, */ stat; 951 952 /* err = */ ATA_IDX_INB(ch, ATA_ERROR); 953 stat = ATA_IDX_INB(ch, ATA_STATUS); 954 955 //if (stat == err && timeout > (stat & ATA_S_BUSY ? 100 : 10)) 956 //break; 957 958 if (!(stat & ATA_S_BUSY)) { 959 //if ((err & 0x7f) == ATA_E_ILI) { 960 return ATA_IDX_INB(ch, ATA_COUNT) | 961 (ATA_IDX_INB(ch, ATA_SECTOR) << 8) | 962 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 16) | 963 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 24); 964 //} 965 //else if (stat & 0x0f) { 966 //stat |= ATA_S_BUSY; 967 //} 968 } 969 970 if (!(stat & ATA_S_BUSY) || (stat == 0xff && timeout > 10)) 971 break; 972 ata_udelay(100000); 973 } 974 return -1; 975 } 976 977 static void 978 ata_promise_mio_dmainit(device_t dev) 979 { 980 struct ata_channel *ch = device_get_softc(dev); 981 982 /* note start and stop are not used here */ 983 ch->dma.setprd = ata_promise_mio_setprd; 984 ch->dma.max_iosize = 65536; 985 ata_dmainit(dev); 986 } 987 988 #define MAXLASTSGSIZE (32 * sizeof(u_int32_t)) 989 static void 990 ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 991 { 992 struct ata_dmasetprd_args *args = xsc; 993 struct ata_dma_prdentry *prd = args->dmatab; 994 int i; 995 996 if ((args->error = error)) 997 return; 998 999 for (i = 0; i < nsegs; i++) { 1000 prd[i].addr = htole32(segs[i].ds_addr); 1001 prd[i].count = htole32(segs[i].ds_len); 1002 } 1003 if (segs[i - 1].ds_len > MAXLASTSGSIZE) { 1004 //printf("split last SG element of %u\n", segs[i - 1].ds_len); 1005 prd[i - 1].count = htole32(segs[i - 1].ds_len - MAXLASTSGSIZE); 1006 prd[i].count = htole32(MAXLASTSGSIZE); 1007 prd[i].addr = htole32(segs[i - 1].ds_addr + 1008 (segs[i - 1].ds_len - MAXLASTSGSIZE)); 1009 nsegs++; 1010 i++; 1011 } 1012 prd[i - 1].count |= htole32(ATA_DMA_EOT); 1013 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n")); 1014 args->nsegs = nsegs; 1015 } 1016 1017 static int 1018 ata_promise_mio_setmode(device_t dev, int target, int mode) 1019 { 1020 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1021 struct ata_channel *ch = device_get_softc(dev); 1022 1023 if ( (ctlr->chip->cfg2 == PR_SATA) || 1024 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2)) || 1025 (ctlr->chip->cfg2 == PR_SATA2) || 1026 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) 1027 mode = ata_sata_setmode(dev, target, mode); 1028 else 1029 mode = ata_promise_setmode(dev, target, mode); 1030 return (mode); 1031 } 1032 1033 static int 1034 ata_promise_mio_getrev(device_t dev, int target) 1035 { 1036 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1037 struct ata_channel *ch = device_get_softc(dev); 1038 1039 if ( (ctlr->chip->cfg2 == PR_SATA) || 1040 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2)) || 1041 (ctlr->chip->cfg2 == PR_SATA2) || 1042 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) 1043 return (ata_sata_getrev(dev, target)); 1044 else 1045 return (0); 1046 } 1047 1048 static void 1049 ata_promise_sx4_intr(void *data) 1050 { 1051 struct ata_pci_controller *ctlr = data; 1052 struct ata_channel *ch; 1053 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480); 1054 int unit; 1055 1056 for (unit = 0; unit < ctlr->channels; unit++) { 1057 if (vector & (1 << (unit + 1))) 1058 if ((ch = ctlr->interrupt[unit].argument)) 1059 ctlr->interrupt[unit].function(ch); 1060 if (vector & (1 << (unit + 5))) 1061 if ((ch = ctlr->interrupt[unit].argument)) 1062 ata_promise_queue_hpkt(ctlr, 1063 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 1064 ATA_PDC_HPKT_OFFSET)); 1065 if (vector & (1 << (unit + 9))) { 1066 ata_promise_next_hpkt(ctlr); 1067 if ((ch = ctlr->interrupt[unit].argument)) 1068 ctlr->interrupt[unit].function(ch); 1069 } 1070 if (vector & (1 << (unit + 13))) { 1071 ata_promise_next_hpkt(ctlr); 1072 if ((ch = ctlr->interrupt[unit].argument)) 1073 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1074 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 1075 ATA_PDC_APKT_OFFSET)); 1076 } 1077 } 1078 } 1079 1080 static int 1081 ata_promise_sx4_command(struct ata_request *request) 1082 { 1083 device_t gparent = device_get_parent(request->parent); 1084 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1085 struct ata_channel *ch = device_get_softc(request->parent); 1086 struct ata_dma_prdentry *prd; 1087 caddr_t window = rman_get_virtual(ctlr->r_res1); 1088 u_int32_t *wordp; 1089 int i, idx; 1090 1091 /* XXX SOS add ATAPI commands support later */ 1092 switch (request->u.ata.command) { 1093 1094 default: 1095 return -1; 1096 1097 case ATA_ATA_IDENTIFY: 1098 case ATA_READ: 1099 case ATA_READ48: 1100 case ATA_READ_MUL: 1101 case ATA_READ_MUL48: 1102 case ATA_WRITE: 1103 case ATA_WRITE48: 1104 case ATA_WRITE_MUL: 1105 case ATA_WRITE_MUL48: 1106 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 1107 return ata_generic_command(request); 1108 1109 case ATA_SETFEATURES: 1110 case ATA_FLUSHCACHE: 1111 case ATA_FLUSHCACHE48: 1112 case ATA_SLEEP: 1113 case ATA_SET_MULTI: 1114 wordp = (u_int32_t *) 1115 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 1116 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24)); 1117 wordp[1] = 0; 1118 wordp[2] = 0; 1119 ata_promise_apkt((u_int8_t *)wordp, request); 1120 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 1121 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 1122 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1123 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET)); 1124 return 0; 1125 1126 case ATA_READ_DMA: 1127 case ATA_READ_DMA48: 1128 case ATA_WRITE_DMA: 1129 case ATA_WRITE_DMA48: 1130 prd = request->dma->sg; 1131 wordp = (u_int32_t *) 1132 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET); 1133 i = idx = 0; 1134 do { 1135 wordp[idx++] = prd[i].addr; 1136 wordp[idx++] = prd[i].count; 1137 } while (!(prd[i++].count & ATA_DMA_EOT)); 1138 1139 wordp = (u_int32_t *) 1140 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET); 1141 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 1142 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 1143 1144 wordp = (u_int32_t *) 1145 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET); 1146 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 1147 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 1148 1149 wordp = (u_int32_t *) 1150 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET); 1151 if (request->flags & ATA_R_READ) 1152 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24)); 1153 if (request->flags & ATA_R_WRITE) 1154 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24)); 1155 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET); 1156 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET); 1157 wordp[3] = 0; 1158 1159 wordp = (u_int32_t *) 1160 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 1161 if (request->flags & ATA_R_READ) 1162 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24)); 1163 if (request->flags & ATA_R_WRITE) 1164 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24)); 1165 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET); 1166 wordp[2] = 0; 1167 ata_promise_apkt((u_int8_t *)wordp, request); 1168 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 1169 1170 if (request->flags & ATA_R_READ) { 1171 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001); 1172 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001); 1173 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1174 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET)); 1175 } 1176 if (request->flags & ATA_R_WRITE) { 1177 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001); 1178 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001); 1179 ata_promise_queue_hpkt(ctlr, 1180 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET)); 1181 } 1182 return 0; 1183 } 1184 } 1185 1186 static int 1187 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request) 1188 { 1189 int i = 12; 1190 1191 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE; 1192 bytep[i++] = ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit); 1193 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL; 1194 bytep[i++] = ATA_A_4BIT; 1195 1196 if (request->flags & ATA_R_48BIT) { 1197 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE; 1198 bytep[i++] = request->u.ata.feature >> 8; 1199 bytep[i++] = request->u.ata.feature; 1200 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT; 1201 bytep[i++] = request->u.ata.count >> 8; 1202 bytep[i++] = request->u.ata.count; 1203 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR; 1204 bytep[i++] = request->u.ata.lba >> 24; 1205 bytep[i++] = request->u.ata.lba; 1206 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 1207 bytep[i++] = request->u.ata.lba >> 32; 1208 bytep[i++] = request->u.ata.lba >> 8; 1209 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 1210 bytep[i++] = request->u.ata.lba >> 40; 1211 bytep[i++] = request->u.ata.lba >> 16; 1212 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 1213 bytep[i++] = ATA_D_LBA | ATA_DEV(request->unit); 1214 } 1215 else { 1216 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE; 1217 bytep[i++] = request->u.ata.feature; 1218 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT; 1219 bytep[i++] = request->u.ata.count; 1220 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR; 1221 bytep[i++] = request->u.ata.lba; 1222 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 1223 bytep[i++] = request->u.ata.lba >> 8; 1224 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 1225 bytep[i++] = request->u.ata.lba >> 16; 1226 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 1227 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ATA_DEV(request->unit) | 1228 ((request->u.ata.lba >> 24)&0xf); 1229 } 1230 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND; 1231 bytep[i++] = request->u.ata.command; 1232 return i; 1233 } 1234 1235 static void 1236 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt) 1237 { 1238 struct ata_promise_sx4 *hpktp = ctlr->chipset_data; 1239 1240 mtx_lock(&hpktp->mtx); 1241 if (hpktp->busy) { 1242 struct host_packet *hp = 1243 malloc(sizeof(struct host_packet), M_TEMP, M_NOWAIT | M_ZERO); 1244 hp->addr = hpkt; 1245 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain); 1246 } 1247 else { 1248 hpktp->busy = 1; 1249 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt); 1250 } 1251 mtx_unlock(&hpktp->mtx); 1252 } 1253 1254 static void 1255 ata_promise_next_hpkt(struct ata_pci_controller *ctlr) 1256 { 1257 struct ata_promise_sx4 *hpktp = ctlr->chipset_data; 1258 struct host_packet *hp; 1259 1260 mtx_lock(&hpktp->mtx); 1261 if ((hp = TAILQ_FIRST(&hpktp->queue))) { 1262 TAILQ_REMOVE(&hpktp->queue, hp, chain); 1263 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr); 1264 free(hp, M_TEMP); 1265 } 1266 else 1267 hpktp->busy = 0; 1268 mtx_unlock(&hpktp->mtx); 1269 } 1270 1271 ATA_DECLARE_DRIVER(ata_promise); 1272