1 /*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/ata.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/malloc.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/sema.h> 41 #include <sys/taskqueue.h> 42 #include <vm/uma.h> 43 #include <machine/stdarg.h> 44 #include <machine/resource.h> 45 #include <machine/bus.h> 46 #include <sys/rman.h> 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/ata/ata-all.h> 50 #include <dev/ata/ata-pci.h> 51 #include <ata_if.h> 52 53 /* local prototypes */ 54 static int ata_promise_chipinit(device_t dev); 55 static int ata_promise_ch_attach(device_t dev); 56 static int ata_promise_status(device_t dev); 57 static int ata_promise_dmastart(struct ata_request *request); 58 static int ata_promise_dmastop(struct ata_request *request); 59 static void ata_promise_dmareset(device_t dev); 60 static int ata_promise_setmode(device_t dev, int target, int mode); 61 static int ata_promise_tx2_ch_attach(device_t dev); 62 static int ata_promise_tx2_status(device_t dev); 63 static int ata_promise_mio_ch_attach(device_t dev); 64 static int ata_promise_mio_ch_detach(device_t dev); 65 static void ata_promise_mio_intr(void *data); 66 static int ata_promise_mio_status(device_t dev); 67 static int ata_promise_mio_command(struct ata_request *request); 68 static void ata_promise_mio_reset(device_t dev); 69 static int ata_promise_mio_pm_read(device_t dev, int port, int reg, u_int32_t *result); 70 static int ata_promise_mio_pm_write(device_t dev, int port, int reg, u_int32_t result); 71 static u_int32_t ata_promise_mio_softreset(device_t dev, int port); 72 static void ata_promise_mio_dmainit(device_t dev); 73 static void ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 74 static int ata_promise_mio_setmode(device_t dev, int target, int mode); 75 static int ata_promise_mio_getrev(device_t dev, int target); 76 static void ata_promise_sx4_intr(void *data); 77 static int ata_promise_sx4_command(struct ata_request *request); 78 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request); 79 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt); 80 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr); 81 82 /* misc defines */ 83 #define PR_OLD 0 84 #define PR_NEW 1 85 #define PR_TX 2 86 #define PR_MIO 3 87 #define PR_TX4 0x01 88 #define PR_SX4X 0x02 89 #define PR_SX6K 0x04 90 #define PR_PATA 0x08 91 #define PR_CMBO 0x10 92 #define PR_CMBO2 0x20 93 #define PR_SATA 0x40 94 #define PR_SATA2 0x80 95 96 /* 97 * Promise chipset support functions 98 */ 99 #define ATA_PDC_APKT_OFFSET 0x00000010 100 #define ATA_PDC_HPKT_OFFSET 0x00000040 101 #define ATA_PDC_ASG_OFFSET 0x00000080 102 #define ATA_PDC_LSG_OFFSET 0x000000c0 103 #define ATA_PDC_HSG_OFFSET 0x00000100 104 #define ATA_PDC_CHN_OFFSET 0x00000400 105 #define ATA_PDC_BUF_BASE 0x00400000 106 #define ATA_PDC_BUF_OFFSET 0x00100000 107 #define ATA_PDC_MAX_HPKT 8 108 #define ATA_PDC_WRITE_REG 0x00 109 #define ATA_PDC_WRITE_CTL 0x0e 110 #define ATA_PDC_WRITE_END 0x08 111 #define ATA_PDC_WAIT_NBUSY 0x10 112 #define ATA_PDC_WAIT_READY 0x18 113 #define ATA_PDC_1B 0x20 114 #define ATA_PDC_2B 0x40 115 116 struct host_packet { 117 u_int32_t addr; 118 TAILQ_ENTRY(host_packet) chain; 119 }; 120 121 struct ata_promise_sx4 { 122 struct mtx mtx; 123 TAILQ_HEAD(, host_packet) queue; 124 int busy; 125 }; 126 127 static int 128 ata_promise_probe(device_t dev) 129 { 130 struct ata_pci_controller *ctlr = device_get_softc(dev); 131 const struct ata_chip_id *idx; 132 static const struct ata_chip_id ids[] = 133 {{ ATA_PDC20246, 0, PR_OLD, 0x00, ATA_UDMA2, "PDC20246" }, 134 { ATA_PDC20262, 0, PR_NEW, 0x00, ATA_UDMA4, "PDC20262" }, 135 { ATA_PDC20263, 0, PR_NEW, 0x00, ATA_UDMA4, "PDC20263" }, 136 { ATA_PDC20265, 0, PR_NEW, 0x00, ATA_UDMA5, "PDC20265" }, 137 { ATA_PDC20267, 0, PR_NEW, 0x00, ATA_UDMA5, "PDC20267" }, 138 { ATA_PDC20268, 0, PR_TX, PR_TX4, ATA_UDMA5, "PDC20268" }, 139 { ATA_PDC20269, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20269" }, 140 { ATA_PDC20270, 0, PR_TX, PR_TX4, ATA_UDMA5, "PDC20270" }, 141 { ATA_PDC20271, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20271" }, 142 { ATA_PDC20275, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20275" }, 143 { ATA_PDC20276, 0, PR_TX, PR_SX6K, ATA_UDMA6, "PDC20276" }, 144 { ATA_PDC20277, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20277" }, 145 { ATA_PDC20318, 0, PR_MIO, PR_SATA, ATA_SA150, "PDC20318" }, 146 { ATA_PDC20319, 0, PR_MIO, PR_SATA, ATA_SA150, "PDC20319" }, 147 { ATA_PDC20371, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20371" }, 148 { ATA_PDC20375, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20375" }, 149 { ATA_PDC20376, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20376" }, 150 { ATA_PDC20377, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20377" }, 151 { ATA_PDC20378, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20378" }, 152 { ATA_PDC20379, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20379" }, 153 { ATA_PDC20571, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20571" }, 154 { ATA_PDC20575, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20575" }, 155 { ATA_PDC20579, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20579" }, 156 { ATA_PDC20771, 0, PR_MIO, PR_CMBO2, ATA_SA300, "PDC20771" }, 157 { ATA_PDC40775, 0, PR_MIO, PR_CMBO2, ATA_SA300, "PDC40775" }, 158 { ATA_PDC20617, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20617" }, 159 { ATA_PDC20618, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20618" }, 160 { ATA_PDC20619, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20619" }, 161 { ATA_PDC20620, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20620" }, 162 { ATA_PDC20621, 0, PR_MIO, PR_SX4X, ATA_UDMA5, "PDC20621" }, 163 { ATA_PDC20622, 0, PR_MIO, PR_SX4X, ATA_SA150, "PDC20622" }, 164 { ATA_PDC40518, 0, PR_MIO, PR_SATA2, ATA_SA150, "PDC40518" }, 165 { ATA_PDC40519, 0, PR_MIO, PR_SATA2, ATA_SA150, "PDC40519" }, 166 { ATA_PDC40718, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40718" }, 167 { ATA_PDC40719, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40719" }, 168 { ATA_PDC40779, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40779" }, 169 { 0, 0, 0, 0, 0, 0}}; 170 char buffer[64]; 171 uintptr_t devid = 0; 172 173 if (pci_get_vendor(dev) != ATA_PROMISE_ID) 174 return ENXIO; 175 176 if (!(idx = ata_match_chip(dev, ids))) 177 return ENXIO; 178 179 /* if we are on a SuperTrak SX6000 dont attach */ 180 if ((idx->cfg2 & PR_SX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 181 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 182 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 183 devid == ATA_I960RM) 184 return ENXIO; 185 186 strcpy(buffer, "Promise "); 187 strcat(buffer, idx->text); 188 189 /* if we are on a FastTrak TX4, adjust the interrupt resource */ 190 if ((idx->cfg2 & PR_TX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 191 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 192 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 193 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) { 194 static long start = 0, end = 0; 195 196 if (pci_get_slot(dev) == 1) { 197 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end); 198 strcat(buffer, " (channel 0+1)"); 199 } 200 else if (pci_get_slot(dev) == 2 && start && end) { 201 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end); 202 strcat(buffer, " (channel 2+3)"); 203 } 204 else { 205 start = end = 0; 206 } 207 } 208 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 209 device_set_desc_copy(dev, buffer); 210 ctlr->chip = idx; 211 ctlr->chipinit = ata_promise_chipinit; 212 return (BUS_PROBE_DEFAULT); 213 } 214 215 static int 216 ata_promise_chipinit(device_t dev) 217 { 218 struct ata_pci_controller *ctlr = device_get_softc(dev); 219 int stat_reg; 220 221 if (ata_setup_interrupt(dev, ata_generic_intr)) 222 return ENXIO; 223 224 switch (ctlr->chip->cfg1) { 225 case PR_NEW: 226 /* setup clocks */ 227 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a); 228 /* FALLTHROUGH */ 229 230 case PR_OLD: 231 /* enable burst mode */ 232 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01); 233 ctlr->ch_attach = ata_promise_ch_attach; 234 ctlr->ch_detach = ata_pci_ch_detach; 235 ctlr->setmode = ata_promise_setmode; 236 return 0; 237 238 case PR_TX: 239 ctlr->ch_attach = ata_promise_tx2_ch_attach; 240 ctlr->ch_detach = ata_pci_ch_detach; 241 ctlr->setmode = ata_promise_setmode; 242 return 0; 243 244 case PR_MIO: 245 ctlr->r_type1 = SYS_RES_MEMORY; 246 ctlr->r_rid1 = PCIR_BAR(4); 247 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 248 &ctlr->r_rid1, RF_ACTIVE))) 249 goto failnfree; 250 251 #ifdef __sparc64__ 252 if (ctlr->chip->cfg2 == PR_SX4X && 253 !bus_space_map(rman_get_bustag(ctlr->r_res1), 254 rman_get_bushandle(ctlr->r_res1), rman_get_size(ctlr->r_res1), 255 BUS_SPACE_MAP_LINEAR, NULL)) 256 goto failnfree; 257 #endif 258 259 ctlr->r_type2 = SYS_RES_MEMORY; 260 ctlr->r_rid2 = PCIR_BAR(3); 261 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 262 &ctlr->r_rid2, RF_ACTIVE))) 263 goto failnfree; 264 265 if (ctlr->chip->cfg2 == PR_SX4X) { 266 struct ata_promise_sx4 *hpkt; 267 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080); 268 269 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 270 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL, 271 ata_promise_sx4_intr, ctlr, &ctlr->handle)) { 272 device_printf(dev, "unable to setup interrupt\n"); 273 goto failnfree; 274 } 275 276 /* print info about cache memory */ 277 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n", 278 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4, 279 ((dimm >> 24) & 0xff), 280 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ? 281 " ECC enabled" : "" ); 282 283 /* adjust cache memory parameters */ 284 ATA_OUTL(ctlr->r_res2, 0x000c000c, 285 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000)); 286 287 /* setup host packet controls */ 288 hpkt = malloc(sizeof(struct ata_promise_sx4), 289 M_ATAPCI, M_NOWAIT | M_ZERO); 290 mtx_init(&hpkt->mtx, "ATA promise HPKT lock", NULL, MTX_DEF); 291 TAILQ_INIT(&hpkt->queue); 292 hpkt->busy = 0; 293 ctlr->chipset_data = hpkt; 294 ctlr->ch_attach = ata_promise_mio_ch_attach; 295 ctlr->ch_detach = ata_promise_mio_ch_detach; 296 ctlr->reset = ata_promise_mio_reset; 297 ctlr->setmode = ata_promise_setmode; 298 ctlr->channels = 4; 299 return 0; 300 } 301 302 /* mio type controllers need an interrupt intercept */ 303 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 304 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL, 305 ata_promise_mio_intr, ctlr, &ctlr->handle)) { 306 device_printf(dev, "unable to setup interrupt\n"); 307 goto failnfree; 308 } 309 310 switch (ctlr->chip->cfg2) { 311 case PR_PATA: 312 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) + 313 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2; 314 goto sata150; 315 case PR_CMBO: 316 ctlr->channels = 3; 317 goto sata150; 318 case PR_SATA: 319 ctlr->channels = 4; 320 sata150: 321 stat_reg = 0x6c; 322 break; 323 324 case PR_CMBO2: 325 ctlr->channels = 3; 326 goto sataii; 327 case PR_SATA2: 328 default: 329 ctlr->channels = 4; 330 sataii: 331 stat_reg = 0x60; 332 break; 333 } 334 335 /* prime fake interrupt register */ 336 ctlr->chipset_data = (void *)(uintptr_t)0xffffffff; 337 338 /* clear SATA status and unmask interrupts */ 339 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff); 340 341 /* enable "long burst length" on gen2 chips */ 342 if ((ctlr->chip->cfg2 == PR_SATA2) || (ctlr->chip->cfg2 == PR_CMBO2)) 343 ATA_OUTL(ctlr->r_res2, 0x44, ATA_INL(ctlr->r_res2, 0x44) | 0x2000); 344 345 ctlr->ch_attach = ata_promise_mio_ch_attach; 346 ctlr->ch_detach = ata_promise_mio_ch_detach; 347 ctlr->reset = ata_promise_mio_reset; 348 ctlr->setmode = ata_promise_mio_setmode; 349 ctlr->getrev = ata_promise_mio_getrev; 350 351 return 0; 352 } 353 354 failnfree: 355 if (ctlr->r_res2) 356 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 357 if (ctlr->r_res1) 358 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1); 359 return ENXIO; 360 } 361 362 static int 363 ata_promise_ch_attach(device_t dev) 364 { 365 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 366 struct ata_channel *ch = device_get_softc(dev); 367 368 if (ata_pci_ch_attach(dev)) 369 return ENXIO; 370 371 if (ctlr->chip->cfg1 == PR_NEW) { 372 ch->dma.start = ata_promise_dmastart; 373 ch->dma.stop = ata_promise_dmastop; 374 ch->dma.reset = ata_promise_dmareset; 375 } 376 377 ch->hw.status = ata_promise_status; 378 ch->flags |= ATA_NO_ATAPI_DMA; 379 ch->flags |= ATA_CHECKS_CABLE; 380 return 0; 381 } 382 383 static int 384 ata_promise_status(device_t dev) 385 { 386 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 387 struct ata_channel *ch = device_get_softc(dev); 388 389 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) { 390 return ata_pci_status(dev); 391 } 392 return 0; 393 } 394 395 static int 396 ata_promise_dmastart(struct ata_request *request) 397 { 398 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 399 struct ata_channel *ch = device_get_softc(request->parent); 400 401 if (request->flags & ATA_R_48BIT) { 402 ATA_OUTB(ctlr->r_res1, 0x11, 403 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02)); 404 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 405 ((request->flags & ATA_R_READ) ? 0x05000000 : 0x06000000) | 406 (request->bytecount >> 1)); 407 } 408 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) | 409 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 410 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, request->dma->sg_bus); 411 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 412 ((request->flags & ATA_R_READ) ? ATA_BMCMD_WRITE_READ : 0) | 413 ATA_BMCMD_START_STOP); 414 ch->dma.flags |= ATA_DMA_ACTIVE; 415 return 0; 416 } 417 418 static int 419 ata_promise_dmastop(struct ata_request *request) 420 { 421 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 422 struct ata_channel *ch = device_get_softc(request->parent); 423 int error; 424 425 if (request->flags & ATA_R_48BIT) { 426 ATA_OUTB(ctlr->r_res1, 0x11, 427 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02)); 428 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0); 429 } 430 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT); 431 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 432 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 433 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 434 ch->dma.flags &= ~ATA_DMA_ACTIVE; 435 return error; 436 } 437 438 static void 439 ata_promise_dmareset(device_t dev) 440 { 441 struct ata_channel *ch = device_get_softc(dev); 442 443 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 444 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 445 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 446 ch->flags &= ~ATA_DMA_ACTIVE; 447 } 448 449 static int 450 ata_promise_setmode(device_t dev, int target, int mode) 451 { 452 device_t parent = device_get_parent(dev); 453 struct ata_pci_controller *ctlr = device_get_softc(parent); 454 struct ata_channel *ch = device_get_softc(dev); 455 int devno = (ch->unit << 1) + target; 456 static const uint32_t timings[][2] = { 457 /* PR_OLD PR_NEW mode */ 458 { 0x004ff329, 0x004fff2f }, /* PIO 0 */ 459 { 0x004fec25, 0x004ff82a }, /* PIO 1 */ 460 { 0x004fe823, 0x004ff026 }, /* PIO 2 */ 461 { 0x004fe622, 0x004fec24 }, /* PIO 3 */ 462 { 0x004fe421, 0x004fe822 }, /* PIO 4 */ 463 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */ 464 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */ 465 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */ 466 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */ 467 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */ 468 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */ 469 { 0, 0x00424ef6 }, /* UDMA 3 */ 470 { 0, 0x004127f3 }, /* UDMA 4 */ 471 { 0, 0x004127f3 } /* UDMA 5 */ 472 }; 473 474 mode = min(mode, ctlr->chip->max_dma); 475 476 switch (ctlr->chip->cfg1) { 477 case PR_OLD: 478 case PR_NEW: 479 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 480 (pci_read_config(parent, 0x50, 2) & 481 (ch->unit ? 1 << 11 : 1 << 10))) { 482 ata_print_cable(dev, "controller"); 483 mode = ATA_UDMA2; 484 } 485 break; 486 487 case PR_TX: 488 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 489 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 490 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) { 491 ata_print_cable(dev, "controller"); 492 mode = ATA_UDMA2; 493 } 494 break; 495 496 case PR_MIO: 497 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 498 (ATA_INL(ctlr->r_res2, 499 (ctlr->chip->cfg2 & PR_SX4X ? 0x000c0260 : 0x0260) + 500 (ch->unit << 7)) & 0x01000000)) { 501 ata_print_cable(dev, "controller"); 502 mode = ATA_UDMA2; 503 } 504 break; 505 } 506 507 if (ctlr->chip->cfg1 < PR_TX) 508 pci_write_config(parent, 0x60 + (devno << 2), 509 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 510 return (mode); 511 } 512 513 static int 514 ata_promise_tx2_ch_attach(device_t dev) 515 { 516 struct ata_channel *ch = device_get_softc(dev); 517 518 if (ata_pci_ch_attach(dev)) 519 return ENXIO; 520 521 ch->hw.status = ata_promise_tx2_status; 522 ch->flags |= ATA_CHECKS_CABLE; 523 return 0; 524 } 525 526 static int 527 ata_promise_tx2_status(device_t dev) 528 { 529 struct ata_channel *ch = device_get_softc(dev); 530 531 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 532 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) { 533 return ata_pci_status(dev); 534 } 535 return 0; 536 } 537 538 static int 539 ata_promise_mio_ch_attach(device_t dev) 540 { 541 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 542 struct ata_channel *ch = device_get_softc(dev); 543 int offset = (ctlr->chip->cfg2 & PR_SX4X) ? 0x000c0000 : 0; 544 int i; 545 546 ata_promise_mio_dmainit(dev); 547 548 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 549 ch->r_io[i].res = ctlr->r_res2; 550 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7); 551 } 552 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 553 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7); 554 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 555 ata_default_registers(dev); 556 if ((ctlr->chip->cfg2 & (PR_SATA | PR_SATA2)) || 557 ((ctlr->chip->cfg2 & (PR_CMBO | PR_CMBO2)) && ch->unit < 2)) { 558 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 559 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8); 560 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 561 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8); 562 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 563 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8); 564 ch->flags |= ATA_NO_SLAVE; 565 ch->flags |= ATA_SATA; 566 } 567 ch->flags |= ATA_USE_16BIT; 568 ch->flags |= ATA_CHECKS_CABLE; 569 570 ata_generic_hw(dev); 571 if (ctlr->chip->cfg2 & PR_SX4X) { 572 ch->hw.command = ata_promise_sx4_command; 573 } 574 else { 575 ch->hw.command = ata_promise_mio_command; 576 ch->hw.status = ata_promise_mio_status; 577 ch->hw.softreset = ata_promise_mio_softreset; 578 ch->hw.pm_read = ata_promise_mio_pm_read; 579 ch->hw.pm_write = ata_promise_mio_pm_write; 580 } 581 return 0; 582 } 583 584 static int 585 ata_promise_mio_ch_detach(device_t dev) 586 { 587 588 ata_dmafini(dev); 589 return (0); 590 } 591 592 static void 593 ata_promise_mio_intr(void *data) 594 { 595 struct ata_pci_controller *ctlr = data; 596 struct ata_channel *ch; 597 u_int32_t vector; 598 int unit; 599 600 /* 601 * since reading interrupt status register on early "mio" chips 602 * clears the status bits we cannot read it for each channel later on 603 * in the generic interrupt routine. 604 */ 605 vector = ATA_INL(ctlr->r_res2, 0x040); 606 ATA_OUTL(ctlr->r_res2, 0x040, vector); 607 ctlr->chipset_data = (void *)(uintptr_t)vector; 608 609 for (unit = 0; unit < ctlr->channels; unit++) { 610 if ((ch = ctlr->interrupt[unit].argument)) 611 ctlr->interrupt[unit].function(ch); 612 } 613 614 ctlr->chipset_data = (void *)(uintptr_t)0xffffffff; 615 } 616 617 static int 618 ata_promise_mio_status(device_t dev) 619 { 620 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 621 struct ata_channel *ch = device_get_softc(dev); 622 u_int32_t stat_reg, vector, status; 623 624 switch (ctlr->chip->cfg2) { 625 case PR_PATA: 626 case PR_CMBO: 627 case PR_SATA: 628 stat_reg = 0x6c; 629 break; 630 case PR_CMBO2: 631 case PR_SATA2: 632 default: 633 stat_reg = 0x60; 634 break; 635 } 636 637 /* read and acknowledge interrupt */ 638 vector = (uint32_t)(uintptr_t)ctlr->chipset_data; 639 640 /* read and clear interface status */ 641 status = ATA_INL(ctlr->r_res2, stat_reg); 642 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit)); 643 644 /* check for and handle disconnect events */ 645 if (status & (0x00000001 << ch->unit)) { 646 if (bootverbose) 647 device_printf(dev, "DISCONNECT requested\n"); 648 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 649 } 650 651 /* check for and handle connect events */ 652 if (status & (0x00000010 << ch->unit)) { 653 if (bootverbose) 654 device_printf(dev, "CONNECT requested\n"); 655 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 656 } 657 658 /* do we have any device action ? */ 659 return (vector & (1 << (ch->unit + 1))); 660 } 661 662 static int 663 ata_promise_mio_command(struct ata_request *request) 664 { 665 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 666 struct ata_channel *ch = device_get_softc(request->parent); 667 668 u_int32_t *wordp = (u_int32_t *)ch->dma.work; 669 670 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001); 671 672 if ((ctlr->chip->cfg2 == PR_SATA2) || 673 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 674 /* set portmultiplier port */ 675 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), request->unit & 0x0f); 676 } 677 678 /* XXX SOS add ATAPI commands support later */ 679 switch (request->u.ata.command) { 680 default: 681 return ata_generic_command(request); 682 683 case ATA_READ_DMA: 684 case ATA_READ_DMA48: 685 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24)); 686 break; 687 688 case ATA_WRITE_DMA: 689 case ATA_WRITE_DMA48: 690 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24)); 691 break; 692 } 693 wordp[1] = htole32(request->dma->sg_bus); 694 wordp[2] = 0; 695 ata_promise_apkt((u_int8_t*)wordp, request); 696 697 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma.work_bus); 698 return 0; 699 } 700 701 static void 702 ata_promise_mio_reset(device_t dev) 703 { 704 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 705 struct ata_channel *ch = device_get_softc(dev); 706 struct ata_promise_sx4 *hpktp; 707 708 switch (ctlr->chip->cfg2) { 709 case PR_SX4X: 710 711 /* softreset channel ATA module */ 712 hpktp = ctlr->chipset_data; 713 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1); 714 ata_udelay(1000); 715 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), 716 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) & 717 ~0x00003f9f) | (ch->unit + 1)); 718 719 /* softreset HOST module */ /* XXX SOS what about other outstandings */ 720 mtx_lock(&hpktp->mtx); 721 ATA_OUTL(ctlr->r_res2, 0xc012c, 722 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11)); 723 DELAY(10); 724 ATA_OUTL(ctlr->r_res2, 0xc012c, 725 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f)); 726 hpktp->busy = 0; 727 mtx_unlock(&hpktp->mtx); 728 ata_generic_reset(dev); 729 break; 730 731 case PR_PATA: 732 case PR_CMBO: 733 case PR_SATA: 734 if ((ctlr->chip->cfg2 == PR_SATA) || 735 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2))) { 736 737 /* mask plug/unplug intr */ 738 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit)); 739 } 740 741 /* softreset channels ATA module */ 742 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 743 ata_udelay(10000); 744 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 745 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 746 ~0x00003f9f) | (ch->unit + 1)); 747 748 if ((ctlr->chip->cfg2 == PR_SATA) || 749 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2))) { 750 751 if (ata_sata_phy_reset(dev, -1, 1)) 752 ata_generic_reset(dev); 753 else 754 ch->devices = 0; 755 756 /* reset and enable plug/unplug intr */ 757 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit)); 758 } 759 else 760 ata_generic_reset(dev); 761 break; 762 763 case PR_CMBO2: 764 case PR_SATA2: 765 if ((ctlr->chip->cfg2 == PR_SATA2) || 766 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 767 /* set portmultiplier port */ 768 //ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 769 770 /* mask plug/unplug intr */ 771 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit)); 772 } 773 774 /* softreset channels ATA module */ 775 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 776 ata_udelay(10000); 777 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 778 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 779 ~0x00003f9f) | (ch->unit + 1)); 780 781 if ((ctlr->chip->cfg2 == PR_SATA2) || 782 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 783 784 /* set PHY mode to "improved" */ 785 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8), 786 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) & 787 ~0x00000003) | 0x00000001); 788 789 if (ata_sata_phy_reset(dev, -1, 1)) { 790 u_int32_t signature = ch->hw.softreset(dev, ATA_PM); 791 792 if (1 | bootverbose) 793 device_printf(dev, "SIGNATURE: %08x\n", signature); 794 795 switch (signature >> 16) { 796 case 0x0000: 797 ch->devices = ATA_ATA_MASTER; 798 break; 799 case 0x9669: 800 ch->devices = ATA_PORTMULTIPLIER; 801 ata_pm_identify(dev); 802 break; 803 case 0xeb14: 804 ch->devices = ATA_ATAPI_MASTER; 805 break; 806 default: /* SOS XXX */ 807 if (bootverbose) 808 device_printf(dev, 809 "No signature, assuming disk device\n"); 810 ch->devices = ATA_ATA_MASTER; 811 } 812 if (bootverbose) 813 device_printf(dev, "promise_mio_reset devices=%08x\n", 814 ch->devices); 815 816 } else 817 ch->devices = 0; 818 819 /* reset and enable plug/unplug intr */ 820 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit)); 821 822 ///* set portmultiplier port */ 823 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00); 824 } 825 else 826 ata_generic_reset(dev); 827 break; 828 829 } 830 } 831 832 static int 833 ata_promise_mio_pm_read(device_t dev, int port, int reg, u_int32_t *result) 834 { 835 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 836 struct ata_channel *ch = device_get_softc(dev); 837 int timeout = 0; 838 839 if (port < 0) { 840 *result = ATA_IDX_INL(ch, reg); 841 return (0); 842 } 843 if (port < ATA_PM) { 844 switch (reg) { 845 case ATA_SSTATUS: 846 reg = 0; 847 break; 848 case ATA_SERROR: 849 reg = 1; 850 break; 851 case ATA_SCONTROL: 852 reg = 2; 853 break; 854 default: 855 return (EINVAL); 856 } 857 } 858 /* set portmultiplier port */ 859 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 860 861 ATA_IDX_OUTB(ch, ATA_FEATURE, reg); 862 ATA_IDX_OUTB(ch, ATA_DRIVE, port); 863 864 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_READ_PM); 865 866 while (timeout < 1000000) { 867 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS); 868 if (!(status & ATA_S_BUSY)) 869 break; 870 timeout += 1000; 871 DELAY(1000); 872 } 873 if (timeout >= 1000000) 874 return ATA_E_ABORT; 875 876 *result = ATA_IDX_INB(ch, ATA_COUNT) | 877 (ATA_IDX_INB(ch, ATA_SECTOR) << 8) | 878 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 16) | 879 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 24); 880 return 0; 881 } 882 883 static int 884 ata_promise_mio_pm_write(device_t dev, int port, int reg, u_int32_t value) 885 { 886 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 887 struct ata_channel *ch = device_get_softc(dev); 888 int timeout = 0; 889 890 if (port < 0) { 891 ATA_IDX_OUTL(ch, reg, value); 892 return (0); 893 } 894 if (port < ATA_PM) { 895 switch (reg) { 896 case ATA_SSTATUS: 897 reg = 0; 898 break; 899 case ATA_SERROR: 900 reg = 1; 901 break; 902 case ATA_SCONTROL: 903 reg = 2; 904 break; 905 default: 906 return (EINVAL); 907 } 908 } 909 /* set portmultiplier port */ 910 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 911 912 ATA_IDX_OUTB(ch, ATA_FEATURE, reg); 913 ATA_IDX_OUTB(ch, ATA_DRIVE, port); 914 ATA_IDX_OUTB(ch, ATA_COUNT, value & 0xff); 915 ATA_IDX_OUTB(ch, ATA_SECTOR, (value >> 8) & 0xff); 916 ATA_IDX_OUTB(ch, ATA_CYL_LSB, (value >> 16) & 0xff); 917 ATA_IDX_OUTB(ch, ATA_CYL_MSB, (value >> 24) & 0xff); 918 919 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_WRITE_PM); 920 921 while (timeout < 1000000) { 922 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS); 923 if (!(status & ATA_S_BUSY)) 924 break; 925 timeout += 1000; 926 DELAY(1000); 927 } 928 if (timeout >= 1000000) 929 return ATA_E_ABORT; 930 931 return ATA_IDX_INB(ch, ATA_ERROR); 932 } 933 934 /* must be called with ATA channel locked and state_mtx held */ 935 static u_int32_t 936 ata_promise_mio_softreset(device_t dev, int port) 937 { 938 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 939 struct ata_channel *ch = device_get_softc(dev); 940 int timeout; 941 942 /* set portmultiplier port */ 943 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), port & 0x0f); 944 945 /* softreset device on this channel */ 946 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 947 DELAY(10); 948 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET); 949 ata_udelay(10000); 950 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS); 951 ata_udelay(150000); 952 ATA_IDX_INB(ch, ATA_ERROR); 953 954 /* wait for BUSY to go inactive */ 955 for (timeout = 0; timeout < 100; timeout++) { 956 u_int8_t err, stat; 957 958 err = ATA_IDX_INB(ch, ATA_ERROR); 959 stat = ATA_IDX_INB(ch, ATA_STATUS); 960 961 //if (stat == err && timeout > (stat & ATA_S_BUSY ? 100 : 10)) 962 //break; 963 964 if (!(stat & ATA_S_BUSY)) { 965 //if ((err & 0x7f) == ATA_E_ILI) { 966 return ATA_IDX_INB(ch, ATA_COUNT) | 967 (ATA_IDX_INB(ch, ATA_SECTOR) << 8) | 968 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 16) | 969 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 24); 970 //} 971 //else if (stat & 0x0f) { 972 //stat |= ATA_S_BUSY; 973 //} 974 } 975 976 if (!(stat & ATA_S_BUSY) || (stat == 0xff && timeout > 10)) 977 break; 978 ata_udelay(100000); 979 } 980 return -1; 981 } 982 983 static void 984 ata_promise_mio_dmainit(device_t dev) 985 { 986 struct ata_channel *ch = device_get_softc(dev); 987 988 /* note start and stop are not used here */ 989 ch->dma.setprd = ata_promise_mio_setprd; 990 ch->dma.max_iosize = 65536; 991 ata_dmainit(dev); 992 } 993 994 #define MAXLASTSGSIZE (32 * sizeof(u_int32_t)) 995 static void 996 ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 997 { 998 struct ata_dmasetprd_args *args = xsc; 999 struct ata_dma_prdentry *prd = args->dmatab; 1000 int i; 1001 1002 if ((args->error = error)) 1003 return; 1004 1005 for (i = 0; i < nsegs; i++) { 1006 prd[i].addr = htole32(segs[i].ds_addr); 1007 prd[i].count = htole32(segs[i].ds_len); 1008 } 1009 if (segs[i - 1].ds_len > MAXLASTSGSIZE) { 1010 //printf("split last SG element of %u\n", segs[i - 1].ds_len); 1011 prd[i - 1].count = htole32(segs[i - 1].ds_len - MAXLASTSGSIZE); 1012 prd[i].count = htole32(MAXLASTSGSIZE); 1013 prd[i].addr = htole32(segs[i - 1].ds_addr + 1014 (segs[i - 1].ds_len - MAXLASTSGSIZE)); 1015 nsegs++; 1016 i++; 1017 } 1018 prd[i - 1].count |= htole32(ATA_DMA_EOT); 1019 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n")); 1020 args->nsegs = nsegs; 1021 } 1022 1023 static int 1024 ata_promise_mio_setmode(device_t dev, int target, int mode) 1025 { 1026 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1027 struct ata_channel *ch = device_get_softc(dev); 1028 1029 if ( (ctlr->chip->cfg2 == PR_SATA) || 1030 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2)) || 1031 (ctlr->chip->cfg2 == PR_SATA2) || 1032 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) 1033 mode = ata_sata_setmode(dev, target, mode); 1034 else 1035 mode = ata_promise_setmode(dev, target, mode); 1036 return (mode); 1037 } 1038 1039 static int 1040 ata_promise_mio_getrev(device_t dev, int target) 1041 { 1042 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1043 struct ata_channel *ch = device_get_softc(dev); 1044 1045 if ( (ctlr->chip->cfg2 == PR_SATA) || 1046 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2)) || 1047 (ctlr->chip->cfg2 == PR_SATA2) || 1048 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) 1049 return (ata_sata_getrev(dev, target)); 1050 else 1051 return (0); 1052 } 1053 1054 static void 1055 ata_promise_sx4_intr(void *data) 1056 { 1057 struct ata_pci_controller *ctlr = data; 1058 struct ata_channel *ch; 1059 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480); 1060 int unit; 1061 1062 for (unit = 0; unit < ctlr->channels; unit++) { 1063 if (vector & (1 << (unit + 1))) 1064 if ((ch = ctlr->interrupt[unit].argument)) 1065 ctlr->interrupt[unit].function(ch); 1066 if (vector & (1 << (unit + 5))) 1067 if ((ch = ctlr->interrupt[unit].argument)) 1068 ata_promise_queue_hpkt(ctlr, 1069 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 1070 ATA_PDC_HPKT_OFFSET)); 1071 if (vector & (1 << (unit + 9))) { 1072 ata_promise_next_hpkt(ctlr); 1073 if ((ch = ctlr->interrupt[unit].argument)) 1074 ctlr->interrupt[unit].function(ch); 1075 } 1076 if (vector & (1 << (unit + 13))) { 1077 ata_promise_next_hpkt(ctlr); 1078 if ((ch = ctlr->interrupt[unit].argument)) 1079 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1080 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 1081 ATA_PDC_APKT_OFFSET)); 1082 } 1083 } 1084 } 1085 1086 static int 1087 ata_promise_sx4_command(struct ata_request *request) 1088 { 1089 device_t gparent = device_get_parent(request->parent); 1090 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1091 struct ata_channel *ch = device_get_softc(request->parent); 1092 struct ata_dma_prdentry *prd; 1093 caddr_t window = rman_get_virtual(ctlr->r_res1); 1094 u_int32_t *wordp; 1095 int i, idx, length = 0; 1096 1097 /* XXX SOS add ATAPI commands support later */ 1098 switch (request->u.ata.command) { 1099 1100 default: 1101 return -1; 1102 1103 case ATA_ATA_IDENTIFY: 1104 case ATA_READ: 1105 case ATA_READ48: 1106 case ATA_READ_MUL: 1107 case ATA_READ_MUL48: 1108 case ATA_WRITE: 1109 case ATA_WRITE48: 1110 case ATA_WRITE_MUL: 1111 case ATA_WRITE_MUL48: 1112 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 1113 return ata_generic_command(request); 1114 1115 case ATA_SETFEATURES: 1116 case ATA_FLUSHCACHE: 1117 case ATA_FLUSHCACHE48: 1118 case ATA_SLEEP: 1119 case ATA_SET_MULTI: 1120 wordp = (u_int32_t *) 1121 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 1122 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24)); 1123 wordp[1] = 0; 1124 wordp[2] = 0; 1125 ata_promise_apkt((u_int8_t *)wordp, request); 1126 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 1127 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 1128 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1129 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET)); 1130 return 0; 1131 1132 case ATA_READ_DMA: 1133 case ATA_READ_DMA48: 1134 case ATA_WRITE_DMA: 1135 case ATA_WRITE_DMA48: 1136 prd = request->dma->sg; 1137 wordp = (u_int32_t *) 1138 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET); 1139 i = idx = 0; 1140 do { 1141 wordp[idx++] = prd[i].addr; 1142 wordp[idx++] = prd[i].count; 1143 length += (prd[i].count & ~ATA_DMA_EOT); 1144 } while (!(prd[i++].count & ATA_DMA_EOT)); 1145 1146 wordp = (u_int32_t *) 1147 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET); 1148 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 1149 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 1150 1151 wordp = (u_int32_t *) 1152 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET); 1153 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 1154 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 1155 1156 wordp = (u_int32_t *) 1157 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET); 1158 if (request->flags & ATA_R_READ) 1159 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24)); 1160 if (request->flags & ATA_R_WRITE) 1161 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24)); 1162 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET); 1163 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET); 1164 wordp[3] = 0; 1165 1166 wordp = (u_int32_t *) 1167 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 1168 if (request->flags & ATA_R_READ) 1169 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24)); 1170 if (request->flags & ATA_R_WRITE) 1171 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24)); 1172 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET); 1173 wordp[2] = 0; 1174 ata_promise_apkt((u_int8_t *)wordp, request); 1175 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 1176 1177 if (request->flags & ATA_R_READ) { 1178 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001); 1179 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001); 1180 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1181 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET)); 1182 } 1183 if (request->flags & ATA_R_WRITE) { 1184 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001); 1185 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001); 1186 ata_promise_queue_hpkt(ctlr, 1187 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET)); 1188 } 1189 return 0; 1190 } 1191 } 1192 1193 static int 1194 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request) 1195 { 1196 int i = 12; 1197 1198 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE; 1199 bytep[i++] = ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit); 1200 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL; 1201 bytep[i++] = ATA_A_4BIT; 1202 1203 if (request->flags & ATA_R_48BIT) { 1204 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE; 1205 bytep[i++] = request->u.ata.feature >> 8; 1206 bytep[i++] = request->u.ata.feature; 1207 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT; 1208 bytep[i++] = request->u.ata.count >> 8; 1209 bytep[i++] = request->u.ata.count; 1210 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR; 1211 bytep[i++] = request->u.ata.lba >> 24; 1212 bytep[i++] = request->u.ata.lba; 1213 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 1214 bytep[i++] = request->u.ata.lba >> 32; 1215 bytep[i++] = request->u.ata.lba >> 8; 1216 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 1217 bytep[i++] = request->u.ata.lba >> 40; 1218 bytep[i++] = request->u.ata.lba >> 16; 1219 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 1220 bytep[i++] = ATA_D_LBA | ATA_DEV(request->unit); 1221 } 1222 else { 1223 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE; 1224 bytep[i++] = request->u.ata.feature; 1225 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT; 1226 bytep[i++] = request->u.ata.count; 1227 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR; 1228 bytep[i++] = request->u.ata.lba; 1229 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 1230 bytep[i++] = request->u.ata.lba >> 8; 1231 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 1232 bytep[i++] = request->u.ata.lba >> 16; 1233 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 1234 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ATA_DEV(request->unit) | 1235 ((request->u.ata.lba >> 24)&0xf); 1236 } 1237 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND; 1238 bytep[i++] = request->u.ata.command; 1239 return i; 1240 } 1241 1242 static void 1243 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt) 1244 { 1245 struct ata_promise_sx4 *hpktp = ctlr->chipset_data; 1246 1247 mtx_lock(&hpktp->mtx); 1248 if (hpktp->busy) { 1249 struct host_packet *hp = 1250 malloc(sizeof(struct host_packet), M_TEMP, M_NOWAIT | M_ZERO); 1251 hp->addr = hpkt; 1252 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain); 1253 } 1254 else { 1255 hpktp->busy = 1; 1256 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt); 1257 } 1258 mtx_unlock(&hpktp->mtx); 1259 } 1260 1261 static void 1262 ata_promise_next_hpkt(struct ata_pci_controller *ctlr) 1263 { 1264 struct ata_promise_sx4 *hpktp = ctlr->chipset_data; 1265 struct host_packet *hp; 1266 1267 mtx_lock(&hpktp->mtx); 1268 if ((hp = TAILQ_FIRST(&hpktp->queue))) { 1269 TAILQ_REMOVE(&hpktp->queue, hp, chain); 1270 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr); 1271 free(hp, M_TEMP); 1272 } 1273 else 1274 hpktp->busy = 0; 1275 mtx_unlock(&hpktp->mtx); 1276 } 1277 1278 ATA_DECLARE_DRIVER(ata_promise); 1279