1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ata.h" 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ata.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/ata/ata-all.h> 51 #include <dev/ata/ata-pci.h> 52 #include <ata_if.h> 53 54 /* local prototypes */ 55 static int ata_via_chipinit(device_t dev); 56 static int ata_via_ch_attach(device_t dev); 57 static int ata_via_ch_detach(device_t dev); 58 static void ata_via_reset(device_t dev); 59 static void ata_via_old_setmode(device_t dev, int mode); 60 static void ata_via_southbridge_fixup(device_t dev); 61 static void ata_via_new_setmode(device_t dev, int mode); 62 63 /* misc defines */ 64 #define VIA33 0 65 #define VIA66 1 66 #define VIA100 2 67 #define VIA133 3 68 69 #define VIACLK 0x01 70 #define VIABUG 0x02 71 #define VIABAR 0x04 72 #define VIAAHCI 0x08 73 74 75 /* 76 * VIA Technologies Inc. chipset support functions 77 */ 78 static int 79 ata_via_probe(device_t dev) 80 { 81 struct ata_pci_controller *ctlr = device_get_softc(dev); 82 static struct ata_chip_id ids[] = 83 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" }, 84 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" }, 85 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" }, 86 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" }, 87 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"}, 88 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" }, 89 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" }, 90 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" }, 91 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" }, 92 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" }, 93 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" }, 94 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" }, 95 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 96 { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" }, 97 { ATA_VIA8237S, 0x00, VIA133, 0x00, ATA_UDMA6, "8237S" }, 98 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" }, 99 { 0, 0, 0, 0, 0, 0 }}; 100 static struct ata_chip_id new_ids[] = 101 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" }, 102 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" }, 103 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" }, 104 { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" }, 105 { ATA_VIA8237S, 0x00, 7, 0x00, ATA_SA150, "8237S" }, 106 { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" }, 107 { 0, 0, 0, 0, 0, 0 }}; 108 109 if (pci_get_vendor(dev) != ATA_VIA_ID) 110 return ENXIO; 111 112 if (pci_get_devid(dev) == ATA_VIA82C571) { 113 if (!(ctlr->chip = ata_find_chip(dev, ids, -99))) 114 return ENXIO; 115 } 116 else { 117 if (!(ctlr->chip = ata_match_chip(dev, new_ids))) 118 return ENXIO; 119 } 120 121 ata_set_desc(dev); 122 ctlr->chipinit = ata_via_chipinit; 123 return 0; 124 } 125 126 static int 127 ata_via_chipinit(device_t dev) 128 { 129 struct ata_pci_controller *ctlr = device_get_softc(dev); 130 131 if (ata_setup_interrupt(dev, ata_generic_intr)) 132 return ENXIO; 133 134 if (ctlr->chip->max_dma >= ATA_SA150) { 135 /* do we have AHCI capability ? */ 136 if ((ctlr->chip->cfg2 == VIAAHCI) && ata_ahci_chipinit(dev) != ENXIO) 137 return 0; 138 139 ctlr->r_type2 = SYS_RES_IOPORT; 140 ctlr->r_rid2 = PCIR_BAR(5); 141 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 142 &ctlr->r_rid2, RF_ACTIVE))) { 143 ctlr->ch_attach = ata_via_ch_attach; 144 ctlr->ch_detach = ata_via_ch_detach; 145 ctlr->reset = ata_via_reset; 146 147 /* enable PCI interrupt */ 148 pci_write_config(dev, PCIR_COMMAND, 149 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 150 } 151 152 if (ctlr->chip->cfg2 & VIABAR) { 153 ctlr->channels = 3; 154 ctlr->setmode = ata_via_new_setmode; 155 } 156 else 157 ctlr->setmode = ata_sata_setmode; 158 return 0; 159 } 160 161 /* prepare for ATA-66 on the 82C686a and 82C596b */ 162 if (ctlr->chip->cfg2 & VIACLK) 163 pci_write_config(dev, 0x50, 0x030b030b, 4); 164 165 /* the southbridge might need the data corruption fix */ 166 if (ctlr->chip->cfg2 & VIABUG) 167 ata_via_southbridge_fixup(dev); 168 169 /* set fifo configuration half'n'half */ 170 pci_write_config(dev, 0x43, 171 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1); 172 173 /* set status register read retry */ 174 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1); 175 176 /* set DMA read & end-of-sector fifo flush */ 177 pci_write_config(dev, 0x46, 178 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1); 179 180 /* set sector size */ 181 pci_write_config(dev, 0x60, DEV_BSIZE, 2); 182 pci_write_config(dev, 0x68, DEV_BSIZE, 2); 183 184 ctlr->setmode = ata_via_old_setmode; 185 return 0; 186 } 187 188 static int 189 ata_via_ch_attach(device_t dev) 190 { 191 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 192 struct ata_channel *ch = device_get_softc(dev); 193 194 /* newer SATA chips has resources in one BAR for each channel */ 195 if (ctlr->chip->cfg2 & VIABAR) { 196 struct resource *r_io; 197 int i, rid; 198 199 ata_pci_dmainit(dev); 200 201 rid = PCIR_BAR(ch->unit); 202 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev), 203 SYS_RES_IOPORT, 204 &rid, RF_ACTIVE))) 205 return ENXIO; 206 207 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 208 ch->r_io[i].res = r_io; 209 ch->r_io[i].offset = i; 210 } 211 ch->r_io[ATA_CONTROL].res = r_io; 212 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE; 213 ch->r_io[ATA_IDX_ADDR].res = r_io; 214 ata_default_registers(dev); 215 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 216 ch->r_io[i].res = ctlr->r_res1; 217 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); 218 } 219 ata_pci_hw(dev); 220 if (ch->unit >= 2) 221 return 0; 222 } 223 else { 224 /* setup the usual register normal pci style */ 225 if (ata_pci_ch_attach(dev)) 226 return ENXIO; 227 } 228 229 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 230 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1); 231 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 232 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1); 233 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 234 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1); 235 ch->flags |= ATA_NO_SLAVE; 236 237 /* XXX SOS PHY hotplug handling missing in VIA chip ?? */ 238 /* XXX SOS unknown how to enable PHY state change interrupt */ 239 return 0; 240 } 241 242 static int 243 ata_via_ch_detach(device_t dev) 244 { 245 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 246 struct ata_channel *ch = device_get_softc(dev); 247 248 /* newer SATA chips has resources in one BAR for each channel */ 249 if (ctlr->chip->cfg2 & VIABAR) { 250 int rid; 251 252 rid = PCIR_BAR(ch->unit); 253 bus_release_resource(device_get_parent(dev), 254 SYS_RES_IOPORT, rid, ch->r_io[ATA_CONTROL].res); 255 256 ata_pci_dmafini(dev); 257 } 258 else { 259 /* setup the usual register normal pci style */ 260 if (ata_pci_ch_detach(dev)) 261 return ENXIO; 262 } 263 264 return 0; 265 } 266 267 static void 268 ata_via_reset(device_t dev) 269 { 270 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 271 struct ata_channel *ch = device_get_softc(dev); 272 273 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) 274 ata_generic_reset(dev); 275 else 276 if (ata_sata_phy_reset(dev)) 277 ata_generic_reset(dev); 278 } 279 280 static void 281 ata_via_new_setmode(device_t dev, int mode) 282 { 283 device_t gparent = GRANDPARENT(dev); 284 struct ata_pci_controller *ctlr = device_get_softc(gparent); 285 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 286 struct ata_device *atadev = device_get_softc(dev); 287 int error; 288 289 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) { 290 u_int8_t pio_timings[] = { 0xa8, 0x65, 0x65, 0x32, 0x20, 291 0x65, 0x32, 0x20, 292 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 293 u_int8_t dma_timings[] = { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 }; 294 295 mode = ata_check_80pin(dev, ata_limit_mode(dev, mode, ATA_UDMA6)); 296 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 297 if (bootverbose) 298 device_printf(dev, "%ssetting %s on %s chip\n", 299 (error) ? "FAILURE " : "", ata_mode2str(mode), 300 ctlr->chip->text); 301 if (!error) { 302 pci_write_config(gparent, 0xab, pio_timings[ata_mode2idx(mode)], 1); 303 if (mode >= ATA_UDMA0) 304 pci_write_config(gparent, 0xb3, 305 dma_timings[mode & ATA_MODE_MASK], 1); 306 atadev->mode = mode; 307 } 308 } 309 else 310 ata_sata_setmode(dev, mode); 311 } 312 313 static void 314 ata_via_old_setmode(device_t dev, int mode) 315 { 316 device_t gparent = GRANDPARENT(dev); 317 struct ata_pci_controller *ctlr = device_get_softc(gparent); 318 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 319 struct ata_device *atadev = device_get_softc(dev); 320 u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20, 321 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 322 int modes[][7] = { 323 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */ 324 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */ 325 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */ 326 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 } }; /* VIA ATA133 */ 327 int devno = (ch->unit << 1) + atadev->unit; 328 int reg = 0x53 - devno; 329 int error; 330 331 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 332 mode = ata_check_80pin(dev, mode); 333 334 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 335 if (bootverbose) 336 device_printf(dev, "%ssetting %s on %s chip\n", 337 (error) ? "FAILURE " : "", ata_mode2str(mode), 338 ctlr->chip->text); 339 if (!error) { 340 if (ctlr->chip->cfg1 != VIA133) 341 pci_write_config(gparent, reg - 0x08,timings[ata_mode2idx(mode)],1); 342 if (mode >= ATA_UDMA0) 343 pci_write_config(gparent, reg, 344 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1); 345 else 346 pci_write_config(gparent, reg, 0x8b, 1); 347 atadev->mode = mode; 348 } 349 } 350 351 static void 352 ata_via_southbridge_fixup(device_t dev) 353 { 354 device_t *children; 355 int nchildren, i; 356 357 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 358 return; 359 360 for (i = 0; i < nchildren; i++) { 361 if (pci_get_devid(children[i]) == ATA_VIA8363 || 362 pci_get_devid(children[i]) == ATA_VIA8371 || 363 pci_get_devid(children[i]) == ATA_VIA8662 || 364 pci_get_devid(children[i]) == ATA_VIA8361) { 365 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1); 366 367 if ((reg76 & 0xf0) != 0xd0) { 368 device_printf(dev, 369 "Correcting VIA config for southbridge data corruption bug\n"); 370 pci_write_config(children[i], 0x75, 0x80, 1); 371 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1); 372 } 373 break; 374 } 375 } 376 free(children, M_TEMP); 377 } 378 379 ATA_DECLARE_DRIVER(ata_via); 380 MODULE_DEPEND(ata_via, ata_ahci, 1, 1, 1); 381