1 /* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 20 #ifndef _ATH_AH_H_ 21 #define _ATH_AH_H_ 22 /* 23 * Atheros Hardware Access Layer 24 * 25 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal 26 * structure for use with the device. Hardware-related operations that 27 * follow must call back into the HAL through interface, supplying the 28 * reference as the first parameter. 29 */ 30 31 #include "ah_osdep.h" 32 33 /* 34 * __ahdecl is analogous to _cdecl; it defines the calling 35 * convention used within the HAL. For most systems this 36 * can just default to be empty and the compiler will (should) 37 * use _cdecl. For systems where _cdecl is not compatible this 38 * must be defined. See linux/ah_osdep.h for an example. 39 */ 40 #ifndef __ahdecl 41 #define __ahdecl 42 #endif 43 44 /* 45 * Status codes that may be returned by the HAL. Note that 46 * interfaces that return a status code set it only when an 47 * error occurs--i.e. you cannot check it for success. 48 */ 49 typedef enum { 50 HAL_OK = 0, /* No error */ 51 HAL_ENXIO = 1, /* No hardware present */ 52 HAL_ENOMEM = 2, /* Memory allocation failed */ 53 HAL_EIO = 3, /* Hardware didn't respond as expected */ 54 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 55 HAL_EEVERSION = 5, /* EEPROM version invalid */ 56 HAL_EELOCKED = 6, /* EEPROM unreadable */ 57 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 58 HAL_EEREAD = 8, /* EEPROM read problem */ 59 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 60 HAL_EESIZE = 10, /* EEPROM size not supported */ 61 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 62 HAL_EINVAL = 12, /* Invalid parameter to function */ 63 HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 64 HAL_ESELFTEST = 14, /* Hardware self-test failed */ 65 HAL_EINPROGRESS = 15, /* Operation incomplete */ 66 HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */ 67 HAL_EEBADCC = 17, /* EEPROM invalid country code */ 68 } HAL_STATUS; 69 70 typedef enum { 71 AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 72 AH_TRUE = 1, 73 } HAL_BOOL; 74 75 typedef enum { 76 HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 77 HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 78 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 79 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 80 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 81 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 82 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 83 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 84 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 85 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ 86 HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 87 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 88 HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 89 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 90 HAL_CAP_TXPOW = 15, /* global tx power limit */ 91 HAL_CAP_TPC = 16, /* per-packet tx power control */ 92 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 93 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 94 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 95 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 96 /* 21 was HAL_CAP_XR */ 97 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ 98 /* 23 was HAL_CAP_CHAN_HALFRATE */ 99 /* 24 was HAL_CAP_CHAN_QUARTERRATE */ 100 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 101 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 102 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 103 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 104 HAL_CAP_INTMIT = 29, /* interference mitigation */ 105 HAL_CAP_RXORN_FATAL = 30, /* HAL_INT_RXORN treated as fatal */ 106 HAL_CAP_HT = 31, /* hardware can support HT */ 107 HAL_CAP_TX_CHAINMASK = 32, /* mask of TX chains supported */ 108 HAL_CAP_RX_CHAINMASK = 33, /* mask of RX chains supported */ 109 HAL_CAP_RXTSTAMP_PREC = 34, /* rx desc tstamp precision (bits) */ 110 HAL_CAP_BB_HANG = 35, /* can baseband hang */ 111 HAL_CAP_MAC_HANG = 36, /* can MAC hang */ 112 HAL_CAP_INTRMASK = 37, /* bitmask of supported interrupts */ 113 HAL_CAP_BSSIDMATCH = 38, /* hardware has disable bssid match */ 114 HAL_CAP_STREAMS = 39, /* how many 802.11n spatial streams are available */ 115 HAP_CAP_SPLIT_4KB_TRANS = 40, /* hardware supports descriptors straddling a 4k page boundary */ 116 } HAL_CAPABILITY_TYPE; 117 118 /* 119 * "States" for setting the LED. These correspond to 120 * the possible 802.11 operational states and there may 121 * be a many-to-one mapping between these states and the 122 * actual hardware state for the LED's (i.e. the hardware 123 * may have fewer states). 124 */ 125 typedef enum { 126 HAL_LED_INIT = 0, 127 HAL_LED_SCAN = 1, 128 HAL_LED_AUTH = 2, 129 HAL_LED_ASSOC = 3, 130 HAL_LED_RUN = 4 131 } HAL_LED_STATE; 132 133 /* 134 * Transmit queue types/numbers. These are used to tag 135 * each transmit queue in the hardware and to identify a set 136 * of transmit queues for operations such as start/stop dma. 137 */ 138 typedef enum { 139 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 140 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 141 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 142 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 143 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */ 144 HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */ 145 } HAL_TX_QUEUE; 146 147 #define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ 148 149 /* 150 * Transmit queue subtype. These map directly to 151 * WME Access Categories (except for UPSD). Refer 152 * to Table 5 of the WME spec. 153 */ 154 typedef enum { 155 HAL_WME_AC_BK = 0, /* background access category */ 156 HAL_WME_AC_BE = 1, /* best effort access category*/ 157 HAL_WME_AC_VI = 2, /* video access category */ 158 HAL_WME_AC_VO = 3, /* voice access category */ 159 HAL_WME_UPSD = 4, /* uplink power save */ 160 } HAL_TX_QUEUE_SUBTYPE; 161 162 /* 163 * Transmit queue flags that control various 164 * operational parameters. 165 */ 166 typedef enum { 167 /* 168 * Per queue interrupt enables. When set the associated 169 * interrupt may be delivered for packets sent through 170 * the queue. Without these enabled no interrupts will 171 * be delivered for transmits through the queue. 172 */ 173 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 174 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 175 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 176 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 177 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 178 /* 179 * Enable hardware compression for packets sent through 180 * the queue. The compression buffer must be setup and 181 * packets must have a key entry marked in the tx descriptor. 182 */ 183 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 184 /* 185 * Disable queue when veol is hit or ready time expires. 186 * By default the queue is disabled only on reaching the 187 * physical end of queue (i.e. a null link ptr in the 188 * descriptor chain). 189 */ 190 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 191 /* 192 * Schedule frames on delivery of a DBA (DMA Beacon Alert) 193 * event. Frames will be transmitted only when this timer 194 * fires, e.g to transmit a beacon in ap or adhoc modes. 195 */ 196 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 197 /* 198 * Each transmit queue has a counter that is incremented 199 * each time the queue is enabled and decremented when 200 * the list of frames to transmit is traversed (or when 201 * the ready time for the queue expires). This counter 202 * must be non-zero for frames to be scheduled for 203 * transmission. The following controls disable bumping 204 * this counter under certain conditions. Typically this 205 * is used to gate frames based on the contents of another 206 * queue (e.g. CAB traffic may only follow a beacon frame). 207 * These are meaningful only when frames are scheduled 208 * with a non-ASAP policy (e.g. DBA-gated). 209 */ 210 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 211 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 212 213 /* 214 * Fragment burst backoff policy. Normally the no backoff 215 * is done after a successful transmission, the next fragment 216 * is sent at SIFS. If this flag is set backoff is done 217 * after each fragment, regardless whether it was ack'd or 218 * not, after the backoff count reaches zero a normal channel 219 * access procedure is done before the next transmit (i.e. 220 * wait AIFS instead of SIFS). 221 */ 222 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 223 /* 224 * Disable post-tx backoff following each frame. 225 */ 226 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 227 /* 228 * DCU arbiter lockout control. This controls how 229 * lower priority tx queues are handled with respect to 230 * to a specific queue when multiple queues have frames 231 * to send. No lockout means lower priority queues arbitrate 232 * concurrently with this queue. Intra-frame lockout 233 * means lower priority queues are locked out until the 234 * current frame transmits (e.g. including backoffs and bursting). 235 * Global lockout means nothing lower can arbitrary so 236 * long as there is traffic activity on this queue (frames, 237 * backoff, etc). 238 */ 239 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 240 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 241 242 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 243 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */ 244 } HAL_TX_QUEUE_FLAGS; 245 246 typedef struct { 247 uint32_t tqi_ver; /* hal TXQ version */ 248 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 249 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 250 uint32_t tqi_priority; /* (not used) */ 251 uint32_t tqi_aifs; /* aifs */ 252 uint32_t tqi_cwmin; /* cwMin */ 253 uint32_t tqi_cwmax; /* cwMax */ 254 uint16_t tqi_shretry; /* rts retry limit */ 255 uint16_t tqi_lgretry; /* long retry limit (not used)*/ 256 uint32_t tqi_cbrPeriod; /* CBR period (us) */ 257 uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */ 258 uint32_t tqi_burstTime; /* max burst duration (us) */ 259 uint32_t tqi_readyTime; /* frame schedule time (us) */ 260 uint32_t tqi_compBuf; /* comp buffer phys addr */ 261 } HAL_TXQ_INFO; 262 263 #define HAL_TQI_NONVAL 0xffff 264 265 /* token to use for aifs, cwmin, cwmax */ 266 #define HAL_TXQ_USEDEFAULT ((uint32_t) -1) 267 268 /* compression definitions */ 269 #define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ 270 #define HAL_COMP_BUF_ALIGN_SIZE 512 271 272 /* 273 * Transmit packet types. This belongs in ah_desc.h, but 274 * is here so we can give a proper type to various parameters 275 * (and not require everyone include the file). 276 * 277 * NB: These values are intentionally assigned for 278 * direct use when setting up h/w descriptors. 279 */ 280 typedef enum { 281 HAL_PKT_TYPE_NORMAL = 0, 282 HAL_PKT_TYPE_ATIM = 1, 283 HAL_PKT_TYPE_PSPOLL = 2, 284 HAL_PKT_TYPE_BEACON = 3, 285 HAL_PKT_TYPE_PROBE_RESP = 4, 286 HAL_PKT_TYPE_CHIRP = 5, 287 HAL_PKT_TYPE_GRP_POLL = 6, 288 HAL_PKT_TYPE_AMPDU = 7, 289 } HAL_PKT_TYPE; 290 291 /* Rx Filter Frame Types */ 292 typedef enum { 293 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 294 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 295 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 296 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 297 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 298 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 299 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 300 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 301 HAL_RX_FILTER_PHYRADAR = 0x00000200, /* Allow phy radar errors */ 302 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */ 303 HAL_RX_FILTER_BSSID = 0x00000800, /* Disable BSSID match */ 304 } HAL_RX_FILTER; 305 306 typedef enum { 307 HAL_PM_AWAKE = 0, 308 HAL_PM_FULL_SLEEP = 1, 309 HAL_PM_NETWORK_SLEEP = 2, 310 HAL_PM_UNDEFINED = 3 311 } HAL_POWER_MODE; 312 313 /* 314 * NOTE WELL: 315 * These are mapped to take advantage of the common locations for many of 316 * the bits on all of the currently supported MAC chips. This is to make 317 * the ISR as efficient as possible, while still abstracting HW differences. 318 * When new hardware breaks this commonality this enumerated type, as well 319 * as the HAL functions using it, must be modified. All values are directly 320 * mapped unless commented otherwise. 321 */ 322 typedef enum { 323 HAL_INT_RX = 0x00000001, /* Non-common mapping */ 324 HAL_INT_RXDESC = 0x00000002, 325 HAL_INT_RXNOFRM = 0x00000008, 326 HAL_INT_RXEOL = 0x00000010, 327 HAL_INT_RXORN = 0x00000020, 328 HAL_INT_TX = 0x00000040, /* Non-common mapping */ 329 HAL_INT_TXDESC = 0x00000080, 330 HAL_INT_TIM_TIMER= 0x00000100, 331 HAL_INT_TXURN = 0x00000800, 332 HAL_INT_MIB = 0x00001000, 333 HAL_INT_RXPHY = 0x00004000, 334 HAL_INT_RXKCM = 0x00008000, 335 HAL_INT_SWBA = 0x00010000, 336 HAL_INT_BMISS = 0x00040000, 337 HAL_INT_BNR = 0x00100000, 338 HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 339 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 340 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ 341 HAL_INT_GPIO = 0x01000000, 342 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 343 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */ 344 HAL_INT_TBTT = 0x08000000, /* Non-common mapping */ 345 HAL_INT_CST = 0x10000000, /* Non-common mapping */ 346 HAL_INT_GTT = 0x20000000, /* Non-common mapping */ 347 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 348 #define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ 349 HAL_INT_BMISC = HAL_INT_TIM 350 | HAL_INT_DTIM 351 | HAL_INT_DTIMSYNC 352 | HAL_INT_CABEND 353 | HAL_INT_TBTT, 354 355 /* Interrupt bits that map directly to ISR/IMR bits */ 356 HAL_INT_COMMON = HAL_INT_RXNOFRM 357 | HAL_INT_RXDESC 358 | HAL_INT_RXEOL 359 | HAL_INT_RXORN 360 | HAL_INT_TXDESC 361 | HAL_INT_TXURN 362 | HAL_INT_MIB 363 | HAL_INT_RXPHY 364 | HAL_INT_RXKCM 365 | HAL_INT_SWBA 366 | HAL_INT_BMISS 367 | HAL_INT_BNR 368 | HAL_INT_GPIO, 369 } HAL_INT; 370 371 typedef enum { 372 HAL_GPIO_MUX_OUTPUT = 0, 373 HAL_GPIO_MUX_PCIE_ATTENTION_LED = 1, 374 HAL_GPIO_MUX_PCIE_POWER_LED = 2, 375 HAL_GPIO_MUX_TX_FRAME = 3, 376 HAL_GPIO_MUX_RX_CLEAR_EXTERNAL = 4, 377 HAL_GPIO_MUX_MAC_NETWORK_LED = 5, 378 HAL_GPIO_MUX_MAC_POWER_LED = 6 379 } HAL_GPIO_MUX_TYPE; 380 381 typedef enum { 382 HAL_GPIO_INTR_LOW = 0, 383 HAL_GPIO_INTR_HIGH = 1, 384 HAL_GPIO_INTR_DISABLE = 2 385 } HAL_GPIO_INTR_TYPE; 386 387 typedef enum { 388 HAL_RFGAIN_INACTIVE = 0, 389 HAL_RFGAIN_READ_REQUESTED = 1, 390 HAL_RFGAIN_NEED_CHANGE = 2 391 } HAL_RFGAIN; 392 393 typedef uint16_t HAL_CTRY_CODE; /* country code */ 394 typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 395 396 #define HAL_ANTENNA_MIN_MODE 0 397 #define HAL_ANTENNA_FIXED_A 1 398 #define HAL_ANTENNA_FIXED_B 2 399 #define HAL_ANTENNA_MAX_MODE 3 400 401 typedef struct { 402 uint32_t ackrcv_bad; 403 uint32_t rts_bad; 404 uint32_t rts_good; 405 uint32_t fcs_bad; 406 uint32_t beacons; 407 } HAL_MIB_STATS; 408 409 enum { 410 HAL_MODE_11A = 0x001, /* 11a channels */ 411 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 412 HAL_MODE_11B = 0x004, /* 11b channels */ 413 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 414 #ifdef notdef 415 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ 416 #else 417 HAL_MODE_11G = 0x008, /* XXX historical */ 418 #endif 419 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 420 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 421 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */ 422 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */ 423 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */ 424 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */ 425 HAL_MODE_11NG_HT20 = 0x008000, 426 HAL_MODE_11NA_HT20 = 0x010000, 427 HAL_MODE_11NG_HT40PLUS = 0x020000, 428 HAL_MODE_11NG_HT40MINUS = 0x040000, 429 HAL_MODE_11NA_HT40PLUS = 0x080000, 430 HAL_MODE_11NA_HT40MINUS = 0x100000, 431 HAL_MODE_ALL = 0xffffff 432 }; 433 434 typedef struct { 435 int rateCount; /* NB: for proper padding */ 436 uint8_t rateCodeToIndex[144]; /* back mapping */ 437 struct { 438 uint8_t valid; /* valid for rate control use */ 439 uint8_t phy; /* CCK/OFDM/XR */ 440 uint32_t rateKbps; /* transfer rate in kbs */ 441 uint8_t rateCode; /* rate for h/w descriptors */ 442 uint8_t shortPreamble; /* mask for enabling short 443 * preamble in CCK rate code */ 444 uint8_t dot11Rate; /* value for supported rates 445 * info element of MLME */ 446 uint8_t controlRate; /* index of next lower basic 447 * rate; used for dur. calcs */ 448 uint16_t lpAckDuration; /* long preamble ACK duration */ 449 uint16_t spAckDuration; /* short preamble ACK duration*/ 450 } info[32]; 451 } HAL_RATE_TABLE; 452 453 typedef struct { 454 u_int rs_count; /* number of valid entries */ 455 uint8_t rs_rates[32]; /* rates */ 456 } HAL_RATE_SET; 457 458 /* 459 * 802.11n specific structures and enums 460 */ 461 typedef enum { 462 HAL_CHAINTYPE_TX = 1, /* Tx chain type */ 463 HAL_CHAINTYPE_RX = 2, /* RX chain type */ 464 } HAL_CHAIN_TYPE; 465 466 typedef struct { 467 u_int Tries; 468 u_int Rate; 469 u_int PktDuration; 470 u_int ChSel; 471 u_int RateFlags; 472 #define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ 473 #define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ 474 #define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ 475 } HAL_11N_RATE_SERIES; 476 477 typedef enum { 478 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ 479 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ 480 } HAL_HT_MACMODE; 481 482 typedef enum { 483 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ 484 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ 485 } HAL_HT_PHYMODE; 486 487 typedef enum { 488 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ 489 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ 490 } HAL_HT_EXTPROTSPACING; 491 492 493 typedef enum { 494 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ 495 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ 496 } HAL_HT_RXCLEAR; 497 498 /* 499 * Antenna switch control. By default antenna selection 500 * enables multiple (2) antenna use. To force use of the 501 * A or B antenna only specify a fixed setting. Fixing 502 * the antenna will also disable any diversity support. 503 */ 504 typedef enum { 505 HAL_ANT_VARIABLE = 0, /* variable by programming */ 506 HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 507 HAL_ANT_FIXED_B = 2, /* fixed antenna B */ 508 } HAL_ANT_SETTING; 509 510 typedef enum { 511 HAL_M_STA = 1, /* infrastructure station */ 512 HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 513 HAL_M_HOSTAP = 6, /* Software Access Point */ 514 HAL_M_MONITOR = 8 /* Monitor mode */ 515 } HAL_OPMODE; 516 517 typedef struct { 518 uint8_t kv_type; /* one of HAL_CIPHER */ 519 uint8_t kv_pad; 520 uint16_t kv_len; /* length in bits */ 521 uint8_t kv_val[16]; /* enough for 128-bit keys */ 522 uint8_t kv_mic[8]; /* TKIP MIC key */ 523 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ 524 } HAL_KEYVAL; 525 526 typedef enum { 527 HAL_CIPHER_WEP = 0, 528 HAL_CIPHER_AES_OCB = 1, 529 HAL_CIPHER_AES_CCM = 2, 530 HAL_CIPHER_CKIP = 3, 531 HAL_CIPHER_TKIP = 4, 532 HAL_CIPHER_CLR = 5, /* no encryption */ 533 534 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 535 } HAL_CIPHER; 536 537 enum { 538 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 539 HAL_SLOT_TIME_9 = 9, 540 HAL_SLOT_TIME_20 = 20, 541 }; 542 543 /* 544 * Per-station beacon timer state. Note that the specified 545 * beacon interval (given in TU's) can also include flags 546 * to force a TSF reset and to enable the beacon xmit logic. 547 * If bs_cfpmaxduration is non-zero the hardware is setup to 548 * coexist with a PCF-capable AP. 549 */ 550 typedef struct { 551 uint32_t bs_nexttbtt; /* next beacon in TU */ 552 uint32_t bs_nextdtim; /* next DTIM in TU */ 553 uint32_t bs_intval; /* beacon interval+flags */ 554 #define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 555 #define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 556 #define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 557 uint32_t bs_dtimperiod; 558 uint16_t bs_cfpperiod; /* CFP period in TU */ 559 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 560 uint32_t bs_cfpnext; /* next CFP in TU */ 561 uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 562 uint16_t bs_bmissthreshold; /* beacon miss threshold */ 563 uint32_t bs_sleepduration; /* max sleep duration */ 564 } HAL_BEACON_STATE; 565 566 /* 567 * Like HAL_BEACON_STATE but for non-station mode setup. 568 * NB: see above flag definitions for bt_intval. 569 */ 570 typedef struct { 571 uint32_t bt_intval; /* beacon interval+flags */ 572 uint32_t bt_nexttbtt; /* next beacon in TU */ 573 uint32_t bt_nextatim; /* next ATIM in TU */ 574 uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 575 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 576 uint32_t bt_flags; /* timer enables */ 577 #define HAL_BEACON_TBTT_EN 0x00000001 578 #define HAL_BEACON_DBA_EN 0x00000002 579 #define HAL_BEACON_SWBA_EN 0x00000004 580 } HAL_BEACON_TIMERS; 581 582 /* 583 * Per-node statistics maintained by the driver for use in 584 * optimizing signal quality and other operational aspects. 585 */ 586 typedef struct { 587 uint32_t ns_avgbrssi; /* average beacon rssi */ 588 uint32_t ns_avgrssi; /* average data rssi */ 589 uint32_t ns_avgtxrssi; /* average tx rssi */ 590 } HAL_NODE_STATS; 591 592 #define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 593 594 struct ath_desc; 595 struct ath_tx_status; 596 struct ath_rx_status; 597 struct ieee80211_channel; 598 599 /* 600 * This is a channel survey sample entry. 601 * 602 * The AR5212 ANI routines fill these samples. The ANI code then uses it 603 * when calculating listen time; it is also exported via a diagnostic 604 * API. 605 */ 606 typedef struct { 607 uint32_t seq_num; 608 uint32_t tx_busy; 609 uint32_t rx_busy; 610 uint32_t chan_busy; 611 uint32_t cycle_count; 612 } HAL_SURVEY_SAMPLE; 613 614 /* 615 * This provides 3.2 seconds of sample space given an 616 * ANI time of 1/10th of a second. This may not be enough! 617 */ 618 #define CHANNEL_SURVEY_SAMPLE_COUNT 32 619 620 typedef struct { 621 HAL_SURVEY_SAMPLE samples[CHANNEL_SURVEY_SAMPLE_COUNT]; 622 uint32_t cur_sample; /* current sample in sequence */ 623 uint32_t cur_seq; /* current sequence number */ 624 } HAL_CHANNEL_SURVEY; 625 626 /* 627 * Hardware Access Layer (HAL) API. 628 * 629 * Clients of the HAL call ath_hal_attach to obtain a reference to an 630 * ath_hal structure for use with the device. Hardware-related operations 631 * that follow must call back into the HAL through interface, supplying 632 * the reference as the first parameter. Note that before using the 633 * reference returned by ath_hal_attach the caller should verify the 634 * ABI version number. 635 */ 636 struct ath_hal { 637 uint32_t ah_magic; /* consistency check magic number */ 638 uint16_t ah_devid; /* PCI device ID */ 639 uint16_t ah_subvendorid; /* PCI subvendor ID */ 640 HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 641 HAL_BUS_TAG ah_st; /* params for register r+w */ 642 HAL_BUS_HANDLE ah_sh; 643 HAL_CTRY_CODE ah_countryCode; 644 645 uint32_t ah_macVersion; /* MAC version id */ 646 uint16_t ah_macRev; /* MAC revision */ 647 uint16_t ah_phyRev; /* PHY revision */ 648 /* NB: when only one radio is present the rev is in 5Ghz */ 649 uint16_t ah_analog5GhzRev;/* 5GHz radio revision */ 650 uint16_t ah_analog2GhzRev;/* 2GHz radio revision */ 651 652 uint16_t *ah_eepromdata; /* eeprom buffer, if needed */ 653 654 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, 655 u_int mode); 656 void __ahdecl(*ah_detach)(struct ath_hal*); 657 658 /* Reset functions */ 659 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, 660 struct ieee80211_channel *, 661 HAL_BOOL bChannelChange, HAL_STATUS *status); 662 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); 663 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *); 664 void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore); 665 void __ahdecl(*ah_disablePCIE)(struct ath_hal *); 666 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 667 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, 668 struct ieee80211_channel *, HAL_BOOL *); 669 HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, 670 struct ieee80211_channel *, u_int chainMask, 671 HAL_BOOL longCal, HAL_BOOL *isCalDone); 672 HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, 673 const struct ieee80211_channel *); 674 HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *, 675 const struct ieee80211_channel *, uint16_t *); 676 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 677 HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *, 678 const struct ieee80211_channel *); 679 680 /* Transmit functions */ 681 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, 682 HAL_BOOL incTrigLevel); 683 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, 684 const HAL_TXQ_INFO *qInfo); 685 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, 686 const HAL_TXQ_INFO *qInfo); 687 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, 688 HAL_TXQ_INFO *qInfo); 689 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); 690 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); 691 uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 692 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp); 693 uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 694 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); 695 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); 696 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, 697 u_int pktLen, u_int hdrLen, 698 HAL_PKT_TYPE type, u_int txPower, 699 u_int txRate0, u_int txTries0, 700 u_int keyIx, u_int antMode, u_int flags, 701 u_int rtsctsRate, u_int rtsctsDuration, 702 u_int compicvLen, u_int compivLen, 703 u_int comp); 704 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, 705 u_int txRate1, u_int txTries1, 706 u_int txRate2, u_int txTries2, 707 u_int txRate3, u_int txTries3); 708 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, 709 u_int segLen, HAL_BOOL firstSeg, 710 HAL_BOOL lastSeg, const struct ath_desc *); 711 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, 712 struct ath_desc *, struct ath_tx_status *); 713 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 714 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); 715 HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *, 716 const struct ath_desc *ds, int *rates, int *tries); 717 718 /* Receive Functions */ 719 uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*); 720 void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp); 721 void __ahdecl(*ah_enableReceive)(struct ath_hal*); 722 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); 723 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*); 724 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); 725 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, 726 uint32_t filter0, uint32_t filter1); 727 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, 728 uint32_t index); 729 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, 730 uint32_t index); 731 uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 732 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t); 733 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 734 uint32_t size, u_int flags); 735 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, 736 struct ath_desc *, uint32_t phyAddr, 737 struct ath_desc *next, uint64_t tsf, 738 struct ath_rx_status *); 739 void __ahdecl(*ah_rxMonitor)(struct ath_hal *, 740 const HAL_NODE_STATS *, 741 const struct ieee80211_channel *); 742 void __ahdecl(*ah_aniPoll)(struct ath_hal *, 743 const struct ieee80211_channel *); 744 void __ahdecl(*ah_procMibEvent)(struct ath_hal *, 745 const HAL_NODE_STATS *); 746 747 /* Misc Functions */ 748 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, 749 HAL_CAPABILITY_TYPE, uint32_t capability, 750 uint32_t *result); 751 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, 752 HAL_CAPABILITY_TYPE, uint32_t capability, 753 uint32_t setting, HAL_STATUS *); 754 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, 755 const void *args, uint32_t argsize, 756 void **result, uint32_t *resultsize); 757 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *); 758 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*); 759 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 760 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*); 761 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, 762 uint16_t, HAL_STATUS *); 763 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); 764 void __ahdecl(*ah_writeAssocid)(struct ath_hal*, 765 const uint8_t *bssid, uint16_t assocId); 766 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, 767 uint32_t gpio, HAL_GPIO_MUX_TYPE); 768 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 769 uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 770 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *, 771 uint32_t gpio, uint32_t val); 772 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 773 uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 774 uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 775 void __ahdecl(*ah_resetTsf)(struct ath_hal*); 776 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*); 777 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, 778 HAL_MIB_STATS*); 779 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*); 780 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*); 781 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int); 782 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*); 783 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*, 784 HAL_ANT_SETTING); 785 HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int); 786 u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*); 787 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); 788 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); 789 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); 790 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*); 791 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int); 792 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*); 793 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); 794 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); 795 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int); 796 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int); 797 798 /* Key Cache Functions */ 799 uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); 800 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t); 801 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, 802 uint16_t); 803 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, 804 uint16_t, const HAL_KEYVAL *, 805 const uint8_t *, int); 806 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, 807 uint16_t, const uint8_t *); 808 809 /* Power Management Functions */ 810 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*, 811 HAL_POWER_MODE mode, int setChip); 812 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); 813 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, 814 const struct ieee80211_channel *); 815 816 /* Beacon Management Functions */ 817 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, 818 const HAL_BEACON_TIMERS *); 819 /* NB: deprecated, use ah_setBeaconTimers instead */ 820 void __ahdecl(*ah_beaconInit)(struct ath_hal *, 821 uint32_t nexttbtt, uint32_t intval); 822 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, 823 const HAL_BEACON_STATE *); 824 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*); 825 826 /* 802.11n Functions */ 827 HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *, 828 struct ath_desc *, u_int, u_int, HAL_PKT_TYPE, 829 u_int, HAL_CIPHER, uint8_t, u_int, HAL_BOOL, 830 HAL_BOOL); 831 HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *, 832 struct ath_desc *, u_int, u_int, u_int, 833 u_int, u_int, u_int, u_int, u_int); 834 HAL_BOOL __ahdecl(*ah_setupLastTxDesc)(struct ath_hal *, 835 struct ath_desc *, const struct ath_desc *); 836 void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *, 837 struct ath_desc *, u_int, u_int, 838 HAL_11N_RATE_SERIES [], u_int, u_int); 839 void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *, 840 struct ath_desc *, u_int); 841 void __ahdecl(*ah_clr11nAggr)(struct ath_hal *, 842 struct ath_desc *); 843 void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *, 844 struct ath_desc *, u_int); 845 uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *); 846 void __ahdecl(*ah_set11nMac2040)(struct ath_hal *, 847 HAL_HT_MACMODE); 848 HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah); 849 void __ahdecl(*ah_set11nRxClear)(struct ath_hal *, 850 HAL_HT_RXCLEAR); 851 852 /* Interrupt functions */ 853 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); 854 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); 855 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); 856 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); 857 }; 858 859 /* 860 * Check the PCI vendor ID and device ID against Atheros' values 861 * and return a printable description for any Atheros hardware. 862 * AH_NULL is returned if the ID's do not describe Atheros hardware. 863 */ 864 extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid); 865 866 /* 867 * Attach the HAL for use with the specified device. The device is 868 * defined by the PCI device ID. The caller provides an opaque pointer 869 * to an upper-layer data structure (HAL_SOFTC) that is stored in the 870 * HAL state block for later use. Hardware register accesses are done 871 * using the specified bus tag and handle. On successful return a 872 * reference to a state block is returned that must be supplied in all 873 * subsequent HAL calls. Storage associated with this reference is 874 * dynamically allocated and must be freed by calling the ah_detach 875 * method when the client is done. If the attach operation fails a 876 * null (AH_NULL) reference will be returned and a status code will 877 * be returned if the status parameter is non-zero. 878 */ 879 extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC, 880 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, HAL_STATUS* status); 881 882 extern const char *ath_hal_mac_name(struct ath_hal *); 883 extern const char *ath_hal_rf_name(struct ath_hal *); 884 885 /* 886 * Regulatory interfaces. Drivers should use ath_hal_init_channels to 887 * request a set of channels for a particular country code and/or 888 * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then 889 * this list is constructed according to the contents of the EEPROM. 890 * ath_hal_getchannels acts similarly but does not alter the operating 891 * state; this can be used to collect information for a particular 892 * regulatory configuration. Finally ath_hal_set_channels installs a 893 * channel list constructed outside the driver. The HAL will adopt the 894 * channel list and setup internal state according to the specified 895 * regulatory configuration (e.g. conformance test limits). 896 * 897 * For all interfaces the channel list is returned in the supplied array. 898 * maxchans defines the maximum size of this array. nchans contains the 899 * actual number of channels returned. If a problem occurred then a 900 * status code != HAL_OK is returned. 901 */ 902 struct ieee80211_channel; 903 904 /* 905 * Return a list of channels according to the specified regulatory. 906 */ 907 extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *, 908 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 909 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 910 HAL_BOOL enableExtendedChannels); 911 912 /* 913 * Return a list of channels and install it as the current operating 914 * regulatory list. 915 */ 916 extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *, 917 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 918 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd, 919 HAL_BOOL enableExtendedChannels); 920 921 /* 922 * Install the list of channels as the current operating regulatory 923 * and setup related state according to the country code and sku. 924 */ 925 extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *, 926 struct ieee80211_channel *chans, int nchans, 927 HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn); 928 929 /* 930 * Calibrate noise floor data following a channel scan or similar. 931 * This must be called prior retrieving noise floor data. 932 */ 933 extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah); 934 935 /* 936 * Return bit mask of wireless modes supported by the hardware. 937 */ 938 extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*); 939 940 /* 941 * Calculate the packet TX time for a legacy or 11n frame 942 */ 943 extern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah, 944 const HAL_RATE_TABLE *rates, uint32_t frameLen, 945 uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble); 946 947 /* 948 * Calculate the duration of an 11n frame. 949 */ 950 extern uint32_t __ahdecl ath_computedur_ht(uint32_t frameLen, uint16_t rate, 951 int streams, HAL_BOOL isht40, HAL_BOOL isShortGI); 952 953 /* 954 * Calculate the transmit duration of a legacy frame. 955 */ 956 extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, 957 const HAL_RATE_TABLE *rates, uint32_t frameLen, 958 uint16_t rateix, HAL_BOOL shortPreamble); 959 #endif /* _ATH_AH_H_ */ 960