1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD$ 20 */ 21 22 #ifndef _ATH_AH_H_ 23 #define _ATH_AH_H_ 24 /* 25 * Atheros Hardware Access Layer 26 * 27 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal 28 * structure for use with the device. Hardware-related operations that 29 * follow must call back into the HAL through interface, supplying the 30 * reference as the first parameter. 31 */ 32 33 #include "ah_osdep.h" 34 35 /* 36 * The maximum number of TX/RX chains supported. 37 * This is intended to be used by various statistics gathering operations 38 * (NF, RSSI, EVM). 39 */ 40 #define AH_MAX_CHAINS 3 41 #define AH_MIMO_MAX_EVM_PILOTS 6 42 43 /* 44 * __ahdecl is analogous to _cdecl; it defines the calling 45 * convention used within the HAL. For most systems this 46 * can just default to be empty and the compiler will (should) 47 * use _cdecl. For systems where _cdecl is not compatible this 48 * must be defined. See linux/ah_osdep.h for an example. 49 */ 50 #ifndef __ahdecl 51 #define __ahdecl 52 #endif 53 54 /* 55 * Status codes that may be returned by the HAL. Note that 56 * interfaces that return a status code set it only when an 57 * error occurs--i.e. you cannot check it for success. 58 */ 59 typedef enum { 60 HAL_OK = 0, /* No error */ 61 HAL_ENXIO = 1, /* No hardware present */ 62 HAL_ENOMEM = 2, /* Memory allocation failed */ 63 HAL_EIO = 3, /* Hardware didn't respond as expected */ 64 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 65 HAL_EEVERSION = 5, /* EEPROM version invalid */ 66 HAL_EELOCKED = 6, /* EEPROM unreadable */ 67 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 68 HAL_EEREAD = 8, /* EEPROM read problem */ 69 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 70 HAL_EESIZE = 10, /* EEPROM size not supported */ 71 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 72 HAL_EINVAL = 12, /* Invalid parameter to function */ 73 HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 74 HAL_ESELFTEST = 14, /* Hardware self-test failed */ 75 HAL_EINPROGRESS = 15, /* Operation incomplete */ 76 HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */ 77 HAL_EEBADCC = 17, /* EEPROM invalid country code */ 78 HAL_INV_PMODE = 18, /* Couldn't bring out of sleep state */ 79 } HAL_STATUS; 80 81 typedef enum { 82 AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 83 AH_TRUE = 1, 84 } HAL_BOOL; 85 86 typedef enum { 87 HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 88 HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 89 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 90 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 91 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 92 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 93 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 94 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 95 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 96 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ 97 HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 98 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 99 HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 100 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 101 HAL_CAP_TXPOW = 15, /* global tx power limit */ 102 HAL_CAP_TPC = 16, /* per-packet tx power control */ 103 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 104 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 105 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 106 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 107 /* 21 was HAL_CAP_XR */ 108 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ 109 /* 23 was HAL_CAP_CHAN_HALFRATE */ 110 /* 24 was HAL_CAP_CHAN_QUARTERRATE */ 111 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 112 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 113 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 114 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 115 HAL_CAP_PCIE_PS = 29, 116 HAL_CAP_HT = 30, /* hardware can support HT */ 117 HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout */ 118 HAL_CAP_FAST_CC = 32, /* hardware supports fast channel change */ 119 HAL_CAP_TX_CHAINMASK = 33, /* mask of TX chains supported */ 120 HAL_CAP_RX_CHAINMASK = 34, /* mask of RX chains supported */ 121 HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */ 122 123 HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */ 124 HAL_CAP_RIFS_RX = 39, 125 HAL_CAP_RIFS_TX = 40, 126 HAL_CAP_FORCE_PPM = 41, 127 HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */ 128 HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */ 129 HAL_CAP_DFS_DMN = 44, /* current DFS domain */ 130 HAL_CAP_EXT_CHAN_DFS = 45, /* DFS support for extension channel */ 131 HAL_CAP_COMBINED_RADAR_RSSI = 46, /* Is combined RSSI for radar accurate */ 132 133 HAL_CAP_AUTO_SLEEP = 48, /* hardware can go to network sleep 134 automatically after waking up to receive TIM */ 135 HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation */ 136 HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors straddling a 4k page boundary */ 137 HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */ 138 HAL_CAP_BB_RIFS_HANG = 52, 139 HAL_CAP_RIFS_RX_ENABLED = 53, 140 HAL_CAP_BB_DFS_HANG = 54, 141 142 HAL_CAP_RX_STBC = 58, 143 HAL_CAP_TX_STBC = 59, 144 145 HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth coexistence */ 146 HAL_CAP_DYNAMIC_SMPS = 61, /* Dynamic MIMO Power Save hardware support */ 147 148 HAL_CAP_DS = 67, /* 2 stream */ 149 HAL_CAP_BB_RX_CLEAR_STUCK_HANG = 68, 150 HAL_CAP_MAC_HANG = 69, /* can MAC hang */ 151 HAL_CAP_MFP = 70, /* Management Frame Protection in hardware */ 152 153 HAL_CAP_TS = 72, /* 3 stream */ 154 155 HAL_CAP_ENHANCED_DMA_SUPPORT = 75, /* DMA FIFO support */ 156 HAL_CAP_NUM_TXMAPS = 76, /* Number of buffers in a transmit descriptor */ 157 HAL_CAP_TXDESCLEN = 77, /* Length of transmit descriptor */ 158 HAL_CAP_TXSTATUSLEN = 78, /* Length of transmit status descriptor */ 159 HAL_CAP_RXSTATUSLEN = 79, /* Length of transmit status descriptor */ 160 HAL_CAP_RXFIFODEPTH = 80, /* Receive hardware FIFO depth */ 161 HAL_CAP_RXBUFSIZE = 81, /* Receive Buffer Length */ 162 HAL_CAP_NUM_MR_RETRIES = 82, /* limit on multirate retries */ 163 HAL_CAP_OL_PWRCTRL = 84, /* Open loop TX power control */ 164 HAL_CAP_SPECTRAL_SCAN = 90, /* Hardware supports spectral scan */ 165 166 HAL_CAP_BB_PANIC_WATCHDOG = 92, 167 168 HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */ 169 170 HAL_CAP_LDPC = 99, 171 172 HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */ 173 174 HAL_CAP_ANT_DIV_COMB = 105, /* Enable antenna diversity/combining */ 175 HAL_CAP_PHYRESTART_CLR_WAR = 106, /* in some cases, clear phy restart to fix bb hang */ 176 HAL_CAP_ENTERPRISE_MODE = 107, /* Enterprise mode features */ 177 HAL_CAP_LDPCWAR = 108, 178 HAL_CAP_CHANNEL_SWITCH_TIME_USEC = 109, /* Channel change time, usec */ 179 HAL_CAP_ENABLE_APM = 110, /* APM enabled */ 180 HAL_CAP_PCIE_LCR_EXTSYNC_EN = 111, 181 HAL_CAP_PCIE_LCR_OFFSET = 112, 182 183 HAL_CAP_ENHANCED_DFS_SUPPORT = 117, /* hardware supports enhanced DFS */ 184 HAL_CAP_MCI = 118, 185 HAL_CAP_SMARTANTENNA = 119, 186 HAL_CAP_TRAFFIC_FAST_RECOVER = 120, 187 HAL_CAP_TX_DIVERSITY = 121, 188 HAL_CAP_CRDC = 122, 189 190 /* The following are private to the FreeBSD HAL (224 onward) */ 191 192 HAL_CAP_INTMIT = 229, /* interference mitigation */ 193 HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */ 194 HAL_CAP_BB_HANG = 235, /* can baseband hang */ 195 HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */ 196 HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */ 197 HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */ 198 HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX descriptor */ 199 HAL_CAP_BB_READ_WAR = 244, /* baseband read WAR */ 200 HAL_CAP_SERIALISE_WAR = 245, /* serialise register access on PCI */ 201 HAL_CAP_ENFORCE_TXOP = 246, /* Enforce TXOP if supported */ 202 HAL_CAP_RX_LNA_MIXING = 247, /* RX hardware uses LNA mixing */ 203 HAL_CAP_DO_MYBEACON = 248, /* Supports HAL_RX_FILTER_MYBEACON */ 204 HAL_CAP_TOA_LOCATIONING = 249, /* time of flight / arrival locationing */ 205 HAL_CAP_TXTSTAMP_PREC = 250, /* tx desc tstamp precision (bits) */ 206 } HAL_CAPABILITY_TYPE; 207 208 /* 209 * "States" for setting the LED. These correspond to 210 * the possible 802.11 operational states and there may 211 * be a many-to-one mapping between these states and the 212 * actual hardware state for the LED's (i.e. the hardware 213 * may have fewer states). 214 */ 215 typedef enum { 216 HAL_LED_INIT = 0, 217 HAL_LED_SCAN = 1, 218 HAL_LED_AUTH = 2, 219 HAL_LED_ASSOC = 3, 220 HAL_LED_RUN = 4 221 } HAL_LED_STATE; 222 223 /* 224 * Transmit queue types/numbers. These are used to tag 225 * each transmit queue in the hardware and to identify a set 226 * of transmit queues for operations such as start/stop dma. 227 */ 228 typedef enum { 229 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 230 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 231 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 232 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 233 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */ 234 HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */ 235 HAL_TX_QUEUE_CFEND = 6, 236 HAL_TX_QUEUE_PAPRD = 7, 237 } HAL_TX_QUEUE; 238 239 #define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ 240 241 /* 242 * Receive queue types. These are used to tag 243 * each transmit queue in the hardware and to identify a set 244 * of transmit queues for operations such as start/stop dma. 245 */ 246 typedef enum { 247 HAL_RX_QUEUE_HP = 0, /* high priority recv queue */ 248 HAL_RX_QUEUE_LP = 1, /* low priority recv queue */ 249 } HAL_RX_QUEUE; 250 251 #define HAL_NUM_RX_QUEUES 2 /* max possible # of queues */ 252 253 #define HAL_TXFIFO_DEPTH 8 /* transmit fifo depth */ 254 255 /* 256 * Transmit queue subtype. These map directly to 257 * WME Access Categories (except for UPSD). Refer 258 * to Table 5 of the WME spec. 259 */ 260 typedef enum { 261 HAL_WME_AC_BK = 0, /* background access category */ 262 HAL_WME_AC_BE = 1, /* best effort access category*/ 263 HAL_WME_AC_VI = 2, /* video access category */ 264 HAL_WME_AC_VO = 3, /* voice access category */ 265 HAL_WME_UPSD = 4, /* uplink power save */ 266 } HAL_TX_QUEUE_SUBTYPE; 267 268 /* 269 * Transmit queue flags that control various 270 * operational parameters. 271 */ 272 typedef enum { 273 /* 274 * Per queue interrupt enables. When set the associated 275 * interrupt may be delivered for packets sent through 276 * the queue. Without these enabled no interrupts will 277 * be delivered for transmits through the queue. 278 */ 279 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 280 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 281 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 282 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 283 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 284 /* 285 * Enable hardware compression for packets sent through 286 * the queue. The compression buffer must be setup and 287 * packets must have a key entry marked in the tx descriptor. 288 */ 289 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 290 /* 291 * Disable queue when veol is hit or ready time expires. 292 * By default the queue is disabled only on reaching the 293 * physical end of queue (i.e. a null link ptr in the 294 * descriptor chain). 295 */ 296 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 297 /* 298 * Schedule frames on delivery of a DBA (DMA Beacon Alert) 299 * event. Frames will be transmitted only when this timer 300 * fires, e.g to transmit a beacon in ap or adhoc modes. 301 */ 302 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 303 /* 304 * Each transmit queue has a counter that is incremented 305 * each time the queue is enabled and decremented when 306 * the list of frames to transmit is traversed (or when 307 * the ready time for the queue expires). This counter 308 * must be non-zero for frames to be scheduled for 309 * transmission. The following controls disable bumping 310 * this counter under certain conditions. Typically this 311 * is used to gate frames based on the contents of another 312 * queue (e.g. CAB traffic may only follow a beacon frame). 313 * These are meaningful only when frames are scheduled 314 * with a non-ASAP policy (e.g. DBA-gated). 315 */ 316 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 317 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 318 319 /* 320 * Fragment burst backoff policy. Normally the no backoff 321 * is done after a successful transmission, the next fragment 322 * is sent at SIFS. If this flag is set backoff is done 323 * after each fragment, regardless whether it was ack'd or 324 * not, after the backoff count reaches zero a normal channel 325 * access procedure is done before the next transmit (i.e. 326 * wait AIFS instead of SIFS). 327 */ 328 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 329 /* 330 * Disable post-tx backoff following each frame. 331 */ 332 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 333 /* 334 * DCU arbiter lockout control. This controls how 335 * lower priority tx queues are handled with respect to 336 * to a specific queue when multiple queues have frames 337 * to send. No lockout means lower priority queues arbitrate 338 * concurrently with this queue. Intra-frame lockout 339 * means lower priority queues are locked out until the 340 * current frame transmits (e.g. including backoffs and bursting). 341 * Global lockout means nothing lower can arbitrary so 342 * long as there is traffic activity on this queue (frames, 343 * backoff, etc). 344 */ 345 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 346 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 347 348 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 349 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */ 350 } HAL_TX_QUEUE_FLAGS; 351 352 typedef struct { 353 uint32_t tqi_ver; /* hal TXQ version */ 354 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 355 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 356 uint32_t tqi_priority; /* (not used) */ 357 uint32_t tqi_aifs; /* aifs */ 358 uint32_t tqi_cwmin; /* cwMin */ 359 uint32_t tqi_cwmax; /* cwMax */ 360 uint16_t tqi_shretry; /* rts retry limit */ 361 uint16_t tqi_lgretry; /* long retry limit (not used)*/ 362 uint32_t tqi_cbrPeriod; /* CBR period (us) */ 363 uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */ 364 uint32_t tqi_burstTime; /* max burst duration (us) */ 365 uint32_t tqi_readyTime; /* frame schedule time (us) */ 366 uint32_t tqi_compBuf; /* comp buffer phys addr */ 367 } HAL_TXQ_INFO; 368 369 #define HAL_TQI_NONVAL 0xffff 370 371 /* token to use for aifs, cwmin, cwmax */ 372 #define HAL_TXQ_USEDEFAULT ((uint32_t) -1) 373 374 /* compression definitions */ 375 #define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ 376 #define HAL_COMP_BUF_ALIGN_SIZE 512 377 378 /* 379 * Transmit packet types. This belongs in ah_desc.h, but 380 * is here so we can give a proper type to various parameters 381 * (and not require everyone include the file). 382 * 383 * NB: These values are intentionally assigned for 384 * direct use when setting up h/w descriptors. 385 */ 386 typedef enum { 387 HAL_PKT_TYPE_NORMAL = 0, 388 HAL_PKT_TYPE_ATIM = 1, 389 HAL_PKT_TYPE_PSPOLL = 2, 390 HAL_PKT_TYPE_BEACON = 3, 391 HAL_PKT_TYPE_PROBE_RESP = 4, 392 HAL_PKT_TYPE_CHIRP = 5, 393 HAL_PKT_TYPE_GRP_POLL = 6, 394 HAL_PKT_TYPE_AMPDU = 7, 395 } HAL_PKT_TYPE; 396 397 /* Rx Filter Frame Types */ 398 typedef enum { 399 /* 400 * These bits correspond to AR_RX_FILTER for all chips. 401 * Not all bits are supported by all chips. 402 */ 403 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 404 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 405 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 406 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 407 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 408 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 409 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 410 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 411 HAL_RX_FILTER_MYBEACON = 0x00000200, /* Filter beacons other than mine */ 412 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */ 413 HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */ 414 HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */ 415 HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PS-POLL frames */ 416 HAL_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, 417 /* Allow all mcast/bcast frames */ 418 419 /* 420 * Magic RX filter flags that aren't targeting hardware bits 421 * but instead the HAL sets individual bits - eg PHYERR will result 422 * in OFDM/CCK timing error frames being received. 423 */ 424 HAL_RX_FILTER_BSSID = 0x40000000, /* Disable BSSID match */ 425 } HAL_RX_FILTER; 426 427 typedef enum { 428 HAL_PM_AWAKE = 0, 429 HAL_PM_FULL_SLEEP = 1, 430 HAL_PM_NETWORK_SLEEP = 2, 431 HAL_PM_UNDEFINED = 3 432 } HAL_POWER_MODE; 433 434 /* 435 * Enterprise mode flags 436 */ 437 #define AH_ENT_DUAL_BAND_DISABLE 0x00000001 438 #define AH_ENT_CHAIN2_DISABLE 0x00000002 439 #define AH_ENT_5MHZ_DISABLE 0x00000004 440 #define AH_ENT_10MHZ_DISABLE 0x00000008 441 #define AH_ENT_49GHZ_DISABLE 0x00000010 442 #define AH_ENT_LOOPBACK_DISABLE 0x00000020 443 #define AH_ENT_TPC_PERF_DISABLE 0x00000040 444 #define AH_ENT_MIN_PKT_SIZE_DISABLE 0x00000080 445 #define AH_ENT_SPECTRAL_PRECISION 0x00000300 446 #define AH_ENT_SPECTRAL_PRECISION_S 8 447 #define AH_ENT_RTSCTS_DELIM_WAR 0x00010000 448 449 #define AH_FIRST_DESC_NDELIMS 60 450 451 /* 452 * NOTE WELL: 453 * These are mapped to take advantage of the common locations for many of 454 * the bits on all of the currently supported MAC chips. This is to make 455 * the ISR as efficient as possible, while still abstracting HW differences. 456 * When new hardware breaks this commonality this enumerated type, as well 457 * as the HAL functions using it, must be modified. All values are directly 458 * mapped unless commented otherwise. 459 */ 460 typedef enum { 461 HAL_INT_RX = 0x00000001, /* Non-common mapping */ 462 HAL_INT_RXDESC = 0x00000002, /* Legacy mapping */ 463 HAL_INT_RXERR = 0x00000004, 464 HAL_INT_RXHP = 0x00000001, /* EDMA */ 465 HAL_INT_RXLP = 0x00000002, /* EDMA */ 466 HAL_INT_RXNOFRM = 0x00000008, 467 HAL_INT_RXEOL = 0x00000010, 468 HAL_INT_RXORN = 0x00000020, 469 HAL_INT_TX = 0x00000040, /* Non-common mapping */ 470 HAL_INT_TXDESC = 0x00000080, 471 HAL_INT_TIM_TIMER= 0x00000100, 472 HAL_INT_MCI = 0x00000200, 473 HAL_INT_BBPANIC = 0x00000400, 474 HAL_INT_TXURN = 0x00000800, 475 HAL_INT_MIB = 0x00001000, 476 HAL_INT_RXPHY = 0x00004000, 477 HAL_INT_RXKCM = 0x00008000, 478 HAL_INT_SWBA = 0x00010000, 479 HAL_INT_BRSSI = 0x00020000, 480 HAL_INT_BMISS = 0x00040000, 481 HAL_INT_BNR = 0x00100000, 482 HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 483 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 484 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ 485 HAL_INT_GPIO = 0x01000000, 486 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 487 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */ 488 HAL_INT_TBTT = 0x08000000, /* Non-common mapping */ 489 /* Atheros ref driver has a generic timer interrupt now..*/ 490 HAL_INT_GENTIMER = 0x08000000, /* Non-common mapping */ 491 HAL_INT_CST = 0x10000000, /* Non-common mapping */ 492 HAL_INT_GTT = 0x20000000, /* Non-common mapping */ 493 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 494 #define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ 495 HAL_INT_BMISC = HAL_INT_TIM 496 | HAL_INT_DTIM 497 | HAL_INT_DTIMSYNC 498 | HAL_INT_CABEND 499 | HAL_INT_TBTT, 500 501 /* Interrupt bits that map directly to ISR/IMR bits */ 502 HAL_INT_COMMON = HAL_INT_RXNOFRM 503 | HAL_INT_RXDESC 504 | HAL_INT_RXEOL 505 | HAL_INT_RXORN 506 | HAL_INT_TXDESC 507 | HAL_INT_TXURN 508 | HAL_INT_MIB 509 | HAL_INT_RXPHY 510 | HAL_INT_RXKCM 511 | HAL_INT_SWBA 512 | HAL_INT_BMISS 513 | HAL_INT_BRSSI 514 | HAL_INT_BNR 515 | HAL_INT_GPIO, 516 } HAL_INT; 517 518 /* 519 * MSI vector assignments 520 */ 521 typedef enum { 522 HAL_MSIVEC_MISC = 0, 523 HAL_MSIVEC_TX = 1, 524 HAL_MSIVEC_RXLP = 2, 525 HAL_MSIVEC_RXHP = 3, 526 } HAL_MSIVEC; 527 528 typedef enum { 529 HAL_INT_LINE = 0, 530 HAL_INT_MSI = 1, 531 } HAL_INT_TYPE; 532 533 /* For interrupt mitigation registers */ 534 typedef enum { 535 HAL_INT_RX_FIRSTPKT=0, 536 HAL_INT_RX_LASTPKT, 537 HAL_INT_TX_FIRSTPKT, 538 HAL_INT_TX_LASTPKT, 539 HAL_INT_THRESHOLD 540 } HAL_INT_MITIGATION; 541 542 /* XXX this is duplicate information! */ 543 typedef struct { 544 u_int32_t cyclecnt_diff; /* delta cycle count */ 545 u_int32_t rxclr_cnt; /* rx clear count */ 546 u_int32_t extrxclr_cnt; /* ext chan rx clear count */ 547 u_int32_t txframecnt_diff; /* delta tx frame count */ 548 u_int32_t rxframecnt_diff; /* delta rx frame count */ 549 u_int32_t listen_time; /* listen time in msec - time for which ch is free */ 550 u_int32_t ofdmphyerr_cnt; /* OFDM err count since last reset */ 551 u_int32_t cckphyerr_cnt; /* CCK err count since last reset */ 552 u_int32_t ofdmphyerrcnt_diff; /* delta OFDM Phy Error Count */ 553 HAL_BOOL valid; /* if the stats are valid*/ 554 } HAL_ANISTATS; 555 556 typedef struct { 557 u_int8_t txctl_offset; 558 u_int8_t txctl_numwords; 559 u_int8_t txstatus_offset; 560 u_int8_t txstatus_numwords; 561 562 u_int8_t rxctl_offset; 563 u_int8_t rxctl_numwords; 564 u_int8_t rxstatus_offset; 565 u_int8_t rxstatus_numwords; 566 567 u_int8_t macRevision; 568 } HAL_DESC_INFO; 569 570 typedef enum { 571 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT = 0, 572 HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED = 1, 573 HAL_GPIO_OUTPUT_MUX_PCIE_POWER_LED = 2, 574 HAL_GPIO_OUTPUT_MUX_MAC_NETWORK_LED = 3, 575 HAL_GPIO_OUTPUT_MUX_MAC_POWER_LED = 4, 576 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE = 5, 577 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME = 6, 578 579 HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA, 580 HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK, 581 HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA, 582 HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK, 583 HAL_GPIO_OUTPUT_MUX_AS_WL_IN_TX, 584 HAL_GPIO_OUTPUT_MUX_AS_WL_IN_RX, 585 HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX, 586 HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX, 587 HAL_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE, 588 HAL_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA, 589 HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0, 590 HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1, 591 HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2, 592 HAL_GPIO_OUTPUT_MUX_NUM_ENTRIES 593 } HAL_GPIO_MUX_TYPE; 594 595 typedef enum { 596 HAL_GPIO_INTR_LOW = 0, 597 HAL_GPIO_INTR_HIGH = 1, 598 HAL_GPIO_INTR_DISABLE = 2 599 } HAL_GPIO_INTR_TYPE; 600 601 typedef struct halCounters { 602 u_int32_t tx_frame_count; 603 u_int32_t rx_frame_count; 604 u_int32_t rx_clear_count; 605 u_int32_t cycle_count; 606 u_int8_t is_rx_active; // true (1) or false (0) 607 u_int8_t is_tx_active; // true (1) or false (0) 608 } HAL_COUNTERS; 609 610 typedef enum { 611 HAL_RFGAIN_INACTIVE = 0, 612 HAL_RFGAIN_READ_REQUESTED = 1, 613 HAL_RFGAIN_NEED_CHANGE = 2 614 } HAL_RFGAIN; 615 616 typedef uint16_t HAL_CTRY_CODE; /* country code */ 617 typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 618 619 #define HAL_ANTENNA_MIN_MODE 0 620 #define HAL_ANTENNA_FIXED_A 1 621 #define HAL_ANTENNA_FIXED_B 2 622 #define HAL_ANTENNA_MAX_MODE 3 623 624 typedef struct { 625 uint32_t ackrcv_bad; 626 uint32_t rts_bad; 627 uint32_t rts_good; 628 uint32_t fcs_bad; 629 uint32_t beacons; 630 } HAL_MIB_STATS; 631 632 /* 633 * These bits represent what's in ah_currentRDext. 634 */ 635 typedef enum { 636 REG_EXT_FCC_MIDBAND = 0, 637 REG_EXT_JAPAN_MIDBAND = 1, 638 REG_EXT_FCC_DFS_HT40 = 2, 639 REG_EXT_JAPAN_NONDFS_HT40 = 3, 640 REG_EXT_JAPAN_DFS_HT40 = 4, 641 REG_EXT_FCC_CH_144 = 5, 642 } REG_EXT_BITMAP; 643 644 enum { 645 HAL_MODE_11A = 0x001, /* 11a channels */ 646 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 647 HAL_MODE_11B = 0x004, /* 11b channels */ 648 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 649 #ifdef notdef 650 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ 651 #else 652 HAL_MODE_11G = 0x008, /* XXX historical */ 653 #endif 654 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 655 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 656 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */ 657 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */ 658 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */ 659 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */ 660 HAL_MODE_11NG_HT20 = 0x008000, 661 HAL_MODE_11NA_HT20 = 0x010000, 662 HAL_MODE_11NG_HT40PLUS = 0x020000, 663 HAL_MODE_11NG_HT40MINUS = 0x040000, 664 HAL_MODE_11NA_HT40PLUS = 0x080000, 665 HAL_MODE_11NA_HT40MINUS = 0x100000, 666 HAL_MODE_ALL = 0xffffff 667 }; 668 669 typedef struct { 670 int rateCount; /* NB: for proper padding */ 671 uint8_t rateCodeToIndex[256]; /* back mapping */ 672 struct { 673 uint8_t valid; /* valid for rate control use */ 674 uint8_t phy; /* CCK/OFDM/XR */ 675 uint32_t rateKbps; /* transfer rate in kbs */ 676 uint8_t rateCode; /* rate for h/w descriptors */ 677 uint8_t shortPreamble; /* mask for enabling short 678 * preamble in CCK rate code */ 679 uint8_t dot11Rate; /* value for supported rates 680 * info element of MLME */ 681 uint8_t controlRate; /* index of next lower basic 682 * rate; used for dur. calcs */ 683 uint16_t lpAckDuration; /* long preamble ACK duration */ 684 uint16_t spAckDuration; /* short preamble ACK duration*/ 685 } info[64]; 686 } HAL_RATE_TABLE; 687 688 typedef struct { 689 u_int rs_count; /* number of valid entries */ 690 uint8_t rs_rates[64]; /* rates */ 691 } HAL_RATE_SET; 692 693 /* 694 * 802.11n specific structures and enums 695 */ 696 typedef enum { 697 HAL_CHAINTYPE_TX = 1, /* Tx chain type */ 698 HAL_CHAINTYPE_RX = 2, /* RX chain type */ 699 } HAL_CHAIN_TYPE; 700 701 typedef struct { 702 u_int Tries; 703 u_int Rate; /* hardware rate code */ 704 u_int RateIndex; /* rate series table index */ 705 u_int PktDuration; 706 u_int ChSel; 707 u_int RateFlags; 708 #define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ 709 #define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ 710 #define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ 711 #define HAL_RATESERIES_STBC 0x0008 /* use STBC for series */ 712 u_int tx_power_cap; /* in 1/2 dBm units XXX TODO */ 713 } HAL_11N_RATE_SERIES; 714 715 typedef enum { 716 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ 717 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ 718 } HAL_HT_MACMODE; 719 720 typedef enum { 721 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ 722 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ 723 } HAL_HT_PHYMODE; 724 725 typedef enum { 726 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ 727 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ 728 } HAL_HT_EXTPROTSPACING; 729 730 731 typedef enum { 732 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ 733 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ 734 } HAL_HT_RXCLEAR; 735 736 typedef enum { 737 HAL_FREQ_BAND_5GHZ = 0, 738 HAL_FREQ_BAND_2GHZ = 1, 739 } HAL_FREQ_BAND; 740 741 /* 742 * Antenna switch control. By default antenna selection 743 * enables multiple (2) antenna use. To force use of the 744 * A or B antenna only specify a fixed setting. Fixing 745 * the antenna will also disable any diversity support. 746 */ 747 typedef enum { 748 HAL_ANT_VARIABLE = 0, /* variable by programming */ 749 HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 750 HAL_ANT_FIXED_B = 2, /* fixed antenna B */ 751 } HAL_ANT_SETTING; 752 753 typedef enum { 754 HAL_M_STA = 1, /* infrastructure station */ 755 HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 756 HAL_M_HOSTAP = 6, /* Software Access Point */ 757 HAL_M_MONITOR = 8 /* Monitor mode */ 758 } HAL_OPMODE; 759 760 typedef enum { 761 HAL_RESET_NORMAL = 0, /* Do normal reset */ 762 HAL_RESET_BBPANIC = 1, /* Reset because of BB panic */ 763 HAL_RESET_FORCE_COLD = 2, /* Force full reset */ 764 } HAL_RESET_TYPE; 765 766 enum { 767 HAL_RESET_POWER_ON, 768 HAL_RESET_WARM, 769 HAL_RESET_COLD 770 }; 771 772 typedef struct { 773 uint8_t kv_type; /* one of HAL_CIPHER */ 774 uint8_t kv_apsd; /* Mask for APSD enabled ACs */ 775 uint16_t kv_len; /* length in bits */ 776 uint8_t kv_val[16]; /* enough for 128-bit keys */ 777 uint8_t kv_mic[8]; /* TKIP MIC key */ 778 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ 779 } HAL_KEYVAL; 780 781 /* 782 * This is the TX descriptor field which marks the key padding requirement. 783 * The naming is unfortunately unclear. 784 */ 785 #define AH_KEYTYPE_MASK 0x0F 786 typedef enum { 787 HAL_KEY_TYPE_CLEAR, 788 HAL_KEY_TYPE_WEP, 789 HAL_KEY_TYPE_AES, 790 HAL_KEY_TYPE_TKIP, 791 } HAL_KEY_TYPE; 792 793 typedef enum { 794 HAL_CIPHER_WEP = 0, 795 HAL_CIPHER_AES_OCB = 1, 796 HAL_CIPHER_AES_CCM = 2, 797 HAL_CIPHER_CKIP = 3, 798 HAL_CIPHER_TKIP = 4, 799 HAL_CIPHER_CLR = 5, /* no encryption */ 800 801 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 802 } HAL_CIPHER; 803 804 enum { 805 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 806 HAL_SLOT_TIME_9 = 9, 807 HAL_SLOT_TIME_20 = 20, 808 }; 809 810 /* 811 * Per-station beacon timer state. Note that the specified 812 * beacon interval (given in TU's) can also include flags 813 * to force a TSF reset and to enable the beacon xmit logic. 814 * If bs_cfpmaxduration is non-zero the hardware is setup to 815 * coexist with a PCF-capable AP. 816 */ 817 typedef struct { 818 uint32_t bs_nexttbtt; /* next beacon in TU */ 819 uint32_t bs_nextdtim; /* next DTIM in TU */ 820 uint32_t bs_intval; /* beacon interval+flags */ 821 /* 822 * HAL_BEACON_PERIOD, HAL_BEACON_ENA and HAL_BEACON_RESET_TSF 823 * are all 1:1 correspondances with the pre-11n chip AR_BEACON 824 * register. 825 */ 826 #define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 827 #define HAL_BEACON_PERIOD_TU8 0x0007ffff /* beacon interval, tu/8 */ 828 #define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 829 #define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 830 #define HAL_TSFOOR_THRESHOLD 0x00004240 /* TSF OOR thresh (16k uS) */ 831 uint32_t bs_dtimperiod; 832 uint16_t bs_cfpperiod; /* CFP period in TU */ 833 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 834 uint32_t bs_cfpnext; /* next CFP in TU */ 835 uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 836 uint16_t bs_bmissthreshold; /* beacon miss threshold */ 837 uint32_t bs_sleepduration; /* max sleep duration */ 838 uint32_t bs_tsfoor_threshold; /* TSF out of range threshold */ 839 } HAL_BEACON_STATE; 840 841 /* 842 * Like HAL_BEACON_STATE but for non-station mode setup. 843 * NB: see above flag definitions for bt_intval. 844 */ 845 typedef struct { 846 uint32_t bt_intval; /* beacon interval+flags */ 847 uint32_t bt_nexttbtt; /* next beacon in TU */ 848 uint32_t bt_nextatim; /* next ATIM in TU */ 849 uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 850 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 851 uint32_t bt_flags; /* timer enables */ 852 #define HAL_BEACON_TBTT_EN 0x00000001 853 #define HAL_BEACON_DBA_EN 0x00000002 854 #define HAL_BEACON_SWBA_EN 0x00000004 855 } HAL_BEACON_TIMERS; 856 857 /* 858 * Per-node statistics maintained by the driver for use in 859 * optimizing signal quality and other operational aspects. 860 */ 861 typedef struct { 862 uint32_t ns_avgbrssi; /* average beacon rssi */ 863 uint32_t ns_avgrssi; /* average data rssi */ 864 uint32_t ns_avgtxrssi; /* average tx rssi */ 865 } HAL_NODE_STATS; 866 867 #define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 868 869 /* 870 * This is the ANI state and MIB stats. 871 * 872 * It's used by the HAL modules to keep state /and/ by the debug ioctl 873 * to fetch ANI information. 874 */ 875 typedef struct { 876 uint32_t ast_ani_niup; /* ANI increased noise immunity */ 877 uint32_t ast_ani_nidown; /* ANI decreased noise immunity */ 878 uint32_t ast_ani_spurup; /* ANI increased spur immunity */ 879 uint32_t ast_ani_spurdown;/* ANI descreased spur immunity */ 880 uint32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */ 881 uint32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */ 882 uint32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */ 883 uint32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */ 884 uint32_t ast_ani_stepup; /* ANI increased first step level */ 885 uint32_t ast_ani_stepdown;/* ANI decreased first step level */ 886 uint32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */ 887 uint32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */ 888 uint32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */ 889 uint32_t ast_ani_lzero; /* ANI listen time forced to zero */ 890 uint32_t ast_ani_lneg; /* ANI listen time calculated < 0 */ 891 HAL_MIB_STATS ast_mibstats; /* MIB counter stats */ 892 HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */ 893 } HAL_ANI_STATS; 894 895 typedef struct { 896 uint8_t noiseImmunityLevel; /* Global for pre-AR9380; OFDM later*/ 897 uint8_t cckNoiseImmunityLevel; /* AR9380: CCK specific NI */ 898 uint8_t spurImmunityLevel; 899 uint8_t firstepLevel; 900 uint8_t ofdmWeakSigDetectOff; 901 uint8_t cckWeakSigThreshold; 902 uint8_t mrcCck; /* MRC CCK is enabled */ 903 uint32_t listenTime; 904 905 /* NB: intentionally ordered so data exported to user space is first */ 906 uint32_t txFrameCount; /* Last txFrameCount */ 907 uint32_t rxFrameCount; /* Last rx Frame count */ 908 uint32_t cycleCount; /* Last cycleCount 909 (to detect wrap-around) */ 910 uint32_t ofdmPhyErrCount;/* OFDM err count since last reset */ 911 uint32_t cckPhyErrCount; /* CCK err count since last reset */ 912 } HAL_ANI_STATE; 913 914 struct ath_desc; 915 struct ath_tx_status; 916 struct ath_rx_status; 917 struct ieee80211_channel; 918 919 /* 920 * This is a channel survey sample entry. 921 * 922 * The AR5212 ANI routines fill these samples. The ANI code then uses it 923 * when calculating listen time; it is also exported via a diagnostic 924 * API. 925 */ 926 typedef struct { 927 uint32_t seq_num; 928 uint32_t tx_busy; 929 uint32_t rx_busy; 930 uint32_t chan_busy; 931 uint32_t ext_chan_busy; 932 uint32_t cycle_count; 933 /* XXX TODO */ 934 uint32_t ofdm_phyerr_count; 935 uint32_t cck_phyerr_count; 936 } HAL_SURVEY_SAMPLE; 937 938 /* 939 * This provides 3.2 seconds of sample space given an 940 * ANI time of 1/10th of a second. This may not be enough! 941 */ 942 #define CHANNEL_SURVEY_SAMPLE_COUNT 32 943 944 typedef struct { 945 HAL_SURVEY_SAMPLE samples[CHANNEL_SURVEY_SAMPLE_COUNT]; 946 uint32_t cur_sample; /* current sample in sequence */ 947 uint32_t cur_seq; /* current sequence number */ 948 } HAL_CHANNEL_SURVEY; 949 950 /* 951 * ANI commands. 952 * 953 * These are used both internally and externally via the diagnostic 954 * API. 955 * 956 * Note that this is NOT the ANI commands being used via the INTMIT 957 * capability - that has a different mapping for some reason. 958 */ 959 typedef enum { 960 HAL_ANI_PRESENT = 0, /* is ANI support present */ 961 HAL_ANI_NOISE_IMMUNITY_LEVEL = 1, /* set level (global or ofdm) */ 962 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 2, /* enable/disable */ 963 HAL_ANI_CCK_WEAK_SIGNAL_THR = 3, /* enable/disable */ 964 HAL_ANI_FIRSTEP_LEVEL = 4, /* set level */ 965 HAL_ANI_SPUR_IMMUNITY_LEVEL = 5, /* set level */ 966 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 967 HAL_ANI_PHYERR_RESET = 7, /* reset phy error stats */ 968 HAL_ANI_MRC_CCK = 8, 969 HAL_ANI_CCK_NOISE_IMMUNITY_LEVEL = 9, /* set level (cck) */ 970 } HAL_ANI_CMD; 971 972 #define HAL_ANI_ALL 0xffffffff 973 974 /* 975 * This is the layout of the ANI INTMIT capability. 976 * 977 * Notice that the command values differ to HAL_ANI_CMD. 978 */ 979 typedef enum { 980 HAL_CAP_INTMIT_PRESENT = 0, 981 HAL_CAP_INTMIT_ENABLE = 1, 982 HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL = 2, 983 HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL = 3, 984 HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR = 4, 985 HAL_CAP_INTMIT_FIRSTEP_LEVEL = 5, 986 HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6 987 } HAL_CAP_INTMIT_CMD; 988 989 typedef struct { 990 int32_t pe_firpwr; /* FIR pwr out threshold */ 991 int32_t pe_rrssi; /* Radar rssi thresh */ 992 int32_t pe_height; /* Pulse height thresh */ 993 int32_t pe_prssi; /* Pulse rssi thresh */ 994 int32_t pe_inband; /* Inband thresh */ 995 996 /* The following params are only for AR5413 and later */ 997 u_int32_t pe_relpwr; /* Relative power threshold in 0.5dB steps */ 998 u_int32_t pe_relstep; /* Pulse Relative step threshold in 0.5dB steps */ 999 u_int32_t pe_maxlen; /* Max length of radar sign in 0.8us units */ 1000 int32_t pe_usefir128; /* Use the average in-band power measured over 128 cycles */ 1001 int32_t pe_blockradar; /* 1002 * Enable to block radar check if pkt detect is done via OFDM 1003 * weak signal detect or pkt is detected immediately after tx 1004 * to rx transition 1005 */ 1006 int32_t pe_enmaxrssi; /* 1007 * Enable to use the max rssi instead of the last rssi during 1008 * fine gain changes for radar detection 1009 */ 1010 int32_t pe_extchannel; /* Enable DFS on ext channel */ 1011 int32_t pe_enabled; /* Whether radar detection is enabled */ 1012 int32_t pe_enrelpwr; 1013 int32_t pe_en_relstep_check; 1014 } HAL_PHYERR_PARAM; 1015 1016 #define HAL_PHYERR_PARAM_NOVAL 65535 1017 1018 typedef struct { 1019 u_int16_t ss_fft_period; /* Skip interval for FFT reports */ 1020 u_int16_t ss_period; /* Spectral scan period */ 1021 u_int16_t ss_count; /* # of reports to return from ss_active */ 1022 u_int16_t ss_short_report;/* Set to report ony 1 set of FFT results */ 1023 u_int8_t radar_bin_thresh_sel; /* strong signal radar FFT threshold configuration */ 1024 u_int16_t ss_spectral_pri; /* are we doing a noise power cal ? */ 1025 int8_t ss_nf_cal[AH_MAX_CHAINS*2]; /* nf calibrated values for ctl+ext from eeprom */ 1026 int8_t ss_nf_pwr[AH_MAX_CHAINS*2]; /* nf pwr values for ctl+ext from eeprom */ 1027 int32_t ss_nf_temp_data; /* temperature data taken during nf scan */ 1028 int ss_enabled; 1029 int ss_active; 1030 } HAL_SPECTRAL_PARAM; 1031 #define HAL_SPECTRAL_PARAM_NOVAL 0xFFFF 1032 #define HAL_SPECTRAL_PARAM_ENABLE 0x8000 /* Enable/Disable if applicable */ 1033 1034 /* 1035 * DFS operating mode flags. 1036 */ 1037 typedef enum { 1038 HAL_DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */ 1039 HAL_DFS_FCC_DOMAIN = 1, /* FCC3 dfs domain */ 1040 HAL_DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */ 1041 HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */ 1042 } HAL_DFS_DOMAIN; 1043 1044 1045 /* 1046 * MFP decryption options for initializing the MAC. 1047 */ 1048 typedef enum { 1049 HAL_MFP_QOSDATA = 0, /* Decrypt MFP frames like QoS data frames. All chips before Merlin. */ 1050 HAL_MFP_PASSTHRU, /* Don't decrypt MFP frames at all. Passthrough */ 1051 HAL_MFP_HW_CRYPTO /* hardware decryption enabled. Merlin can do it. */ 1052 } HAL_MFP_OPT_T; 1053 1054 /* LNA config supported */ 1055 typedef enum { 1056 HAL_ANT_DIV_COMB_LNA1_MINUS_LNA2 = 0, 1057 HAL_ANT_DIV_COMB_LNA2 = 1, 1058 HAL_ANT_DIV_COMB_LNA1 = 2, 1059 HAL_ANT_DIV_COMB_LNA1_PLUS_LNA2 = 3, 1060 } HAL_ANT_DIV_COMB_LNA_CONF; 1061 1062 typedef struct { 1063 u_int8_t main_lna_conf; 1064 u_int8_t alt_lna_conf; 1065 u_int8_t fast_div_bias; 1066 u_int8_t main_gaintb; 1067 u_int8_t alt_gaintb; 1068 u_int8_t antdiv_configgroup; 1069 int8_t lna1_lna2_delta; 1070 } HAL_ANT_COMB_CONFIG; 1071 1072 #define DEFAULT_ANTDIV_CONFIG_GROUP 0x00 1073 #define HAL_ANTDIV_CONFIG_GROUP_1 0x01 1074 #define HAL_ANTDIV_CONFIG_GROUP_2 0x02 1075 #define HAL_ANTDIV_CONFIG_GROUP_3 0x03 1076 1077 /* 1078 * Flag for setting QUIET period 1079 */ 1080 typedef enum { 1081 HAL_QUIET_DISABLE = 0x0, 1082 HAL_QUIET_ENABLE = 0x1, 1083 HAL_QUIET_ADD_CURRENT_TSF = 0x2, /* add current TSF to next_start offset */ 1084 HAL_QUIET_ADD_SWBA_RESP_TIME = 0x4, /* add beacon response time to next_start offset */ 1085 } HAL_QUIET_FLAG; 1086 1087 #define HAL_DFS_EVENT_PRICH 0x0000001 1088 #define HAL_DFS_EVENT_EXTCH 0x0000002 1089 #define HAL_DFS_EVENT_EXTEARLY 0x0000004 1090 #define HAL_DFS_EVENT_ISDC 0x0000008 1091 1092 struct hal_dfs_event { 1093 uint64_t re_full_ts; /* 64-bit full timestamp from interrupt time */ 1094 uint32_t re_ts; /* Original 15 bit recv timestamp */ 1095 uint8_t re_rssi; /* rssi of radar event */ 1096 uint8_t re_dur; /* duration of radar pulse */ 1097 uint32_t re_flags; /* Flags (see above) */ 1098 }; 1099 typedef struct hal_dfs_event HAL_DFS_EVENT; 1100 1101 /* 1102 * Generic Timer domain 1103 */ 1104 typedef enum { 1105 HAL_GEN_TIMER_TSF = 0, 1106 HAL_GEN_TIMER_TSF2, 1107 HAL_GEN_TIMER_TSF_ANY 1108 } HAL_GEN_TIMER_DOMAIN; 1109 1110 /* 1111 * BT Co-existence definitions 1112 */ 1113 #include "ath_hal/ah_btcoex.h" 1114 1115 struct hal_bb_panic_info { 1116 u_int32_t status; 1117 u_int32_t tsf; 1118 u_int32_t phy_panic_wd_ctl1; 1119 u_int32_t phy_panic_wd_ctl2; 1120 u_int32_t phy_gen_ctrl; 1121 u_int32_t rxc_pcnt; 1122 u_int32_t rxf_pcnt; 1123 u_int32_t txf_pcnt; 1124 u_int32_t cycles; 1125 u_int32_t wd; 1126 u_int32_t det; 1127 u_int32_t rdar; 1128 u_int32_t r_odfm; 1129 u_int32_t r_cck; 1130 u_int32_t t_odfm; 1131 u_int32_t t_cck; 1132 u_int32_t agc; 1133 u_int32_t src; 1134 }; 1135 1136 /* Serialize Register Access Mode */ 1137 typedef enum { 1138 SER_REG_MODE_OFF = 0, 1139 SER_REG_MODE_ON = 1, 1140 SER_REG_MODE_AUTO = 2, 1141 } SER_REG_MODE; 1142 1143 typedef struct 1144 { 1145 int ah_debug; /* only used if AH_DEBUG is defined */ 1146 int ah_ar5416_biasadj; /* enable AR2133 radio specific bias fiddling */ 1147 1148 /* NB: these are deprecated; they exist for now for compatibility */ 1149 int ah_dma_beacon_response_time;/* in TU's */ 1150 int ah_sw_beacon_response_time; /* in TU's */ 1151 int ah_additional_swba_backoff; /* in TU's */ 1152 int ah_force_full_reset; /* force full chip reset rather then warm reset */ 1153 int ah_serialise_reg_war; /* force serialisation of register IO */ 1154 1155 /* XXX these don't belong here, they're just for the ar9300 HAL port effort */ 1156 int ath_hal_desc_tpc; /* Per-packet TPC */ 1157 int ath_hal_sta_update_tx_pwr_enable; /* GreenTX */ 1158 int ath_hal_sta_update_tx_pwr_enable_S1; /* GreenTX */ 1159 int ath_hal_sta_update_tx_pwr_enable_S2; /* GreenTX */ 1160 int ath_hal_sta_update_tx_pwr_enable_S3; /* GreenTX */ 1161 1162 /* I'm not sure what the default values for these should be */ 1163 int ath_hal_pll_pwr_save; 1164 int ath_hal_pcie_power_save_enable; 1165 int ath_hal_intr_mitigation_rx; 1166 int ath_hal_intr_mitigation_tx; 1167 1168 int ath_hal_pcie_clock_req; 1169 #define AR_PCIE_PLL_PWRSAVE_CONTROL (1<<0) 1170 #define AR_PCIE_PLL_PWRSAVE_ON_D3 (1<<1) 1171 #define AR_PCIE_PLL_PWRSAVE_ON_D0 (1<<2) 1172 1173 int ath_hal_pcie_waen; 1174 int ath_hal_pcie_ser_des_write; 1175 1176 /* these are important for correct AR9300 behaviour */ 1177 int ath_hal_ht_enable; /* needs to be enabled for AR9300 HT */ 1178 int ath_hal_diversity_control; 1179 int ath_hal_antenna_switch_swap; 1180 int ath_hal_ext_lna_ctl_gpio; 1181 int ath_hal_spur_mode; 1182 int ath_hal_6mb_ack; /* should set this to 1 for 11a/11na? */ 1183 int ath_hal_enable_msi; /* enable MSI interrupts (needed?) */ 1184 int ath_hal_beacon_filter_interval; /* ok to be 0 for now? */ 1185 1186 /* For now, set this to 0 - net80211 needs to know about hardware MFP support */ 1187 int ath_hal_mfp_support; 1188 1189 int ath_hal_enable_ani; /* should set this.. */ 1190 int ath_hal_cwm_ignore_ext_cca; 1191 int ath_hal_show_bb_panic; 1192 int ath_hal_ant_ctrl_comm2g_switch_enable; 1193 int ath_hal_ext_atten_margin_cfg; 1194 int ath_hal_min_gainidx; 1195 int ath_hal_war70c; 1196 uint32_t ath_hal_mci_config; 1197 } HAL_OPS_CONFIG; 1198 1199 /* 1200 * Hardware Access Layer (HAL) API. 1201 * 1202 * Clients of the HAL call ath_hal_attach to obtain a reference to an 1203 * ath_hal structure for use with the device. Hardware-related operations 1204 * that follow must call back into the HAL through interface, supplying 1205 * the reference as the first parameter. Note that before using the 1206 * reference returned by ath_hal_attach the caller should verify the 1207 * ABI version number. 1208 */ 1209 struct ath_hal { 1210 uint32_t ah_magic; /* consistency check magic number */ 1211 uint16_t ah_devid; /* PCI device ID */ 1212 uint16_t ah_subvendorid; /* PCI subvendor ID */ 1213 HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 1214 HAL_BUS_TAG ah_st; /* params for register r+w */ 1215 HAL_BUS_HANDLE ah_sh; 1216 HAL_CTRY_CODE ah_countryCode; 1217 1218 uint32_t ah_macVersion; /* MAC version id */ 1219 uint16_t ah_macRev; /* MAC revision */ 1220 uint16_t ah_phyRev; /* PHY revision */ 1221 /* NB: when only one radio is present the rev is in 5Ghz */ 1222 uint16_t ah_analog5GhzRev;/* 5GHz radio revision */ 1223 uint16_t ah_analog2GhzRev;/* 2GHz radio revision */ 1224 1225 uint16_t *ah_eepromdata; /* eeprom buffer, if needed */ 1226 1227 uint32_t ah_intrstate[8]; /* last int state */ 1228 uint32_t ah_syncstate; /* last sync intr state */ 1229 1230 /* Current powerstate from HAL calls */ 1231 HAL_POWER_MODE ah_powerMode; 1232 1233 HAL_OPS_CONFIG ah_config; 1234 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, 1235 u_int mode); 1236 void __ahdecl(*ah_detach)(struct ath_hal*); 1237 1238 /* Reset functions */ 1239 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, 1240 struct ieee80211_channel *, 1241 HAL_BOOL bChannelChange, 1242 HAL_RESET_TYPE resetType, 1243 HAL_STATUS *status); 1244 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); 1245 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *); 1246 void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore, 1247 HAL_BOOL power_off); 1248 void __ahdecl(*ah_disablePCIE)(struct ath_hal *); 1249 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 1250 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, 1251 struct ieee80211_channel *, HAL_BOOL *); 1252 HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, 1253 struct ieee80211_channel *, u_int chainMask, 1254 HAL_BOOL longCal, HAL_BOOL *isCalDone); 1255 HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, 1256 const struct ieee80211_channel *); 1257 HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *, 1258 const struct ieee80211_channel *, uint16_t *); 1259 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 1260 HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *, 1261 const struct ieee80211_channel *); 1262 1263 /* Transmit functions */ 1264 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, 1265 HAL_BOOL incTrigLevel); 1266 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, 1267 const HAL_TXQ_INFO *qInfo); 1268 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, 1269 const HAL_TXQ_INFO *qInfo); 1270 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, 1271 HAL_TXQ_INFO *qInfo); 1272 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); 1273 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); 1274 uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 1275 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp); 1276 uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 1277 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); 1278 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); 1279 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, 1280 u_int pktLen, u_int hdrLen, 1281 HAL_PKT_TYPE type, u_int txPower, 1282 u_int txRate0, u_int txTries0, 1283 u_int keyIx, u_int antMode, u_int flags, 1284 u_int rtsctsRate, u_int rtsctsDuration, 1285 u_int compicvLen, u_int compivLen, 1286 u_int comp); 1287 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, 1288 u_int txRate1, u_int txTries1, 1289 u_int txRate2, u_int txTries2, 1290 u_int txRate3, u_int txTries3); 1291 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, 1292 HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, 1293 u_int descId, u_int qcuId, HAL_BOOL firstSeg, 1294 HAL_BOOL lastSeg, const struct ath_desc *); 1295 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, 1296 struct ath_desc *, struct ath_tx_status *); 1297 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 1298 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); 1299 HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *, 1300 const struct ath_desc *ds, int *rates, int *tries); 1301 void __ahdecl(*ah_setTxDescLink)(struct ath_hal *ah, void *ds, 1302 uint32_t link); 1303 void __ahdecl(*ah_getTxDescLink)(struct ath_hal *ah, void *ds, 1304 uint32_t *link); 1305 void __ahdecl(*ah_getTxDescLinkPtr)(struct ath_hal *ah, void *ds, 1306 uint32_t **linkptr); 1307 void __ahdecl(*ah_setupTxStatusRing)(struct ath_hal *, 1308 void *ts_start, uint32_t ts_paddr_start, 1309 uint16_t size); 1310 void __ahdecl(*ah_getTxRawTxDesc)(struct ath_hal *, u_int32_t *); 1311 1312 /* Receive Functions */ 1313 uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*, HAL_RX_QUEUE); 1314 void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp, HAL_RX_QUEUE); 1315 void __ahdecl(*ah_enableReceive)(struct ath_hal*); 1316 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); 1317 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*, HAL_BOOL); 1318 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); 1319 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, 1320 uint32_t filter0, uint32_t filter1); 1321 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, 1322 uint32_t index); 1323 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, 1324 uint32_t index); 1325 uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 1326 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t); 1327 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 1328 uint32_t size, u_int flags); 1329 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, 1330 struct ath_desc *, uint32_t phyAddr, 1331 struct ath_desc *next, uint64_t tsf, 1332 struct ath_rx_status *); 1333 void __ahdecl(*ah_rxMonitor)(struct ath_hal *, 1334 const HAL_NODE_STATS *, 1335 const struct ieee80211_channel *); 1336 void __ahdecl(*ah_aniPoll)(struct ath_hal *, 1337 const struct ieee80211_channel *); 1338 void __ahdecl(*ah_procMibEvent)(struct ath_hal *, 1339 const HAL_NODE_STATS *); 1340 1341 /* Misc Functions */ 1342 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, 1343 HAL_CAPABILITY_TYPE, uint32_t capability, 1344 uint32_t *result); 1345 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, 1346 HAL_CAPABILITY_TYPE, uint32_t capability, 1347 uint32_t setting, HAL_STATUS *); 1348 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, 1349 const void *args, uint32_t argsize, 1350 void **result, uint32_t *resultsize); 1351 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *); 1352 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*); 1353 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 1354 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*); 1355 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, 1356 uint16_t, HAL_STATUS *); 1357 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); 1358 void __ahdecl(*ah_writeAssocid)(struct ath_hal*, 1359 const uint8_t *bssid, uint16_t assocId); 1360 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, 1361 uint32_t gpio, HAL_GPIO_MUX_TYPE); 1362 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 1363 uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 1364 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *, 1365 uint32_t gpio, uint32_t val); 1366 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 1367 uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 1368 uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 1369 void __ahdecl(*ah_setTsf64)(struct ath_hal *, uint64_t); 1370 void __ahdecl(*ah_resetTsf)(struct ath_hal*); 1371 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*); 1372 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, 1373 HAL_MIB_STATS*); 1374 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*); 1375 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*); 1376 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int); 1377 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*); 1378 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*, 1379 HAL_ANT_SETTING); 1380 HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int); 1381 u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*); 1382 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); 1383 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); 1384 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); 1385 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*); 1386 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int); 1387 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*); 1388 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); 1389 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); 1390 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int); 1391 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int); 1392 HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t period, 1393 uint32_t duration, uint32_t nextStart, 1394 HAL_QUIET_FLAG flag); 1395 void __ahdecl(*ah_setChainMasks)(struct ath_hal *, 1396 uint32_t, uint32_t); 1397 1398 /* DFS functions */ 1399 void __ahdecl(*ah_enableDfs)(struct ath_hal *ah, 1400 HAL_PHYERR_PARAM *pe); 1401 void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah, 1402 HAL_PHYERR_PARAM *pe); 1403 HAL_BOOL __ahdecl(*ah_getDfsDefaultThresh)(struct ath_hal *ah, 1404 HAL_PHYERR_PARAM *pe); 1405 HAL_BOOL __ahdecl(*ah_procRadarEvent)(struct ath_hal *ah, 1406 struct ath_rx_status *rxs, uint64_t fulltsf, 1407 const char *buf, HAL_DFS_EVENT *event); 1408 HAL_BOOL __ahdecl(*ah_isFastClockEnabled)(struct ath_hal *ah); 1409 void __ahdecl(*ah_setDfsCacTxQuiet)(struct ath_hal *, HAL_BOOL); 1410 1411 /* Spectral Scan functions */ 1412 void __ahdecl(*ah_spectralConfigure)(struct ath_hal *ah, 1413 HAL_SPECTRAL_PARAM *sp); 1414 void __ahdecl(*ah_spectralGetConfig)(struct ath_hal *ah, 1415 HAL_SPECTRAL_PARAM *sp); 1416 void __ahdecl(*ah_spectralStart)(struct ath_hal *); 1417 void __ahdecl(*ah_spectralStop)(struct ath_hal *); 1418 HAL_BOOL __ahdecl(*ah_spectralIsEnabled)(struct ath_hal *); 1419 HAL_BOOL __ahdecl(*ah_spectralIsActive)(struct ath_hal *); 1420 /* XXX getNfPri() and getNfExt() */ 1421 1422 /* Key Cache Functions */ 1423 uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); 1424 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t); 1425 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, 1426 uint16_t); 1427 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, 1428 uint16_t, const HAL_KEYVAL *, 1429 const uint8_t *, int); 1430 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, 1431 uint16_t, const uint8_t *); 1432 1433 /* Power Management Functions */ 1434 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*, 1435 HAL_POWER_MODE mode, int setChip); 1436 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); 1437 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, 1438 const struct ieee80211_channel *); 1439 1440 /* Beacon Management Functions */ 1441 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, 1442 const HAL_BEACON_TIMERS *); 1443 /* NB: deprecated, use ah_setBeaconTimers instead */ 1444 void __ahdecl(*ah_beaconInit)(struct ath_hal *, 1445 uint32_t nexttbtt, uint32_t intval); 1446 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, 1447 const HAL_BEACON_STATE *); 1448 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*); 1449 uint64_t __ahdecl(*ah_getNextTBTT)(struct ath_hal *); 1450 1451 /* 802.11n Functions */ 1452 HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *, 1453 struct ath_desc *, 1454 HAL_DMA_ADDR *bufAddrList, 1455 uint32_t *segLenList, 1456 u_int, u_int, HAL_PKT_TYPE, 1457 u_int, HAL_CIPHER, uint8_t, HAL_BOOL, 1458 HAL_BOOL, HAL_BOOL); 1459 HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *, 1460 struct ath_desc *, u_int, u_int, u_int, 1461 u_int, u_int, u_int, u_int, u_int); 1462 HAL_BOOL __ahdecl(*ah_setupLastTxDesc)(struct ath_hal *, 1463 struct ath_desc *, const struct ath_desc *); 1464 void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *, 1465 struct ath_desc *, u_int, u_int, 1466 HAL_11N_RATE_SERIES [], u_int, u_int); 1467 1468 /* 1469 * The next 4 (set11ntxdesc -> set11naggrlast) are specific 1470 * to the EDMA HAL. Descriptors are chained together by 1471 * using filltxdesc (not ChainTxDesc) and then setting the 1472 * aggregate flags appropriately using first/middle/last. 1473 */ 1474 void __ahdecl(*ah_set11nTxDesc)(struct ath_hal *, 1475 void *, u_int, HAL_PKT_TYPE, u_int, u_int, 1476 u_int); 1477 void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *, 1478 struct ath_desc *, u_int, u_int); 1479 void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *, 1480 struct ath_desc *, u_int); 1481 void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *, 1482 struct ath_desc *); 1483 void __ahdecl(*ah_clr11nAggr)(struct ath_hal *, 1484 struct ath_desc *); 1485 void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *, 1486 struct ath_desc *, u_int); 1487 void __ahdecl(*ah_set11nVirtMoreFrag)(struct ath_hal *, 1488 struct ath_desc *, u_int); 1489 1490 HAL_BOOL __ahdecl(*ah_getMibCycleCounts) (struct ath_hal *, 1491 HAL_SURVEY_SAMPLE *); 1492 1493 uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *); 1494 void __ahdecl(*ah_set11nMac2040)(struct ath_hal *, 1495 HAL_HT_MACMODE); 1496 HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah); 1497 void __ahdecl(*ah_set11nRxClear)(struct ath_hal *, 1498 HAL_HT_RXCLEAR); 1499 1500 /* Interrupt functions */ 1501 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); 1502 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); 1503 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); 1504 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); 1505 1506 /* Bluetooth Coexistence functions */ 1507 void __ahdecl(*ah_btCoexSetInfo)(struct ath_hal *, 1508 HAL_BT_COEX_INFO *); 1509 void __ahdecl(*ah_btCoexSetConfig)(struct ath_hal *, 1510 HAL_BT_COEX_CONFIG *); 1511 void __ahdecl(*ah_btCoexSetQcuThresh)(struct ath_hal *, 1512 int); 1513 void __ahdecl(*ah_btCoexSetWeights)(struct ath_hal *, 1514 uint32_t); 1515 void __ahdecl(*ah_btCoexSetBmissThresh)(struct ath_hal *, 1516 uint32_t); 1517 void __ahdecl(*ah_btCoexSetParameter)(struct ath_hal *, 1518 uint32_t, uint32_t); 1519 void __ahdecl(*ah_btCoexDisable)(struct ath_hal *); 1520 int __ahdecl(*ah_btCoexEnable)(struct ath_hal *); 1521 1522 /* Bluetooth MCI methods */ 1523 void __ahdecl(*ah_btMciSetup)(struct ath_hal *, 1524 uint32_t, void *, uint16_t, uint32_t); 1525 HAL_BOOL __ahdecl(*ah_btMciSendMessage)(struct ath_hal *, 1526 uint8_t, uint32_t, uint32_t *, uint8_t, 1527 HAL_BOOL, HAL_BOOL); 1528 uint32_t __ahdecl(*ah_btMciGetInterrupt)(struct ath_hal *, 1529 uint32_t *, uint32_t *); 1530 uint32_t __ahdecl(*ah_btMciState)(struct ath_hal *, 1531 uint32_t, uint32_t *); 1532 void __ahdecl(*ah_btMciDetach)(struct ath_hal *); 1533 1534 /* LNA diversity configuration */ 1535 void __ahdecl(*ah_divLnaConfGet)(struct ath_hal *, 1536 HAL_ANT_COMB_CONFIG *); 1537 void __ahdecl(*ah_divLnaConfSet)(struct ath_hal *, 1538 HAL_ANT_COMB_CONFIG *); 1539 }; 1540 1541 /* 1542 * Check the PCI vendor ID and device ID against Atheros' values 1543 * and return a printable description for any Atheros hardware. 1544 * AH_NULL is returned if the ID's do not describe Atheros hardware. 1545 */ 1546 extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid); 1547 1548 /* 1549 * Attach the HAL for use with the specified device. The device is 1550 * defined by the PCI device ID. The caller provides an opaque pointer 1551 * to an upper-layer data structure (HAL_SOFTC) that is stored in the 1552 * HAL state block for later use. Hardware register accesses are done 1553 * using the specified bus tag and handle. On successful return a 1554 * reference to a state block is returned that must be supplied in all 1555 * subsequent HAL calls. Storage associated with this reference is 1556 * dynamically allocated and must be freed by calling the ah_detach 1557 * method when the client is done. If the attach operation fails a 1558 * null (AH_NULL) reference will be returned and a status code will 1559 * be returned if the status parameter is non-zero. 1560 */ 1561 extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC, 1562 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 1563 HAL_OPS_CONFIG *ah_config, HAL_STATUS* status); 1564 1565 extern const char *ath_hal_mac_name(struct ath_hal *); 1566 extern const char *ath_hal_rf_name(struct ath_hal *); 1567 1568 /* 1569 * Regulatory interfaces. Drivers should use ath_hal_init_channels to 1570 * request a set of channels for a particular country code and/or 1571 * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then 1572 * this list is constructed according to the contents of the EEPROM. 1573 * ath_hal_getchannels acts similarly but does not alter the operating 1574 * state; this can be used to collect information for a particular 1575 * regulatory configuration. Finally ath_hal_set_channels installs a 1576 * channel list constructed outside the driver. The HAL will adopt the 1577 * channel list and setup internal state according to the specified 1578 * regulatory configuration (e.g. conformance test limits). 1579 * 1580 * For all interfaces the channel list is returned in the supplied array. 1581 * maxchans defines the maximum size of this array. nchans contains the 1582 * actual number of channels returned. If a problem occurred then a 1583 * status code != HAL_OK is returned. 1584 */ 1585 struct ieee80211_channel; 1586 1587 /* 1588 * Return a list of channels according to the specified regulatory. 1589 */ 1590 extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *, 1591 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1592 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 1593 HAL_BOOL enableExtendedChannels); 1594 1595 /* 1596 * Return a list of channels and install it as the current operating 1597 * regulatory list. 1598 */ 1599 extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *, 1600 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1601 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd, 1602 HAL_BOOL enableExtendedChannels); 1603 1604 /* 1605 * Install the list of channels as the current operating regulatory 1606 * and setup related state according to the country code and sku. 1607 */ 1608 extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *, 1609 struct ieee80211_channel *chans, int nchans, 1610 HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn); 1611 1612 /* 1613 * Fetch the ctl/ext noise floor values reported by a MIMO 1614 * radio. Returns 1 for valid results, 0 for invalid channel. 1615 */ 1616 extern int __ahdecl ath_hal_get_mimo_chan_noise(struct ath_hal *ah, 1617 const struct ieee80211_channel *chan, int16_t *nf_ctl, 1618 int16_t *nf_ext); 1619 1620 /* 1621 * Calibrate noise floor data following a channel scan or similar. 1622 * This must be called prior retrieving noise floor data. 1623 */ 1624 extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah); 1625 1626 /* 1627 * Return bit mask of wireless modes supported by the hardware. 1628 */ 1629 extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*); 1630 1631 /* 1632 * Get the HAL wireless mode for the given channel. 1633 */ 1634 extern int ath_hal_get_curmode(struct ath_hal *ah, 1635 const struct ieee80211_channel *chan); 1636 1637 /* 1638 * Calculate the packet TX time for a legacy or 11n frame 1639 */ 1640 extern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah, 1641 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1642 uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble, 1643 HAL_BOOL includeSifs); 1644 1645 /* 1646 * Calculate the duration of an 11n frame. 1647 */ 1648 extern uint32_t __ahdecl ath_computedur_ht(uint32_t frameLen, uint16_t rate, 1649 int streams, HAL_BOOL isht40, HAL_BOOL isShortGI); 1650 1651 /* 1652 * Calculate the transmit duration of a legacy frame. 1653 */ 1654 extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, 1655 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1656 uint16_t rateix, HAL_BOOL shortPreamble, 1657 HAL_BOOL includeSifs); 1658 1659 /* 1660 * Adjust the TSF. 1661 */ 1662 extern void __ahdecl ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta); 1663 1664 /* 1665 * Enable or disable CCA. 1666 */ 1667 void __ahdecl ath_hal_setcca(struct ath_hal *ah, int ena); 1668 1669 /* 1670 * Get CCA setting. 1671 */ 1672 int __ahdecl ath_hal_getcca(struct ath_hal *ah); 1673 1674 /* 1675 * Enable/disable and get self-gen frame (ACK, CTS) for CAC. 1676 */ 1677 void __ahdecl ath_hal_set_dfs_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL ena); 1678 1679 /* 1680 * Read EEPROM data from ah_eepromdata 1681 */ 1682 HAL_BOOL __ahdecl ath_hal_EepromDataRead(struct ath_hal *ah, 1683 u_int off, uint16_t *data); 1684 1685 /* 1686 * For now, simply pass through MFP frames. 1687 */ 1688 static inline u_int32_t 1689 ath_hal_get_mfp_qos(struct ath_hal *ah) 1690 { 1691 //return AH_PRIVATE(ah)->ah_mfp_qos; 1692 return HAL_MFP_QOSDATA; 1693 } 1694 1695 /* 1696 * Convert between microseconds and core system clocks. 1697 */ 1698 extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 1699 extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 1700 extern uint64_t ath_hal_mac_psec(struct ath_hal *ah, u_int clks); 1701 1702 #endif /* _ATH_AH_H_ */ 1703