1 /* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #ifndef _ATH_AH_INTERAL_H_ 20 #define _ATH_AH_INTERAL_H_ 21 /* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26 #define AH_NULL 0 27 #define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28 #define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30 #include <net80211/_ieee80211.h> 31 32 #ifndef NBBY 33 #define NBBY 8 /* number of bits/byte */ 34 #endif 35 36 #ifndef roundup 37 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 38 #endif 39 #ifndef howmany 40 #define howmany(x, y) (((x)+((y)-1))/(y)) 41 #endif 42 43 #ifndef offsetof 44 #define offsetof(type, field) ((size_t)(&((type *)0)->field)) 45 #endif 46 47 typedef struct { 48 uint16_t start; /* first register */ 49 uint16_t end; /* ending register or zero */ 50 } HAL_REGRANGE; 51 52 typedef struct { 53 uint32_t addr; /* regiser address/offset */ 54 uint32_t value; /* value to write */ 55 } HAL_REGWRITE; 56 57 /* 58 * Transmit power scale factor. 59 * 60 * NB: This is not public because we want to discourage the use of 61 * scaling; folks should use the tx power limit interface. 62 */ 63 typedef enum { 64 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 65 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 66 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 67 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 68 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 69 } HAL_TP_SCALE; 70 71 typedef enum { 72 HAL_CAP_RADAR = 0, /* Radar capability */ 73 HAL_CAP_AR = 1, /* AR capability */ 74 } HAL_PHYDIAG_CAPS; 75 76 /* 77 * Each chip or class of chips registers to offer support. 78 */ 79 struct ath_hal_chip { 80 const char *name; 81 const char *(*probe)(uint16_t vendorid, uint16_t devid); 82 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 83 HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS *error); 84 }; 85 #ifndef AH_CHIP 86 #define AH_CHIP(_name, _probe, _attach) \ 87 static struct ath_hal_chip _name##_chip = { \ 88 .name = #_name, \ 89 .probe = _probe, \ 90 .attach = _attach \ 91 }; \ 92 OS_DATA_SET(ah_chips, _name##_chip) 93 #endif 94 95 /* 96 * Each RF backend registers to offer support; this is mostly 97 * used by multi-chip 5212 solutions. Single-chip solutions 98 * have a fixed idea about which RF to use. 99 */ 100 struct ath_hal_rf { 101 const char *name; 102 HAL_BOOL (*probe)(struct ath_hal *ah); 103 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 104 }; 105 #ifndef AH_RF 106 #define AH_RF(_name, _probe, _attach) \ 107 static struct ath_hal_rf _name##_rf = { \ 108 .name = __STRING(_name), \ 109 .probe = _probe, \ 110 .attach = _attach \ 111 }; \ 112 OS_DATA_SET(ah_rfs, _name##_rf) 113 #endif 114 115 struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 116 117 /* 118 * Maximum number of internal channels. Entries are per unique 119 * frequency so this might be need to be increased to handle all 120 * usage cases; typically no more than 32 are really needed but 121 * dynamically allocating the data structures is a bit painful 122 * right now. 123 */ 124 #ifndef AH_MAXCHAN 125 #define AH_MAXCHAN 96 126 #endif 127 128 /* 129 * Internal per-channel state. These are found 130 * using ic_devdata in the ieee80211_channel. 131 */ 132 typedef struct { 133 uint16_t channel; /* h/w frequency, NB: may be mapped */ 134 uint8_t privFlags; 135 #define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 136 #define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 137 #define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 138 uint8_t calValid; /* bitmask of cal types */ 139 int8_t iCoff; 140 int8_t qCoff; 141 int16_t rawNoiseFloor; 142 int16_t noiseFloorAdjust; 143 uint16_t mainSpur; /* cached spur value for this channel */ 144 } HAL_CHANNEL_INTERNAL; 145 146 /* channel requires noise floor check */ 147 #define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 148 149 /* all full-width channels */ 150 #define IEEE80211_CHAN_ALLFULL \ 151 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 152 #define IEEE80211_CHAN_ALLTURBOFULL \ 153 (IEEE80211_CHAN_ALLTURBO - \ 154 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 155 156 typedef struct { 157 uint32_t halChanSpreadSupport : 1, 158 halSleepAfterBeaconBroken : 1, 159 halCompressSupport : 1, 160 halBurstSupport : 1, 161 halFastFramesSupport : 1, 162 halChapTuningSupport : 1, 163 halTurboGSupport : 1, 164 halTurboPrimeSupport : 1, 165 halMicAesCcmSupport : 1, 166 halMicCkipSupport : 1, 167 halMicTkipSupport : 1, 168 halTkipMicTxRxKeySupport : 1, 169 halCipherAesCcmSupport : 1, 170 halCipherCkipSupport : 1, 171 halCipherTkipSupport : 1, 172 halPSPollBroken : 1, 173 halVEOLSupport : 1, 174 halBssIdMaskSupport : 1, 175 halMcastKeySrchSupport : 1, 176 halTsfAddSupport : 1, 177 halChanHalfRate : 1, 178 halChanQuarterRate : 1, 179 halHTSupport : 1, 180 halRfSilentSupport : 1, 181 halHwPhyCounterSupport : 1, 182 halWowSupport : 1, 183 halWowMatchPatternExact : 1, 184 halAutoSleepSupport : 1, 185 halFastCCSupport : 1, 186 halBtCoexSupport : 1; 187 uint32_t halRxStbcSupport : 1, 188 halTxStbcSupport : 1, 189 halGTTSupport : 1, 190 halCSTSupport : 1, 191 halRifsRxSupport : 1, 192 halRifsTxSupport : 1, 193 halExtChanDfsSupport : 1, 194 halForcePpmSupport : 1, 195 halEnhancedPmSupport : 1, 196 halMbssidAggrSupport : 1; 197 uint32_t halWirelessModes; 198 uint16_t halTotalQueues; 199 uint16_t halKeyCacheSize; 200 uint16_t halLow5GhzChan, halHigh5GhzChan; 201 uint16_t halLow2GhzChan, halHigh2GhzChan; 202 int halTstampPrecision; 203 int halRtsAggrLimit; 204 uint8_t halTxChainMask; 205 uint8_t halRxChainMask; 206 uint8_t halNumGpioPins; 207 uint8_t halNumAntCfg2GHz; 208 uint8_t halNumAntCfg5GHz; 209 } HAL_CAPABILITIES; 210 211 struct regDomain; 212 213 /* 214 * The ``private area'' follows immediately after the ``public area'' 215 * in the data structure returned by ath_hal_attach. Private data are 216 * used by device-independent code such as the regulatory domain support. 217 * In general, code within the HAL should never depend on data in the 218 * public area. Instead any public data needed internally should be 219 * shadowed here. 220 * 221 * When declaring a device-specific ath_hal data structure this structure 222 * is assumed to at the front; e.g. 223 * 224 * struct ath_hal_5212 { 225 * struct ath_hal_private ah_priv; 226 * ... 227 * }; 228 * 229 * It might be better to manage the method pointers in this structure 230 * using an indirect pointer to a read-only data structure but this would 231 * disallow class-style method overriding. 232 */ 233 struct ath_hal_private { 234 struct ath_hal h; /* public area */ 235 236 /* NB: all methods go first to simplify initialization */ 237 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 238 uint16_t channelFlags, 239 uint16_t *lowChannel, uint16_t *highChannel); 240 u_int (*ah_getWirelessModes)(struct ath_hal*); 241 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 242 uint16_t *data); 243 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 244 uint16_t data); 245 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 246 struct ieee80211_channel *); 247 int16_t (*ah_getNfAdjust)(struct ath_hal *, 248 const HAL_CHANNEL_INTERNAL*); 249 void (*ah_getNoiseFloor)(struct ath_hal *, 250 int16_t nfarray[]); 251 252 void *ah_eeprom; /* opaque EEPROM state */ 253 uint16_t ah_eeversion; /* EEPROM version */ 254 void (*ah_eepromDetach)(struct ath_hal *); 255 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 256 HAL_BOOL (*ah_eepromSet)(struct ath_hal *, int, int); 257 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 258 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 259 const void *args, uint32_t argsize, 260 void **result, uint32_t *resultsize); 261 262 /* 263 * Device revision information. 264 */ 265 uint16_t ah_devid; /* PCI device ID */ 266 uint16_t ah_subvendorid; /* PCI subvendor ID */ 267 uint32_t ah_macVersion; /* MAC version id */ 268 uint16_t ah_macRev; /* MAC revision */ 269 uint16_t ah_phyRev; /* PHY revision */ 270 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 271 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 272 uint8_t ah_ispcie; /* PCIE, special treatment */ 273 274 HAL_OPMODE ah_opmode; /* operating mode from reset */ 275 const struct ieee80211_channel *ah_curchan;/* operating channel */ 276 HAL_CAPABILITIES ah_caps; /* device capabilities */ 277 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 278 int16_t ah_powerLimit; /* tx power cap */ 279 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 280 u_int ah_tpScale; /* tx power scale factor */ 281 uint32_t ah_11nCompat; /* 11n compat controls */ 282 283 /* 284 * State for regulatory domain handling. 285 */ 286 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 287 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 288 u_int ah_nchan; /* valid items in ah_channels */ 289 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 290 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 291 292 uint8_t ah_coverageClass; /* coverage class */ 293 /* 294 * RF Silent handling; setup according to the EEPROM. 295 */ 296 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 297 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 298 /* 299 * Diagnostic support for discriminating HIUERR reports. 300 */ 301 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 302 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 303 }; 304 305 #define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 306 307 #define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 308 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 309 #define ath_hal_getWirelessModes(_ah) \ 310 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 311 #define ath_hal_eepromRead(_ah, _off, _data) \ 312 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 313 #define ath_hal_eepromWrite(_ah, _off, _data) \ 314 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 315 #define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 316 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 317 #define ath_hal_gpioCfgInput(_ah, _gpio) \ 318 (_ah)->ah_gpioCfgInput(_ah, _gpio) 319 #define ath_hal_gpioGet(_ah, _gpio) \ 320 (_ah)->ah_gpioGet(_ah, _gpio) 321 #define ath_hal_gpioSet(_ah, _gpio, _val) \ 322 (_ah)->ah_gpioSet(_ah, _gpio, _val) 323 #define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 324 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 325 #define ath_hal_getpowerlimits(_ah, _chan) \ 326 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 327 #define ath_hal_getNfAdjust(_ah, _c) \ 328 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 329 #define ath_hal_getNoiseFloor(_ah, _nfArray) \ 330 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 331 #define ath_hal_configPCIE(_ah, _reset) \ 332 (_ah)->ah_configPCIE(_ah, _reset) 333 #define ath_hal_disablePCIE(_ah) \ 334 (_ah)->ah_disablePCIE(_ah) 335 336 #define ath_hal_eepromDetach(_ah) \ 337 AH_PRIVATE(_ah)->ah_eepromDetach(_ah) 338 #define ath_hal_eepromGet(_ah, _param, _val) \ 339 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 340 #define ath_hal_eepromSet(_ah, _param, _val) \ 341 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 342 #define ath_hal_eepromGetFlag(_ah, _param) \ 343 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 344 #define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 345 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 346 #define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 347 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 348 349 #ifndef _NET_IF_IEEE80211_H_ 350 /* 351 * Stuff that would naturally come from _ieee80211.h 352 */ 353 #define IEEE80211_ADDR_LEN 6 354 355 #define IEEE80211_WEP_IVLEN 3 /* 24bit */ 356 #define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 357 #define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 358 359 #define IEEE80211_CRC_LEN 4 360 361 #define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 362 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 363 #endif /* _NET_IF_IEEE80211_H_ */ 364 365 #define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 366 367 #define INIT_AIFS 2 368 #define INIT_CWMIN 15 369 #define INIT_CWMIN_11B 31 370 #define INIT_CWMAX 1023 371 #define INIT_SH_RETRY 10 372 #define INIT_LG_RETRY 10 373 #define INIT_SSH_RETRY 32 374 #define INIT_SLG_RETRY 32 375 376 typedef struct { 377 uint32_t tqi_ver; /* HAL TXQ verson */ 378 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 379 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 380 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 381 uint32_t tqi_priority; 382 uint32_t tqi_aifs; /* aifs */ 383 uint32_t tqi_cwmin; /* cwMin */ 384 uint32_t tqi_cwmax; /* cwMax */ 385 uint16_t tqi_shretry; /* frame short retry limit */ 386 uint16_t tqi_lgretry; /* frame long retry limit */ 387 uint32_t tqi_cbrPeriod; 388 uint32_t tqi_cbrOverflowLimit; 389 uint32_t tqi_burstTime; 390 uint32_t tqi_readyTime; 391 uint32_t tqi_physCompBuf; 392 uint32_t tqi_intFlags; /* flags for internal use */ 393 } HAL_TX_QUEUE_INFO; 394 395 extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 396 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 397 extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 398 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 399 400 typedef enum { 401 HAL_ANI_PRESENT, /* is ANI support present */ 402 HAL_ANI_NOISE_IMMUNITY_LEVEL, /* set level */ 403 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, /* enable/disable */ 404 HAL_ANI_CCK_WEAK_SIGNAL_THR, /* enable/disable */ 405 HAL_ANI_FIRSTEP_LEVEL, /* set level */ 406 HAL_ANI_SPUR_IMMUNITY_LEVEL, /* set level */ 407 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 408 HAL_ANI_PHYERR_RESET, /* reset phy error stats */ 409 } HAL_ANI_CMD; 410 411 #define HAL_SPUR_VAL_MASK 0x3FFF 412 #define HAL_SPUR_CHAN_WIDTH 87 413 #define HAL_BIN_WIDTH_BASE_100HZ 3125 414 #define HAL_BIN_WIDTH_TURBO_100HZ 6250 415 #define HAL_MAX_BINS_ALLOWED 28 416 417 #define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 418 #define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 419 420 #define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 421 422 /* 423 * Deduce if the host cpu has big- or litt-endian byte order. 424 */ 425 static __inline__ int 426 isBigEndian(void) 427 { 428 union { 429 int32_t i; 430 char c[4]; 431 } u; 432 u.i = 1; 433 return (u.c[0] == 0); 434 } 435 436 /* unalligned little endian access */ 437 #define LE_READ_2(p) \ 438 ((uint16_t) \ 439 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 440 #define LE_READ_4(p) \ 441 ((uint32_t) \ 442 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 443 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 444 445 /* 446 * Register manipulation macros that expect bit field defines 447 * to follow the convention that an _S suffix is appended for 448 * a shift count, while the field mask has no suffix. 449 */ 450 #define SM(_v, _f) (((_v) << _f##_S) & (_f)) 451 #define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 452 #define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 453 OS_REG_WRITE(_a, _r, \ 454 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 455 #define OS_REG_SET_BIT(_a, _r, _f) \ 456 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 457 #define OS_REG_CLR_BIT(_a, _r, _f) \ 458 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 459 460 /* system-configurable parameters */ 461 extern int ath_hal_dma_beacon_response_time; /* in TU's */ 462 extern int ath_hal_sw_beacon_response_time; /* in TU's */ 463 extern int ath_hal_additional_swba_backoff; /* in TU's */ 464 465 /* wait for the register contents to have the specified value */ 466 extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 467 uint32_t mask, uint32_t val); 468 469 /* return the first n bits in val reversed */ 470 extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 471 472 /* printf interfaces */ 473 extern void ath_hal_printf(struct ath_hal *, const char*, ...) 474 __printflike(2,3); 475 extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 476 __printflike(2, 0); 477 extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 478 479 /* allocate and free memory */ 480 extern void *ath_hal_malloc(size_t); 481 extern void ath_hal_free(void *); 482 483 /* common debugging interfaces */ 484 #ifdef AH_DEBUG 485 #include "ah_debug.h" 486 extern int ath_hal_debug; 487 extern void HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 488 __printflike(3,4); 489 #else 490 #define HALDEBUG(_ah, __m, _fmt, ...) 491 #endif /* AH_DEBUG */ 492 493 /* 494 * Register logging definitions shared with ardecode. 495 */ 496 #include "ah_decode.h" 497 498 /* 499 * Common assertion interface. Note: it is a bad idea to generate 500 * an assertion failure for any recoverable event. Instead catch 501 * the violation and, if possible, fix it up or recover from it; either 502 * with an error return value or a diagnostic messages. System software 503 * does not panic unless the situation is hopeless. 504 */ 505 #ifdef AH_ASSERT 506 extern void ath_hal_assert_failed(const char* filename, 507 int lineno, const char* msg); 508 509 #define HALASSERT(_x) do { \ 510 if (!(_x)) { \ 511 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 512 } \ 513 } while (0) 514 #else 515 #define HALASSERT(_x) 516 #endif /* AH_ASSERT */ 517 518 /* 519 * Regulatory domain support. 520 */ 521 522 /* 523 * Return the max allowed antenna gain and apply any regulatory 524 * domain specific changes. 525 */ 526 u_int ath_hal_getantennareduction(struct ath_hal *ah, 527 const struct ieee80211_channel *chan, u_int twiceGain); 528 529 /* 530 * Return the test group for the specific channel based on 531 * the current regulatory setup. 532 */ 533 u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 534 535 /* 536 * Map a public channel definition to the corresponding 537 * internal data structure. This implicitly specifies 538 * whether or not the specified channel is ok to use 539 * based on the current regulatory domain constraints. 540 */ 541 #ifndef AH_DEBUG 542 static OS_INLINE HAL_CHANNEL_INTERNAL * 543 ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 544 { 545 HAL_CHANNEL_INTERNAL *cc; 546 547 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 548 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 549 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 550 return cc; 551 } 552 #else 553 /* NB: non-inline version that checks state */ 554 HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 555 const struct ieee80211_channel *); 556 #endif /* AH_DEBUG */ 557 558 /* 559 * Return the h/w frequency for a channel. This may be 560 * different from ic_freq if this is a GSM device that 561 * takes 2.4GHz frequencies and down-converts them. 562 */ 563 static OS_INLINE uint16_t 564 ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 565 { 566 return ath_hal_checkchannel(ah, c)->channel; 567 } 568 569 /* 570 * Convert between microseconds and core system clocks. 571 */ 572 extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 573 extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 574 575 /* 576 * Generic get/set capability support. Each chip overrides 577 * this routine to support chip-specific capabilities. 578 */ 579 extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 580 HAL_CAPABILITY_TYPE type, uint32_t capability, 581 uint32_t *result); 582 extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 583 HAL_CAPABILITY_TYPE type, uint32_t capability, 584 uint32_t setting, HAL_STATUS *status); 585 586 /* 587 * Diagnostic interface. This is an open-ended interface that 588 * is opaque to applications. Diagnostic programs use this to 589 * retrieve internal data structures, etc. There is no guarantee 590 * that calling conventions for calls other than HAL_DIAG_REVS 591 * are stable between HAL releases; a diagnostic application must 592 * use the HAL revision information to deal with ABI/API differences. 593 * 594 * NB: do not renumber these, certain codes are publicly used. 595 */ 596 enum { 597 HAL_DIAG_REVS = 0, /* MAC/PHY/Radio revs */ 598 HAL_DIAG_EEPROM = 1, /* EEPROM contents */ 599 HAL_DIAG_EEPROM_EXP_11A = 2, /* EEPROM 5112 power exp for 11a */ 600 HAL_DIAG_EEPROM_EXP_11B = 3, /* EEPROM 5112 power exp for 11b */ 601 HAL_DIAG_EEPROM_EXP_11G = 4, /* EEPROM 5112 power exp for 11g */ 602 HAL_DIAG_ANI_CURRENT = 5, /* ANI current channel state */ 603 HAL_DIAG_ANI_OFDM = 6, /* ANI OFDM timing error stats */ 604 HAL_DIAG_ANI_CCK = 7, /* ANI CCK timing error stats */ 605 HAL_DIAG_ANI_STATS = 8, /* ANI statistics */ 606 HAL_DIAG_RFGAIN = 9, /* RfGain GAIN_VALUES */ 607 HAL_DIAG_RFGAIN_CURSTEP = 10, /* RfGain GAIN_OPTIMIZATION_STEP */ 608 HAL_DIAG_PCDAC = 11, /* PCDAC table */ 609 HAL_DIAG_TXRATES = 12, /* Transmit rate table */ 610 HAL_DIAG_REGS = 13, /* Registers */ 611 HAL_DIAG_ANI_CMD = 14, /* ANI issue command (XXX do not change!) */ 612 HAL_DIAG_SETKEY = 15, /* Set keycache backdoor */ 613 HAL_DIAG_RESETKEY = 16, /* Reset keycache backdoor */ 614 HAL_DIAG_EEREAD = 17, /* Read EEPROM word */ 615 HAL_DIAG_EEWRITE = 18, /* Write EEPROM word */ 616 /* 19-26 removed, do not reuse */ 617 HAL_DIAG_RDWRITE = 27, /* Write regulatory domain */ 618 HAL_DIAG_RDREAD = 28, /* Get regulatory domain */ 619 HAL_DIAG_FATALERR = 29, /* Read cached interrupt state */ 620 HAL_DIAG_11NCOMPAT = 30, /* 11n compatibility tweaks */ 621 HAL_DIAG_ANI_PARAMS = 31, /* ANI noise immunity parameters */ 622 HAL_DIAG_CHECK_HANGS = 32, /* check h/w hangs */ 623 HAL_DIAG_SETREGS = 33, /* write registers */ 624 }; 625 626 enum { 627 HAL_BB_HANG_DFS = 0x0001, 628 HAL_BB_HANG_RIFS = 0x0002, 629 HAL_BB_HANG_RX_CLEAR = 0x0004, 630 HAL_BB_HANG_UNKNOWN = 0x0080, 631 632 HAL_MAC_HANG_SIG1 = 0x0100, 633 HAL_MAC_HANG_SIG2 = 0x0200, 634 HAL_MAC_HANG_UNKNOWN = 0x8000, 635 636 HAL_BB_HANGS = HAL_BB_HANG_DFS 637 | HAL_BB_HANG_RIFS 638 | HAL_BB_HANG_RX_CLEAR 639 | HAL_BB_HANG_UNKNOWN, 640 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 641 | HAL_MAC_HANG_SIG2 642 | HAL_MAC_HANG_UNKNOWN, 643 }; 644 645 /* 646 * Device revision information. 647 */ 648 typedef struct { 649 uint16_t ah_devid; /* PCI device ID */ 650 uint16_t ah_subvendorid; /* PCI subvendor ID */ 651 uint32_t ah_macVersion; /* MAC version id */ 652 uint16_t ah_macRev; /* MAC revision */ 653 uint16_t ah_phyRev; /* PHY revision */ 654 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 655 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 656 } HAL_REVS; 657 658 /* 659 * Argument payload for HAL_DIAG_SETKEY. 660 */ 661 typedef struct { 662 HAL_KEYVAL dk_keyval; 663 uint16_t dk_keyix; /* key index */ 664 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 665 int dk_xor; /* XOR key data */ 666 } HAL_DIAG_KEYVAL; 667 668 /* 669 * Argument payload for HAL_DIAG_EEWRITE. 670 */ 671 typedef struct { 672 uint16_t ee_off; /* eeprom offset */ 673 uint16_t ee_data; /* write data */ 674 } HAL_DIAG_EEVAL; 675 676 677 typedef struct { 678 u_int offset; /* reg offset */ 679 uint32_t val; /* reg value */ 680 } HAL_DIAG_REGVAL; 681 682 /* 683 * 11n compatibility tweaks. 684 */ 685 #define HAL_DIAG_11N_SERVICES 0x00000003 686 #define HAL_DIAG_11N_SERVICES_S 0 687 #define HAL_DIAG_11N_TXSTOMP 0x0000000c 688 #define HAL_DIAG_11N_TXSTOMP_S 2 689 690 typedef struct { 691 int maxNoiseImmunityLevel; /* [0..4] */ 692 int totalSizeDesired[5]; 693 int coarseHigh[5]; 694 int coarseLow[5]; 695 int firpwr[5]; 696 697 int maxSpurImmunityLevel; /* [0..7] */ 698 int cycPwrThr1[8]; 699 700 int maxFirstepLevel; /* [0..2] */ 701 int firstep[3]; 702 703 uint32_t ofdmTrigHigh; 704 uint32_t ofdmTrigLow; 705 int32_t cckTrigHigh; 706 int32_t cckTrigLow; 707 int32_t rssiThrLow; 708 int32_t rssiThrHigh; 709 710 int period; /* update listen period */ 711 } HAL_ANI_PARAMS; 712 713 extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 714 const void *args, uint32_t argsize, 715 void **result, uint32_t *resultsize); 716 717 /* 718 * Setup a h/w rate table for use. 719 */ 720 extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 721 722 /* 723 * Common routine for implementing getChanNoise api. 724 */ 725 int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 726 727 /* 728 * Initialization support. 729 */ 730 typedef struct { 731 const uint32_t *data; 732 int rows, cols; 733 } HAL_INI_ARRAY; 734 735 #define HAL_INI_INIT(_ia, _data, _cols) do { \ 736 (_ia)->data = (const uint32_t *)(_data); \ 737 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 738 (_ia)->cols = (_cols); \ 739 } while (0) 740 #define HAL_INI_VAL(_ia, _r, _c) \ 741 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 742 743 /* 744 * OS_DELAY() does a PIO READ on the PCI bus which allows 745 * other cards' DMA reads to complete in the middle of our reset. 746 */ 747 #define DMA_YIELD(x) do { \ 748 if ((++(x) % 64) == 0) \ 749 OS_DELAY(1); \ 750 } while (0) 751 752 #define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 753 int r; \ 754 for (r = 0; r < N(regArray); r++) { \ 755 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 756 DMA_YIELD(regWr); \ 757 } \ 758 } while (0) 759 760 #define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 761 int r; \ 762 for (r = 0; r < N(regArray); r++) { \ 763 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 764 DMA_YIELD(regWr); \ 765 } \ 766 } while (0) 767 768 extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 769 int col, int regWr); 770 extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 771 int col); 772 extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 773 const uint32_t data[], int regWr); 774 775 #define CCK_SIFS_TIME 10 776 #define CCK_PREAMBLE_BITS 144 777 #define CCK_PLCP_BITS 48 778 779 #define OFDM_SIFS_TIME 16 780 #define OFDM_PREAMBLE_TIME 20 781 #define OFDM_PLCP_BITS 22 782 #define OFDM_SYMBOL_TIME 4 783 784 #define OFDM_HALF_SIFS_TIME 32 785 #define OFDM_HALF_PREAMBLE_TIME 40 786 #define OFDM_HALF_PLCP_BITS 22 787 #define OFDM_HALF_SYMBOL_TIME 8 788 789 #define OFDM_QUARTER_SIFS_TIME 64 790 #define OFDM_QUARTER_PREAMBLE_TIME 80 791 #define OFDM_QUARTER_PLCP_BITS 22 792 #define OFDM_QUARTER_SYMBOL_TIME 16 793 794 #define TURBO_SIFS_TIME 8 795 #define TURBO_PREAMBLE_TIME 14 796 #define TURBO_PLCP_BITS 22 797 #define TURBO_SYMBOL_TIME 4 798 799 #define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 800 #endif /* _ATH_AH_INTERAL_H_ */ 801