1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * Copyright (c) 2005-2006 Atheros Communications, Inc. 6 * All rights reserved. 7 * 8 * Permission to use, copy, modify, and/or distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 * 20 * $FreeBSD$ 21 */ 22 23 #ifndef __AH_REGDOMAIN_DOMAINS_H__ 24 #define __AH_REGDOMAIN_DOMAINS_H__ 25 26 /* 27 * BMLEN defines the size of the bitmask used to hold frequency 28 * band specifications. Note this must agree with the BM macro 29 * definition that's used to setup initializers. See also further 30 * comments below. 31 */ 32 /* BMLEN is now defined in ah_regdomain.h */ 33 #define W0(_a) \ 34 (((_a) >= 0 && (_a) < 64 ? (((uint64_t) 1)<<(_a)) : (uint64_t) 0)) 35 #define W1(_a) \ 36 (((_a) > 63 && (_a) < 128 ? (((uint64_t) 1)<<((_a)-64)) : (uint64_t) 0)) 37 #define BM1(_fa) { W0(_fa), W1(_fa) } 38 #define BM2(_fa, _fb) { W0(_fa) | W0(_fb), W1(_fa) | W1(_fb) } 39 #define BM3(_fa, _fb, _fc) \ 40 { W0(_fa) | W0(_fb) | W0(_fc), W1(_fa) | W1(_fb) | W1(_fc) } 41 #define BM4(_fa, _fb, _fc, _fd) \ 42 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd), \ 43 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) } 44 #define BM5(_fa, _fb, _fc, _fd, _fe) \ 45 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe), \ 46 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) } 47 #define BM6(_fa, _fb, _fc, _fd, _fe, _ff) \ 48 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff), \ 49 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) } 50 #define BM7(_fa, _fb, _fc, _fd, _fe, _ff, _fg) \ 51 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) | \ 52 W0(_fg),\ 53 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) | \ 54 W1(_fg) } 55 #define BM8(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh) \ 56 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) | \ 57 W0(_fg) | W0(_fh) , \ 58 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) | \ 59 W1(_fg) | W1(_fh) } 60 #define BM9(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh, _fi) \ 61 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) | \ 62 W0(_fg) | W0(_fh) | W0(_fi) , \ 63 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) | \ 64 W1(_fg) | W1(_fh) | W1(_fi) } 65 66 static REG_DOMAIN regDomains[] = { 67 68 {.regDmnEnum = DEBUG_REG_DMN, 69 .conformanceTestLimit = FCC, 70 .dfsMask = DFS_FCC3, 71 .chan11a = BM4(F1_4950_4980, 72 F1_5120_5240, 73 F1_5260_5700, 74 F1_5745_5825), 75 .chan11a_half = BM4(F1_4945_4985, 76 F2_5120_5240, 77 F2_5260_5700, 78 F7_5745_5825), 79 .chan11a_quarter = BM4(F1_4942_4987, 80 F3_5120_5240, 81 F3_5260_5700, 82 F8_5745_5825), 83 .chan11a_turbo = BM8(T1_5130_5210, 84 T1_5250_5330, 85 T1_5370_5490, 86 T1_5530_5650, 87 T1_5150_5190, 88 T1_5230_5310, 89 T1_5350_5470, 90 T1_5510_5670), 91 .chan11a_dyn_turbo = BM4(T1_5200_5240, 92 T1_5280_5280, 93 T1_5540_5660, 94 T1_5765_5805), 95 .chan11b = BM4(F1_2312_2372, 96 F1_2412_2472, 97 F1_2484_2484, 98 F1_2512_2732), 99 .chan11g = BM3(G1_2312_2372, G1_2412_2472, G1_2512_2732), 100 .chan11g_turbo = BM3(T1_2312_2372, T1_2437_2437, T1_2512_2732), 101 .chan11g_half = BM3(G2_2312_2372, G4_2412_2472, G2_2512_2732), 102 .chan11g_quarter = BM3(G3_2312_2372, G5_2412_2472, G3_2512_2732), 103 }, 104 105 {.regDmnEnum = APL1, 106 .conformanceTestLimit = FCC, 107 .chan11a = BM1(F4_5745_5825), 108 }, 109 110 {.regDmnEnum = APL2, 111 .conformanceTestLimit = FCC, 112 .chan11a = BM1(F1_5745_5805), 113 }, 114 115 {.regDmnEnum = APL3, 116 .conformanceTestLimit = FCC, 117 .chan11a = BM2(F1_5280_5320, F2_5745_5805), 118 }, 119 120 {.regDmnEnum = APL4, 121 .conformanceTestLimit = FCC, 122 .chan11a = BM2(F4_5180_5240, F3_5745_5825), 123 }, 124 125 {.regDmnEnum = APL5, 126 .conformanceTestLimit = FCC, 127 .chan11a = BM1(F2_5745_5825), 128 }, 129 130 {.regDmnEnum = APL6, 131 .conformanceTestLimit = ETSI, 132 .dfsMask = DFS_ETSI, 133 .pscan = PSCAN_FCC_T | PSCAN_FCC, 134 .chan11a = BM3(F4_5180_5240, F2_5260_5320, F3_5745_5825), 135 .chan11a_turbo = BM3(T2_5210_5210, T1_5250_5290, T1_5760_5800), 136 }, 137 138 {.regDmnEnum = APL8, 139 .conformanceTestLimit = ETSI, 140 .flags = DISALLOW_ADHOC_11A|DISALLOW_ADHOC_11A_TURB, 141 .chan11a = BM2(F6_5260_5320, F4_5745_5825), 142 }, 143 144 {.regDmnEnum = APL9, 145 .conformanceTestLimit = ETSI, 146 .dfsMask = DFS_ETSI, 147 .pscan = PSCAN_ETSI, 148 .flags = DISALLOW_ADHOC_11A|DISALLOW_ADHOC_11A_TURB, 149 .chan11a = BM3(F1_5180_5320, F1_5500_5620, F3_5745_5805), 150 }, 151 152 {.regDmnEnum = ETSI1, 153 .conformanceTestLimit = ETSI, 154 .dfsMask = DFS_ETSI, 155 .pscan = PSCAN_ETSI, 156 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 157 .chan11a = BM3(W2_5180_5240, F2_5260_5320, F2_5500_5700), 158 }, 159 160 {.regDmnEnum = ETSI2, 161 .conformanceTestLimit = ETSI, 162 .dfsMask = DFS_ETSI, 163 .pscan = PSCAN_ETSI, 164 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 165 .chan11a = BM1(F3_5180_5240), 166 }, 167 168 {.regDmnEnum = ETSI3, 169 .conformanceTestLimit = ETSI, 170 .dfsMask = DFS_ETSI, 171 .pscan = PSCAN_ETSI, 172 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 173 .chan11a = BM2(W2_5180_5240, F2_5260_5320), 174 }, 175 176 {.regDmnEnum = ETSI4, 177 .conformanceTestLimit = ETSI, 178 .dfsMask = DFS_ETSI, 179 .pscan = PSCAN_ETSI, 180 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 181 .chan11a = BM2(F3_5180_5240, F1_5260_5320), 182 }, 183 184 {.regDmnEnum = ETSI5, 185 .conformanceTestLimit = ETSI, 186 .dfsMask = DFS_ETSI, 187 .pscan = PSCAN_ETSI, 188 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 189 .chan11a = BM1(F1_5180_5240), 190 }, 191 192 {.regDmnEnum = ETSI6, 193 .conformanceTestLimit = ETSI, 194 .dfsMask = DFS_ETSI, 195 .pscan = PSCAN_ETSI, 196 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 197 .chan11a = BM3(F5_5180_5240, F1_5260_5280, F3_5500_5700), 198 }, 199 200 {.regDmnEnum = FCC1, 201 .conformanceTestLimit = FCC, 202 .chan11a = BM3(F2_5180_5240, F4_5260_5320, F5_5745_5825), 203 .chan11a_turbo = BM3(T1_5210_5210, T2_5250_5290, T2_5760_5800), 204 .chan11a_dyn_turbo = BM3(T1_5200_5240, T1_5280_5280, T1_5765_5805), 205 }, 206 207 {.regDmnEnum = FCC2, 208 .conformanceTestLimit = FCC, 209 .chan11a = BM3(F6_5180_5240, F5_5260_5320, F6_5745_5825), 210 .chan11a_dyn_turbo = BM3(T2_5200_5240, T1_5280_5280, T1_5765_5805), 211 }, 212 213 {.regDmnEnum = FCC3, 214 .conformanceTestLimit = FCC, 215 .dfsMask = DFS_FCC3, 216 .pscan = PSCAN_FCC | PSCAN_FCC_T, 217 .chan11a = BM4(F2_5180_5240, 218 F3_5260_5320, 219 F1_5500_5700, 220 F5_5745_5825), 221 .chan11a_turbo = BM4(T1_5210_5210, 222 T1_5250_5250, 223 T1_5290_5290, 224 T2_5760_5800), 225 .chan11a_dyn_turbo = BM3(T1_5200_5240, T2_5280_5280, T1_5540_5660), 226 }, 227 228 {.regDmnEnum = FCC4, 229 .conformanceTestLimit = FCC, 230 .dfsMask = DFS_FCC3, 231 .pscan = PSCAN_FCC | PSCAN_FCC_T, 232 .chan11a = BM1(F1_4950_4980), 233 .chan11a_half = BM1(F1_4945_4985), 234 .chan11a_quarter = BM1(F1_4942_4987), 235 }, 236 237 /* FCC1 w/ 1/2 and 1/4 width channels */ 238 {.regDmnEnum = FCC5, 239 .conformanceTestLimit = FCC, 240 .chan11a = BM3(F2_5180_5240, F4_5260_5320, F5_5745_5825), 241 .chan11a_turbo = BM3(T1_5210_5210, T2_5250_5290, T2_5760_5800), 242 .chan11a_dyn_turbo = BM3(T1_5200_5240, T1_5280_5280, T1_5765_5805), 243 .chan11a_half = BM3(F7_5180_5240, F7_5260_5320, F9_5745_5825), 244 .chan11a_quarter = BM3(F8_5180_5240, F8_5260_5320,F10_5745_5825), 245 }, 246 247 {.regDmnEnum = FCC6, 248 .conformanceTestLimit = FCC, 249 .chan11a = BM5(F8_5180_5240, F5_5260_5320, F1_5500_5580, F2_5660_5720, F6_5745_5825), 250 .chan11a_turbo = BM3(T7_5210_5210, T3_5250_5290, T2_5760_5800), 251 .chan11a_dyn_turbo = BM4(T7_5200_5200, T1_5240_5240, T2_5280_5280, T1_5765_5805), 252 #if 0 253 .chan11a_half = BM3(F7_5180_5240, F7_5260_5320, F9_5745_5825), 254 .chan11a_quarter = BM3(F8_5180_5240, F8_5260_5320,F10_5745_5825), 255 #endif 256 }, 257 258 {.regDmnEnum = MKK1, 259 .conformanceTestLimit = MKK, 260 .pscan = PSCAN_MKK1, 261 .flags = DISALLOW_ADHOC_11A_TURB, 262 .chan11a = BM1(F1_5170_5230), 263 }, 264 265 {.regDmnEnum = MKK2, 266 .conformanceTestLimit = MKK, 267 .pscan = PSCAN_MKK2, 268 .flags = DISALLOW_ADHOC_11A_TURB, 269 .chan11a = BM3(F1_4920_4980, F1_5040_5080, F1_5170_5230), 270 .chan11a_half = BM4(F1_4915_4925, 271 F1_4935_4945, 272 F1_5035_5040, 273 F1_5055_5055), 274 }, 275 276 /* UNI-1 even */ 277 {.regDmnEnum = MKK3, 278 .conformanceTestLimit = MKK, 279 .pscan = PSCAN_MKK3, 280 .flags = DISALLOW_ADHOC_11A_TURB, 281 .chan11a = BM1(F4_5180_5240), 282 }, 283 284 /* UNI-1 even + UNI-2 */ 285 {.regDmnEnum = MKK4, 286 .conformanceTestLimit = MKK, 287 .dfsMask = DFS_MKK4, 288 .pscan = PSCAN_MKK3, 289 .flags = DISALLOW_ADHOC_11A_TURB, 290 .chan11a = BM2(F4_5180_5240, F2_5260_5320), 291 }, 292 293 /* UNI-1 even + UNI-2 + mid-band */ 294 {.regDmnEnum = MKK5, 295 .conformanceTestLimit = MKK, 296 .dfsMask = DFS_MKK4, 297 .pscan = PSCAN_MKK3, 298 .flags = DISALLOW_ADHOC_11A_TURB, 299 .chan11a = BM3(F4_5180_5240, F2_5260_5320, F4_5500_5700), 300 }, 301 302 /* UNI-1 odd + even */ 303 {.regDmnEnum = MKK6, 304 .conformanceTestLimit = MKK, 305 .pscan = PSCAN_MKK1, 306 .flags = DISALLOW_ADHOC_11A_TURB, 307 .chan11a = BM2(F2_5170_5230, F4_5180_5240), 308 }, 309 310 /* UNI-1 odd + UNI-1 even + UNI-2 */ 311 {.regDmnEnum = MKK7, 312 .conformanceTestLimit = MKK, 313 .dfsMask = DFS_MKK4, 314 .pscan = PSCAN_MKK1 | PSCAN_MKK3, 315 .flags = DISALLOW_ADHOC_11A_TURB, 316 .chan11a = BM3(F1_5170_5230, F4_5180_5240, F2_5260_5320), 317 }, 318 319 /* UNI-1 odd + UNI-1 even + UNI-2 + mid-band */ 320 {.regDmnEnum = MKK8, 321 .conformanceTestLimit = MKK, 322 .dfsMask = DFS_MKK4, 323 .pscan = PSCAN_MKK1 | PSCAN_MKK3, 324 .flags = DISALLOW_ADHOC_11A_TURB, 325 .chan11a = BM4(F1_5170_5230, 326 F4_5180_5240, 327 F2_5260_5320, 328 F4_5500_5700), 329 }, 330 331 /* UNI-1 even + 4.9 GHZ */ 332 {.regDmnEnum = MKK9, 333 .conformanceTestLimit = MKK, 334 .pscan = PSCAN_MKK3, 335 .flags = DISALLOW_ADHOC_11A_TURB, 336 .chan11a = BM7(F1_4915_4925, 337 F1_4935_4945, 338 F1_4920_4980, 339 F1_5035_5040, 340 F1_5055_5055, 341 F1_5040_5080, 342 F4_5180_5240), 343 }, 344 345 /* UNI-1 even + UNI-2 + 4.9 GHZ */ 346 {.regDmnEnum = MKK10, 347 .conformanceTestLimit = MKK, 348 .dfsMask = DFS_MKK4, 349 .pscan = PSCAN_MKK3, 350 .flags = DISALLOW_ADHOC_11A_TURB, 351 .chan11a = BM8(F1_4915_4925, 352 F1_4935_4945, 353 F1_4920_4980, 354 F1_5035_5040, 355 F1_5055_5055, 356 F1_5040_5080, 357 F4_5180_5240, 358 F2_5260_5320), 359 }, 360 361 /* Defined here to use when 2G channels are authorised for country K2 */ 362 {.regDmnEnum = APLD, 363 .conformanceTestLimit = NO_CTL, 364 .chan11b = BM2(F2_2312_2372,F2_2412_2472), 365 .chan11g = BM2(G2_2312_2372,G2_2412_2472), 366 }, 367 368 {.regDmnEnum = ETSIA, 369 .conformanceTestLimit = NO_CTL, 370 .pscan = PSCAN_ETSIA, 371 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 372 .chan11b = BM1(F1_2457_2472), 373 .chan11g = BM1(G1_2457_2472), 374 .chan11g_turbo = BM1(T2_2437_2437) 375 }, 376 377 {.regDmnEnum = ETSIB, 378 .conformanceTestLimit = ETSI, 379 .pscan = PSCAN_ETSIB, 380 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 381 .chan11b = BM1(F1_2432_2442), 382 .chan11g = BM1(G1_2432_2442), 383 .chan11g_turbo = BM1(T2_2437_2437) 384 }, 385 386 {.regDmnEnum = ETSIC, 387 .conformanceTestLimit = ETSI, 388 .pscan = PSCAN_ETSIC, 389 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 390 .chan11b = BM1(F3_2412_2472), 391 .chan11g = BM1(G3_2412_2472), 392 .chan11g_turbo = BM1(T2_2437_2437) 393 }, 394 395 {.regDmnEnum = FCCA, 396 .conformanceTestLimit = FCC, 397 .chan11b = BM1(F1_2412_2462), 398 .chan11g = BM1(G1_2412_2462), 399 .chan11g_turbo = BM1(T2_2437_2437), 400 }, 401 402 /* FCCA w/ 1/2 and 1/4 width channels */ 403 {.regDmnEnum = FCCB, 404 .conformanceTestLimit = FCC, 405 .chan11b = BM1(F1_2412_2462), 406 .chan11g = BM1(G1_2412_2462), 407 .chan11g_turbo = BM1(T2_2437_2437), 408 .chan11g_half = BM1(G3_2412_2462), 409 .chan11g_quarter = BM1(G4_2412_2462), 410 }, 411 412 {.regDmnEnum = MKKA, 413 .conformanceTestLimit = MKK, 414 .pscan = PSCAN_MKKA | PSCAN_MKKA_G 415 | PSCAN_MKKA1 | PSCAN_MKKA1_G 416 | PSCAN_MKKA2 | PSCAN_MKKA2_G, 417 .flags = DISALLOW_ADHOC_11A_TURB, 418 .chan11b = BM3(F2_2412_2462, F1_2467_2472, F2_2484_2484), 419 .chan11g = BM2(G2_2412_2462, G1_2467_2472), 420 .chan11g_turbo = BM1(T2_2437_2437) 421 }, 422 423 {.regDmnEnum = MKKC, 424 .conformanceTestLimit = MKK, 425 .chan11b = BM1(F2_2412_2472), 426 .chan11g = BM1(G2_2412_2472), 427 .chan11g_turbo = BM1(T2_2437_2437) 428 }, 429 430 {.regDmnEnum = WORLD, 431 .conformanceTestLimit = ETSI, 432 .chan11b = BM1(F2_2412_2472), 433 .chan11g = BM1(G2_2412_2472), 434 .chan11g_turbo = BM1(T2_2437_2437) 435 }, 436 437 {.regDmnEnum = WOR0_WORLD, 438 .conformanceTestLimit = NO_CTL, 439 .dfsMask = DFS_FCC3 | DFS_ETSI, 440 .pscan = PSCAN_WWR, 441 .flags = ADHOC_PER_11D, 442 .chan11a = BM5(W1_5260_5320, 443 W1_5180_5240, 444 W1_5170_5230, 445 W1_5745_5825, 446 W1_5500_5700), 447 .chan11a_turbo = BM3(WT1_5210_5250, 448 WT1_5290_5290, 449 WT1_5760_5800), 450 .chan11b = BM8(W1_2412_2412, 451 W1_2437_2442, 452 W1_2462_2462, 453 W1_2472_2472, 454 W1_2417_2432, 455 W1_2447_2457, 456 W1_2467_2467, 457 W1_2484_2484), 458 .chan11g = BM7(WG1_2412_2412, 459 WG1_2437_2442, 460 WG1_2462_2462, 461 WG1_2472_2472, 462 WG1_2417_2432, 463 WG1_2447_2457, 464 WG1_2467_2467), 465 .chan11g_turbo = BM1(T3_2437_2437) 466 }, 467 468 {.regDmnEnum = WOR01_WORLD, 469 .conformanceTestLimit = NO_CTL, 470 .dfsMask = DFS_FCC3 | DFS_ETSI, 471 .pscan = PSCAN_WWR, 472 .flags = ADHOC_PER_11D, 473 .chan11a = BM5(W1_5260_5320, 474 W1_5180_5240, 475 W1_5170_5230, 476 W1_5745_5825, 477 W1_5500_5700), 478 .chan11a_turbo = BM3(WT1_5210_5250, 479 WT1_5290_5290, 480 WT1_5760_5800), 481 .chan11b = BM5(W1_2412_2412, 482 W1_2437_2442, 483 W1_2462_2462, 484 W1_2417_2432, 485 W1_2447_2457), 486 .chan11g = BM5(WG1_2412_2412, 487 WG1_2437_2442, 488 WG1_2462_2462, 489 WG1_2417_2432, 490 WG1_2447_2457), 491 .chan11g_turbo = BM1(T3_2437_2437)}, 492 493 {.regDmnEnum = WOR02_WORLD, 494 .conformanceTestLimit = NO_CTL, 495 .dfsMask = DFS_FCC3 | DFS_ETSI, 496 .pscan = PSCAN_WWR, 497 .flags = ADHOC_PER_11D, 498 .chan11a = BM5(W1_5260_5320, 499 W1_5180_5240, 500 W1_5170_5230, 501 W1_5745_5825, 502 W1_5500_5700), 503 .chan11a_turbo = BM3(WT1_5210_5250, 504 WT1_5290_5290, 505 WT1_5760_5800), 506 .chan11b = BM7(W1_2412_2412, 507 W1_2437_2442, 508 W1_2462_2462, 509 W1_2472_2472, 510 W1_2417_2432, 511 W1_2447_2457, 512 W1_2467_2467), 513 .chan11g = BM7(WG1_2412_2412, 514 WG1_2437_2442, 515 WG1_2462_2462, 516 WG1_2472_2472, 517 WG1_2417_2432, 518 WG1_2447_2457, 519 WG1_2467_2467), 520 .chan11g_turbo = BM1(T3_2437_2437)}, 521 522 {.regDmnEnum = EU1_WORLD, 523 .conformanceTestLimit = NO_CTL, 524 .dfsMask = DFS_FCC3 | DFS_ETSI, 525 .pscan = PSCAN_WWR, 526 .flags = ADHOC_PER_11D, 527 .chan11a = BM5(W1_5260_5320, 528 W1_5180_5240, 529 W1_5170_5230, 530 W1_5745_5825, 531 W1_5500_5700), 532 .chan11a_turbo = BM3(WT1_5210_5250, 533 WT1_5290_5290, 534 WT1_5760_5800), 535 .chan11b = BM7(W1_2412_2412, 536 W1_2437_2442, 537 W1_2462_2462, 538 W2_2472_2472, 539 W1_2417_2432, 540 W1_2447_2457, 541 W2_2467_2467), 542 .chan11g = BM7(WG1_2412_2412, 543 WG1_2437_2442, 544 WG1_2462_2462, 545 WG2_2472_2472, 546 WG1_2417_2432, 547 WG1_2447_2457, 548 WG2_2467_2467), 549 .chan11g_turbo = BM1(T3_2437_2437)}, 550 551 {.regDmnEnum = WOR1_WORLD, 552 .conformanceTestLimit = NO_CTL, 553 .dfsMask = DFS_FCC3 | DFS_ETSI, 554 .pscan = PSCAN_WWR, 555 .flags = DISALLOW_ADHOC_11A, 556 .chan11a = BM5(W1_5260_5320, 557 W1_5180_5240, 558 W1_5170_5230, 559 W1_5745_5825, 560 W1_5500_5700), 561 .chan11b = BM8(W1_2412_2412, 562 W1_2437_2442, 563 W1_2462_2462, 564 W1_2472_2472, 565 W1_2417_2432, 566 W1_2447_2457, 567 W1_2467_2467, 568 W1_2484_2484), 569 .chan11g = BM7(WG1_2412_2412, 570 WG1_2437_2442, 571 WG1_2462_2462, 572 WG1_2472_2472, 573 WG1_2417_2432, 574 WG1_2447_2457, 575 WG1_2467_2467), 576 .chan11g_turbo = BM1(T3_2437_2437) 577 }, 578 579 {.regDmnEnum = WOR2_WORLD, 580 .conformanceTestLimit = NO_CTL, 581 .dfsMask = DFS_FCC3 | DFS_ETSI, 582 .pscan = PSCAN_WWR, 583 .flags = DISALLOW_ADHOC_11A, 584 .chan11a = BM5(W1_5260_5320, 585 W1_5180_5240, 586 W1_5170_5230, 587 W1_5745_5825, 588 W1_5500_5700), 589 .chan11a_turbo = BM3(WT1_5210_5250, 590 WT1_5290_5290, 591 WT1_5760_5800), 592 .chan11b = BM8(W1_2412_2412, 593 W1_2437_2442, 594 W1_2462_2462, 595 W1_2472_2472, 596 W1_2417_2432, 597 W1_2447_2457, 598 W1_2467_2467, 599 W1_2484_2484), 600 .chan11g = BM7(WG1_2412_2412, 601 WG1_2437_2442, 602 WG1_2462_2462, 603 WG1_2472_2472, 604 WG1_2417_2432, 605 WG1_2447_2457, 606 WG1_2467_2467), 607 .chan11g_turbo = BM1(T3_2437_2437)}, 608 609 {.regDmnEnum = WOR3_WORLD, 610 .conformanceTestLimit = NO_CTL, 611 .dfsMask = DFS_FCC3 | DFS_ETSI, 612 .pscan = PSCAN_WWR, 613 .flags = ADHOC_PER_11D, 614 .chan11a = BM4(W1_5260_5320, 615 W1_5180_5240, 616 W1_5170_5230, 617 W1_5745_5825), 618 .chan11a_turbo = BM3(WT1_5210_5250, 619 WT1_5290_5290, 620 WT1_5760_5800), 621 .chan11b = BM7(W1_2412_2412, 622 W1_2437_2442, 623 W1_2462_2462, 624 W1_2472_2472, 625 W1_2417_2432, 626 W1_2447_2457, 627 W1_2467_2467), 628 .chan11g = BM7(WG1_2412_2412, 629 WG1_2437_2442, 630 WG1_2462_2462, 631 WG1_2472_2472, 632 WG1_2417_2432, 633 WG1_2447_2457, 634 WG1_2467_2467), 635 .chan11g_turbo = BM1(T3_2437_2437)}, 636 637 {.regDmnEnum = WOR4_WORLD, 638 .conformanceTestLimit = NO_CTL, 639 .dfsMask = DFS_FCC3 | DFS_ETSI, 640 .pscan = PSCAN_WWR, 641 .flags = DISALLOW_ADHOC_11A, 642 .chan11a = BM4(W2_5260_5320, 643 W2_5180_5240, 644 F2_5745_5805, 645 W2_5825_5825), 646 .chan11a_turbo = BM3(WT1_5210_5250, 647 WT1_5290_5290, 648 WT1_5760_5800), 649 .chan11b = BM5(W1_2412_2412, 650 W1_2437_2442, 651 W1_2462_2462, 652 W1_2417_2432, 653 W1_2447_2457), 654 .chan11g = BM5(WG1_2412_2412, 655 WG1_2437_2442, 656 WG1_2462_2462, 657 WG1_2417_2432, 658 WG1_2447_2457), 659 .chan11g_turbo = BM1(T3_2437_2437)}, 660 661 {.regDmnEnum = WOR5_ETSIC, 662 .conformanceTestLimit = NO_CTL, 663 .dfsMask = DFS_FCC3 | DFS_ETSI, 664 .pscan = PSCAN_WWR, 665 .flags = DISALLOW_ADHOC_11A, 666 .chan11a = BM3(W1_5260_5320, W2_5180_5240, F6_5745_5825), 667 .chan11b = BM7(W1_2412_2412, 668 W1_2437_2442, 669 W1_2462_2462, 670 W2_2472_2472, 671 W1_2417_2432, 672 W1_2447_2457, 673 W2_2467_2467), 674 .chan11g = BM7(WG1_2412_2412, 675 WG1_2437_2442, 676 WG1_2462_2462, 677 WG2_2472_2472, 678 WG1_2417_2432, 679 WG1_2447_2457, 680 WG2_2467_2467), 681 .chan11g_turbo = BM1(T3_2437_2437)}, 682 683 {.regDmnEnum = WOR9_WORLD, 684 .conformanceTestLimit = NO_CTL, 685 .dfsMask = DFS_FCC3 | DFS_ETSI, 686 .pscan = PSCAN_WWR, 687 .flags = DISALLOW_ADHOC_11A, 688 .chan11a = BM4(W1_5260_5320, 689 W1_5180_5240, 690 W1_5745_5825, 691 W1_5500_5700), 692 .chan11a_turbo = BM3(WT1_5210_5250, 693 WT1_5290_5290, 694 WT1_5760_5800), 695 .chan11b = BM5(W1_2412_2412, 696 W1_2437_2442, 697 W1_2462_2462, 698 W1_2417_2432, 699 W1_2447_2457), 700 .chan11g = BM5(WG1_2412_2412, 701 WG1_2437_2442, 702 WG1_2462_2462, 703 WG1_2417_2432, 704 WG1_2447_2457), 705 .chan11g_turbo = BM1(T3_2437_2437)}, 706 707 {.regDmnEnum = WORA_WORLD, 708 .conformanceTestLimit = NO_CTL, 709 .dfsMask = DFS_FCC3 | DFS_ETSI, 710 .pscan = PSCAN_WWR, 711 .flags = DISALLOW_ADHOC_11A, 712 .chan11a = BM4(W1_5260_5320, 713 W1_5180_5240, 714 W1_5745_5825, 715 W1_5500_5700), 716 .chan11b = BM7(W1_2412_2412, 717 W1_2437_2442, 718 W1_2462_2462, 719 W1_2472_2472, 720 W1_2417_2432, 721 W1_2447_2457, 722 W1_2467_2467), 723 .chan11g = BM7(WG1_2412_2412, 724 WG1_2437_2442, 725 WG1_2462_2462, 726 WG1_2472_2472, 727 WG1_2417_2432, 728 WG1_2447_2457, 729 WG1_2467_2467), 730 .chan11g_turbo = BM1(T3_2437_2437)}, 731 732 {.regDmnEnum = WORB_WORLD, 733 .conformanceTestLimit = NO_CTL, 734 .dfsMask = DFS_FCC3 | DFS_ETSI, 735 .pscan = PSCAN_WWR, 736 .flags = DISALLOW_ADHOC_11A, 737 .chan11a = BM4(W1_5260_5320, 738 W1_5180_5240, 739 W1_5745_5825, 740 W1_5500_5700), 741 .chan11b = BM7(W1_2412_2412, 742 W1_2437_2442, 743 W1_2462_2462, 744 W1_2472_2472, 745 W1_2417_2432, 746 W1_2447_2457, 747 W1_2467_2467), 748 .chan11g = BM7(WG1_2412_2412, 749 WG1_2437_2442, 750 WG1_2462_2462, 751 WG1_2472_2472, 752 WG1_2417_2432, 753 WG1_2447_2457, 754 WG1_2467_2467), 755 .chan11g_turbo = BM1(T3_2437_2437)}, 756 757 {.regDmnEnum = WORC_WORLD, 758 .conformanceTestLimit = NO_CTL, 759 .dfsMask = DFS_FCC3 | DFS_ETSI, 760 .pscan = PSCAN_WWR, 761 .flags = ADHOC_PER_11D, 762 .chan11a = BM4(W1_5260_5320, 763 W1_5180_5240, 764 W1_5745_5825, 765 W1_5500_5700), 766 .chan11b = BM7(W1_2412_2412, 767 W1_2437_2442, 768 W1_2462_2462, 769 W1_2472_2472, 770 W1_2417_2432, 771 W1_2447_2457, 772 W1_2467_2467), 773 .chan11g = BM7(WG1_2412_2412, 774 WG1_2437_2442, 775 WG1_2462_2462, 776 WG1_2472_2472, 777 WG1_2417_2432, 778 WG1_2447_2457, 779 WG1_2467_2467), 780 .chan11g_turbo = BM1(T3_2437_2437)}, 781 782 {.regDmnEnum = NULL1, 783 .conformanceTestLimit = NO_CTL, 784 } 785 }; 786 787 #endif 788