1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD$ 20 */ 21 #include "opt_ah.h" 22 23 #include "ah.h" 24 #include "ah_internal.h" 25 #include "ah_desc.h" 26 27 #include "ar5212/ar5212.h" 28 #include "ar5212/ar5212reg.h" 29 #include "ar5212/ar5212desc.h" 30 31 /* 32 * Get the RXDP. 33 */ 34 uint32_t 35 ar5212GetRxDP(struct ath_hal *ath, HAL_RX_QUEUE qtype) 36 { 37 38 HALASSERT(qtype == HAL_RX_QUEUE_HP); 39 return OS_REG_READ(ath, AR_RXDP); 40 } 41 42 /* 43 * Set the RxDP. 44 */ 45 void 46 ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE qtype) 47 { 48 49 HALASSERT(qtype == HAL_RX_QUEUE_HP); 50 OS_REG_WRITE(ah, AR_RXDP, rxdp); 51 HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp); 52 } 53 54 /* 55 * Set Receive Enable bits. 56 */ 57 void 58 ar5212EnableReceive(struct ath_hal *ah) 59 { 60 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE); 61 } 62 63 /* 64 * Stop Receive at the DMA engine 65 */ 66 HAL_BOOL 67 ar5212StopDmaReceive(struct ath_hal *ah) 68 { 69 OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP); 70 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ 71 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) { 72 OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP_ERR); 73 #ifdef AH_DEBUG 74 ath_hal_printf(ah, "%s: dma failed to stop in 10ms\n" 75 "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n", 76 __func__, 77 OS_REG_READ(ah, AR_CR), 78 OS_REG_READ(ah, AR_DIAG_SW)); 79 #endif 80 return AH_FALSE; 81 } else { 82 return AH_TRUE; 83 } 84 } 85 86 /* 87 * Start Transmit at the PCU engine (unpause receive) 88 */ 89 void 90 ar5212StartPcuReceive(struct ath_hal *ah) 91 { 92 struct ath_hal_private *ahp = AH_PRIVATE(ah); 93 94 OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_PCU_START); 95 OS_REG_WRITE(ah, AR_DIAG_SW, 96 OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS); 97 ar5212EnableMibCounters(ah); 98 /* NB: restore current settings */ 99 ar5212AniReset(ah, ahp->ah_curchan, ahp->ah_opmode, AH_TRUE); 100 } 101 102 /* 103 * Stop Transmit at the PCU engine (pause receive) 104 */ 105 void 106 ar5212StopPcuReceive(struct ath_hal *ah) 107 { 108 OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_PCU_STOP); 109 OS_REG_WRITE(ah, AR_DIAG_SW, 110 OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS); 111 ar5212DisableMibCounters(ah); 112 } 113 114 /* 115 * Set multicast filter 0 (lower 32-bits) 116 * filter 1 (upper 32-bits) 117 */ 118 void 119 ar5212SetMulticastFilter(struct ath_hal *ah, uint32_t filter0, uint32_t filter1) 120 { 121 OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0); 122 OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1); 123 } 124 125 /* 126 * Clear multicast filter by index 127 */ 128 HAL_BOOL 129 ar5212ClrMulticastFilterIndex(struct ath_hal *ah, uint32_t ix) 130 { 131 uint32_t val; 132 133 if (ix >= 64) 134 return AH_FALSE; 135 if (ix >= 32) { 136 val = OS_REG_READ(ah, AR_MCAST_FIL1); 137 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32)))); 138 } else { 139 val = OS_REG_READ(ah, AR_MCAST_FIL0); 140 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix))); 141 } 142 return AH_TRUE; 143 } 144 145 /* 146 * Set multicast filter by index 147 */ 148 HAL_BOOL 149 ar5212SetMulticastFilterIndex(struct ath_hal *ah, uint32_t ix) 150 { 151 uint32_t val; 152 153 if (ix >= 64) 154 return AH_FALSE; 155 if (ix >= 32) { 156 val = OS_REG_READ(ah, AR_MCAST_FIL1); 157 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32)))); 158 } else { 159 val = OS_REG_READ(ah, AR_MCAST_FIL0); 160 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix))); 161 } 162 return AH_TRUE; 163 } 164 165 /* 166 * Get the receive filter. 167 */ 168 uint32_t 169 ar5212GetRxFilter(struct ath_hal *ah) 170 { 171 uint32_t bits = OS_REG_READ(ah, AR_RX_FILTER); 172 uint32_t phybits = OS_REG_READ(ah, AR_PHY_ERR); 173 if (phybits & AR_PHY_ERR_RADAR) 174 bits |= HAL_RX_FILTER_PHYRADAR; 175 if (phybits & (AR_PHY_ERR_OFDM_TIMING|AR_PHY_ERR_CCK_TIMING)) 176 bits |= HAL_RX_FILTER_PHYERR; 177 if (AH_PRIVATE(ah)->ah_caps.halBssidMatchSupport && 178 (AH5212(ah)->ah_miscMode & AR_MISC_MODE_BSSID_MATCH_FORCE)) 179 bits |= HAL_RX_FILTER_BSSID; 180 return bits; 181 } 182 183 /* 184 * Set the receive filter. 185 */ 186 void 187 ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits) 188 { 189 struct ath_hal_5212 *ahp = AH5212(ah); 190 uint32_t phybits; 191 192 OS_REG_WRITE(ah, AR_RX_FILTER, 193 bits &~ (HAL_RX_FILTER_PHYRADAR|HAL_RX_FILTER_PHYERR| 194 HAL_RX_FILTER_BSSID)); 195 phybits = 0; 196 if (bits & HAL_RX_FILTER_PHYRADAR) 197 phybits |= AR_PHY_ERR_RADAR; 198 if (bits & HAL_RX_FILTER_PHYERR) 199 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 200 OS_REG_WRITE(ah, AR_PHY_ERR, phybits); 201 if (phybits) { 202 OS_REG_WRITE(ah, AR_RXCFG, 203 OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); 204 } else { 205 OS_REG_WRITE(ah, AR_RXCFG, 206 OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA); 207 } 208 if (AH_PRIVATE(ah)->ah_caps.halBssidMatchSupport) { 209 if (bits & HAL_RX_FILTER_BSSID) 210 ahp->ah_miscMode |= AR_MISC_MODE_BSSID_MATCH_FORCE; 211 else 212 ahp->ah_miscMode &= ~AR_MISC_MODE_BSSID_MATCH_FORCE; 213 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 214 } 215 } 216 217 /* 218 * Initialize RX descriptor, by clearing the status and setting 219 * the size (and any other flags). 220 */ 221 HAL_BOOL 222 ar5212SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds, 223 uint32_t size, u_int flags) 224 { 225 struct ar5212_desc *ads = AR5212DESC(ds); 226 227 HALASSERT((size &~ AR_BufLen) == 0); 228 229 ads->ds_ctl0 = 0; 230 ads->ds_ctl1 = size & AR_BufLen; 231 232 if (flags & HAL_RXDESC_INTREQ) 233 ads->ds_ctl1 |= AR_RxInterReq; 234 ads->ds_rxstatus0 = ads->ds_rxstatus1 = 0; 235 236 return AH_TRUE; 237 } 238 239 /* 240 * Process an RX descriptor, and return the status to the caller. 241 * Copy some hardware specific items into the software portion 242 * of the descriptor. 243 * 244 * NB: the caller is responsible for validating the memory contents 245 * of the descriptor (e.g. flushing any cached copy). 246 */ 247 HAL_STATUS 248 ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds, 249 uint32_t pa, struct ath_desc *nds, uint64_t tsf, 250 struct ath_rx_status *rs) 251 { 252 struct ar5212_desc *ads = AR5212DESC(ds); 253 struct ar5212_desc *ands = AR5212DESC(nds); 254 255 if ((ads->ds_rxstatus1 & AR_Done) == 0) 256 return HAL_EINPROGRESS; 257 /* 258 * Given the use of a self-linked tail be very sure that the hw is 259 * done with this descriptor; the hw may have done this descriptor 260 * once and picked it up again...make sure the hw has moved on. 261 */ 262 if ((ands->ds_rxstatus1&AR_Done) == 0 && OS_REG_READ(ah, AR_RXDP) == pa) 263 return HAL_EINPROGRESS; 264 265 rs->rs_datalen = ads->ds_rxstatus0 & AR_DataLen; 266 rs->rs_tstamp = MS(ads->ds_rxstatus1, AR_RcvTimestamp); 267 rs->rs_status = 0; 268 /* XXX what about KeyCacheMiss? */ 269 rs->rs_rssi = MS(ads->ds_rxstatus0, AR_RcvSigStrength); 270 /* discard invalid h/w rssi data */ 271 if (rs->rs_rssi == -128) 272 rs->rs_rssi = 0; 273 if (ads->ds_rxstatus1 & AR_KeyIdxValid) 274 rs->rs_keyix = MS(ads->ds_rxstatus1, AR_KeyIdx); 275 else 276 rs->rs_keyix = HAL_RXKEYIX_INVALID; 277 /* NB: caller expected to do rate table mapping */ 278 rs->rs_rate = MS(ads->ds_rxstatus0, AR_RcvRate); 279 rs->rs_antenna = MS(ads->ds_rxstatus0, AR_RcvAntenna); 280 rs->rs_more = (ads->ds_rxstatus0 & AR_More) ? 1 : 0; 281 282 /* 283 * The AR5413 (at least) sometimes sets both AR_CRCErr and 284 * AR_PHYErr when reporting radar pulses. In this instance 285 * set HAL_RXERR_PHY as well as HAL_RXERR_CRC and 286 * let the driver layer figure out what to do. 287 * 288 * See PR kern/169362. 289 */ 290 if ((ads->ds_rxstatus1 & AR_FrmRcvOK) == 0) { 291 /* 292 * These four bits should not be set together. The 293 * 5212 spec states a Michael error can only occur if 294 * DecryptCRCErr not set (and TKIP is used). Experience 295 * indicates however that you can also get Michael errors 296 * when a CRC error is detected, but these are specious. 297 * Consequently we filter them out here so we don't 298 * confuse and/or complicate drivers. 299 */ 300 if (ads->ds_rxstatus1 & AR_PHYErr) { 301 u_int phyerr; 302 303 rs->rs_status |= HAL_RXERR_PHY; 304 phyerr = MS(ads->ds_rxstatus1, AR_PHYErrCode); 305 rs->rs_phyerr = phyerr; 306 if (!AH5212(ah)->ah_hasHwPhyCounters && 307 phyerr != HAL_PHYERR_RADAR) 308 ar5212AniPhyErrReport(ah, rs); 309 } 310 311 if (ads->ds_rxstatus1 & AR_CRCErr) 312 rs->rs_status |= HAL_RXERR_CRC; 313 else if (ads->ds_rxstatus1 & AR_DecryptCRCErr) 314 rs->rs_status |= HAL_RXERR_DECRYPT; 315 else if (ads->ds_rxstatus1 & AR_MichaelErr) 316 rs->rs_status |= HAL_RXERR_MIC; 317 } 318 return HAL_OK; 319 } 320