114779705SSam Leffler /* 259efa8b5SSam Leffler * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 314779705SSam Leffler * Copyright (c) 2002-2008 Atheros Communications, Inc. 414779705SSam Leffler * 514779705SSam Leffler * Permission to use, copy, modify, and/or distribute this software for any 614779705SSam Leffler * purpose with or without fee is hereby granted, provided that the above 714779705SSam Leffler * copyright notice and this permission notice appear in all copies. 814779705SSam Leffler * 914779705SSam Leffler * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 1014779705SSam Leffler * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 1114779705SSam Leffler * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 1214779705SSam Leffler * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 1314779705SSam Leffler * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 1414779705SSam Leffler * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 1514779705SSam Leffler * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 1614779705SSam Leffler * 178698ea65SSam Leffler * $FreeBSD$ 1814779705SSam Leffler */ 1914779705SSam Leffler #include "opt_ah.h" 2014779705SSam Leffler 2114779705SSam Leffler #include "ah.h" 2214779705SSam Leffler #include "ah_internal.h" 2314779705SSam Leffler #include "ah_devid.h" 2414779705SSam Leffler 2514779705SSam Leffler #include "ar5212/ar5212.h" 2614779705SSam Leffler #include "ar5212/ar5212reg.h" 2714779705SSam Leffler #include "ar5212/ar5212phy.h" 2814779705SSam Leffler 2914779705SSam Leffler #include "ah_eeprom_v3.h" 3014779705SSam Leffler 3114779705SSam Leffler /* Additional Time delay to wait after activiting the Base band */ 3214779705SSam Leffler #define BASE_ACTIVATE_DELAY 100 /* 100 usec */ 3314779705SSam Leffler #define PLL_SETTLE_DELAY 300 /* 300 usec */ 3414779705SSam Leffler 3514779705SSam Leffler static HAL_BOOL ar5212SetResetReg(struct ath_hal *, uint32_t resetMask); 3614779705SSam Leffler /* NB: public for 5312 use */ 3759efa8b5SSam Leffler HAL_BOOL ar5212IsSpurChannel(struct ath_hal *, 3859efa8b5SSam Leffler const struct ieee80211_channel *); 3959efa8b5SSam Leffler HAL_BOOL ar5212ChannelChange(struct ath_hal *, 4059efa8b5SSam Leffler const struct ieee80211_channel *); 4159efa8b5SSam Leffler int16_t ar5212GetNf(struct ath_hal *, struct ieee80211_channel *); 4259efa8b5SSam Leffler HAL_BOOL ar5212SetBoardValues(struct ath_hal *, 4359efa8b5SSam Leffler const struct ieee80211_channel *); 4459efa8b5SSam Leffler void ar5212SetDeltaSlope(struct ath_hal *, 4559efa8b5SSam Leffler const struct ieee80211_channel *); 4614779705SSam Leffler HAL_BOOL ar5212SetTransmitPower(struct ath_hal *ah, 4759efa8b5SSam Leffler const struct ieee80211_channel *chan, uint16_t *rfXpdGain); 4814779705SSam Leffler static HAL_BOOL ar5212SetRateTable(struct ath_hal *, 4959efa8b5SSam Leffler const struct ieee80211_channel *, int16_t tpcScaleReduction, 5059efa8b5SSam Leffler int16_t powerLimit, 5114779705SSam Leffler HAL_BOOL commit, int16_t *minPower, int16_t *maxPower); 5214779705SSam Leffler static void ar5212CorrectGainDelta(struct ath_hal *, int twiceOfdmCckDelta); 5359efa8b5SSam Leffler static void ar5212GetTargetPowers(struct ath_hal *, 5459efa8b5SSam Leffler const struct ieee80211_channel *, 5514779705SSam Leffler const TRGT_POWER_INFO *pPowerInfo, uint16_t numChannels, 5614779705SSam Leffler TRGT_POWER_INFO *pNewPower); 5714779705SSam Leffler static uint16_t ar5212GetMaxEdgePower(uint16_t channel, 5814779705SSam Leffler const RD_EDGES_POWER *pRdEdgesPower); 5959efa8b5SSam Leffler void ar5212SetRateDurationTable(struct ath_hal *, 6059efa8b5SSam Leffler const struct ieee80211_channel *); 6159efa8b5SSam Leffler void ar5212SetIFSTiming(struct ath_hal *, 6259efa8b5SSam Leffler const struct ieee80211_channel *); 6314779705SSam Leffler 6414779705SSam Leffler /* NB: public for RF backend use */ 6514779705SSam Leffler void ar5212GetLowerUpperValues(uint16_t value, 6614779705SSam Leffler uint16_t *pList, uint16_t listSize, 6714779705SSam Leffler uint16_t *pLowerValue, uint16_t *pUpperValue); 6814779705SSam Leffler void ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32, 6914779705SSam Leffler uint32_t numBits, uint32_t firstBit, uint32_t column); 7014779705SSam Leffler 7114779705SSam Leffler static int 7214779705SSam Leffler write_common(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 7314779705SSam Leffler HAL_BOOL bChannelChange, int writes) 7414779705SSam Leffler { 7514779705SSam Leffler #define IS_NO_RESET_TIMER_ADDR(x) \ 7614779705SSam Leffler ( (((x) >= AR_BEACON) && ((x) <= AR_CFP_DUR)) || \ 7714779705SSam Leffler (((x) >= AR_SLEEP1) && ((x) <= AR_SLEEP3))) 7814779705SSam Leffler #define V(r, c) (ia)->data[((r)*(ia)->cols) + (c)] 7914779705SSam Leffler int r; 8014779705SSam Leffler 8114779705SSam Leffler /* Write Common Array Parameters */ 8214779705SSam Leffler for (r = 0; r < ia->rows; r++) { 8314779705SSam Leffler uint32_t reg = V(r, 0); 8414779705SSam Leffler /* XXX timer/beacon setup registers? */ 8514779705SSam Leffler /* On channel change, don't reset the PCU registers */ 8614779705SSam Leffler if (!(bChannelChange && IS_NO_RESET_TIMER_ADDR(reg))) { 8714779705SSam Leffler OS_REG_WRITE(ah, reg, V(r, 1)); 8814779705SSam Leffler DMA_YIELD(writes); 8914779705SSam Leffler } 9014779705SSam Leffler } 9114779705SSam Leffler return writes; 9214779705SSam Leffler #undef IS_NO_RESET_TIMER_ADDR 9314779705SSam Leffler #undef V 9414779705SSam Leffler } 9514779705SSam Leffler 9614779705SSam Leffler #define IS_DISABLE_FAST_ADC_CHAN(x) (((x) == 2462) || ((x) == 2467)) 9714779705SSam Leffler 9814779705SSam Leffler /* 9914779705SSam Leffler * Places the device in and out of reset and then places sane 10014779705SSam Leffler * values in the registers based on EEPROM config, initialization 10114779705SSam Leffler * vectors (as determined by the mode), and station configuration 10214779705SSam Leffler * 10314779705SSam Leffler * bChannelChange is used to preserve DMA/PCU registers across 10414779705SSam Leffler * a HW Reset during channel change. 10514779705SSam Leffler */ 10614779705SSam Leffler HAL_BOOL 10714779705SSam Leffler ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode, 10859efa8b5SSam Leffler struct ieee80211_channel *chan, 10959efa8b5SSam Leffler HAL_BOOL bChannelChange, HAL_STATUS *status) 11014779705SSam Leffler { 11114779705SSam Leffler #define N(a) (sizeof (a) / sizeof (a[0])) 11214779705SSam Leffler #define FAIL(_code) do { ecode = _code; goto bad; } while (0) 11314779705SSam Leffler struct ath_hal_5212 *ahp = AH5212(ah); 11414779705SSam Leffler HAL_CHANNEL_INTERNAL *ichan = AH_NULL; 11514779705SSam Leffler const HAL_EEPROM *ee; 11614779705SSam Leffler uint32_t softLedCfg, softLedState; 11714779705SSam Leffler uint32_t saveFrameSeqCount, saveDefAntenna, saveLedState; 11814779705SSam Leffler uint32_t macStaId1, synthDelay, txFrm2TxDStart; 11914779705SSam Leffler uint16_t rfXpdGain[MAX_NUM_PDGAINS_PER_CHANNEL]; 12014779705SSam Leffler int16_t cckOfdmPwrDelta = 0; 12114779705SSam Leffler u_int modesIndex, freqIndex; 12214779705SSam Leffler HAL_STATUS ecode; 12314779705SSam Leffler int i, regWrites; 12414779705SSam Leffler uint32_t testReg, powerVal; 12514779705SSam Leffler int8_t twiceAntennaGain, twiceAntennaReduction; 12614779705SSam Leffler uint32_t ackTpcPow, ctsTpcPow, chirpTpcPow; 12714779705SSam Leffler HAL_BOOL isBmode = AH_FALSE; 12814779705SSam Leffler 12914779705SSam Leffler HALASSERT(ah->ah_magic == AR5212_MAGIC); 13014779705SSam Leffler ee = AH_PRIVATE(ah)->ah_eeprom; 13114779705SSam Leffler 13214779705SSam Leffler OS_MARK(ah, AH_MARK_RESET, bChannelChange); 13314779705SSam Leffler 13414779705SSam Leffler /* Bring out of sleep mode */ 13514779705SSam Leffler if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 13614779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip did not wakeup\n", 13714779705SSam Leffler __func__); 13814779705SSam Leffler FAIL(HAL_EIO); 13914779705SSam Leffler } 14014779705SSam Leffler 14114779705SSam Leffler /* 14214779705SSam Leffler * Map public channel to private. 14314779705SSam Leffler */ 14414779705SSam Leffler ichan = ath_hal_checkchannel(ah, chan); 14559efa8b5SSam Leffler if (ichan == AH_NULL) 14614779705SSam Leffler FAIL(HAL_EINVAL); 14714779705SSam Leffler switch (opmode) { 14814779705SSam Leffler case HAL_M_STA: 14914779705SSam Leffler case HAL_M_IBSS: 15014779705SSam Leffler case HAL_M_HOSTAP: 15114779705SSam Leffler case HAL_M_MONITOR: 15214779705SSam Leffler break; 15314779705SSam Leffler default: 15414779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n", 15514779705SSam Leffler __func__, opmode); 15614779705SSam Leffler FAIL(HAL_EINVAL); 15714779705SSam Leffler break; 15814779705SSam Leffler } 15914779705SSam Leffler HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3); 16014779705SSam Leffler 16114779705SSam Leffler SAVE_CCK(ah, chan, isBmode); 16214779705SSam Leffler 16314779705SSam Leffler /* Preserve certain DMA hardware registers on a channel change */ 16414779705SSam Leffler if (bChannelChange) { 16514779705SSam Leffler /* 16614779705SSam Leffler * On Venice, the TSF is almost preserved across a reset; 16714779705SSam Leffler * it requires doubling writes to the RESET_TSF 16814779705SSam Leffler * bit in the AR_BEACON register; it also has the quirk 16914779705SSam Leffler * of the TSF going back in time on the station (station 17014779705SSam Leffler * latches onto the last beacon's tsf during a reset 50% 17114779705SSam Leffler * of the times); the latter is not a problem for adhoc 17214779705SSam Leffler * stations since as long as the TSF is behind, it will 17314779705SSam Leffler * get resynchronized on receiving the next beacon; the 17414779705SSam Leffler * TSF going backwards in time could be a problem for the 17514779705SSam Leffler * sleep operation (supported on infrastructure stations 17614779705SSam Leffler * only) - the best and most general fix for this situation 17714779705SSam Leffler * is to resynchronize the various sleep/beacon timers on 17814779705SSam Leffler * the receipt of the next beacon i.e. when the TSF itself 17914779705SSam Leffler * gets resynchronized to the AP's TSF - power save is 18014779705SSam Leffler * needed to be temporarily disabled until that time 18114779705SSam Leffler * 18214779705SSam Leffler * Need to save the sequence number to restore it after 18314779705SSam Leffler * the reset! 18414779705SSam Leffler */ 18514779705SSam Leffler saveFrameSeqCount = OS_REG_READ(ah, AR_D_SEQNUM); 18614779705SSam Leffler } else 18714779705SSam Leffler saveFrameSeqCount = 0; /* NB: silence compiler */ 18814779705SSam Leffler #if 0 18914779705SSam Leffler /* 19014779705SSam Leffler * XXX disable for now; this appears to sometimes cause OFDM 19114779705SSam Leffler * XXX timing error floods when ani is enabled and bg scanning 19214779705SSam Leffler * XXX kicks in 19314779705SSam Leffler */ 19414779705SSam Leffler /* If the channel change is across the same mode - perform a fast channel change */ 19514779705SSam Leffler if (IS_2413(ah) || IS_5413(ah)) { 19614779705SSam Leffler /* 19714779705SSam Leffler * Fast channel change can only be used when: 19814779705SSam Leffler * -channel change requested - so it's not the initial reset. 19914779705SSam Leffler * -it's not a change to the current channel - 20014779705SSam Leffler * often called when switching modes on a channel 20114779705SSam Leffler * -the modes of the previous and requested channel are the 20214779705SSam Leffler * same 20314779705SSam Leffler * XXX opmode shouldn't change either? 20414779705SSam Leffler */ 20514779705SSam Leffler if (bChannelChange && 20614779705SSam Leffler (AH_PRIVATE(ah)->ah_curchan != AH_NULL) && 20759efa8b5SSam Leffler (chan->ic_freq != AH_PRIVATE(ah)->ah_curchan->ic_freq) && 20859efa8b5SSam Leffler ((chan->ic_flags & IEEE80211_CHAN_ALLTURBO) == 20959efa8b5SSam Leffler (AH_PRIVATE(ah)->ah_curchan->ic_flags & IEEE80211_CHAN_ALLTURBO))) { 21014779705SSam Leffler if (ar5212ChannelChange(ah, chan)) { 21114779705SSam Leffler /* If ChannelChange completed - skip the rest of reset */ 21214779705SSam Leffler /* XXX ani? */ 21359efa8b5SSam Leffler goto done; 21414779705SSam Leffler } 21514779705SSam Leffler } 21614779705SSam Leffler } 21714779705SSam Leffler #endif 21814779705SSam Leffler /* 21914779705SSam Leffler * Preserve the antenna on a channel change 22014779705SSam Leffler */ 22114779705SSam Leffler saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA); 22214779705SSam Leffler if (saveDefAntenna == 0) /* XXX magic constants */ 22314779705SSam Leffler saveDefAntenna = 1; 22414779705SSam Leffler 22514779705SSam Leffler /* Save hardware flag before chip reset clears the register */ 22614779705SSam Leffler macStaId1 = OS_REG_READ(ah, AR_STA_ID1) & 22714779705SSam Leffler (AR_STA_ID1_BASE_RATE_11B | AR_STA_ID1_USE_DEFANT); 22814779705SSam Leffler 22914779705SSam Leffler /* Save led state from pci config register */ 23014779705SSam Leffler saveLedState = OS_REG_READ(ah, AR_PCICFG) & 23114779705SSam Leffler (AR_PCICFG_LEDCTL | AR_PCICFG_LEDMODE | AR_PCICFG_LEDBLINK | 23214779705SSam Leffler AR_PCICFG_LEDSLOW); 23314779705SSam Leffler softLedCfg = OS_REG_READ(ah, AR_GPIOCR); 23414779705SSam Leffler softLedState = OS_REG_READ(ah, AR_GPIODO); 23514779705SSam Leffler 23614779705SSam Leffler ar5212RestoreClock(ah, opmode); /* move to refclk operation */ 23714779705SSam Leffler 23814779705SSam Leffler /* 23914779705SSam Leffler * Adjust gain parameters before reset if 24014779705SSam Leffler * there's an outstanding gain updated. 24114779705SSam Leffler */ 24214779705SSam Leffler (void) ar5212GetRfgain(ah); 24314779705SSam Leffler 24414779705SSam Leffler if (!ar5212ChipReset(ah, chan)) { 24514779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 24614779705SSam Leffler FAIL(HAL_EIO); 24714779705SSam Leffler } 24814779705SSam Leffler 24914779705SSam Leffler /* Setup the indices for the next set of register array writes */ 25059efa8b5SSam Leffler if (IEEE80211_IS_CHAN_2GHZ(chan)) { 25114779705SSam Leffler freqIndex = 2; 25259efa8b5SSam Leffler if (IEEE80211_IS_CHAN_108G(chan)) 25314779705SSam Leffler modesIndex = 5; 25459efa8b5SSam Leffler else if (IEEE80211_IS_CHAN_G(chan)) 25559efa8b5SSam Leffler modesIndex = 4; 25659efa8b5SSam Leffler else if (IEEE80211_IS_CHAN_B(chan)) 25759efa8b5SSam Leffler modesIndex = 3; 25859efa8b5SSam Leffler else { 25959efa8b5SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, 26059efa8b5SSam Leffler "%s: invalid channel %u/0x%x\n", 26159efa8b5SSam Leffler __func__, chan->ic_freq, chan->ic_flags); 26214779705SSam Leffler FAIL(HAL_EINVAL); 26314779705SSam Leffler } 26459efa8b5SSam Leffler } else { 26559efa8b5SSam Leffler freqIndex = 1; 26659efa8b5SSam Leffler if (IEEE80211_IS_CHAN_TURBO(chan)) 26759efa8b5SSam Leffler modesIndex = 2; 26859efa8b5SSam Leffler else if (IEEE80211_IS_CHAN_A(chan)) 26959efa8b5SSam Leffler modesIndex = 1; 27059efa8b5SSam Leffler else { 27159efa8b5SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, 27259efa8b5SSam Leffler "%s: invalid channel %u/0x%x\n", 27359efa8b5SSam Leffler __func__, chan->ic_freq, chan->ic_flags); 27459efa8b5SSam Leffler FAIL(HAL_EINVAL); 27559efa8b5SSam Leffler } 27659efa8b5SSam Leffler } 27714779705SSam Leffler 27814779705SSam Leffler OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 27914779705SSam Leffler 28014779705SSam Leffler /* Set correct Baseband to analog shift setting to access analog chips. */ 28114779705SSam Leffler OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 28214779705SSam Leffler 28314779705SSam Leffler regWrites = ath_hal_ini_write(ah, &ahp->ah_ini_modes, modesIndex, 0); 28414779705SSam Leffler regWrites = write_common(ah, &ahp->ah_ini_common, bChannelChange, 28514779705SSam Leffler regWrites); 28614779705SSam Leffler ahp->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 28714779705SSam Leffler 28814779705SSam Leffler OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 28914779705SSam Leffler 29059efa8b5SSam Leffler if (IEEE80211_IS_CHAN_HALF(chan) || IEEE80211_IS_CHAN_QUARTER(chan)) { 29114779705SSam Leffler ar5212SetIFSTiming(ah, chan); 29214779705SSam Leffler if (IS_5413(ah)) { 29314779705SSam Leffler /* 29414779705SSam Leffler * Force window_length for 1/2 and 1/4 rate channels, 29514779705SSam Leffler * the ini file sets this to zero otherwise. 29614779705SSam Leffler */ 29714779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, 29814779705SSam Leffler AR_PHY_FRAME_CTL_WINLEN, 3); 29914779705SSam Leffler } 30014779705SSam Leffler } 30114779705SSam Leffler 30214779705SSam Leffler /* Overwrite INI values for revised chipsets */ 30314779705SSam Leffler if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_2) { 30414779705SSam Leffler /* ADC_CTL */ 30514779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_ADC_CTL, 30614779705SSam Leffler SM(2, AR_PHY_ADC_CTL_OFF_INBUFGAIN) | 30714779705SSam Leffler SM(2, AR_PHY_ADC_CTL_ON_INBUFGAIN) | 30814779705SSam Leffler AR_PHY_ADC_CTL_OFF_PWDDAC | 30914779705SSam Leffler AR_PHY_ADC_CTL_OFF_PWDADC); 31014779705SSam Leffler 31114779705SSam Leffler /* TX_PWR_ADJ */ 31259efa8b5SSam Leffler if (ichan->channel == 2484) { 31314779705SSam Leffler cckOfdmPwrDelta = SCALE_OC_DELTA( 31414779705SSam Leffler ee->ee_cckOfdmPwrDelta - 31514779705SSam Leffler ee->ee_scaledCh14FilterCckDelta); 31614779705SSam Leffler } else { 31714779705SSam Leffler cckOfdmPwrDelta = SCALE_OC_DELTA( 31814779705SSam Leffler ee->ee_cckOfdmPwrDelta); 31914779705SSam Leffler } 32014779705SSam Leffler 32159efa8b5SSam Leffler if (IEEE80211_IS_CHAN_G(chan)) { 32214779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_TXPWRADJ, 32314779705SSam Leffler SM((ee->ee_cckOfdmPwrDelta*-1), 32414779705SSam Leffler AR_PHY_TXPWRADJ_CCK_GAIN_DELTA) | 32514779705SSam Leffler SM((cckOfdmPwrDelta*-1), 32614779705SSam Leffler AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX)); 32714779705SSam Leffler } else { 32814779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_TXPWRADJ, 0); 32914779705SSam Leffler } 33014779705SSam Leffler 33114779705SSam Leffler /* Add barker RSSI thresh enable as disabled */ 33214779705SSam Leffler OS_REG_CLR_BIT(ah, AR_PHY_DAG_CTRLCCK, 33314779705SSam Leffler AR_PHY_DAG_CTRLCCK_EN_RSSI_THR); 33414779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_DAG_CTRLCCK, 33514779705SSam Leffler AR_PHY_DAG_CTRLCCK_RSSI_THR, 2); 33614779705SSam Leffler 33714779705SSam Leffler /* Set the mute mask to the correct default */ 33814779705SSam Leffler OS_REG_WRITE(ah, AR_SEQ_MASK, 0x0000000F); 33914779705SSam Leffler } 34014779705SSam Leffler 34114779705SSam Leffler if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_3) { 34214779705SSam Leffler /* Clear reg to alllow RX_CLEAR line debug */ 34314779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_BLUETOOTH, 0); 34414779705SSam Leffler } 34514779705SSam Leffler if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_4) { 34614779705SSam Leffler #ifdef notyet 34714779705SSam Leffler /* Enable burst prefetch for the data queues */ 34814779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_D_FPCTL, ... ); 34914779705SSam Leffler /* Enable double-buffering */ 35014779705SSam Leffler OS_REG_CLR_BIT(ah, AR_TXCFG, AR_TXCFG_DBL_BUF_DIS); 35114779705SSam Leffler #endif 35214779705SSam Leffler } 35314779705SSam Leffler 35414779705SSam Leffler /* Set ADC/DAC select values */ 35514779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e); 35614779705SSam Leffler 35714779705SSam Leffler if (IS_5413(ah) || IS_2417(ah)) { 35814779705SSam Leffler uint32_t newReg = 1; 35959efa8b5SSam Leffler if (IS_DISABLE_FAST_ADC_CHAN(ichan->channel)) 36014779705SSam Leffler newReg = 0; 36114779705SSam Leffler /* As it's a clock changing register, only write when the value needs to be changed */ 36214779705SSam Leffler if (OS_REG_READ(ah, AR_PHY_FAST_ADC) != newReg) 36314779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_FAST_ADC, newReg); 36414779705SSam Leffler } 36514779705SSam Leffler 36614779705SSam Leffler /* Setup the transmit power values. */ 36759efa8b5SSam Leffler if (!ar5212SetTransmitPower(ah, chan, rfXpdGain)) { 36814779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, 36914779705SSam Leffler "%s: error init'ing transmit power\n", __func__); 37014779705SSam Leffler FAIL(HAL_EIO); 37114779705SSam Leffler } 37214779705SSam Leffler 37314779705SSam Leffler /* Write the analog registers */ 37459efa8b5SSam Leffler if (!ahp->ah_rfHal->setRfRegs(ah, chan, modesIndex, rfXpdGain)) { 37514779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5212SetRfRegs failed\n", 37614779705SSam Leffler __func__); 37714779705SSam Leffler FAIL(HAL_EIO); 37814779705SSam Leffler } 37914779705SSam Leffler 38014779705SSam Leffler /* Write delta slope for OFDM enabled modes (A, G, Turbo) */ 38159efa8b5SSam Leffler if (IEEE80211_IS_CHAN_OFDM(chan)) { 38259efa8b5SSam Leffler if (IS_5413(ah) || 38359efa8b5SSam Leffler AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3) 38459efa8b5SSam Leffler ar5212SetSpurMitigation(ah, chan); 38514779705SSam Leffler ar5212SetDeltaSlope(ah, chan); 38614779705SSam Leffler } 38714779705SSam Leffler 38814779705SSam Leffler /* Setup board specific options for EEPROM version 3 */ 38959efa8b5SSam Leffler if (!ar5212SetBoardValues(ah, chan)) { 39014779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, 39114779705SSam Leffler "%s: error setting board options\n", __func__); 39214779705SSam Leffler FAIL(HAL_EIO); 39314779705SSam Leffler } 39414779705SSam Leffler 39514779705SSam Leffler /* Restore certain DMA hardware registers on a channel change */ 39614779705SSam Leffler if (bChannelChange) 39714779705SSam Leffler OS_REG_WRITE(ah, AR_D_SEQNUM, saveFrameSeqCount); 39814779705SSam Leffler 39914779705SSam Leffler OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 40014779705SSam Leffler 40114779705SSam Leffler OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr)); 40214779705SSam Leffler OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4) 40314779705SSam Leffler | macStaId1 40414779705SSam Leffler | AR_STA_ID1_RTS_USE_DEF 40514779705SSam Leffler | ahp->ah_staId1Defaults 40614779705SSam Leffler ); 40714779705SSam Leffler ar5212SetOperatingMode(ah, opmode); 40814779705SSam Leffler 40914779705SSam Leffler /* Set Venice BSSID mask according to current state */ 41014779705SSam Leffler OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask)); 41114779705SSam Leffler OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4)); 41214779705SSam Leffler 41314779705SSam Leffler /* Restore previous led state */ 41414779705SSam Leffler OS_REG_WRITE(ah, AR_PCICFG, OS_REG_READ(ah, AR_PCICFG) | saveLedState); 41514779705SSam Leffler 41614779705SSam Leffler /* Restore soft Led state to GPIO */ 41714779705SSam Leffler OS_REG_WRITE(ah, AR_GPIOCR, softLedCfg); 41814779705SSam Leffler OS_REG_WRITE(ah, AR_GPIODO, softLedState); 41914779705SSam Leffler 42014779705SSam Leffler /* Restore previous antenna */ 42114779705SSam Leffler OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 42214779705SSam Leffler 42314779705SSam Leffler /* then our BSSID */ 42414779705SSam Leffler OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); 42514779705SSam Leffler OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4)); 42614779705SSam Leffler 42714779705SSam Leffler /* Restore bmiss rssi & count thresholds */ 42814779705SSam Leffler OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr); 42914779705SSam Leffler 43014779705SSam Leffler OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */ 43114779705SSam Leffler 43259efa8b5SSam Leffler if (!ar5212SetChannel(ah, chan)) 43314779705SSam Leffler FAIL(HAL_EIO); 43414779705SSam Leffler 43514779705SSam Leffler OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 43614779705SSam Leffler 43714779705SSam Leffler ar5212SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1); 43814779705SSam Leffler 43914779705SSam Leffler ar5212SetRateDurationTable(ah, chan); 44014779705SSam Leffler 44114779705SSam Leffler /* Set Tx frame start to tx data start delay */ 44214779705SSam Leffler if (IS_RAD5112_ANY(ah) && 44359efa8b5SSam Leffler (IEEE80211_IS_CHAN_HALF(chan) || IEEE80211_IS_CHAN_QUARTER(chan))) { 44414779705SSam Leffler txFrm2TxDStart = 44559efa8b5SSam Leffler IEEE80211_IS_CHAN_HALF(chan) ? 44614779705SSam Leffler TX_FRAME_D_START_HALF_RATE: 44714779705SSam Leffler TX_FRAME_D_START_QUARTER_RATE; 44814779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_TX_CTL, 44914779705SSam Leffler AR_PHY_TX_FRAME_TO_TX_DATA_START, txFrm2TxDStart); 45014779705SSam Leffler } 45114779705SSam Leffler 45214779705SSam Leffler /* 45314779705SSam Leffler * Setup fast diversity. 45414779705SSam Leffler * Fast diversity can be enabled or disabled via regadd.txt. 45514779705SSam Leffler * Default is enabled. 45614779705SSam Leffler * For reference, 45714779705SSam Leffler * Disable: reg val 45814779705SSam Leffler * 0x00009860 0x00009d18 (if 11a / 11g, else no change) 45914779705SSam Leffler * 0x00009970 0x192bb514 46014779705SSam Leffler * 0x0000a208 0xd03e4648 46114779705SSam Leffler * 46214779705SSam Leffler * Enable: 0x00009860 0x00009d10 (if 11a / 11g, else no change) 46314779705SSam Leffler * 0x00009970 0x192fb514 46414779705SSam Leffler * 0x0000a208 0xd03e6788 46514779705SSam Leffler */ 46614779705SSam Leffler 46714779705SSam Leffler /* XXX Setup pre PHY ENABLE EAR additions */ 46814779705SSam Leffler /* 46914779705SSam Leffler * Wait for the frequency synth to settle (synth goes on 47014779705SSam Leffler * via AR_PHY_ACTIVE_EN). Read the phy active delay register. 47114779705SSam Leffler * Value is in 100ns increments. 47214779705SSam Leffler */ 47314779705SSam Leffler synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 47459efa8b5SSam Leffler if (IEEE80211_IS_CHAN_B(chan)) { 47514779705SSam Leffler synthDelay = (4 * synthDelay) / 22; 47614779705SSam Leffler } else { 47714779705SSam Leffler synthDelay /= 10; 47814779705SSam Leffler } 47914779705SSam Leffler 48014779705SSam Leffler /* Activate the PHY (includes baseband activate and synthesizer on) */ 48114779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 48214779705SSam Leffler 48314779705SSam Leffler /* 48414779705SSam Leffler * There is an issue if the AP starts the calibration before 48514779705SSam Leffler * the base band timeout completes. This could result in the 48614779705SSam Leffler * rx_clear false triggering. As a workaround we add delay an 48714779705SSam Leffler * extra BASE_ACTIVATE_DELAY usecs to ensure this condition 48814779705SSam Leffler * does not happen. 48914779705SSam Leffler */ 49059efa8b5SSam Leffler if (IEEE80211_IS_CHAN_HALF(chan)) { 49114779705SSam Leffler OS_DELAY((synthDelay << 1) + BASE_ACTIVATE_DELAY); 49259efa8b5SSam Leffler } else if (IEEE80211_IS_CHAN_QUARTER(chan)) { 49314779705SSam Leffler OS_DELAY((synthDelay << 2) + BASE_ACTIVATE_DELAY); 49414779705SSam Leffler } else { 49514779705SSam Leffler OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY); 49614779705SSam Leffler } 49714779705SSam Leffler 49814779705SSam Leffler /* 49914779705SSam Leffler * The udelay method is not reliable with notebooks. 50014779705SSam Leffler * Need to check to see if the baseband is ready 50114779705SSam Leffler */ 50214779705SSam Leffler testReg = OS_REG_READ(ah, AR_PHY_TESTCTRL); 50314779705SSam Leffler /* Selects the Tx hold */ 50414779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_TESTCTRL, AR_PHY_TESTCTRL_TXHOLD); 50514779705SSam Leffler i = 0; 50614779705SSam Leffler while ((i++ < 20) && 50714779705SSam Leffler (OS_REG_READ(ah, 0x9c24) & 0x10)) /* test if baseband not ready */ OS_DELAY(200); 50814779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_TESTCTRL, testReg); 50914779705SSam Leffler 51014779705SSam Leffler /* Calibrate the AGC and start a NF calculation */ 51114779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, 51214779705SSam Leffler OS_REG_READ(ah, AR_PHY_AGC_CONTROL) 51314779705SSam Leffler | AR_PHY_AGC_CONTROL_CAL 51414779705SSam Leffler | AR_PHY_AGC_CONTROL_NF); 51514779705SSam Leffler 51659efa8b5SSam Leffler if (!IEEE80211_IS_CHAN_B(chan) && ahp->ah_bIQCalibration != IQ_CAL_DONE) { 51714779705SSam Leffler /* Start IQ calibration w/ 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples */ 51814779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 51914779705SSam Leffler AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, 52014779705SSam Leffler INIT_IQCAL_LOG_COUNT_MAX); 52114779705SSam Leffler OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 52214779705SSam Leffler AR_PHY_TIMING_CTRL4_DO_IQCAL); 52314779705SSam Leffler ahp->ah_bIQCalibration = IQ_CAL_RUNNING; 52414779705SSam Leffler } else 52514779705SSam Leffler ahp->ah_bIQCalibration = IQ_CAL_INACTIVE; 52614779705SSam Leffler 52714779705SSam Leffler /* Setup compression registers */ 52814779705SSam Leffler ar5212SetCompRegs(ah); 52914779705SSam Leffler 53014779705SSam Leffler /* Set 1:1 QCU to DCU mapping for all queues */ 53114779705SSam Leffler for (i = 0; i < AR_NUM_DCU; i++) 53214779705SSam Leffler OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 53314779705SSam Leffler 53414779705SSam Leffler ahp->ah_intrTxqs = 0; 53514779705SSam Leffler for (i = 0; i < AH_PRIVATE(ah)->ah_caps.halTotalQueues; i++) 53614779705SSam Leffler ar5212ResetTxQueue(ah, i); 53714779705SSam Leffler 53814779705SSam Leffler /* 53914779705SSam Leffler * Setup interrupt handling. Note that ar5212ResetTxQueue 54014779705SSam Leffler * manipulates the secondary IMR's as queues are enabled 54114779705SSam Leffler * and disabled. This is done with RMW ops to insure the 54214779705SSam Leffler * settings we make here are preserved. 54314779705SSam Leffler */ 54414779705SSam Leffler ahp->ah_maskReg = AR_IMR_TXOK | AR_IMR_TXERR | AR_IMR_TXURN 54514779705SSam Leffler | AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXORN 54614779705SSam Leffler | AR_IMR_HIUERR 54714779705SSam Leffler ; 54814779705SSam Leffler if (opmode == HAL_M_HOSTAP) 54914779705SSam Leffler ahp->ah_maskReg |= AR_IMR_MIB; 55014779705SSam Leffler OS_REG_WRITE(ah, AR_IMR, ahp->ah_maskReg); 55114779705SSam Leffler /* Enable bus errors that are OR'd to set the HIUERR bit */ 55214779705SSam Leffler OS_REG_WRITE(ah, AR_IMR_S2, 55314779705SSam Leffler OS_REG_READ(ah, AR_IMR_S2) 55414779705SSam Leffler | AR_IMR_S2_MCABT | AR_IMR_S2_SSERR | AR_IMR_S2_DPERR); 55514779705SSam Leffler 55614779705SSam Leffler if (AH_PRIVATE(ah)->ah_rfkillEnabled) 55714779705SSam Leffler ar5212EnableRfKill(ah); 55814779705SSam Leffler 55914779705SSam Leffler if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) { 56014779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, 56114779705SSam Leffler "%s: offset calibration failed to complete in 1ms;" 56214779705SSam Leffler " noisy environment?\n", __func__); 56314779705SSam Leffler } 56414779705SSam Leffler 56514779705SSam Leffler /* 56614779705SSam Leffler * Set clocks back to 32kHz if they had been using refClk, then 56714779705SSam Leffler * use an external 32kHz crystal when sleeping, if one exists. 56814779705SSam Leffler */ 56914779705SSam Leffler ar5212SetupClock(ah, opmode); 57014779705SSam Leffler 57114779705SSam Leffler /* 57214779705SSam Leffler * Writing to AR_BEACON will start timers. Hence it should 57314779705SSam Leffler * be the last register to be written. Do not reset tsf, do 57414779705SSam Leffler * not enable beacons at this point, but preserve other values 57514779705SSam Leffler * like beaconInterval. 57614779705SSam Leffler */ 57714779705SSam Leffler OS_REG_WRITE(ah, AR_BEACON, 57814779705SSam Leffler (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_EN | AR_BEACON_RESET_TSF))); 57914779705SSam Leffler 58014779705SSam Leffler /* XXX Setup post reset EAR additions */ 58114779705SSam Leffler 58214779705SSam Leffler /* QoS support */ 58314779705SSam Leffler if (AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE || 58414779705SSam Leffler (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 58514779705SSam Leffler AH_PRIVATE(ah)->ah_macRev >= AR_SREV_GRIFFIN_LITE)) { 58614779705SSam Leffler OS_REG_WRITE(ah, AR_QOS_CONTROL, 0x100aa); /* XXX magic */ 58714779705SSam Leffler OS_REG_WRITE(ah, AR_QOS_SELECT, 0x3210); /* XXX magic */ 58814779705SSam Leffler } 58914779705SSam Leffler 59014779705SSam Leffler /* Turn on NOACK Support for QoS packets */ 59114779705SSam Leffler OS_REG_WRITE(ah, AR_NOACK, 59214779705SSam Leffler SM(2, AR_NOACK_2BIT_VALUE) | 59314779705SSam Leffler SM(5, AR_NOACK_BIT_OFFSET) | 59414779705SSam Leffler SM(0, AR_NOACK_BYTE_OFFSET)); 59514779705SSam Leffler 59614779705SSam Leffler /* Get Antenna Gain reduction */ 59759efa8b5SSam Leffler if (IEEE80211_IS_CHAN_5GHZ(chan)) { 59814779705SSam Leffler ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_5, &twiceAntennaGain); 59914779705SSam Leffler } else { 60014779705SSam Leffler ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_2, &twiceAntennaGain); 60114779705SSam Leffler } 60214779705SSam Leffler twiceAntennaReduction = 60314779705SSam Leffler ath_hal_getantennareduction(ah, chan, twiceAntennaGain); 60414779705SSam Leffler 60514779705SSam Leffler /* TPC for self-generated frames */ 60614779705SSam Leffler 60714779705SSam Leffler ackTpcPow = MS(ahp->ah_macTPC, AR_TPC_ACK); 60859efa8b5SSam Leffler if ((ackTpcPow-ahp->ah_txPowerIndexOffset) > chan->ic_maxpower) 60959efa8b5SSam Leffler ackTpcPow = chan->ic_maxpower+ahp->ah_txPowerIndexOffset; 61014779705SSam Leffler 61159efa8b5SSam Leffler if (ackTpcPow > (2*chan->ic_maxregpower - twiceAntennaReduction)) 61259efa8b5SSam Leffler ackTpcPow = (2*chan->ic_maxregpower - twiceAntennaReduction) 61314779705SSam Leffler + ahp->ah_txPowerIndexOffset; 61414779705SSam Leffler 61514779705SSam Leffler ctsTpcPow = MS(ahp->ah_macTPC, AR_TPC_CTS); 61659efa8b5SSam Leffler if ((ctsTpcPow-ahp->ah_txPowerIndexOffset) > chan->ic_maxpower) 61759efa8b5SSam Leffler ctsTpcPow = chan->ic_maxpower+ahp->ah_txPowerIndexOffset; 61814779705SSam Leffler 61959efa8b5SSam Leffler if (ctsTpcPow > (2*chan->ic_maxregpower - twiceAntennaReduction)) 62059efa8b5SSam Leffler ctsTpcPow = (2*chan->ic_maxregpower - twiceAntennaReduction) 62114779705SSam Leffler + ahp->ah_txPowerIndexOffset; 62214779705SSam Leffler 62314779705SSam Leffler chirpTpcPow = MS(ahp->ah_macTPC, AR_TPC_CHIRP); 62459efa8b5SSam Leffler if ((chirpTpcPow-ahp->ah_txPowerIndexOffset) > chan->ic_maxpower) 62559efa8b5SSam Leffler chirpTpcPow = chan->ic_maxpower+ahp->ah_txPowerIndexOffset; 62614779705SSam Leffler 62759efa8b5SSam Leffler if (chirpTpcPow > (2*chan->ic_maxregpower - twiceAntennaReduction)) 62859efa8b5SSam Leffler chirpTpcPow = (2*chan->ic_maxregpower - twiceAntennaReduction) 62914779705SSam Leffler + ahp->ah_txPowerIndexOffset; 63014779705SSam Leffler 63114779705SSam Leffler if (ackTpcPow > 63) 63214779705SSam Leffler ackTpcPow = 63; 63314779705SSam Leffler if (ctsTpcPow > 63) 63414779705SSam Leffler ctsTpcPow = 63; 63514779705SSam Leffler if (chirpTpcPow > 63) 63614779705SSam Leffler chirpTpcPow = 63; 63714779705SSam Leffler 63814779705SSam Leffler powerVal = SM(ackTpcPow, AR_TPC_ACK) | 63914779705SSam Leffler SM(ctsTpcPow, AR_TPC_CTS) | 64014779705SSam Leffler SM(chirpTpcPow, AR_TPC_CHIRP); 64114779705SSam Leffler 64214779705SSam Leffler OS_REG_WRITE(ah, AR_TPC, powerVal); 64314779705SSam Leffler 64414779705SSam Leffler /* Restore user-specified settings */ 64514779705SSam Leffler if (ahp->ah_miscMode != 0) 64614779705SSam Leffler OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode); 64714779705SSam Leffler if (ahp->ah_sifstime != (u_int) -1) 64814779705SSam Leffler ar5212SetSifsTime(ah, ahp->ah_sifstime); 64914779705SSam Leffler if (ahp->ah_slottime != (u_int) -1) 65014779705SSam Leffler ar5212SetSlotTime(ah, ahp->ah_slottime); 65114779705SSam Leffler if (ahp->ah_acktimeout != (u_int) -1) 65214779705SSam Leffler ar5212SetAckTimeout(ah, ahp->ah_acktimeout); 65314779705SSam Leffler if (ahp->ah_ctstimeout != (u_int) -1) 65414779705SSam Leffler ar5212SetCTSTimeout(ah, ahp->ah_ctstimeout); 65514779705SSam Leffler if (AH_PRIVATE(ah)->ah_diagreg != 0) 65614779705SSam Leffler OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); 65714779705SSam Leffler 65814779705SSam Leffler AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */ 65959efa8b5SSam Leffler #if 0 66059efa8b5SSam Leffler done: 66159efa8b5SSam Leffler #endif 66259efa8b5SSam Leffler if (bChannelChange && !IEEE80211_IS_CHAN_DFS(chan)) 66359efa8b5SSam Leffler chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT; 66414779705SSam Leffler 66514779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__); 66614779705SSam Leffler 66714779705SSam Leffler RESTORE_CCK(ah, chan, isBmode); 66814779705SSam Leffler 66914779705SSam Leffler OS_MARK(ah, AH_MARK_RESET_DONE, 0); 67014779705SSam Leffler 67114779705SSam Leffler return AH_TRUE; 67214779705SSam Leffler bad: 67314779705SSam Leffler RESTORE_CCK(ah, chan, isBmode); 67414779705SSam Leffler 67514779705SSam Leffler OS_MARK(ah, AH_MARK_RESET_DONE, ecode); 6768698ea65SSam Leffler if (status != AH_NULL) 67714779705SSam Leffler *status = ecode; 67814779705SSam Leffler return AH_FALSE; 67914779705SSam Leffler #undef FAIL 68014779705SSam Leffler #undef N 68114779705SSam Leffler } 68214779705SSam Leffler 68314779705SSam Leffler /* 68414779705SSam Leffler * Call the rf backend to change the channel. 68514779705SSam Leffler */ 68614779705SSam Leffler HAL_BOOL 68759efa8b5SSam Leffler ar5212SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan) 68814779705SSam Leffler { 68914779705SSam Leffler struct ath_hal_5212 *ahp = AH5212(ah); 69014779705SSam Leffler 69114779705SSam Leffler /* Change the synth */ 69214779705SSam Leffler if (!ahp->ah_rfHal->setChannel(ah, chan)) 69314779705SSam Leffler return AH_FALSE; 69414779705SSam Leffler return AH_TRUE; 69514779705SSam Leffler } 69614779705SSam Leffler 69714779705SSam Leffler /* 69814779705SSam Leffler * This channel change evaluates whether the selected hardware can 69914779705SSam Leffler * perform a synthesizer-only channel change (no reset). If the 70014779705SSam Leffler * TX is not stopped, or the RFBus cannot be granted in the given 70114779705SSam Leffler * time, the function returns false as a reset is necessary 70214779705SSam Leffler */ 70314779705SSam Leffler HAL_BOOL 70459efa8b5SSam Leffler ar5212ChannelChange(struct ath_hal *ah, const struct ieee80211_channel *chan) 70514779705SSam Leffler { 70614779705SSam Leffler uint32_t ulCount; 70714779705SSam Leffler uint32_t data, synthDelay, qnum; 70814779705SSam Leffler uint16_t rfXpdGain[MAX_NUM_PDGAINS_PER_CHANNEL]; 70914779705SSam Leffler HAL_BOOL txStopped = AH_TRUE; 71014779705SSam Leffler HAL_CHANNEL_INTERNAL *ichan; 71114779705SSam Leffler 71214779705SSam Leffler /* 71314779705SSam Leffler * Map public channel to private. 71414779705SSam Leffler */ 71514779705SSam Leffler ichan = ath_hal_checkchannel(ah, chan); 71614779705SSam Leffler 71714779705SSam Leffler /* TX must be stopped or RF Bus grant will not work */ 71814779705SSam Leffler for (qnum = 0; qnum < AH_PRIVATE(ah)->ah_caps.halTotalQueues; qnum++) { 71914779705SSam Leffler if (ar5212NumTxPending(ah, qnum)) { 72014779705SSam Leffler txStopped = AH_FALSE; 72114779705SSam Leffler break; 72214779705SSam Leffler } 72314779705SSam Leffler } 72414779705SSam Leffler if (!txStopped) 72514779705SSam Leffler return AH_FALSE; 72614779705SSam Leffler 72714779705SSam Leffler /* Kill last Baseband Rx Frame */ 72814779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_REQUEST); /* Request analog bus grant */ 72914779705SSam Leffler for (ulCount = 0; ulCount < 100; ulCount++) { 73014779705SSam Leffler if (OS_REG_READ(ah, AR_PHY_RFBUS_GNT)) 73114779705SSam Leffler break; 73214779705SSam Leffler OS_DELAY(5); 73314779705SSam Leffler } 73414779705SSam Leffler if (ulCount >= 100) 73514779705SSam Leffler return AH_FALSE; 73614779705SSam Leffler 73714779705SSam Leffler /* Change the synth */ 73859efa8b5SSam Leffler if (!ar5212SetChannel(ah, chan)) 73914779705SSam Leffler return AH_FALSE; 74014779705SSam Leffler 74114779705SSam Leffler /* 74214779705SSam Leffler * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN). 74314779705SSam Leffler * Read the phy active delay register. Value is in 100ns increments. 74414779705SSam Leffler */ 74514779705SSam Leffler data = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 74659efa8b5SSam Leffler if (IEEE80211_IS_CHAN_B(chan)) { 74714779705SSam Leffler synthDelay = (4 * data) / 22; 74814779705SSam Leffler } else { 74914779705SSam Leffler synthDelay = data / 10; 75014779705SSam Leffler } 75114779705SSam Leffler OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY); 75214779705SSam Leffler 75314779705SSam Leffler /* Setup the transmit power values. */ 75459efa8b5SSam Leffler if (!ar5212SetTransmitPower(ah, chan, rfXpdGain)) { 75514779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, 75614779705SSam Leffler "%s: error init'ing transmit power\n", __func__); 75714779705SSam Leffler return AH_FALSE; 75814779705SSam Leffler } 75914779705SSam Leffler 76014779705SSam Leffler /* Write delta slope for OFDM enabled modes (A, G, Turbo) */ 76159efa8b5SSam Leffler if (IEEE80211_IS_CHAN_OFDM(chan)) { 76259efa8b5SSam Leffler if (IS_5413(ah) || 76359efa8b5SSam Leffler AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3) 76459efa8b5SSam Leffler ar5212SetSpurMitigation(ah, chan); 76514779705SSam Leffler ar5212SetDeltaSlope(ah, chan); 76614779705SSam Leffler } 76714779705SSam Leffler 76814779705SSam Leffler /* Release the RFBus Grant */ 76914779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 77014779705SSam Leffler 77114779705SSam Leffler /* Start Noise Floor Cal */ 77214779705SSam Leffler OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 77314779705SSam Leffler return AH_TRUE; 77414779705SSam Leffler } 77514779705SSam Leffler 77614779705SSam Leffler void 77714779705SSam Leffler ar5212SetOperatingMode(struct ath_hal *ah, int opmode) 77814779705SSam Leffler { 77914779705SSam Leffler uint32_t val; 78014779705SSam Leffler 78114779705SSam Leffler val = OS_REG_READ(ah, AR_STA_ID1); 78214779705SSam Leffler val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC); 78314779705SSam Leffler switch (opmode) { 78414779705SSam Leffler case HAL_M_HOSTAP: 78514779705SSam Leffler OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP 78614779705SSam Leffler | AR_STA_ID1_KSRCH_MODE); 78714779705SSam Leffler OS_REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 78814779705SSam Leffler break; 78914779705SSam Leffler case HAL_M_IBSS: 79014779705SSam Leffler OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC 79114779705SSam Leffler | AR_STA_ID1_KSRCH_MODE); 79214779705SSam Leffler OS_REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 79314779705SSam Leffler break; 79414779705SSam Leffler case HAL_M_STA: 79514779705SSam Leffler case HAL_M_MONITOR: 79614779705SSam Leffler OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); 79714779705SSam Leffler break; 79814779705SSam Leffler } 79914779705SSam Leffler } 80014779705SSam Leffler 80114779705SSam Leffler /* 80214779705SSam Leffler * Places the PHY and Radio chips into reset. A full reset 80314779705SSam Leffler * must be called to leave this state. The PCI/MAC/PCU are 80414779705SSam Leffler * not placed into reset as we must receive interrupt to 80514779705SSam Leffler * re-enable the hardware. 80614779705SSam Leffler */ 80714779705SSam Leffler HAL_BOOL 80814779705SSam Leffler ar5212PhyDisable(struct ath_hal *ah) 80914779705SSam Leffler { 81014779705SSam Leffler return ar5212SetResetReg(ah, AR_RC_BB); 81114779705SSam Leffler } 81214779705SSam Leffler 81314779705SSam Leffler /* 81414779705SSam Leffler * Places all of hardware into reset 81514779705SSam Leffler */ 81614779705SSam Leffler HAL_BOOL 81714779705SSam Leffler ar5212Disable(struct ath_hal *ah) 81814779705SSam Leffler { 81914779705SSam Leffler if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 82014779705SSam Leffler return AH_FALSE; 82114779705SSam Leffler /* 82214779705SSam Leffler * Reset the HW - PCI must be reset after the rest of the 82314779705SSam Leffler * device has been reset. 82414779705SSam Leffler */ 82514779705SSam Leffler return ar5212SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI); 82614779705SSam Leffler } 82714779705SSam Leffler 82814779705SSam Leffler /* 82914779705SSam Leffler * Places the hardware into reset and then pulls it out of reset 83014779705SSam Leffler * 83114779705SSam Leffler * TODO: Only write the PLL if we're changing to or from CCK mode 83214779705SSam Leffler * 83314779705SSam Leffler * WARNING: The order of the PLL and mode registers must be correct. 83414779705SSam Leffler */ 83514779705SSam Leffler HAL_BOOL 83659efa8b5SSam Leffler ar5212ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan) 83714779705SSam Leffler { 83814779705SSam Leffler 83959efa8b5SSam Leffler OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->ic_freq : 0); 84014779705SSam Leffler 84114779705SSam Leffler /* 84214779705SSam Leffler * Reset the HW - PCI must be reset after the rest of the 84314779705SSam Leffler * device has been reset 84414779705SSam Leffler */ 84514779705SSam Leffler if (!ar5212SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI)) 84614779705SSam Leffler return AH_FALSE; 84714779705SSam Leffler 84814779705SSam Leffler /* Bring out of sleep mode (AGAIN) */ 84914779705SSam Leffler if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 85014779705SSam Leffler return AH_FALSE; 85114779705SSam Leffler 85214779705SSam Leffler /* Clear warm reset register */ 85314779705SSam Leffler if (!ar5212SetResetReg(ah, 0)) 85414779705SSam Leffler return AH_FALSE; 85514779705SSam Leffler 85614779705SSam Leffler /* 85714779705SSam Leffler * Perform warm reset before the mode/PLL/turbo registers 85814779705SSam Leffler * are changed in order to deactivate the radio. Mode changes 85914779705SSam Leffler * with an active radio can result in corrupted shifts to the 86014779705SSam Leffler * radio device. 86114779705SSam Leffler */ 86214779705SSam Leffler 86314779705SSam Leffler /* 86414779705SSam Leffler * Set CCK and Turbo modes correctly. 86514779705SSam Leffler */ 86614779705SSam Leffler if (chan != AH_NULL) { /* NB: can be null during attach */ 86714779705SSam Leffler uint32_t rfMode, phyPLL = 0, curPhyPLL, turbo; 86814779705SSam Leffler 86914779705SSam Leffler if (IS_5413(ah)) { /* NB: =>'s 5424 also */ 87014779705SSam Leffler rfMode = AR_PHY_MODE_AR5112; 87159efa8b5SSam Leffler if (IEEE80211_IS_CHAN_HALF(chan)) 87214779705SSam Leffler rfMode |= AR_PHY_MODE_HALF; 87359efa8b5SSam Leffler else if (IEEE80211_IS_CHAN_QUARTER(chan)) 87414779705SSam Leffler rfMode |= AR_PHY_MODE_QUARTER; 87514779705SSam Leffler 87659efa8b5SSam Leffler if (IEEE80211_IS_CHAN_CCK(chan)) 87714779705SSam Leffler phyPLL = AR_PHY_PLL_CTL_44_5112; 87814779705SSam Leffler else 87914779705SSam Leffler phyPLL = AR_PHY_PLL_CTL_40_5413; 88014779705SSam Leffler } else if (IS_RAD5111(ah)) { 88114779705SSam Leffler rfMode = AR_PHY_MODE_AR5111; 88259efa8b5SSam Leffler if (IEEE80211_IS_CHAN_CCK(chan)) 88314779705SSam Leffler phyPLL = AR_PHY_PLL_CTL_44; 88414779705SSam Leffler else 88514779705SSam Leffler phyPLL = AR_PHY_PLL_CTL_40; 88659efa8b5SSam Leffler if (IEEE80211_IS_CHAN_HALF(chan)) 88714779705SSam Leffler phyPLL = AR_PHY_PLL_CTL_HALF; 88859efa8b5SSam Leffler else if (IEEE80211_IS_CHAN_QUARTER(chan)) 88914779705SSam Leffler phyPLL = AR_PHY_PLL_CTL_QUARTER; 89014779705SSam Leffler } else { /* 5112, 2413, 2316, 2317 */ 89114779705SSam Leffler rfMode = AR_PHY_MODE_AR5112; 89259efa8b5SSam Leffler if (IEEE80211_IS_CHAN_CCK(chan)) 89314779705SSam Leffler phyPLL = AR_PHY_PLL_CTL_44_5112; 89414779705SSam Leffler else 89514779705SSam Leffler phyPLL = AR_PHY_PLL_CTL_40_5112; 89659efa8b5SSam Leffler if (IEEE80211_IS_CHAN_HALF(chan)) 89714779705SSam Leffler phyPLL |= AR_PHY_PLL_CTL_HALF; 89859efa8b5SSam Leffler else if (IEEE80211_IS_CHAN_QUARTER(chan)) 89914779705SSam Leffler phyPLL |= AR_PHY_PLL_CTL_QUARTER; 90014779705SSam Leffler } 90159efa8b5SSam Leffler if (IEEE80211_IS_CHAN_G(chan)) 90214779705SSam Leffler rfMode |= AR_PHY_MODE_DYNAMIC; 90359efa8b5SSam Leffler else if (IEEE80211_IS_CHAN_OFDM(chan)) 90414779705SSam Leffler rfMode |= AR_PHY_MODE_OFDM; 90514779705SSam Leffler else 90614779705SSam Leffler rfMode |= AR_PHY_MODE_CCK; 90759efa8b5SSam Leffler if (IEEE80211_IS_CHAN_5GHZ(chan)) 90814779705SSam Leffler rfMode |= AR_PHY_MODE_RF5GHZ; 90914779705SSam Leffler else 91014779705SSam Leffler rfMode |= AR_PHY_MODE_RF2GHZ; 91159efa8b5SSam Leffler turbo = IEEE80211_IS_CHAN_TURBO(chan) ? 91214779705SSam Leffler (AR_PHY_FC_TURBO_MODE | AR_PHY_FC_TURBO_SHORT) : 0; 91314779705SSam Leffler curPhyPLL = OS_REG_READ(ah, AR_PHY_PLL_CTL); 91414779705SSam Leffler /* 91514779705SSam Leffler * PLL, Mode, and Turbo values must be written in the correct 91614779705SSam Leffler * order to ensure: 91714779705SSam Leffler * - The PLL cannot be set to 44 unless the CCK or DYNAMIC 91814779705SSam Leffler * mode bit is set 91914779705SSam Leffler * - Turbo cannot be set at the same time as CCK or DYNAMIC 92014779705SSam Leffler */ 92159efa8b5SSam Leffler if (IEEE80211_IS_CHAN_CCK(chan)) { 92214779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_TURBO, turbo); 92314779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_MODE, rfMode); 92414779705SSam Leffler if (curPhyPLL != phyPLL) { 92514779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_PLL_CTL, phyPLL); 92614779705SSam Leffler /* Wait for the PLL to settle */ 92714779705SSam Leffler OS_DELAY(PLL_SETTLE_DELAY); 92814779705SSam Leffler } 92914779705SSam Leffler } else { 93014779705SSam Leffler if (curPhyPLL != phyPLL) { 93114779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_PLL_CTL, phyPLL); 93214779705SSam Leffler /* Wait for the PLL to settle */ 93314779705SSam Leffler OS_DELAY(PLL_SETTLE_DELAY); 93414779705SSam Leffler } 93514779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_TURBO, turbo); 93614779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_MODE, rfMode); 93714779705SSam Leffler } 93814779705SSam Leffler } 93914779705SSam Leffler return AH_TRUE; 94014779705SSam Leffler } 94114779705SSam Leffler 94214779705SSam Leffler /* 94314779705SSam Leffler * Recalibrate the lower PHY chips to account for temperature/environment 94414779705SSam Leffler * changes. 94514779705SSam Leffler */ 94614779705SSam Leffler HAL_BOOL 94759efa8b5SSam Leffler ar5212PerCalibrationN(struct ath_hal *ah, 94859efa8b5SSam Leffler struct ieee80211_channel *chan, 94959efa8b5SSam Leffler u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone) 95014779705SSam Leffler { 95114779705SSam Leffler #define IQ_CAL_TRIES 10 95214779705SSam Leffler struct ath_hal_5212 *ahp = AH5212(ah); 95314779705SSam Leffler HAL_CHANNEL_INTERNAL *ichan; 95414779705SSam Leffler int32_t qCoff, qCoffDenom; 95514779705SSam Leffler int32_t iqCorrMeas, iCoff, iCoffDenom; 95614779705SSam Leffler uint32_t powerMeasQ, powerMeasI; 95755a2313aSSam Leffler HAL_BOOL isBmode = AH_FALSE; 95814779705SSam Leffler 95959efa8b5SSam Leffler OS_MARK(ah, AH_MARK_PERCAL, chan->ic_freq); 96014779705SSam Leffler *isCalDone = AH_FALSE; 96114779705SSam Leffler ichan = ath_hal_checkchannel(ah, chan); 96214779705SSam Leffler if (ichan == AH_NULL) { 96314779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, 96414779705SSam Leffler "%s: invalid channel %u/0x%x; no mapping\n", 96559efa8b5SSam Leffler __func__, chan->ic_freq, chan->ic_flags); 96614779705SSam Leffler return AH_FALSE; 96714779705SSam Leffler } 96814779705SSam Leffler SAVE_CCK(ah, chan, isBmode); 96914779705SSam Leffler 97014779705SSam Leffler if (ahp->ah_bIQCalibration == IQ_CAL_DONE || 97114779705SSam Leffler ahp->ah_bIQCalibration == IQ_CAL_INACTIVE) 97214779705SSam Leffler *isCalDone = AH_TRUE; 97314779705SSam Leffler 97414779705SSam Leffler /* IQ calibration in progress. Check to see if it has finished. */ 97514779705SSam Leffler if (ahp->ah_bIQCalibration == IQ_CAL_RUNNING && 97614779705SSam Leffler !(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_IQCAL)) { 97714779705SSam Leffler int i; 97814779705SSam Leffler 97914779705SSam Leffler /* IQ Calibration has finished. */ 98014779705SSam Leffler ahp->ah_bIQCalibration = IQ_CAL_INACTIVE; 98114779705SSam Leffler *isCalDone = AH_TRUE; 98214779705SSam Leffler 98314779705SSam Leffler /* workaround for misgated IQ Cal results */ 98414779705SSam Leffler i = 0; 98514779705SSam Leffler do { 98614779705SSam Leffler /* Read calibration results. */ 98714779705SSam Leffler powerMeasI = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_I); 98814779705SSam Leffler powerMeasQ = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_Q); 98914779705SSam Leffler iqCorrMeas = OS_REG_READ(ah, AR_PHY_IQCAL_RES_IQ_CORR_MEAS); 99014779705SSam Leffler if (powerMeasI && powerMeasQ) 99114779705SSam Leffler break; 99214779705SSam Leffler /* Do we really need this??? */ 9935c5b75f9SSam Leffler OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 99414779705SSam Leffler AR_PHY_TIMING_CTRL4_DO_IQCAL); 99514779705SSam Leffler } while (++i < IQ_CAL_TRIES); 99614779705SSam Leffler 99714779705SSam Leffler /* 99814779705SSam Leffler * Prescale these values to remove 64-bit operation 99914779705SSam Leffler * requirement at the loss of a little precision. 100014779705SSam Leffler */ 100114779705SSam Leffler iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128; 100214779705SSam Leffler qCoffDenom = powerMeasQ / 128; 100314779705SSam Leffler 100414779705SSam Leffler /* Protect against divide-by-0 and loss of sign bits. */ 100514779705SSam Leffler if (iCoffDenom != 0 && qCoffDenom >= 2) { 100614779705SSam Leffler iCoff = (int8_t)(-iqCorrMeas) / iCoffDenom; 100714779705SSam Leffler /* IQCORR_Q_I_COFF is a signed 6 bit number */ 100814779705SSam Leffler if (iCoff < -32) { 100914779705SSam Leffler iCoff = -32; 101014779705SSam Leffler } else if (iCoff > 31) { 101114779705SSam Leffler iCoff = 31; 101214779705SSam Leffler } 101314779705SSam Leffler 101414779705SSam Leffler /* IQCORR_Q_Q_COFF is a signed 5 bit number */ 101514779705SSam Leffler qCoff = (powerMeasI / qCoffDenom) - 128; 101614779705SSam Leffler if (qCoff < -16) { 101714779705SSam Leffler qCoff = -16; 101814779705SSam Leffler } else if (qCoff > 15) { 101914779705SSam Leffler qCoff = 15; 102014779705SSam Leffler } 102114779705SSam Leffler 102214779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_PERCAL, 102314779705SSam Leffler "****************** MISGATED IQ CAL! *******************\n"); 102414779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_PERCAL, 102514779705SSam Leffler "time = %d, i = %d, \n", OS_GETUPTIME(ah), i); 102614779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_PERCAL, 102714779705SSam Leffler "powerMeasI = 0x%08x\n", powerMeasI); 102814779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_PERCAL, 102914779705SSam Leffler "powerMeasQ = 0x%08x\n", powerMeasQ); 103014779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_PERCAL, 103114779705SSam Leffler "iqCorrMeas = 0x%08x\n", iqCorrMeas); 103214779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_PERCAL, 103314779705SSam Leffler "iCoff = %d\n", iCoff); 103414779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_PERCAL, 103514779705SSam Leffler "qCoff = %d\n", qCoff); 103614779705SSam Leffler 103714779705SSam Leffler /* Write values and enable correction */ 103814779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 103914779705SSam Leffler AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, iCoff); 104014779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 104114779705SSam Leffler AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, qCoff); 104214779705SSam Leffler OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 104314779705SSam Leffler AR_PHY_TIMING_CTRL4_IQCORR_ENABLE); 104414779705SSam Leffler 104514779705SSam Leffler ahp->ah_bIQCalibration = IQ_CAL_DONE; 104659efa8b5SSam Leffler ichan->privFlags |= CHANNEL_IQVALID; 104714779705SSam Leffler ichan->iCoff = iCoff; 104814779705SSam Leffler ichan->qCoff = qCoff; 104914779705SSam Leffler } 10503b00bfe1SSam Leffler } else if (!IEEE80211_IS_CHAN_B(chan) && 10513b00bfe1SSam Leffler ahp->ah_bIQCalibration == IQ_CAL_DONE && 105259efa8b5SSam Leffler (ichan->privFlags & CHANNEL_IQVALID) == 0) { 105314779705SSam Leffler /* 105414779705SSam Leffler * Start IQ calibration if configured channel has changed. 105514779705SSam Leffler * Use a magic number of 15 based on default value. 105614779705SSam Leffler */ 105714779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 105814779705SSam Leffler AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, 105914779705SSam Leffler INIT_IQCAL_LOG_COUNT_MAX); 106014779705SSam Leffler OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 106114779705SSam Leffler AR_PHY_TIMING_CTRL4_DO_IQCAL); 106214779705SSam Leffler ahp->ah_bIQCalibration = IQ_CAL_RUNNING; 106314779705SSam Leffler } 106414779705SSam Leffler /* XXX EAR */ 106514779705SSam Leffler 106614779705SSam Leffler if (longCal) { 106714779705SSam Leffler /* Check noise floor results */ 106859efa8b5SSam Leffler ar5212GetNf(ah, chan); 106959efa8b5SSam Leffler if (!IEEE80211_IS_CHAN_CWINT(chan)) { 107014779705SSam Leffler /* Perform cal for 5Ghz channels and any OFDM on 5112 */ 107159efa8b5SSam Leffler if (IEEE80211_IS_CHAN_5GHZ(chan) || 107259efa8b5SSam Leffler (IS_RAD5112(ah) && IEEE80211_IS_CHAN_OFDM(chan))) 107314779705SSam Leffler ar5212RequestRfgain(ah); 107414779705SSam Leffler } 107514779705SSam Leffler } 107614779705SSam Leffler RESTORE_CCK(ah, chan, isBmode); 107714779705SSam Leffler 107814779705SSam Leffler return AH_TRUE; 107914779705SSam Leffler #undef IQ_CAL_TRIES 108014779705SSam Leffler } 108114779705SSam Leffler 108214779705SSam Leffler HAL_BOOL 108359efa8b5SSam Leffler ar5212PerCalibration(struct ath_hal *ah, struct ieee80211_channel *chan, 108459efa8b5SSam Leffler HAL_BOOL *isIQdone) 108514779705SSam Leffler { 108614779705SSam Leffler return ar5212PerCalibrationN(ah, chan, 0x1, AH_TRUE, isIQdone); 108714779705SSam Leffler } 108814779705SSam Leffler 108914779705SSam Leffler HAL_BOOL 109059efa8b5SSam Leffler ar5212ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *chan) 109114779705SSam Leffler { 109214779705SSam Leffler /* XXX */ 109314779705SSam Leffler return AH_TRUE; 109414779705SSam Leffler } 109514779705SSam Leffler 109614779705SSam Leffler /* 109714779705SSam Leffler * Write the given reset bit mask into the reset register 109814779705SSam Leffler */ 109914779705SSam Leffler static HAL_BOOL 110014779705SSam Leffler ar5212SetResetReg(struct ath_hal *ah, uint32_t resetMask) 110114779705SSam Leffler { 110214779705SSam Leffler uint32_t mask = resetMask ? resetMask : ~0; 110314779705SSam Leffler HAL_BOOL rt; 110414779705SSam Leffler 110514779705SSam Leffler /* XXX ar5212MacStop & co. */ 110614779705SSam Leffler 110714779705SSam Leffler if (IS_PCIE(ah)) { 110814779705SSam Leffler resetMask &= ~AR_RC_PCI; 110914779705SSam Leffler } 111014779705SSam Leffler 111114779705SSam Leffler (void) OS_REG_READ(ah, AR_RXDP);/* flush any pending MMR writes */ 111214779705SSam Leffler OS_REG_WRITE(ah, AR_RC, resetMask); 111314779705SSam Leffler OS_DELAY(15); /* need to wait at least 128 clocks 111414779705SSam Leffler when reseting PCI before read */ 111514779705SSam Leffler mask &= (AR_RC_MAC | AR_RC_BB); 111614779705SSam Leffler resetMask &= (AR_RC_MAC | AR_RC_BB); 111714779705SSam Leffler rt = ath_hal_wait(ah, AR_RC, mask, resetMask); 111814779705SSam Leffler if ((resetMask & AR_RC_MAC) == 0) { 111914779705SSam Leffler if (isBigEndian()) { 112014779705SSam Leffler /* 112114779705SSam Leffler * Set CFG, little-endian for register 112214779705SSam Leffler * and descriptor accesses. 112314779705SSam Leffler */ 112414779705SSam Leffler mask = INIT_CONFIG_STATUS | AR_CFG_SWRD | AR_CFG_SWRG; 112514779705SSam Leffler #ifndef AH_NEED_DESC_SWAP 112614779705SSam Leffler mask |= AR_CFG_SWTD; 112714779705SSam Leffler #endif 112814779705SSam Leffler OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask)); 112914779705SSam Leffler } else 113014779705SSam Leffler OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS); 113114779705SSam Leffler if (ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 113214779705SSam Leffler (void) OS_REG_READ(ah, AR_ISR_RAC); 113314779705SSam Leffler } 113414779705SSam Leffler 113514779705SSam Leffler /* track PHY power state so we don't try to r/w BB registers */ 113614779705SSam Leffler AH5212(ah)->ah_phyPowerOn = ((resetMask & AR_RC_BB) == 0); 113714779705SSam Leffler return rt; 113814779705SSam Leffler } 113914779705SSam Leffler 114014779705SSam Leffler int16_t 114114779705SSam Leffler ar5212GetNoiseFloor(struct ath_hal *ah) 114214779705SSam Leffler { 114314779705SSam Leffler int16_t nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff; 114414779705SSam Leffler if (nf & 0x100) 114514779705SSam Leffler nf = 0 - ((nf ^ 0x1ff) + 1); 114614779705SSam Leffler return nf; 114714779705SSam Leffler } 114814779705SSam Leffler 114914779705SSam Leffler static HAL_BOOL 115059efa8b5SSam Leffler getNoiseFloorThresh(struct ath_hal *ah, const struct ieee80211_channel *chan, 115114779705SSam Leffler int16_t *nft) 115214779705SSam Leffler { 115314779705SSam Leffler const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 115414779705SSam Leffler 115514779705SSam Leffler HALASSERT(ah->ah_magic == AR5212_MAGIC); 115614779705SSam Leffler 115759efa8b5SSam Leffler switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) { 115859efa8b5SSam Leffler case IEEE80211_CHAN_A: 115914779705SSam Leffler *nft = ee->ee_noiseFloorThresh[headerInfo11A]; 116014779705SSam Leffler break; 116159efa8b5SSam Leffler case IEEE80211_CHAN_B: 116214779705SSam Leffler *nft = ee->ee_noiseFloorThresh[headerInfo11B]; 116314779705SSam Leffler break; 116459efa8b5SSam Leffler case IEEE80211_CHAN_G: 116559efa8b5SSam Leffler case IEEE80211_CHAN_PUREG: /* NB: really 108G */ 116614779705SSam Leffler *nft = ee->ee_noiseFloorThresh[headerInfo11G]; 116714779705SSam Leffler break; 116814779705SSam Leffler default: 116959efa8b5SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, 117059efa8b5SSam Leffler "%s: invalid channel flags %u/0x%x\n", 117159efa8b5SSam Leffler __func__, chan->ic_freq, chan->ic_flags); 117214779705SSam Leffler return AH_FALSE; 117314779705SSam Leffler } 117414779705SSam Leffler return AH_TRUE; 117514779705SSam Leffler } 117614779705SSam Leffler 117714779705SSam Leffler /* 117814779705SSam Leffler * Setup the noise floor cal history buffer. 117914779705SSam Leffler */ 118014779705SSam Leffler void 118114779705SSam Leffler ar5212InitNfCalHistBuffer(struct ath_hal *ah) 118214779705SSam Leffler { 118314779705SSam Leffler struct ath_hal_5212 *ahp = AH5212(ah); 118414779705SSam Leffler int i; 118514779705SSam Leffler 118614779705SSam Leffler ahp->ah_nfCalHist.first_run = 1; 118714779705SSam Leffler ahp->ah_nfCalHist.currIndex = 0; 118814779705SSam Leffler ahp->ah_nfCalHist.privNF = AR5212_CCA_MAX_GOOD_VALUE; 118914779705SSam Leffler ahp->ah_nfCalHist.invalidNFcount = AR512_NF_CAL_HIST_MAX; 119014779705SSam Leffler for (i = 0; i < AR512_NF_CAL_HIST_MAX; i ++) 119114779705SSam Leffler ahp->ah_nfCalHist.nfCalBuffer[i] = AR5212_CCA_MAX_GOOD_VALUE; 119214779705SSam Leffler } 119314779705SSam Leffler 119414779705SSam Leffler /* 119514779705SSam Leffler * Add a noise floor value to the ring buffer. 119614779705SSam Leffler */ 119714779705SSam Leffler static __inline void 119814779705SSam Leffler updateNFHistBuff(struct ar5212NfCalHist *h, int16_t nf) 119914779705SSam Leffler { 120014779705SSam Leffler h->nfCalBuffer[h->currIndex] = nf; 120114779705SSam Leffler if (++h->currIndex >= AR512_NF_CAL_HIST_MAX) 120214779705SSam Leffler h->currIndex = 0; 120314779705SSam Leffler } 120414779705SSam Leffler 120514779705SSam Leffler /* 120614779705SSam Leffler * Return the median noise floor value in the ring buffer. 120714779705SSam Leffler */ 120814779705SSam Leffler int16_t 120914779705SSam Leffler ar5212GetNfHistMid(const int16_t calData[AR512_NF_CAL_HIST_MAX]) 121014779705SSam Leffler { 121114779705SSam Leffler int16_t sort[AR512_NF_CAL_HIST_MAX]; 121214779705SSam Leffler int i, j; 121314779705SSam Leffler 121414779705SSam Leffler OS_MEMCPY(sort, calData, AR512_NF_CAL_HIST_MAX*sizeof(int16_t)); 121514779705SSam Leffler for (i = 0; i < AR512_NF_CAL_HIST_MAX-1; i ++) { 121614779705SSam Leffler for (j = 1; j < AR512_NF_CAL_HIST_MAX-i; j ++) { 121714779705SSam Leffler if (sort[j] > sort[j-1]) { 121814779705SSam Leffler int16_t nf = sort[j]; 121914779705SSam Leffler sort[j] = sort[j-1]; 122014779705SSam Leffler sort[j-1] = nf; 122114779705SSam Leffler } 122214779705SSam Leffler } 122314779705SSam Leffler } 122414779705SSam Leffler return sort[(AR512_NF_CAL_HIST_MAX-1)>>1]; 122514779705SSam Leffler } 122614779705SSam Leffler 122714779705SSam Leffler /* 122814779705SSam Leffler * Read the NF and check it against the noise floor threshhold 122914779705SSam Leffler */ 123014779705SSam Leffler int16_t 123159efa8b5SSam Leffler ar5212GetNf(struct ath_hal *ah, struct ieee80211_channel *chan) 123214779705SSam Leffler { 123314779705SSam Leffler struct ath_hal_5212 *ahp = AH5212(ah); 123414779705SSam Leffler struct ar5212NfCalHist *h = &ahp->ah_nfCalHist; 123559efa8b5SSam Leffler HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 123614779705SSam Leffler int16_t nf, nfThresh; 123714779705SSam Leffler int32_t val; 123814779705SSam Leffler 123914779705SSam Leffler if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { 124014779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, 124114779705SSam Leffler "%s: NF did not complete in calibration window\n", __func__); 124259efa8b5SSam Leffler ichan->rawNoiseFloor = h->privNF; /* most recent value */ 124359efa8b5SSam Leffler return ichan->rawNoiseFloor; 124414779705SSam Leffler } 124514779705SSam Leffler 124614779705SSam Leffler /* 124714779705SSam Leffler * Finished NF cal, check against threshold. 124814779705SSam Leffler */ 124914779705SSam Leffler nf = ar5212GetNoiseFloor(ah); 125014779705SSam Leffler if (getNoiseFloorThresh(ah, chan, &nfThresh)) { 125114779705SSam Leffler if (nf > nfThresh) { 125214779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, 125314779705SSam Leffler "%s: noise floor failed detected; detected %u, " 125414779705SSam Leffler "threshold %u\n", __func__, nf, nfThresh); 125514779705SSam Leffler /* 125614779705SSam Leffler * NB: Don't discriminate 2.4 vs 5Ghz, if this 125714779705SSam Leffler * happens it indicates a problem regardless 125814779705SSam Leffler * of the band. 125914779705SSam Leffler */ 126059efa8b5SSam Leffler chan->ic_state |= IEEE80211_CHANSTATE_CWINT; 126114779705SSam Leffler nf = 0; 126214779705SSam Leffler } 126314779705SSam Leffler } else 126414779705SSam Leffler nf = 0; 126514779705SSam Leffler 126614779705SSam Leffler /* 126714779705SSam Leffler * Pass through histogram and write median value as 126814779705SSam Leffler * calculated from the accrued window. We require a 126914779705SSam Leffler * full window of in-range values to be seen before we 127014779705SSam Leffler * start using the history. 127114779705SSam Leffler */ 127214779705SSam Leffler updateNFHistBuff(h, nf); 127314779705SSam Leffler if (h->first_run) { 127414779705SSam Leffler if (nf < AR5212_CCA_MIN_BAD_VALUE || 127514779705SSam Leffler nf > AR5212_CCA_MAX_HIGH_VALUE) { 127614779705SSam Leffler nf = AR5212_CCA_MAX_GOOD_VALUE; 127714779705SSam Leffler h->invalidNFcount = AR512_NF_CAL_HIST_MAX; 127814779705SSam Leffler } else if (--(h->invalidNFcount) == 0) { 127914779705SSam Leffler h->first_run = 0; 128014779705SSam Leffler h->privNF = nf = ar5212GetNfHistMid(h->nfCalBuffer); 128114779705SSam Leffler } else { 128214779705SSam Leffler nf = AR5212_CCA_MAX_GOOD_VALUE; 128314779705SSam Leffler } 128414779705SSam Leffler } else { 128514779705SSam Leffler h->privNF = nf = ar5212GetNfHistMid(h->nfCalBuffer); 128614779705SSam Leffler } 128714779705SSam Leffler 128814779705SSam Leffler val = OS_REG_READ(ah, AR_PHY(25)); 128914779705SSam Leffler val &= 0xFFFFFE00; 129014779705SSam Leffler val |= (((uint32_t)nf << 1) & 0x1FF); 129114779705SSam Leffler OS_REG_WRITE(ah, AR_PHY(25), val); 129214779705SSam Leffler OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); 129314779705SSam Leffler OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); 129414779705SSam Leffler OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 129514779705SSam Leffler 129614779705SSam Leffler if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF, 0)) { 129714779705SSam Leffler #ifdef AH_DEBUG 129814779705SSam Leffler ath_hal_printf(ah, "%s: AGC not ready AGC_CONTROL 0x%x\n", 129914779705SSam Leffler __func__, OS_REG_READ(ah, AR_PHY_AGC_CONTROL)); 130014779705SSam Leffler #endif 130114779705SSam Leffler } 130214779705SSam Leffler 130314779705SSam Leffler /* 130414779705SSam Leffler * Now load a high maxCCAPower value again so that we're 130514779705SSam Leffler * not capped by the median we just loaded 130614779705SSam Leffler */ 130714779705SSam Leffler val &= 0xFFFFFE00; 130814779705SSam Leffler val |= (((uint32_t)(-50) << 1) & 0x1FF); 130914779705SSam Leffler OS_REG_WRITE(ah, AR_PHY(25), val); 131014779705SSam Leffler OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); 131114779705SSam Leffler OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); 131214779705SSam Leffler OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 131314779705SSam Leffler 131459efa8b5SSam Leffler return (ichan->rawNoiseFloor = nf); 131514779705SSam Leffler } 131614779705SSam Leffler 131714779705SSam Leffler /* 131814779705SSam Leffler * Set up compression configuration registers 131914779705SSam Leffler */ 132014779705SSam Leffler void 132114779705SSam Leffler ar5212SetCompRegs(struct ath_hal *ah) 132214779705SSam Leffler { 132314779705SSam Leffler struct ath_hal_5212 *ahp = AH5212(ah); 132414779705SSam Leffler int i; 132514779705SSam Leffler 132614779705SSam Leffler /* Check if h/w supports compression */ 132714779705SSam Leffler if (!AH_PRIVATE(ah)->ah_caps.halCompressSupport) 132814779705SSam Leffler return; 132914779705SSam Leffler 133014779705SSam Leffler OS_REG_WRITE(ah, AR_DCCFG, 1); 133114779705SSam Leffler 133214779705SSam Leffler OS_REG_WRITE(ah, AR_CCFG, 133314779705SSam Leffler (AR_COMPRESSION_WINDOW_SIZE >> 8) & AR_CCFG_WIN_M); 133414779705SSam Leffler 133514779705SSam Leffler OS_REG_WRITE(ah, AR_CCFG, 133614779705SSam Leffler OS_REG_READ(ah, AR_CCFG) | AR_CCFG_MIB_INT_EN); 133714779705SSam Leffler OS_REG_WRITE(ah, AR_CCUCFG, 133814779705SSam Leffler AR_CCUCFG_RESET_VAL | AR_CCUCFG_CATCHUP_EN); 133914779705SSam Leffler 134014779705SSam Leffler OS_REG_WRITE(ah, AR_CPCOVF, 0); 134114779705SSam Leffler 134214779705SSam Leffler /* reset decompression mask */ 134314779705SSam Leffler for (i = 0; i < HAL_DECOMP_MASK_SIZE; i++) { 134414779705SSam Leffler OS_REG_WRITE(ah, AR_DCM_A, i); 134514779705SSam Leffler OS_REG_WRITE(ah, AR_DCM_D, ahp->ah_decompMask[i]); 134614779705SSam Leffler } 134714779705SSam Leffler } 134814779705SSam Leffler 134914779705SSam Leffler HAL_BOOL 135014779705SSam Leffler ar5212SetAntennaSwitchInternal(struct ath_hal *ah, HAL_ANT_SETTING settings, 135159efa8b5SSam Leffler const struct ieee80211_channel *chan) 135214779705SSam Leffler { 135314779705SSam Leffler #define ANT_SWITCH_TABLE1 AR_PHY(88) 135414779705SSam Leffler #define ANT_SWITCH_TABLE2 AR_PHY(89) 135514779705SSam Leffler struct ath_hal_5212 *ahp = AH5212(ah); 135614779705SSam Leffler const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 135714779705SSam Leffler uint32_t antSwitchA, antSwitchB; 135814779705SSam Leffler int ix; 135914779705SSam Leffler 136014779705SSam Leffler HALASSERT(ah->ah_magic == AR5212_MAGIC); 136114779705SSam Leffler HALASSERT(ahp->ah_phyPowerOn); 136214779705SSam Leffler 136359efa8b5SSam Leffler switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) { 136459efa8b5SSam Leffler case IEEE80211_CHAN_A: 136559efa8b5SSam Leffler ix = 0; 136659efa8b5SSam Leffler break; 136759efa8b5SSam Leffler case IEEE80211_CHAN_G: 136859efa8b5SSam Leffler case IEEE80211_CHAN_PUREG: /* NB: 108G */ 136959efa8b5SSam Leffler ix = 2; 137059efa8b5SSam Leffler break; 137159efa8b5SSam Leffler case IEEE80211_CHAN_B: 137259efa8b5SSam Leffler if (IS_2425(ah) || IS_2417(ah)) { 137359efa8b5SSam Leffler /* NB: Nala/Swan: 11b is handled using 11g */ 137459efa8b5SSam Leffler ix = 2; 137559efa8b5SSam Leffler } else 137659efa8b5SSam Leffler ix = 1; 137759efa8b5SSam Leffler break; 137814779705SSam Leffler default: 137914779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n", 138059efa8b5SSam Leffler __func__, chan->ic_flags); 138114779705SSam Leffler return AH_FALSE; 138214779705SSam Leffler } 138314779705SSam Leffler 138414779705SSam Leffler antSwitchA = ee->ee_antennaControl[1][ix] 138514779705SSam Leffler | (ee->ee_antennaControl[2][ix] << 6) 138614779705SSam Leffler | (ee->ee_antennaControl[3][ix] << 12) 138714779705SSam Leffler | (ee->ee_antennaControl[4][ix] << 18) 138814779705SSam Leffler | (ee->ee_antennaControl[5][ix] << 24) 138914779705SSam Leffler ; 139014779705SSam Leffler antSwitchB = ee->ee_antennaControl[6][ix] 139114779705SSam Leffler | (ee->ee_antennaControl[7][ix] << 6) 139214779705SSam Leffler | (ee->ee_antennaControl[8][ix] << 12) 139314779705SSam Leffler | (ee->ee_antennaControl[9][ix] << 18) 139414779705SSam Leffler | (ee->ee_antennaControl[10][ix] << 24) 139514779705SSam Leffler ; 139614779705SSam Leffler /* 139714779705SSam Leffler * For fixed antenna, give the same setting for both switch banks 139814779705SSam Leffler */ 139914779705SSam Leffler switch (settings) { 140014779705SSam Leffler case HAL_ANT_FIXED_A: 140114779705SSam Leffler antSwitchB = antSwitchA; 140214779705SSam Leffler break; 140314779705SSam Leffler case HAL_ANT_FIXED_B: 140414779705SSam Leffler antSwitchA = antSwitchB; 140514779705SSam Leffler break; 140614779705SSam Leffler case HAL_ANT_VARIABLE: 140714779705SSam Leffler break; 140814779705SSam Leffler default: 140914779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad antenna setting %u\n", 141014779705SSam Leffler __func__, settings); 141114779705SSam Leffler return AH_FALSE; 141214779705SSam Leffler } 141314779705SSam Leffler if (antSwitchB == antSwitchA) { 141414779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_RFPARAM, 141514779705SSam Leffler "%s: Setting fast diversity off.\n", __func__); 141614779705SSam Leffler OS_REG_CLR_BIT(ah,AR_PHY_CCK_DETECT, 141714779705SSam Leffler AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 141814779705SSam Leffler ahp->ah_diversity = AH_FALSE; 141914779705SSam Leffler } else { 142014779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_RFPARAM, 142114779705SSam Leffler "%s: Setting fast diversity on.\n", __func__); 142214779705SSam Leffler OS_REG_SET_BIT(ah,AR_PHY_CCK_DETECT, 142314779705SSam Leffler AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 142414779705SSam Leffler ahp->ah_diversity = AH_TRUE; 142514779705SSam Leffler } 142614779705SSam Leffler ahp->ah_antControl = settings; 142714779705SSam Leffler 142814779705SSam Leffler OS_REG_WRITE(ah, ANT_SWITCH_TABLE1, antSwitchA); 142914779705SSam Leffler OS_REG_WRITE(ah, ANT_SWITCH_TABLE2, antSwitchB); 143014779705SSam Leffler 143114779705SSam Leffler return AH_TRUE; 143214779705SSam Leffler #undef ANT_SWITCH_TABLE2 143314779705SSam Leffler #undef ANT_SWITCH_TABLE1 143414779705SSam Leffler } 143514779705SSam Leffler 143614779705SSam Leffler HAL_BOOL 143759efa8b5SSam Leffler ar5212IsSpurChannel(struct ath_hal *ah, const struct ieee80211_channel *chan) 143814779705SSam Leffler { 143959efa8b5SSam Leffler uint16_t freq = ath_hal_gethwchannel(ah, chan); 144014779705SSam Leffler uint32_t clockFreq = 144114779705SSam Leffler ((IS_5413(ah) || IS_RAD5112_ANY(ah) || IS_2417(ah)) ? 40 : 32); 144259efa8b5SSam Leffler return ( ((freq % clockFreq) != 0) 144359efa8b5SSam Leffler && (((freq % clockFreq) < 10) 144459efa8b5SSam Leffler || (((freq) % clockFreq) > 22)) ); 144514779705SSam Leffler } 144614779705SSam Leffler 144714779705SSam Leffler /* 144814779705SSam Leffler * Read EEPROM header info and program the device for correct operation 144914779705SSam Leffler * given the channel value. 145014779705SSam Leffler */ 145114779705SSam Leffler HAL_BOOL 145259efa8b5SSam Leffler ar5212SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan) 145314779705SSam Leffler { 145414779705SSam Leffler #define NO_FALSE_DETECT_BACKOFF 2 145514779705SSam Leffler #define CB22_FALSE_DETECT_BACKOFF 6 145614779705SSam Leffler #define AR_PHY_BIS(_ah, _reg, _mask, _val) \ 145714779705SSam Leffler OS_REG_WRITE(_ah, AR_PHY(_reg), \ 145814779705SSam Leffler (OS_REG_READ(_ah, AR_PHY(_reg)) & _mask) | (_val)); 145914779705SSam Leffler struct ath_hal_5212 *ahp = AH5212(ah); 146014779705SSam Leffler const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 146114779705SSam Leffler int arrayMode, falseDectectBackoff; 146259efa8b5SSam Leffler int is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 146359efa8b5SSam Leffler HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 146414779705SSam Leffler int8_t adcDesiredSize, pgaDesiredSize; 146514779705SSam Leffler uint16_t switchSettling, txrxAtten, rxtxMargin; 146614779705SSam Leffler int iCoff, qCoff; 146714779705SSam Leffler 146814779705SSam Leffler HALASSERT(ah->ah_magic == AR5212_MAGIC); 146914779705SSam Leffler 147059efa8b5SSam Leffler switch (chan->ic_flags & IEEE80211_CHAN_ALLTURBOFULL) { 147159efa8b5SSam Leffler case IEEE80211_CHAN_A: 147259efa8b5SSam Leffler case IEEE80211_CHAN_ST: 147314779705SSam Leffler arrayMode = headerInfo11A; 147414779705SSam Leffler if (!IS_RAD5112_ANY(ah) && !IS_2413(ah) && !IS_5413(ah)) 147514779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, 147614779705SSam Leffler AR_PHY_FRAME_CTL_TX_CLIP, 147714779705SSam Leffler ahp->ah_gainValues.currStep->paramVal[GP_TXCLIP]); 147814779705SSam Leffler break; 147959efa8b5SSam Leffler case IEEE80211_CHAN_B: 148014779705SSam Leffler arrayMode = headerInfo11B; 148114779705SSam Leffler break; 148259efa8b5SSam Leffler case IEEE80211_CHAN_G: 148359efa8b5SSam Leffler case IEEE80211_CHAN_108G: 148414779705SSam Leffler arrayMode = headerInfo11G; 148514779705SSam Leffler break; 148614779705SSam Leffler default: 148714779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n", 148859efa8b5SSam Leffler __func__, chan->ic_flags); 148914779705SSam Leffler return AH_FALSE; 149014779705SSam Leffler } 149114779705SSam Leffler 149214779705SSam Leffler /* Set the antenna register(s) correctly for the chip revision */ 149314779705SSam Leffler AR_PHY_BIS(ah, 68, 0xFFFFFC06, 149414779705SSam Leffler (ee->ee_antennaControl[0][arrayMode] << 4) | 0x1); 149514779705SSam Leffler 149614779705SSam Leffler ar5212SetAntennaSwitchInternal(ah, ahp->ah_antControl, chan); 149714779705SSam Leffler 149814779705SSam Leffler /* Set the Noise Floor Thresh on ar5211 devices */ 149914779705SSam Leffler OS_REG_WRITE(ah, AR_PHY(90), 150014779705SSam Leffler (ee->ee_noiseFloorThresh[arrayMode] & 0x1FF) 150114779705SSam Leffler | (1 << 9)); 150214779705SSam Leffler 150359efa8b5SSam Leffler if (ee->ee_version >= AR_EEPROM_VER5_0 && IEEE80211_IS_CHAN_TURBO(chan)) { 150414779705SSam Leffler switchSettling = ee->ee_switchSettlingTurbo[is2GHz]; 150514779705SSam Leffler adcDesiredSize = ee->ee_adcDesiredSizeTurbo[is2GHz]; 150614779705SSam Leffler pgaDesiredSize = ee->ee_pgaDesiredSizeTurbo[is2GHz]; 150714779705SSam Leffler txrxAtten = ee->ee_txrxAttenTurbo[is2GHz]; 150814779705SSam Leffler rxtxMargin = ee->ee_rxtxMarginTurbo[is2GHz]; 150914779705SSam Leffler } else { 151014779705SSam Leffler switchSettling = ee->ee_switchSettling[arrayMode]; 151114779705SSam Leffler adcDesiredSize = ee->ee_adcDesiredSize[arrayMode]; 151214779705SSam Leffler pgaDesiredSize = ee->ee_pgaDesiredSize[is2GHz]; 151314779705SSam Leffler txrxAtten = ee->ee_txrxAtten[is2GHz]; 151414779705SSam Leffler rxtxMargin = ee->ee_rxtxMargin[is2GHz]; 151514779705SSam Leffler } 151614779705SSam Leffler 151714779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, 151814779705SSam Leffler AR_PHY_SETTLING_SWITCH, switchSettling); 151914779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, 152014779705SSam Leffler AR_PHY_DESIRED_SZ_ADC, adcDesiredSize); 152114779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, 152214779705SSam Leffler AR_PHY_DESIRED_SZ_PGA, pgaDesiredSize); 152314779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 152414779705SSam Leffler AR_PHY_RXGAIN_TXRX_ATTEN, txrxAtten); 152514779705SSam Leffler OS_REG_WRITE(ah, AR_PHY(13), 152614779705SSam Leffler (ee->ee_txEndToXPAOff[arrayMode] << 24) 152714779705SSam Leffler | (ee->ee_txEndToXPAOff[arrayMode] << 16) 152814779705SSam Leffler | (ee->ee_txFrameToXPAOn[arrayMode] << 8) 152914779705SSam Leffler | ee->ee_txFrameToXPAOn[arrayMode]); 153014779705SSam Leffler AR_PHY_BIS(ah, 10, 0xFFFF00FF, 153114779705SSam Leffler ee->ee_txEndToXLNAOn[arrayMode] << 8); 153214779705SSam Leffler AR_PHY_BIS(ah, 25, 0xFFF80FFF, 153314779705SSam Leffler (ee->ee_thresh62[arrayMode] << 12) & 0x7F000); 153414779705SSam Leffler 153514779705SSam Leffler /* 153614779705SSam Leffler * False detect backoff - suspected 32 MHz spur causes false 153714779705SSam Leffler * detects in OFDM, causing Tx Hangs. Decrease weak signal 153814779705SSam Leffler * sensitivity for this card. 153914779705SSam Leffler */ 154014779705SSam Leffler falseDectectBackoff = NO_FALSE_DETECT_BACKOFF; 154114779705SSam Leffler if (ee->ee_version < AR_EEPROM_VER3_3) { 154214779705SSam Leffler /* XXX magic number */ 154314779705SSam Leffler if (AH_PRIVATE(ah)->ah_subvendorid == 0x1022 && 154459efa8b5SSam Leffler IEEE80211_IS_CHAN_OFDM(chan)) 154514779705SSam Leffler falseDectectBackoff += CB22_FALSE_DETECT_BACKOFF; 154614779705SSam Leffler } else { 154759efa8b5SSam Leffler if (ar5212IsSpurChannel(ah, chan)) 154814779705SSam Leffler falseDectectBackoff += ee->ee_falseDetectBackoff[arrayMode]; 154914779705SSam Leffler } 155014779705SSam Leffler AR_PHY_BIS(ah, 73, 0xFFFFFF01, (falseDectectBackoff << 1) & 0xFE); 155114779705SSam Leffler 155259efa8b5SSam Leffler if (ichan->privFlags & CHANNEL_IQVALID) { 155359efa8b5SSam Leffler iCoff = ichan->iCoff; 155459efa8b5SSam Leffler qCoff = ichan->qCoff; 155514779705SSam Leffler } else { 155614779705SSam Leffler iCoff = ee->ee_iqCalI[is2GHz]; 155714779705SSam Leffler qCoff = ee->ee_iqCalQ[is2GHz]; 155814779705SSam Leffler } 155914779705SSam Leffler 156014779705SSam Leffler /* write previous IQ results */ 156114779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 156214779705SSam Leffler AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, iCoff); 156314779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 156414779705SSam Leffler AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, qCoff); 156514779705SSam Leffler OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 156614779705SSam Leffler AR_PHY_TIMING_CTRL4_IQCORR_ENABLE); 156714779705SSam Leffler 156814779705SSam Leffler if (ee->ee_version >= AR_EEPROM_VER4_1) { 156959efa8b5SSam Leffler if (!IEEE80211_IS_CHAN_108G(chan) || ee->ee_version >= AR_EEPROM_VER5_0) 157014779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 157114779705SSam Leffler AR_PHY_GAIN_2GHZ_RXTX_MARGIN, rxtxMargin); 157214779705SSam Leffler } 157314779705SSam Leffler if (ee->ee_version >= AR_EEPROM_VER5_1) { 157414779705SSam Leffler /* for now always disabled */ 157514779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_HEAVY_CLIP_ENABLE, 0); 157614779705SSam Leffler } 157714779705SSam Leffler 157814779705SSam Leffler return AH_TRUE; 157914779705SSam Leffler #undef AR_PHY_BIS 158014779705SSam Leffler #undef NO_FALSE_DETECT_BACKOFF 158114779705SSam Leffler #undef CB22_FALSE_DETECT_BACKOFF 158214779705SSam Leffler } 158314779705SSam Leffler 158414779705SSam Leffler /* 158514779705SSam Leffler * Apply Spur Immunity to Boards that require it. 158614779705SSam Leffler * Applies only to OFDM RX operation. 158714779705SSam Leffler */ 158814779705SSam Leffler 158914779705SSam Leffler void 159059efa8b5SSam Leffler ar5212SetSpurMitigation(struct ath_hal *ah, 159159efa8b5SSam Leffler const struct ieee80211_channel *chan) 159214779705SSam Leffler { 159314779705SSam Leffler uint32_t pilotMask[2] = {0, 0}, binMagMask[4] = {0, 0, 0 , 0}; 159414779705SSam Leffler uint16_t i, finalSpur, curChanAsSpur, binWidth = 0, spurDetectWidth, spurChan; 159514779705SSam Leffler int32_t spurDeltaPhase = 0, spurFreqSd = 0, spurOffset, binOffsetNumT16, curBinOffset; 159614779705SSam Leffler int16_t numBinOffsets; 159714779705SSam Leffler static const uint16_t magMapFor4[4] = {1, 2, 2, 1}; 159814779705SSam Leffler static const uint16_t magMapFor3[3] = {1, 2, 1}; 159914779705SSam Leffler const uint16_t *pMagMap; 160059efa8b5SSam Leffler HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 160159efa8b5SSam Leffler HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 160214779705SSam Leffler uint32_t val; 160314779705SSam Leffler 160414779705SSam Leffler #define CHAN_TO_SPUR(_f, _freq) ( ((_freq) - ((_f) ? 2300 : 4900)) * 10 ) 160514779705SSam Leffler if (IS_2417(ah)) { 160614779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: no spur mitigation\n", 160714779705SSam Leffler __func__); 160814779705SSam Leffler return; 160914779705SSam Leffler } 161014779705SSam Leffler 161114779705SSam Leffler curChanAsSpur = CHAN_TO_SPUR(is2GHz, ichan->channel); 161214779705SSam Leffler 161314779705SSam Leffler if (ichan->mainSpur) { 161414779705SSam Leffler /* Pull out the saved spur value */ 161514779705SSam Leffler finalSpur = ichan->mainSpur; 161614779705SSam Leffler } else { 161714779705SSam Leffler /* 161814779705SSam Leffler * Check if spur immunity should be performed for this channel 161914779705SSam Leffler * Should only be performed once per channel and then saved 162014779705SSam Leffler */ 162114779705SSam Leffler finalSpur = AR_NO_SPUR; 162214779705SSam Leffler spurDetectWidth = HAL_SPUR_CHAN_WIDTH; 162359efa8b5SSam Leffler if (IEEE80211_IS_CHAN_TURBO(chan)) 162414779705SSam Leffler spurDetectWidth *= 2; 162514779705SSam Leffler 162614779705SSam Leffler /* Decide if any spur affects the current channel */ 162714779705SSam Leffler for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 162814779705SSam Leffler spurChan = ath_hal_getSpurChan(ah, i, is2GHz); 162914779705SSam Leffler if (spurChan == AR_NO_SPUR) { 163014779705SSam Leffler break; 163114779705SSam Leffler } 163214779705SSam Leffler if ((curChanAsSpur - spurDetectWidth <= (spurChan & HAL_SPUR_VAL_MASK)) && 163314779705SSam Leffler (curChanAsSpur + spurDetectWidth >= (spurChan & HAL_SPUR_VAL_MASK))) { 163414779705SSam Leffler finalSpur = spurChan & HAL_SPUR_VAL_MASK; 163514779705SSam Leffler break; 163614779705SSam Leffler } 163714779705SSam Leffler } 163814779705SSam Leffler /* Save detected spur (or no spur) for this channel */ 163914779705SSam Leffler ichan->mainSpur = finalSpur; 164014779705SSam Leffler } 164114779705SSam Leffler 164214779705SSam Leffler /* Write spur immunity data */ 164314779705SSam Leffler if (finalSpur == AR_NO_SPUR) { 164414779705SSam Leffler /* Disable Spur Immunity Regs if they appear set */ 164514779705SSam Leffler if (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER) { 164614779705SSam Leffler /* Clear Spur Delta Phase, Spur Freq, and enable bits */ 164714779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_RATE, 0); 164814779705SSam Leffler val = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4); 164914779705SSam Leffler val &= ~(AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 165014779705SSam Leffler AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 165114779705SSam Leffler AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 165214779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_MASK_CTL, val); 165314779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_TIMING11, 0); 165414779705SSam Leffler 165514779705SSam Leffler /* Clear pilot masks */ 165614779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_TIMING7, 0); 165714779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_TIMING8, AR_PHY_TIMING8_PILOT_MASK_2, 0); 165814779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_TIMING9, 0); 165914779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_TIMING10, AR_PHY_TIMING10_PILOT_MASK_2, 0); 166014779705SSam Leffler 166114779705SSam Leffler /* Clear magnitude masks */ 166214779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, 0); 166314779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, 0); 166414779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, 0); 166514779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_MASK_4, 0); 166614779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, 0); 166714779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, 0); 166814779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, 0); 166914779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_BIN_MASK2_4, AR_PHY_BIN_MASK2_4_MASK_4, 0); 167014779705SSam Leffler } 167114779705SSam Leffler } else { 167214779705SSam Leffler spurOffset = finalSpur - curChanAsSpur; 167314779705SSam Leffler /* 167414779705SSam Leffler * Spur calculations: 167514779705SSam Leffler * spurDeltaPhase is (spurOffsetIn100KHz / chipFrequencyIn100KHz) << 21 167614779705SSam Leffler * spurFreqSd is (spurOffsetIn100KHz / sampleFrequencyIn100KHz) << 11 167714779705SSam Leffler */ 167859efa8b5SSam Leffler if (IEEE80211_IS_CHAN_TURBO(chan)) { 167959efa8b5SSam Leffler /* Chip Frequency & sampleFrequency are 80 MHz */ 168014779705SSam Leffler spurDeltaPhase = (spurOffset << 16) / 25; 168114779705SSam Leffler spurFreqSd = spurDeltaPhase >> 10; 168214779705SSam Leffler binWidth = HAL_BIN_WIDTH_TURBO_100HZ; 168359efa8b5SSam Leffler } else if (IEEE80211_IS_CHAN_G(chan)) { 168459efa8b5SSam Leffler /* Chip Frequency is 44MHz, sampleFrequency is 40 MHz */ 168559efa8b5SSam Leffler spurFreqSd = (spurOffset << 8) / 55; 168659efa8b5SSam Leffler spurDeltaPhase = (spurOffset << 17) / 25; 168759efa8b5SSam Leffler binWidth = HAL_BIN_WIDTH_BASE_100HZ; 168859efa8b5SSam Leffler } else { 168959efa8b5SSam Leffler HALASSERT(!IEEE80211_IS_CHAN_B(chan)); 169059efa8b5SSam Leffler /* Chip Frequency & sampleFrequency are 40 MHz */ 169159efa8b5SSam Leffler spurDeltaPhase = (spurOffset << 17) / 25; 169259efa8b5SSam Leffler spurFreqSd = spurDeltaPhase >> 10; 169359efa8b5SSam Leffler binWidth = HAL_BIN_WIDTH_BASE_100HZ; 169414779705SSam Leffler } 169514779705SSam Leffler 169614779705SSam Leffler /* Compute Pilot Mask */ 169714779705SSam Leffler binOffsetNumT16 = ((spurOffset * 1000) << 4) / binWidth; 169814779705SSam Leffler /* The spur is on a bin if it's remainder at times 16 is 0 */ 169914779705SSam Leffler if (binOffsetNumT16 & 0xF) { 170014779705SSam Leffler numBinOffsets = 4; 170114779705SSam Leffler pMagMap = magMapFor4; 170214779705SSam Leffler } else { 170314779705SSam Leffler numBinOffsets = 3; 170414779705SSam Leffler pMagMap = magMapFor3; 170514779705SSam Leffler } 170614779705SSam Leffler for (i = 0; i < numBinOffsets; i++) { 170714779705SSam Leffler if ((binOffsetNumT16 >> 4) > HAL_MAX_BINS_ALLOWED) { 170814779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, 170914779705SSam Leffler "Too man bins in spur mitigation\n"); 171014779705SSam Leffler return; 171114779705SSam Leffler } 171214779705SSam Leffler 171314779705SSam Leffler /* Get Pilot Mask values */ 171414779705SSam Leffler curBinOffset = (binOffsetNumT16 >> 4) + i + 25; 171514779705SSam Leffler if ((curBinOffset >= 0) && (curBinOffset <= 32)) { 171614779705SSam Leffler if (curBinOffset <= 25) 171714779705SSam Leffler pilotMask[0] |= 1 << curBinOffset; 171814779705SSam Leffler else if (curBinOffset >= 27) 171914779705SSam Leffler pilotMask[0] |= 1 << (curBinOffset - 1); 172014779705SSam Leffler } else if ((curBinOffset >= 33) && (curBinOffset <= 52)) 172114779705SSam Leffler pilotMask[1] |= 1 << (curBinOffset - 33); 172214779705SSam Leffler 172314779705SSam Leffler /* Get viterbi values */ 172414779705SSam Leffler if ((curBinOffset >= -1) && (curBinOffset <= 14)) 172514779705SSam Leffler binMagMask[0] |= pMagMap[i] << (curBinOffset + 1) * 2; 172614779705SSam Leffler else if ((curBinOffset >= 15) && (curBinOffset <= 30)) 172714779705SSam Leffler binMagMask[1] |= pMagMap[i] << (curBinOffset - 15) * 2; 172814779705SSam Leffler else if ((curBinOffset >= 31) && (curBinOffset <= 46)) 172914779705SSam Leffler binMagMask[2] |= pMagMap[i] << (curBinOffset -31) * 2; 173014779705SSam Leffler else if((curBinOffset >= 47) && (curBinOffset <= 53)) 173114779705SSam Leffler binMagMask[3] |= pMagMap[i] << (curBinOffset -47) * 2; 173214779705SSam Leffler } 173314779705SSam Leffler 173414779705SSam Leffler /* Write Spur Delta Phase, Spur Freq, and enable bits */ 173514779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_RATE, 0xFF); 173614779705SSam Leffler val = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4); 173714779705SSam Leffler val |= (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 173814779705SSam Leffler AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 173914779705SSam Leffler AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 174014779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, val); 174114779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_TIMING11, AR_PHY_TIMING11_USE_SPUR_IN_AGC | 174214779705SSam Leffler SM(spurFreqSd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 174314779705SSam Leffler SM(spurDeltaPhase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 174414779705SSam Leffler 174514779705SSam Leffler /* Write pilot masks */ 174614779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_TIMING7, pilotMask[0]); 174714779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_TIMING8, AR_PHY_TIMING8_PILOT_MASK_2, pilotMask[1]); 174814779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_TIMING9, pilotMask[0]); 174914779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_TIMING10, AR_PHY_TIMING10_PILOT_MASK_2, pilotMask[1]); 175014779705SSam Leffler 175114779705SSam Leffler /* Write magnitude masks */ 175214779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, binMagMask[0]); 175314779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, binMagMask[1]); 175414779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, binMagMask[2]); 175514779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_MASK_4, binMagMask[3]); 175614779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, binMagMask[0]); 175714779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, binMagMask[1]); 175814779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, binMagMask[2]); 175914779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_BIN_MASK2_4, AR_PHY_BIN_MASK2_4_MASK_4, binMagMask[3]); 176014779705SSam Leffler } 176114779705SSam Leffler #undef CHAN_TO_SPUR 176214779705SSam Leffler } 176314779705SSam Leffler 176414779705SSam Leffler 176514779705SSam Leffler /* 176614779705SSam Leffler * Delta slope coefficient computation. 176714779705SSam Leffler * Required for OFDM operation. 176814779705SSam Leffler */ 176914779705SSam Leffler void 177059efa8b5SSam Leffler ar5212SetDeltaSlope(struct ath_hal *ah, const struct ieee80211_channel *chan) 177114779705SSam Leffler { 177214779705SSam Leffler #define COEF_SCALE_S 24 177314779705SSam Leffler #define INIT_CLOCKMHZSCALED 0x64000000 177459efa8b5SSam Leffler uint16_t freq = ath_hal_gethwchannel(ah, chan); 177514779705SSam Leffler unsigned long coef_scaled, coef_exp, coef_man, ds_coef_exp, ds_coef_man; 177614779705SSam Leffler unsigned long clockMhzScaled = INIT_CLOCKMHZSCALED; 177714779705SSam Leffler 177859efa8b5SSam Leffler if (IEEE80211_IS_CHAN_TURBO(chan)) 177914779705SSam Leffler clockMhzScaled *= 2; 178014779705SSam Leffler /* half and quarter rate can divide the scaled clock by 2 or 4 respectively */ 178114779705SSam Leffler /* scale for selected channel bandwidth */ 178259efa8b5SSam Leffler if (IEEE80211_IS_CHAN_HALF(chan)) { 178314779705SSam Leffler clockMhzScaled = clockMhzScaled >> 1; 178459efa8b5SSam Leffler } else if (IEEE80211_IS_CHAN_QUARTER(chan)) { 178514779705SSam Leffler clockMhzScaled = clockMhzScaled >> 2; 178614779705SSam Leffler } 178714779705SSam Leffler 178814779705SSam Leffler /* 178914779705SSam Leffler * ALGO -> coef = 1e8/fcarrier*fclock/40; 179014779705SSam Leffler * scaled coef to provide precision for this floating calculation 179114779705SSam Leffler */ 179259efa8b5SSam Leffler coef_scaled = clockMhzScaled / freq; 179314779705SSam Leffler 179414779705SSam Leffler /* 179514779705SSam Leffler * ALGO -> coef_exp = 14-floor(log2(coef)); 179614779705SSam Leffler * floor(log2(x)) is the highest set bit position 179714779705SSam Leffler */ 179814779705SSam Leffler for (coef_exp = 31; coef_exp > 0; coef_exp--) 179914779705SSam Leffler if ((coef_scaled >> coef_exp) & 0x1) 180014779705SSam Leffler break; 180114779705SSam Leffler /* A coef_exp of 0 is a legal bit position but an unexpected coef_exp */ 180214779705SSam Leffler HALASSERT(coef_exp); 180314779705SSam Leffler coef_exp = 14 - (coef_exp - COEF_SCALE_S); 180414779705SSam Leffler 180514779705SSam Leffler /* 180614779705SSam Leffler * ALGO -> coef_man = floor(coef* 2^coef_exp+0.5); 180714779705SSam Leffler * The coefficient is already shifted up for scaling 180814779705SSam Leffler */ 180914779705SSam Leffler coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 181014779705SSam Leffler ds_coef_man = coef_man >> (COEF_SCALE_S - coef_exp); 181114779705SSam Leffler ds_coef_exp = coef_exp - 16; 181214779705SSam Leffler 181314779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, 181414779705SSam Leffler AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 181514779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, 181614779705SSam Leffler AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 181714779705SSam Leffler #undef INIT_CLOCKMHZSCALED 181814779705SSam Leffler #undef COEF_SCALE_S 181914779705SSam Leffler } 182014779705SSam Leffler 182114779705SSam Leffler /* 182214779705SSam Leffler * Set a limit on the overall output power. Used for dynamic 182314779705SSam Leffler * transmit power control and the like. 182414779705SSam Leffler * 182514779705SSam Leffler * NB: limit is in units of 0.5 dbM. 182614779705SSam Leffler */ 182714779705SSam Leffler HAL_BOOL 182814779705SSam Leffler ar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit) 182914779705SSam Leffler { 183059efa8b5SSam Leffler /* XXX blech, construct local writable copy */ 183159efa8b5SSam Leffler struct ieee80211_channel dummy = *AH_PRIVATE(ah)->ah_curchan; 183214779705SSam Leffler uint16_t dummyXpdGains[2]; 183359efa8b5SSam Leffler HAL_BOOL isBmode; 183414779705SSam Leffler 183559efa8b5SSam Leffler SAVE_CCK(ah, &dummy, isBmode); 183614779705SSam Leffler AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER); 183759efa8b5SSam Leffler return ar5212SetTransmitPower(ah, &dummy, dummyXpdGains); 183814779705SSam Leffler } 183914779705SSam Leffler 184014779705SSam Leffler /* 184114779705SSam Leffler * Set the transmit power in the baseband for the given 184214779705SSam Leffler * operating channel and mode. 184314779705SSam Leffler */ 184414779705SSam Leffler HAL_BOOL 184559efa8b5SSam Leffler ar5212SetTransmitPower(struct ath_hal *ah, 184659efa8b5SSam Leffler const struct ieee80211_channel *chan, uint16_t *rfXpdGain) 184714779705SSam Leffler { 184814779705SSam Leffler #define POW_OFDM(_r, _s) (((0 & 1)<< ((_s)+6)) | (((_r) & 0x3f) << (_s))) 184914779705SSam Leffler #define POW_CCK(_r, _s) (((_r) & 0x3f) << (_s)) 185014779705SSam Leffler #define N(a) (sizeof (a) / sizeof (a[0])) 185114779705SSam Leffler static const uint16_t tpcScaleReductionTable[5] = 185214779705SSam Leffler { 0, 3, 6, 9, MAX_RATE_POWER }; 185314779705SSam Leffler struct ath_hal_5212 *ahp = AH5212(ah); 185459efa8b5SSam Leffler uint16_t freq = ath_hal_gethwchannel(ah, chan); 185514779705SSam Leffler const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 185614779705SSam Leffler int16_t minPower, maxPower, tpcInDb, powerLimit; 185714779705SSam Leffler int i; 185814779705SSam Leffler 185914779705SSam Leffler HALASSERT(ah->ah_magic == AR5212_MAGIC); 186014779705SSam Leffler 186114779705SSam Leffler OS_MEMZERO(ahp->ah_pcdacTable, ahp->ah_pcdacTableSize); 186214779705SSam Leffler OS_MEMZERO(ahp->ah_ratesArray, sizeof(ahp->ah_ratesArray)); 186314779705SSam Leffler 186414779705SSam Leffler powerLimit = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 186514779705SSam Leffler if (powerLimit >= MAX_RATE_POWER || powerLimit == 0) 186614779705SSam Leffler tpcInDb = tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale]; 186714779705SSam Leffler else 186814779705SSam Leffler tpcInDb = 0; 186959efa8b5SSam Leffler if (!ar5212SetRateTable(ah, chan, tpcInDb, powerLimit, 187014779705SSam Leffler AH_TRUE, &minPower, &maxPower)) { 187114779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set rate table\n", 187214779705SSam Leffler __func__); 187314779705SSam Leffler return AH_FALSE; 187414779705SSam Leffler } 187514779705SSam Leffler if (!ahp->ah_rfHal->setPowerTable(ah, 187614779705SSam Leffler &minPower, &maxPower, chan, rfXpdGain)) { 187714779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n", 187814779705SSam Leffler __func__); 187914779705SSam Leffler return AH_FALSE; 188014779705SSam Leffler } 188114779705SSam Leffler 188214779705SSam Leffler /* 188314779705SSam Leffler * Adjust XR power/rate up by 2 dB to account for greater peak 188414779705SSam Leffler * to avg ratio - except in newer avg power designs 188514779705SSam Leffler */ 188614779705SSam Leffler if (!IS_2413(ah) && !IS_5413(ah)) 188714779705SSam Leffler ahp->ah_ratesArray[15] += 4; 188814779705SSam Leffler /* 188914779705SSam Leffler * txPowerIndexOffset is set by the SetPowerTable() call - 189014779705SSam Leffler * adjust the rate table 189114779705SSam Leffler */ 189214779705SSam Leffler for (i = 0; i < N(ahp->ah_ratesArray); i++) { 189314779705SSam Leffler ahp->ah_ratesArray[i] += ahp->ah_txPowerIndexOffset; 189414779705SSam Leffler if (ahp->ah_ratesArray[i] > 63) 189514779705SSam Leffler ahp->ah_ratesArray[i] = 63; 189614779705SSam Leffler } 189714779705SSam Leffler 189814779705SSam Leffler if (ee->ee_eepMap < 2) { 189914779705SSam Leffler /* 190014779705SSam Leffler * Correct gain deltas for 5212 G operation - 190114779705SSam Leffler * Removed with revised chipset 190214779705SSam Leffler */ 190314779705SSam Leffler if (AH_PRIVATE(ah)->ah_phyRev < AR_PHY_CHIP_ID_REV_2 && 190459efa8b5SSam Leffler IEEE80211_IS_CHAN_G(chan)) { 190514779705SSam Leffler uint16_t cckOfdmPwrDelta; 190614779705SSam Leffler 190759efa8b5SSam Leffler if (freq == 2484) 190814779705SSam Leffler cckOfdmPwrDelta = SCALE_OC_DELTA( 190914779705SSam Leffler ee->ee_cckOfdmPwrDelta - 191014779705SSam Leffler ee->ee_scaledCh14FilterCckDelta); 191114779705SSam Leffler else 191214779705SSam Leffler cckOfdmPwrDelta = SCALE_OC_DELTA( 191314779705SSam Leffler ee->ee_cckOfdmPwrDelta); 191414779705SSam Leffler ar5212CorrectGainDelta(ah, cckOfdmPwrDelta); 191514779705SSam Leffler } 191614779705SSam Leffler /* 191714779705SSam Leffler * Finally, write the power values into the 191814779705SSam Leffler * baseband power table 191914779705SSam Leffler */ 192014779705SSam Leffler for (i = 0; i < (PWR_TABLE_SIZE/2); i++) { 192114779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_PCDAC_TX_POWER(i), 192214779705SSam Leffler ((((ahp->ah_pcdacTable[2*i + 1] << 8) | 0xff) & 0xffff) << 16) 192314779705SSam Leffler | (((ahp->ah_pcdacTable[2*i] << 8) | 0xff) & 0xffff) 192414779705SSam Leffler ); 192514779705SSam Leffler } 192614779705SSam Leffler } 192714779705SSam Leffler 192814779705SSam Leffler /* Write the OFDM power per rate set */ 192914779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 193014779705SSam Leffler POW_OFDM(ahp->ah_ratesArray[3], 24) 193114779705SSam Leffler | POW_OFDM(ahp->ah_ratesArray[2], 16) 193214779705SSam Leffler | POW_OFDM(ahp->ah_ratesArray[1], 8) 193314779705SSam Leffler | POW_OFDM(ahp->ah_ratesArray[0], 0) 193414779705SSam Leffler ); 193514779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, 193614779705SSam Leffler POW_OFDM(ahp->ah_ratesArray[7], 24) 193714779705SSam Leffler | POW_OFDM(ahp->ah_ratesArray[6], 16) 193814779705SSam Leffler | POW_OFDM(ahp->ah_ratesArray[5], 8) 193914779705SSam Leffler | POW_OFDM(ahp->ah_ratesArray[4], 0) 194014779705SSam Leffler ); 194114779705SSam Leffler 194214779705SSam Leffler /* Write the CCK power per rate set */ 194314779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, 194414779705SSam Leffler POW_CCK(ahp->ah_ratesArray[10], 24) 194514779705SSam Leffler | POW_CCK(ahp->ah_ratesArray[9], 16) 194614779705SSam Leffler | POW_CCK(ahp->ah_ratesArray[15], 8) /* XR target power */ 194714779705SSam Leffler | POW_CCK(ahp->ah_ratesArray[8], 0) 194814779705SSam Leffler ); 194914779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, 195014779705SSam Leffler POW_CCK(ahp->ah_ratesArray[14], 24) 195114779705SSam Leffler | POW_CCK(ahp->ah_ratesArray[13], 16) 195214779705SSam Leffler | POW_CCK(ahp->ah_ratesArray[12], 8) 195314779705SSam Leffler | POW_CCK(ahp->ah_ratesArray[11], 0) 195414779705SSam Leffler ); 195514779705SSam Leffler 195614779705SSam Leffler /* 195714779705SSam Leffler * Set max power to 30 dBm and, optionally, 195814779705SSam Leffler * enable TPC in tx descriptors. 195914779705SSam Leffler */ 196014779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, MAX_RATE_POWER | 196114779705SSam Leffler (ahp->ah_tpcEnabled ? AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE : 0)); 196214779705SSam Leffler 196314779705SSam Leffler return AH_TRUE; 196414779705SSam Leffler #undef N 196514779705SSam Leffler #undef POW_CCK 196614779705SSam Leffler #undef POW_OFDM 196714779705SSam Leffler } 196814779705SSam Leffler 196914779705SSam Leffler /* 197014779705SSam Leffler * Sets the transmit power in the baseband for the given 197114779705SSam Leffler * operating channel and mode. 197214779705SSam Leffler */ 197314779705SSam Leffler static HAL_BOOL 197459efa8b5SSam Leffler ar5212SetRateTable(struct ath_hal *ah, const struct ieee80211_channel *chan, 197514779705SSam Leffler int16_t tpcScaleReduction, int16_t powerLimit, HAL_BOOL commit, 197614779705SSam Leffler int16_t *pMinPower, int16_t *pMaxPower) 197714779705SSam Leffler { 197814779705SSam Leffler struct ath_hal_5212 *ahp = AH5212(ah); 197959efa8b5SSam Leffler uint16_t freq = ath_hal_gethwchannel(ah, chan); 198014779705SSam Leffler const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 198114779705SSam Leffler uint16_t *rpow = ahp->ah_ratesArray; 198214779705SSam Leffler uint16_t twiceMaxEdgePower = MAX_RATE_POWER; 198314779705SSam Leffler uint16_t twiceMaxEdgePowerCck = MAX_RATE_POWER; 198414779705SSam Leffler uint16_t twiceMaxRDPower = MAX_RATE_POWER; 198514779705SSam Leffler int i; 198614779705SSam Leffler uint8_t cfgCtl; 198714779705SSam Leffler int8_t twiceAntennaGain, twiceAntennaReduction; 198814779705SSam Leffler const RD_EDGES_POWER *rep; 198914779705SSam Leffler TRGT_POWER_INFO targetPowerOfdm, targetPowerCck; 199014779705SSam Leffler int16_t scaledPower, maxAvailPower = 0; 199114779705SSam Leffler int16_t r13, r9, r7, r0; 199214779705SSam Leffler 199314779705SSam Leffler HALASSERT(ah->ah_magic == AR5212_MAGIC); 199414779705SSam Leffler 199559efa8b5SSam Leffler twiceMaxRDPower = chan->ic_maxregpower * 2; 199614779705SSam Leffler *pMaxPower = -MAX_RATE_POWER; 199714779705SSam Leffler *pMinPower = MAX_RATE_POWER; 199814779705SSam Leffler 199914779705SSam Leffler /* Get conformance test limit maximum for this channel */ 200014779705SSam Leffler cfgCtl = ath_hal_getctl(ah, chan); 200114779705SSam Leffler for (i = 0; i < ee->ee_numCtls; i++) { 200214779705SSam Leffler uint16_t twiceMinEdgePower; 200314779705SSam Leffler 200414779705SSam Leffler if (ee->ee_ctl[i] == 0) 200514779705SSam Leffler continue; 200614779705SSam Leffler if (ee->ee_ctl[i] == cfgCtl || 200714779705SSam Leffler cfgCtl == ((ee->ee_ctl[i] & CTL_MODE_M) | SD_NO_CTL)) { 200814779705SSam Leffler rep = &ee->ee_rdEdgesPower[i * NUM_EDGES]; 200959efa8b5SSam Leffler twiceMinEdgePower = ar5212GetMaxEdgePower(freq, rep); 201014779705SSam Leffler if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 201114779705SSam Leffler /* Find the minimum of all CTL edge powers that apply to this channel */ 201214779705SSam Leffler twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower); 201314779705SSam Leffler } else { 201414779705SSam Leffler twiceMaxEdgePower = twiceMinEdgePower; 201514779705SSam Leffler break; 201614779705SSam Leffler } 201714779705SSam Leffler } 201814779705SSam Leffler } 201914779705SSam Leffler 202059efa8b5SSam Leffler if (IEEE80211_IS_CHAN_G(chan)) { 202114779705SSam Leffler /* Check for a CCK CTL for 11G CCK powers */ 202214779705SSam Leffler cfgCtl = (cfgCtl & ~CTL_MODE_M) | CTL_11B; 202314779705SSam Leffler for (i = 0; i < ee->ee_numCtls; i++) { 202414779705SSam Leffler uint16_t twiceMinEdgePowerCck; 202514779705SSam Leffler 202614779705SSam Leffler if (ee->ee_ctl[i] == 0) 202714779705SSam Leffler continue; 202814779705SSam Leffler if (ee->ee_ctl[i] == cfgCtl || 202914779705SSam Leffler cfgCtl == ((ee->ee_ctl[i] & CTL_MODE_M) | SD_NO_CTL)) { 203014779705SSam Leffler rep = &ee->ee_rdEdgesPower[i * NUM_EDGES]; 203159efa8b5SSam Leffler twiceMinEdgePowerCck = ar5212GetMaxEdgePower(freq, rep); 203214779705SSam Leffler if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 203314779705SSam Leffler /* Find the minimum of all CTL edge powers that apply to this channel */ 203414779705SSam Leffler twiceMaxEdgePowerCck = AH_MIN(twiceMaxEdgePowerCck, twiceMinEdgePowerCck); 203514779705SSam Leffler } else { 203614779705SSam Leffler twiceMaxEdgePowerCck = twiceMinEdgePowerCck; 203714779705SSam Leffler break; 203814779705SSam Leffler } 203914779705SSam Leffler } 204014779705SSam Leffler } 204114779705SSam Leffler } else { 204214779705SSam Leffler /* Set the 11B cck edge power to the one found before */ 204314779705SSam Leffler twiceMaxEdgePowerCck = twiceMaxEdgePower; 204414779705SSam Leffler } 204514779705SSam Leffler 204614779705SSam Leffler /* Get Antenna Gain reduction */ 204759efa8b5SSam Leffler if (IEEE80211_IS_CHAN_5GHZ(chan)) { 204814779705SSam Leffler ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_5, &twiceAntennaGain); 204914779705SSam Leffler } else { 205014779705SSam Leffler ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_2, &twiceAntennaGain); 205114779705SSam Leffler } 205214779705SSam Leffler twiceAntennaReduction = 205314779705SSam Leffler ath_hal_getantennareduction(ah, chan, twiceAntennaGain); 205414779705SSam Leffler 205559efa8b5SSam Leffler if (IEEE80211_IS_CHAN_OFDM(chan)) { 205614779705SSam Leffler /* Get final OFDM target powers */ 205759efa8b5SSam Leffler if (IEEE80211_IS_CHAN_2GHZ(chan)) { 205814779705SSam Leffler ar5212GetTargetPowers(ah, chan, ee->ee_trgtPwr_11g, 205914779705SSam Leffler ee->ee_numTargetPwr_11g, &targetPowerOfdm); 206014779705SSam Leffler } else { 206114779705SSam Leffler ar5212GetTargetPowers(ah, chan, ee->ee_trgtPwr_11a, 206214779705SSam Leffler ee->ee_numTargetPwr_11a, &targetPowerOfdm); 206314779705SSam Leffler } 206414779705SSam Leffler 206514779705SSam Leffler /* Get Maximum OFDM power */ 206614779705SSam Leffler /* Minimum of target and edge powers */ 206714779705SSam Leffler scaledPower = AH_MIN(twiceMaxEdgePower, 206814779705SSam Leffler twiceMaxRDPower - twiceAntennaReduction); 206914779705SSam Leffler 207014779705SSam Leffler /* 207114779705SSam Leffler * If turbo is set, reduce power to keep power 207214779705SSam Leffler * consumption under 2 Watts. Note that we always do 207314779705SSam Leffler * this unless specially configured. Then we limit 207414779705SSam Leffler * power only for non-AP operation. 207514779705SSam Leffler */ 207659efa8b5SSam Leffler if (IEEE80211_IS_CHAN_TURBO(chan) 207714779705SSam Leffler #ifdef AH_ENABLE_AP_SUPPORT 207814779705SSam Leffler && AH_PRIVATE(ah)->ah_opmode != HAL_M_HOSTAP 207914779705SSam Leffler #endif 208014779705SSam Leffler ) { 208114779705SSam Leffler /* 208214779705SSam Leffler * If turbo is set, reduce power to keep power 208314779705SSam Leffler * consumption under 2 Watts 208414779705SSam Leffler */ 208514779705SSam Leffler if (ee->ee_version >= AR_EEPROM_VER3_1) 208614779705SSam Leffler scaledPower = AH_MIN(scaledPower, 208714779705SSam Leffler ee->ee_turbo2WMaxPower5); 208814779705SSam Leffler /* 208914779705SSam Leffler * EEPROM version 4.0 added an additional 209014779705SSam Leffler * constraint on 2.4GHz channels. 209114779705SSam Leffler */ 209214779705SSam Leffler if (ee->ee_version >= AR_EEPROM_VER4_0 && 209359efa8b5SSam Leffler IEEE80211_IS_CHAN_2GHZ(chan)) 209414779705SSam Leffler scaledPower = AH_MIN(scaledPower, 209514779705SSam Leffler ee->ee_turbo2WMaxPower2); 209614779705SSam Leffler } 209714779705SSam Leffler 209814779705SSam Leffler maxAvailPower = AH_MIN(scaledPower, 209914779705SSam Leffler targetPowerOfdm.twicePwr6_24); 210014779705SSam Leffler 210114779705SSam Leffler /* Reduce power by max regulatory domain allowed restrictions */ 210214779705SSam Leffler scaledPower = maxAvailPower - (tpcScaleReduction * 2); 210314779705SSam Leffler scaledPower = (scaledPower < 0) ? 0 : scaledPower; 210414779705SSam Leffler scaledPower = AH_MIN(scaledPower, powerLimit); 210514779705SSam Leffler 210614779705SSam Leffler if (commit) { 210714779705SSam Leffler /* Set OFDM rates 9, 12, 18, 24 */ 210814779705SSam Leffler r0 = rpow[0] = rpow[1] = rpow[2] = rpow[3] = rpow[4] = scaledPower; 210914779705SSam Leffler 211014779705SSam Leffler /* Set OFDM rates 36, 48, 54, XR */ 211114779705SSam Leffler rpow[5] = AH_MIN(rpow[0], targetPowerOfdm.twicePwr36); 211214779705SSam Leffler rpow[6] = AH_MIN(rpow[0], targetPowerOfdm.twicePwr48); 211314779705SSam Leffler r7 = rpow[7] = AH_MIN(rpow[0], targetPowerOfdm.twicePwr54); 211414779705SSam Leffler 211514779705SSam Leffler if (ee->ee_version >= AR_EEPROM_VER4_0) { 211614779705SSam Leffler /* Setup XR target power from EEPROM */ 211759efa8b5SSam Leffler rpow[15] = AH_MIN(scaledPower, IEEE80211_IS_CHAN_2GHZ(chan) ? 211814779705SSam Leffler ee->ee_xrTargetPower2 : ee->ee_xrTargetPower5); 211914779705SSam Leffler } else { 212014779705SSam Leffler /* XR uses 6mb power */ 212114779705SSam Leffler rpow[15] = rpow[0]; 212214779705SSam Leffler } 212314779705SSam Leffler ahp->ah_ofdmTxPower = *pMaxPower; 212414779705SSam Leffler 212514779705SSam Leffler } else { 212614779705SSam Leffler r0 = scaledPower; 212714779705SSam Leffler r7 = AH_MIN(r0, targetPowerOfdm.twicePwr54); 212814779705SSam Leffler } 212914779705SSam Leffler *pMinPower = r7; 213014779705SSam Leffler *pMaxPower = r0; 213114779705SSam Leffler 213214779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_RFPARAM, 213314779705SSam Leffler "%s: MaxRD: %d TurboMax: %d MaxCTL: %d " 213414779705SSam Leffler "TPC_Reduction %d chan=%d (0x%x) maxAvailPower=%d pwr6_24=%d, maxPower=%d\n", 213514779705SSam Leffler __func__, twiceMaxRDPower, ee->ee_turbo2WMaxPower5, 213614779705SSam Leffler twiceMaxEdgePower, tpcScaleReduction * 2, 213759efa8b5SSam Leffler chan->ic_freq, chan->ic_flags, 213814779705SSam Leffler maxAvailPower, targetPowerOfdm.twicePwr6_24, *pMaxPower); 213914779705SSam Leffler } 214014779705SSam Leffler 214159efa8b5SSam Leffler if (IEEE80211_IS_CHAN_CCK(chan)) { 214214779705SSam Leffler /* Get final CCK target powers */ 214314779705SSam Leffler ar5212GetTargetPowers(ah, chan, ee->ee_trgtPwr_11b, 214414779705SSam Leffler ee->ee_numTargetPwr_11b, &targetPowerCck); 214514779705SSam Leffler 214614779705SSam Leffler /* Reduce power by max regulatory domain allowed restrictions */ 214714779705SSam Leffler scaledPower = AH_MIN(twiceMaxEdgePowerCck, 214814779705SSam Leffler twiceMaxRDPower - twiceAntennaReduction); 214914779705SSam Leffler if (maxAvailPower < AH_MIN(scaledPower, targetPowerCck.twicePwr6_24)) 215014779705SSam Leffler maxAvailPower = AH_MIN(scaledPower, targetPowerCck.twicePwr6_24); 215114779705SSam Leffler 215214779705SSam Leffler /* Reduce power by user selection */ 215314779705SSam Leffler scaledPower = AH_MIN(scaledPower, targetPowerCck.twicePwr6_24) - (tpcScaleReduction * 2); 215414779705SSam Leffler scaledPower = (scaledPower < 0) ? 0 : scaledPower; 215514779705SSam Leffler scaledPower = AH_MIN(scaledPower, powerLimit); 215614779705SSam Leffler 215714779705SSam Leffler if (commit) { 215814779705SSam Leffler /* Set CCK rates 2L, 2S, 5.5L, 5.5S, 11L, 11S */ 215914779705SSam Leffler rpow[8] = AH_MIN(scaledPower, targetPowerCck.twicePwr6_24); 216014779705SSam Leffler r9 = rpow[9] = AH_MIN(scaledPower, targetPowerCck.twicePwr36); 216114779705SSam Leffler rpow[10] = rpow[9]; 216214779705SSam Leffler rpow[11] = AH_MIN(scaledPower, targetPowerCck.twicePwr48); 216314779705SSam Leffler rpow[12] = rpow[11]; 216414779705SSam Leffler r13 = rpow[13] = AH_MIN(scaledPower, targetPowerCck.twicePwr54); 216514779705SSam Leffler rpow[14] = rpow[13]; 216614779705SSam Leffler } else { 216714779705SSam Leffler r9 = AH_MIN(scaledPower, targetPowerCck.twicePwr36); 216814779705SSam Leffler r13 = AH_MIN(scaledPower, targetPowerCck.twicePwr54); 216914779705SSam Leffler } 217014779705SSam Leffler 217114779705SSam Leffler /* Set min/max power based off OFDM values or initialization */ 217214779705SSam Leffler if (r13 < *pMinPower) 217314779705SSam Leffler *pMinPower = r13; 217414779705SSam Leffler if (r9 > *pMaxPower) 217514779705SSam Leffler *pMaxPower = r9; 217614779705SSam Leffler 217714779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_RFPARAM, 217814779705SSam Leffler "%s: cck: MaxRD: %d MaxCTL: %d " 217914779705SSam Leffler "TPC_Reduction %d chan=%d (0x%x) maxAvailPower=%d pwr6_24=%d, maxPower=%d\n", 218014779705SSam Leffler __func__, twiceMaxRDPower, twiceMaxEdgePowerCck, 218159efa8b5SSam Leffler tpcScaleReduction * 2, chan->ic_freq, chan->ic_flags, 218214779705SSam Leffler maxAvailPower, targetPowerCck.twicePwr6_24, *pMaxPower); 218314779705SSam Leffler } 218414779705SSam Leffler if (commit) { 218514779705SSam Leffler ahp->ah_tx6PowerInHalfDbm = *pMaxPower; 218614779705SSam Leffler AH_PRIVATE(ah)->ah_maxPowerLevel = ahp->ah_tx6PowerInHalfDbm; 218714779705SSam Leffler } 218814779705SSam Leffler return AH_TRUE; 218914779705SSam Leffler } 219014779705SSam Leffler 219114779705SSam Leffler HAL_BOOL 219259efa8b5SSam Leffler ar5212GetChipPowerLimits(struct ath_hal *ah, struct ieee80211_channel *chan) 219314779705SSam Leffler { 219414779705SSam Leffler struct ath_hal_5212 *ahp = AH5212(ah); 219559efa8b5SSam Leffler #if 0 219614779705SSam Leffler static const uint16_t tpcScaleReductionTable[5] = 219714779705SSam Leffler { 0, 3, 6, 9, MAX_RATE_POWER }; 219859efa8b5SSam Leffler int16_t tpcInDb, powerLimit; 219959efa8b5SSam Leffler #endif 220059efa8b5SSam Leffler int16_t minPower, maxPower; 220114779705SSam Leffler 220214779705SSam Leffler /* 220314779705SSam Leffler * Get Pier table max and min powers. 220414779705SSam Leffler */ 220514779705SSam Leffler if (ahp->ah_rfHal->getChannelMaxMinPower(ah, chan, &maxPower, &minPower)) { 220614779705SSam Leffler /* NB: rf code returns 1/4 dBm units, convert */ 220759efa8b5SSam Leffler chan->ic_maxpower = maxPower / 2; 220859efa8b5SSam Leffler chan->ic_minpower = minPower / 2; 220914779705SSam Leffler } else { 221014779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, 221114779705SSam Leffler "%s: no min/max power for %u/0x%x\n", 221259efa8b5SSam Leffler __func__, chan->ic_freq, chan->ic_flags); 221359efa8b5SSam Leffler chan->ic_maxpower = MAX_RATE_POWER; 221459efa8b5SSam Leffler chan->ic_minpower = 0; 221514779705SSam Leffler } 221659efa8b5SSam Leffler #if 0 221714779705SSam Leffler /* 221814779705SSam Leffler * Now adjust to reflect any global scale and/or CTL's. 221914779705SSam Leffler * (XXX is that correct?) 222014779705SSam Leffler */ 222114779705SSam Leffler powerLimit = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 222214779705SSam Leffler if (powerLimit >= MAX_RATE_POWER || powerLimit == 0) 222314779705SSam Leffler tpcInDb = tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale]; 222414779705SSam Leffler else 222514779705SSam Leffler tpcInDb = 0; 222659efa8b5SSam Leffler if (!ar5212SetRateTable(ah, chan, tpcInDb, powerLimit, 222714779705SSam Leffler AH_FALSE, &minPower, &maxPower)) { 222814779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, 222914779705SSam Leffler "%s: unable to find max/min power\n",__func__); 223014779705SSam Leffler return AH_FALSE; 223114779705SSam Leffler } 223259efa8b5SSam Leffler if (maxPower < chan->ic_maxpower) 223359efa8b5SSam Leffler chan->ic_maxpower = maxPower; 223459efa8b5SSam Leffler if (minPower < chan->ic_minpower) 223559efa8b5SSam Leffler chan->ic_minpower = minPower; 223614779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_RESET, 223714779705SSam Leffler "Chan %d: MaxPow = %d MinPow = %d\n", 223859efa8b5SSam Leffler chan->ic_freq, chan->ic_maxpower, chans->ic_minpower); 223914779705SSam Leffler #endif 224014779705SSam Leffler return AH_TRUE; 224114779705SSam Leffler } 224214779705SSam Leffler 224314779705SSam Leffler /* 224414779705SSam Leffler * Correct for the gain-delta between ofdm and cck mode target 224514779705SSam Leffler * powers. Write the results to the rate table and the power table. 224614779705SSam Leffler * 224714779705SSam Leffler * Conventions : 224814779705SSam Leffler * 1. rpow[ii] is the integer value of 2*(desired power 224914779705SSam Leffler * for the rate ii in dBm) to provide 0.5dB resolution. rate 225014779705SSam Leffler * mapping is as following : 225114779705SSam Leffler * [0..7] --> ofdm 6, 9, .. 48, 54 225214779705SSam Leffler * [8..14] --> cck 1L, 2L, 2S, .. 11L, 11S 225314779705SSam Leffler * [15] --> XR (all rates get the same power) 225414779705SSam Leffler * 2. powv[ii] is the pcdac corresponding to ii/2 dBm. 225514779705SSam Leffler */ 225614779705SSam Leffler static void 225714779705SSam Leffler ar5212CorrectGainDelta(struct ath_hal *ah, int twiceOfdmCckDelta) 225814779705SSam Leffler { 225914779705SSam Leffler #define N(_a) (sizeof(_a) / sizeof(_a[0])) 226014779705SSam Leffler struct ath_hal_5212 *ahp = AH5212(ah); 226114779705SSam Leffler const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 226214779705SSam Leffler int16_t ratesIndex[N(ahp->ah_ratesArray)]; 226314779705SSam Leffler uint16_t ii, jj, iter; 226414779705SSam Leffler int32_t cckIndex; 226514779705SSam Leffler int16_t gainDeltaAdjust; 226614779705SSam Leffler 226714779705SSam Leffler HALASSERT(ah->ah_magic == AR5212_MAGIC); 226814779705SSam Leffler 226914779705SSam Leffler gainDeltaAdjust = ee->ee_cckOfdmGainDelta; 227014779705SSam Leffler 227114779705SSam Leffler /* make a local copy of desired powers as initial indices */ 227214779705SSam Leffler OS_MEMCPY(ratesIndex, ahp->ah_ratesArray, sizeof(ratesIndex)); 227314779705SSam Leffler 227414779705SSam Leffler /* fix only the CCK indices */ 227514779705SSam Leffler for (ii = 8; ii < 15; ii++) { 227614779705SSam Leffler /* apply a gain_delta correction of -15 for CCK */ 227714779705SSam Leffler ratesIndex[ii] -= gainDeltaAdjust; 227814779705SSam Leffler 227914779705SSam Leffler /* Now check for contention with all ofdm target powers */ 228014779705SSam Leffler jj = 0; 228114779705SSam Leffler iter = 0; 228214779705SSam Leffler /* indicates not all ofdm rates checked forcontention yet */ 228314779705SSam Leffler while (jj < 16) { 228414779705SSam Leffler if (ratesIndex[ii] < 0) 228514779705SSam Leffler ratesIndex[ii] = 0; 228614779705SSam Leffler if (jj == 8) { /* skip CCK rates */ 228714779705SSam Leffler jj = 15; 228814779705SSam Leffler continue; 228914779705SSam Leffler } 229014779705SSam Leffler if (ratesIndex[ii] == ahp->ah_ratesArray[jj]) { 229114779705SSam Leffler if (ahp->ah_ratesArray[jj] == 0) 229214779705SSam Leffler ratesIndex[ii]++; 229314779705SSam Leffler else if (iter > 50) { 229414779705SSam Leffler /* 229514779705SSam Leffler * To avoid pathological case of of 229614779705SSam Leffler * dm target powers 0 and 0.5dBm 229714779705SSam Leffler */ 229814779705SSam Leffler ratesIndex[ii]++; 229914779705SSam Leffler } else 230014779705SSam Leffler ratesIndex[ii]--; 230114779705SSam Leffler /* check with all rates again */ 230214779705SSam Leffler jj = 0; 230314779705SSam Leffler iter++; 230414779705SSam Leffler } else 230514779705SSam Leffler jj++; 230614779705SSam Leffler } 230714779705SSam Leffler if (ratesIndex[ii] >= PWR_TABLE_SIZE) 230814779705SSam Leffler ratesIndex[ii] = PWR_TABLE_SIZE -1; 230914779705SSam Leffler cckIndex = ahp->ah_ratesArray[ii] - twiceOfdmCckDelta; 231014779705SSam Leffler if (cckIndex < 0) 231114779705SSam Leffler cckIndex = 0; 231214779705SSam Leffler 231314779705SSam Leffler /* 231414779705SSam Leffler * Validate that the indexes for the powv are not 231514779705SSam Leffler * out of bounds. 231614779705SSam Leffler */ 231714779705SSam Leffler HALASSERT(cckIndex < PWR_TABLE_SIZE); 231814779705SSam Leffler HALASSERT(ratesIndex[ii] < PWR_TABLE_SIZE); 231914779705SSam Leffler ahp->ah_pcdacTable[ratesIndex[ii]] = 232014779705SSam Leffler ahp->ah_pcdacTable[cckIndex]; 232114779705SSam Leffler } 232214779705SSam Leffler /* Override rate per power table with new values */ 232314779705SSam Leffler for (ii = 8; ii < 15; ii++) 232414779705SSam Leffler ahp->ah_ratesArray[ii] = ratesIndex[ii]; 232514779705SSam Leffler #undef N 232614779705SSam Leffler } 232714779705SSam Leffler 232814779705SSam Leffler /* 232914779705SSam Leffler * Find the maximum conformance test limit for the given channel and CTL info 233014779705SSam Leffler */ 233114779705SSam Leffler static uint16_t 233214779705SSam Leffler ar5212GetMaxEdgePower(uint16_t channel, const RD_EDGES_POWER *pRdEdgesPower) 233314779705SSam Leffler { 233414779705SSam Leffler /* temp array for holding edge channels */ 233514779705SSam Leffler uint16_t tempChannelList[NUM_EDGES]; 233614779705SSam Leffler uint16_t clo, chi, twiceMaxEdgePower; 233714779705SSam Leffler int i, numEdges; 233814779705SSam Leffler 233914779705SSam Leffler /* Get the edge power */ 234014779705SSam Leffler for (i = 0; i < NUM_EDGES; i++) { 234114779705SSam Leffler if (pRdEdgesPower[i].rdEdge == 0) 234214779705SSam Leffler break; 234314779705SSam Leffler tempChannelList[i] = pRdEdgesPower[i].rdEdge; 234414779705SSam Leffler } 234514779705SSam Leffler numEdges = i; 234614779705SSam Leffler 234714779705SSam Leffler ar5212GetLowerUpperValues(channel, tempChannelList, 234814779705SSam Leffler numEdges, &clo, &chi); 234914779705SSam Leffler /* Get the index for the lower channel */ 235014779705SSam Leffler for (i = 0; i < numEdges && clo != tempChannelList[i]; i++) 235114779705SSam Leffler ; 235214779705SSam Leffler /* Is lower channel ever outside the rdEdge? */ 235314779705SSam Leffler HALASSERT(i != numEdges); 235414779705SSam Leffler 235514779705SSam Leffler if ((clo == chi && clo == channel) || (pRdEdgesPower[i].flag)) { 235614779705SSam Leffler /* 235714779705SSam Leffler * If there's an exact channel match or an inband flag set 235814779705SSam Leffler * on the lower channel use the given rdEdgePower 235914779705SSam Leffler */ 236014779705SSam Leffler twiceMaxEdgePower = pRdEdgesPower[i].twice_rdEdgePower; 236114779705SSam Leffler HALASSERT(twiceMaxEdgePower > 0); 236214779705SSam Leffler } else 236314779705SSam Leffler twiceMaxEdgePower = MAX_RATE_POWER; 236414779705SSam Leffler return twiceMaxEdgePower; 236514779705SSam Leffler } 236614779705SSam Leffler 236714779705SSam Leffler /* 236814779705SSam Leffler * Returns interpolated or the scaled up interpolated value 236914779705SSam Leffler */ 237014779705SSam Leffler static uint16_t 237114779705SSam Leffler interpolate(uint16_t target, uint16_t srcLeft, uint16_t srcRight, 237214779705SSam Leffler uint16_t targetLeft, uint16_t targetRight) 237314779705SSam Leffler { 237414779705SSam Leffler uint16_t rv; 237514779705SSam Leffler int16_t lRatio; 237614779705SSam Leffler 237714779705SSam Leffler /* to get an accurate ratio, always scale, if want to scale, then don't scale back down */ 237814779705SSam Leffler if ((targetLeft * targetRight) == 0) 237914779705SSam Leffler return 0; 238014779705SSam Leffler 238114779705SSam Leffler if (srcRight != srcLeft) { 238214779705SSam Leffler /* 238314779705SSam Leffler * Note the ratio always need to be scaled, 238414779705SSam Leffler * since it will be a fraction. 238514779705SSam Leffler */ 238614779705SSam Leffler lRatio = (target - srcLeft) * EEP_SCALE / (srcRight - srcLeft); 238714779705SSam Leffler if (lRatio < 0) { 238814779705SSam Leffler /* Return as Left target if value would be negative */ 238914779705SSam Leffler rv = targetLeft; 239014779705SSam Leffler } else if (lRatio > EEP_SCALE) { 239114779705SSam Leffler /* Return as Right target if Ratio is greater than 100% (SCALE) */ 239214779705SSam Leffler rv = targetRight; 239314779705SSam Leffler } else { 239414779705SSam Leffler rv = (lRatio * targetRight + (EEP_SCALE - lRatio) * 239514779705SSam Leffler targetLeft) / EEP_SCALE; 239614779705SSam Leffler } 239714779705SSam Leffler } else { 239814779705SSam Leffler rv = targetLeft; 239914779705SSam Leffler } 240014779705SSam Leffler return rv; 240114779705SSam Leffler } 240214779705SSam Leffler 240314779705SSam Leffler /* 240414779705SSam Leffler * Return the four rates of target power for the given target power table 240514779705SSam Leffler * channel, and number of channels 240614779705SSam Leffler */ 240714779705SSam Leffler static void 240859efa8b5SSam Leffler ar5212GetTargetPowers(struct ath_hal *ah, const struct ieee80211_channel *chan, 240914779705SSam Leffler const TRGT_POWER_INFO *powInfo, 241014779705SSam Leffler uint16_t numChannels, TRGT_POWER_INFO *pNewPower) 241114779705SSam Leffler { 241259efa8b5SSam Leffler uint16_t freq = ath_hal_gethwchannel(ah, chan); 241314779705SSam Leffler /* temp array for holding target power channels */ 241414779705SSam Leffler uint16_t tempChannelList[NUM_TEST_FREQUENCIES]; 241514779705SSam Leffler uint16_t clo, chi, ixlo, ixhi; 241614779705SSam Leffler int i; 241714779705SSam Leffler 241814779705SSam Leffler /* Copy the target powers into the temp channel list */ 241914779705SSam Leffler for (i = 0; i < numChannels; i++) 242014779705SSam Leffler tempChannelList[i] = powInfo[i].testChannel; 242114779705SSam Leffler 242259efa8b5SSam Leffler ar5212GetLowerUpperValues(freq, tempChannelList, 242314779705SSam Leffler numChannels, &clo, &chi); 242414779705SSam Leffler 242514779705SSam Leffler /* Get the indices for the channel */ 242614779705SSam Leffler ixlo = ixhi = 0; 242714779705SSam Leffler for (i = 0; i < numChannels; i++) { 242814779705SSam Leffler if (clo == tempChannelList[i]) { 242914779705SSam Leffler ixlo = i; 243014779705SSam Leffler } 243114779705SSam Leffler if (chi == tempChannelList[i]) { 243214779705SSam Leffler ixhi = i; 243314779705SSam Leffler break; 243414779705SSam Leffler } 243514779705SSam Leffler } 243614779705SSam Leffler 243714779705SSam Leffler /* 243814779705SSam Leffler * Get the lower and upper channels, target powers, 243914779705SSam Leffler * and interpolate between them. 244014779705SSam Leffler */ 244159efa8b5SSam Leffler pNewPower->twicePwr6_24 = interpolate(freq, clo, chi, 244214779705SSam Leffler powInfo[ixlo].twicePwr6_24, powInfo[ixhi].twicePwr6_24); 244359efa8b5SSam Leffler pNewPower->twicePwr36 = interpolate(freq, clo, chi, 244414779705SSam Leffler powInfo[ixlo].twicePwr36, powInfo[ixhi].twicePwr36); 244559efa8b5SSam Leffler pNewPower->twicePwr48 = interpolate(freq, clo, chi, 244614779705SSam Leffler powInfo[ixlo].twicePwr48, powInfo[ixhi].twicePwr48); 244759efa8b5SSam Leffler pNewPower->twicePwr54 = interpolate(freq, clo, chi, 244814779705SSam Leffler powInfo[ixlo].twicePwr54, powInfo[ixhi].twicePwr54); 244914779705SSam Leffler } 245014779705SSam Leffler 245114779705SSam Leffler /* 245214779705SSam Leffler * Search a list for a specified value v that is within 245314779705SSam Leffler * EEP_DELTA of the search values. Return the closest 245414779705SSam Leffler * values in the list above and below the desired value. 245514779705SSam Leffler * EEP_DELTA is a factional value; everything is scaled 245614779705SSam Leffler * so only integer arithmetic is used. 245714779705SSam Leffler * 245814779705SSam Leffler * NB: the input list is assumed to be sorted in ascending order 245914779705SSam Leffler */ 246014779705SSam Leffler void 246114779705SSam Leffler ar5212GetLowerUpperValues(uint16_t v, uint16_t *lp, uint16_t listSize, 246214779705SSam Leffler uint16_t *vlo, uint16_t *vhi) 246314779705SSam Leffler { 246414779705SSam Leffler uint32_t target = v * EEP_SCALE; 246514779705SSam Leffler uint16_t *ep = lp+listSize; 246614779705SSam Leffler 246714779705SSam Leffler /* 246814779705SSam Leffler * Check first and last elements for out-of-bounds conditions. 246914779705SSam Leffler */ 247014779705SSam Leffler if (target < (uint32_t)(lp[0] * EEP_SCALE - EEP_DELTA)) { 247114779705SSam Leffler *vlo = *vhi = lp[0]; 247214779705SSam Leffler return; 247314779705SSam Leffler } 247414779705SSam Leffler if (target > (uint32_t)(ep[-1] * EEP_SCALE + EEP_DELTA)) { 247514779705SSam Leffler *vlo = *vhi = ep[-1]; 247614779705SSam Leffler return; 247714779705SSam Leffler } 247814779705SSam Leffler 247914779705SSam Leffler /* look for value being near or between 2 values in list */ 248014779705SSam Leffler for (; lp < ep; lp++) { 248114779705SSam Leffler /* 248214779705SSam Leffler * If value is close to the current value of the list 248314779705SSam Leffler * then target is not between values, it is one of the values 248414779705SSam Leffler */ 248514779705SSam Leffler if (abs(lp[0] * EEP_SCALE - target) < EEP_DELTA) { 248614779705SSam Leffler *vlo = *vhi = lp[0]; 248714779705SSam Leffler return; 248814779705SSam Leffler } 248914779705SSam Leffler /* 249014779705SSam Leffler * Look for value being between current value and next value 249114779705SSam Leffler * if so return these 2 values 249214779705SSam Leffler */ 249314779705SSam Leffler if (target < (uint32_t)(lp[1] * EEP_SCALE - EEP_DELTA)) { 249414779705SSam Leffler *vlo = lp[0]; 249514779705SSam Leffler *vhi = lp[1]; 249614779705SSam Leffler return; 249714779705SSam Leffler } 249814779705SSam Leffler } 249914779705SSam Leffler HALASSERT(AH_FALSE); /* should not reach here */ 250014779705SSam Leffler } 250114779705SSam Leffler 250214779705SSam Leffler /* 250314779705SSam Leffler * Perform analog "swizzling" of parameters into their location 250414779705SSam Leffler * 250514779705SSam Leffler * NB: used by RF backends 250614779705SSam Leffler */ 250714779705SSam Leffler void 250814779705SSam Leffler ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32, uint32_t numBits, 250914779705SSam Leffler uint32_t firstBit, uint32_t column) 251014779705SSam Leffler { 251114779705SSam Leffler #define MAX_ANALOG_START 319 /* XXX */ 251214779705SSam Leffler uint32_t tmp32, mask, arrayEntry, lastBit; 251314779705SSam Leffler int32_t bitPosition, bitsLeft; 251414779705SSam Leffler 251514779705SSam Leffler HALASSERT(column <= 3); 251614779705SSam Leffler HALASSERT(numBits <= 32); 251714779705SSam Leffler HALASSERT(firstBit + numBits <= MAX_ANALOG_START); 251814779705SSam Leffler 251914779705SSam Leffler tmp32 = ath_hal_reverseBits(reg32, numBits); 252014779705SSam Leffler arrayEntry = (firstBit - 1) / 8; 252114779705SSam Leffler bitPosition = (firstBit - 1) % 8; 252214779705SSam Leffler bitsLeft = numBits; 252314779705SSam Leffler while (bitsLeft > 0) { 252414779705SSam Leffler lastBit = (bitPosition + bitsLeft > 8) ? 252514779705SSam Leffler 8 : bitPosition + bitsLeft; 252614779705SSam Leffler mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) << 252714779705SSam Leffler (column * 8); 252814779705SSam Leffler rfBuf[arrayEntry] &= ~mask; 252914779705SSam Leffler rfBuf[arrayEntry] |= ((tmp32 << bitPosition) << 253014779705SSam Leffler (column * 8)) & mask; 253114779705SSam Leffler bitsLeft -= 8 - bitPosition; 253214779705SSam Leffler tmp32 = tmp32 >> (8 - bitPosition); 253314779705SSam Leffler bitPosition = 0; 253414779705SSam Leffler arrayEntry++; 253514779705SSam Leffler } 253614779705SSam Leffler #undef MAX_ANALOG_START 253714779705SSam Leffler } 253814779705SSam Leffler 253914779705SSam Leffler /* 254014779705SSam Leffler * Sets the rate to duration values in MAC - used for multi- 254114779705SSam Leffler * rate retry. 254214779705SSam Leffler * The rate duration table needs to cover all valid rate codes; 254314779705SSam Leffler * the 11g table covers all ofdm rates, while the 11b table 254414779705SSam Leffler * covers all cck rates => all valid rates get covered between 254514779705SSam Leffler * these two mode's ratetables! 254614779705SSam Leffler * But if we're turbo, the ofdm phy is replaced by the turbo phy 254714779705SSam Leffler * and cck is not valid with turbo => all rates get covered 254814779705SSam Leffler * by the turbo ratetable only 254914779705SSam Leffler */ 255014779705SSam Leffler void 255159efa8b5SSam Leffler ar5212SetRateDurationTable(struct ath_hal *ah, 255259efa8b5SSam Leffler const struct ieee80211_channel *chan) 255314779705SSam Leffler { 255414779705SSam Leffler const HAL_RATE_TABLE *rt; 255514779705SSam Leffler int i; 255614779705SSam Leffler 255714779705SSam Leffler /* NB: band doesn't matter for 1/2 and 1/4 rate */ 255859efa8b5SSam Leffler if (IEEE80211_IS_CHAN_HALF(chan)) { 255914779705SSam Leffler rt = ar5212GetRateTable(ah, HAL_MODE_11A_HALF_RATE); 256059efa8b5SSam Leffler } else if (IEEE80211_IS_CHAN_QUARTER(chan)) { 256114779705SSam Leffler rt = ar5212GetRateTable(ah, HAL_MODE_11A_QUARTER_RATE); 256214779705SSam Leffler } else { 256314779705SSam Leffler rt = ar5212GetRateTable(ah, 256459efa8b5SSam Leffler IEEE80211_IS_CHAN_TURBO(chan) ? HAL_MODE_TURBO : HAL_MODE_11G); 256514779705SSam Leffler } 256614779705SSam Leffler 256714779705SSam Leffler for (i = 0; i < rt->rateCount; ++i) 256814779705SSam Leffler OS_REG_WRITE(ah, 256914779705SSam Leffler AR_RATE_DURATION(rt->info[i].rateCode), 257014779705SSam Leffler ath_hal_computetxtime(ah, rt, 257114779705SSam Leffler WLAN_CTRL_FRAME_SIZE, 257214779705SSam Leffler rt->info[i].controlRate, AH_FALSE)); 257359efa8b5SSam Leffler if (!IEEE80211_IS_CHAN_TURBO(chan)) { 257414779705SSam Leffler /* 11g Table is used to cover the CCK rates. */ 257514779705SSam Leffler rt = ar5212GetRateTable(ah, HAL_MODE_11G); 257614779705SSam Leffler for (i = 0; i < rt->rateCount; ++i) { 257714779705SSam Leffler uint32_t reg = AR_RATE_DURATION(rt->info[i].rateCode); 257814779705SSam Leffler 257914779705SSam Leffler if (rt->info[i].phy != IEEE80211_T_CCK) 258014779705SSam Leffler continue; 258114779705SSam Leffler 258214779705SSam Leffler OS_REG_WRITE(ah, reg, 258314779705SSam Leffler ath_hal_computetxtime(ah, rt, 258414779705SSam Leffler WLAN_CTRL_FRAME_SIZE, 258514779705SSam Leffler rt->info[i].controlRate, AH_FALSE)); 258614779705SSam Leffler /* cck rates have short preamble option also */ 258714779705SSam Leffler if (rt->info[i].shortPreamble) { 258814779705SSam Leffler reg += rt->info[i].shortPreamble << 2; 258914779705SSam Leffler OS_REG_WRITE(ah, reg, 259014779705SSam Leffler ath_hal_computetxtime(ah, rt, 259114779705SSam Leffler WLAN_CTRL_FRAME_SIZE, 259214779705SSam Leffler rt->info[i].controlRate, 259314779705SSam Leffler AH_TRUE)); 259414779705SSam Leffler } 259514779705SSam Leffler } 259614779705SSam Leffler } 259714779705SSam Leffler } 259814779705SSam Leffler 259914779705SSam Leffler /* Adjust various register settings based on half/quarter rate clock setting. 260014779705SSam Leffler * This includes: +USEC, TX/RX latency, 260114779705SSam Leffler * + IFS params: slot, eifs, misc etc. 260214779705SSam Leffler */ 260314779705SSam Leffler void 260459efa8b5SSam Leffler ar5212SetIFSTiming(struct ath_hal *ah, const struct ieee80211_channel *chan) 260514779705SSam Leffler { 260614779705SSam Leffler uint32_t txLat, rxLat, usec, slot, refClock, eifs, init_usec; 260714779705SSam Leffler 260859efa8b5SSam Leffler HALASSERT(IEEE80211_IS_CHAN_HALF(chan) || 260959efa8b5SSam Leffler IEEE80211_IS_CHAN_QUARTER(chan)); 261014779705SSam Leffler 261114779705SSam Leffler refClock = OS_REG_READ(ah, AR_USEC) & AR_USEC_USEC32; 261259efa8b5SSam Leffler if (IEEE80211_IS_CHAN_HALF(chan)) { 261314779705SSam Leffler slot = IFS_SLOT_HALF_RATE; 261414779705SSam Leffler rxLat = RX_NON_FULL_RATE_LATENCY << AR5212_USEC_RX_LAT_S; 261514779705SSam Leffler txLat = TX_HALF_RATE_LATENCY << AR5212_USEC_TX_LAT_S; 261614779705SSam Leffler usec = HALF_RATE_USEC; 261714779705SSam Leffler eifs = IFS_EIFS_HALF_RATE; 261814779705SSam Leffler init_usec = INIT_USEC >> 1; 261914779705SSam Leffler } else { /* quarter rate */ 262014779705SSam Leffler slot = IFS_SLOT_QUARTER_RATE; 262114779705SSam Leffler rxLat = RX_NON_FULL_RATE_LATENCY << AR5212_USEC_RX_LAT_S; 262214779705SSam Leffler txLat = TX_QUARTER_RATE_LATENCY << AR5212_USEC_TX_LAT_S; 262314779705SSam Leffler usec = QUARTER_RATE_USEC; 262414779705SSam Leffler eifs = IFS_EIFS_QUARTER_RATE; 262514779705SSam Leffler init_usec = INIT_USEC >> 2; 262614779705SSam Leffler } 262714779705SSam Leffler 262814779705SSam Leffler OS_REG_WRITE(ah, AR_USEC, (usec | refClock | txLat | rxLat)); 262914779705SSam Leffler OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, slot); 263014779705SSam Leffler OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, eifs); 263114779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_D_GBL_IFS_MISC, 263214779705SSam Leffler AR_D_GBL_IFS_MISC_USEC_DURATION, init_usec); 263314779705SSam Leffler } 2634