114779705SSam Leffler /* 259efa8b5SSam Leffler * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 314779705SSam Leffler * Copyright (c) 2002-2008 Atheros Communications, Inc. 414779705SSam Leffler * 514779705SSam Leffler * Permission to use, copy, modify, and/or distribute this software for any 614779705SSam Leffler * purpose with or without fee is hereby granted, provided that the above 714779705SSam Leffler * copyright notice and this permission notice appear in all copies. 814779705SSam Leffler * 914779705SSam Leffler * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 1014779705SSam Leffler * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 1114779705SSam Leffler * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 1214779705SSam Leffler * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 1314779705SSam Leffler * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 1414779705SSam Leffler * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 1514779705SSam Leffler * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 1614779705SSam Leffler * 178698ea65SSam Leffler * $FreeBSD$ 1814779705SSam Leffler */ 1914779705SSam Leffler #include "opt_ah.h" 2014779705SSam Leffler 2114779705SSam Leffler #include "ah.h" 2214779705SSam Leffler #include "ah_internal.h" 2314779705SSam Leffler #include "ah_devid.h" 2414779705SSam Leffler 2514779705SSam Leffler #include "ar5212/ar5212.h" 2614779705SSam Leffler #include "ar5212/ar5212reg.h" 2714779705SSam Leffler #include "ar5212/ar5212phy.h" 2814779705SSam Leffler 2914779705SSam Leffler #include "ah_eeprom_v3.h" 3014779705SSam Leffler 3114779705SSam Leffler /* Additional Time delay to wait after activiting the Base band */ 3214779705SSam Leffler #define BASE_ACTIVATE_DELAY 100 /* 100 usec */ 3314779705SSam Leffler #define PLL_SETTLE_DELAY 300 /* 300 usec */ 3414779705SSam Leffler 3514779705SSam Leffler static HAL_BOOL ar5212SetResetReg(struct ath_hal *, uint32_t resetMask); 3614779705SSam Leffler /* NB: public for 5312 use */ 3759efa8b5SSam Leffler HAL_BOOL ar5212IsSpurChannel(struct ath_hal *, 3859efa8b5SSam Leffler const struct ieee80211_channel *); 3959efa8b5SSam Leffler HAL_BOOL ar5212ChannelChange(struct ath_hal *, 4059efa8b5SSam Leffler const struct ieee80211_channel *); 4159efa8b5SSam Leffler int16_t ar5212GetNf(struct ath_hal *, struct ieee80211_channel *); 4259efa8b5SSam Leffler HAL_BOOL ar5212SetBoardValues(struct ath_hal *, 4359efa8b5SSam Leffler const struct ieee80211_channel *); 4459efa8b5SSam Leffler void ar5212SetDeltaSlope(struct ath_hal *, 4559efa8b5SSam Leffler const struct ieee80211_channel *); 4614779705SSam Leffler HAL_BOOL ar5212SetTransmitPower(struct ath_hal *ah, 4759efa8b5SSam Leffler const struct ieee80211_channel *chan, uint16_t *rfXpdGain); 4814779705SSam Leffler static HAL_BOOL ar5212SetRateTable(struct ath_hal *, 4959efa8b5SSam Leffler const struct ieee80211_channel *, int16_t tpcScaleReduction, 5059efa8b5SSam Leffler int16_t powerLimit, 5114779705SSam Leffler HAL_BOOL commit, int16_t *minPower, int16_t *maxPower); 5214779705SSam Leffler static void ar5212CorrectGainDelta(struct ath_hal *, int twiceOfdmCckDelta); 5359efa8b5SSam Leffler static void ar5212GetTargetPowers(struct ath_hal *, 5459efa8b5SSam Leffler const struct ieee80211_channel *, 5514779705SSam Leffler const TRGT_POWER_INFO *pPowerInfo, uint16_t numChannels, 5614779705SSam Leffler TRGT_POWER_INFO *pNewPower); 5714779705SSam Leffler static uint16_t ar5212GetMaxEdgePower(uint16_t channel, 5814779705SSam Leffler const RD_EDGES_POWER *pRdEdgesPower); 5959efa8b5SSam Leffler void ar5212SetRateDurationTable(struct ath_hal *, 6059efa8b5SSam Leffler const struct ieee80211_channel *); 6159efa8b5SSam Leffler void ar5212SetIFSTiming(struct ath_hal *, 6259efa8b5SSam Leffler const struct ieee80211_channel *); 6314779705SSam Leffler 6414779705SSam Leffler /* NB: public for RF backend use */ 6514779705SSam Leffler void ar5212GetLowerUpperValues(uint16_t value, 6614779705SSam Leffler uint16_t *pList, uint16_t listSize, 6714779705SSam Leffler uint16_t *pLowerValue, uint16_t *pUpperValue); 6814779705SSam Leffler void ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32, 6914779705SSam Leffler uint32_t numBits, uint32_t firstBit, uint32_t column); 7014779705SSam Leffler 7114779705SSam Leffler static int 7214779705SSam Leffler write_common(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 7314779705SSam Leffler HAL_BOOL bChannelChange, int writes) 7414779705SSam Leffler { 7514779705SSam Leffler #define IS_NO_RESET_TIMER_ADDR(x) \ 7614779705SSam Leffler ( (((x) >= AR_BEACON) && ((x) <= AR_CFP_DUR)) || \ 7714779705SSam Leffler (((x) >= AR_SLEEP1) && ((x) <= AR_SLEEP3))) 7814779705SSam Leffler #define V(r, c) (ia)->data[((r)*(ia)->cols) + (c)] 7914779705SSam Leffler int r; 8014779705SSam Leffler 8114779705SSam Leffler /* Write Common Array Parameters */ 8214779705SSam Leffler for (r = 0; r < ia->rows; r++) { 8314779705SSam Leffler uint32_t reg = V(r, 0); 8414779705SSam Leffler /* XXX timer/beacon setup registers? */ 8514779705SSam Leffler /* On channel change, don't reset the PCU registers */ 8614779705SSam Leffler if (!(bChannelChange && IS_NO_RESET_TIMER_ADDR(reg))) { 8714779705SSam Leffler OS_REG_WRITE(ah, reg, V(r, 1)); 8814779705SSam Leffler DMA_YIELD(writes); 8914779705SSam Leffler } 9014779705SSam Leffler } 9114779705SSam Leffler return writes; 9214779705SSam Leffler #undef IS_NO_RESET_TIMER_ADDR 9314779705SSam Leffler #undef V 9414779705SSam Leffler } 9514779705SSam Leffler 9614779705SSam Leffler #define IS_DISABLE_FAST_ADC_CHAN(x) (((x) == 2462) || ((x) == 2467)) 9714779705SSam Leffler 9814779705SSam Leffler /* 990cbbe870SAdrian Chadd * XXX NDIS 5.x code had MAX_RESET_WAIT set to 2000 for AP code 1000cbbe870SAdrian Chadd * and 10 for Client code 1010cbbe870SAdrian Chadd */ 1020cbbe870SAdrian Chadd #define MAX_RESET_WAIT 10 1030cbbe870SAdrian Chadd 1040cbbe870SAdrian Chadd #define TX_QUEUEPEND_CHECK 1 1050cbbe870SAdrian Chadd #define TX_ENABLE_CHECK 2 1060cbbe870SAdrian Chadd #define RX_ENABLE_CHECK 4 1070cbbe870SAdrian Chadd 1080cbbe870SAdrian Chadd /* 10914779705SSam Leffler * Places the device in and out of reset and then places sane 11014779705SSam Leffler * values in the registers based on EEPROM config, initialization 11114779705SSam Leffler * vectors (as determined by the mode), and station configuration 11214779705SSam Leffler * 11314779705SSam Leffler * bChannelChange is used to preserve DMA/PCU registers across 11414779705SSam Leffler * a HW Reset during channel change. 11514779705SSam Leffler */ 11614779705SSam Leffler HAL_BOOL 11714779705SSam Leffler ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode, 11859efa8b5SSam Leffler struct ieee80211_channel *chan, 119f50e4ebfSAdrian Chadd HAL_BOOL bChannelChange, 1201ce01724SRenato Botelho HAL_RESET_TYPE resetType, 121f50e4ebfSAdrian Chadd HAL_STATUS *status) 12214779705SSam Leffler { 12314779705SSam Leffler #define N(a) (sizeof (a) / sizeof (a[0])) 12414779705SSam Leffler #define FAIL(_code) do { ecode = _code; goto bad; } while (0) 12514779705SSam Leffler struct ath_hal_5212 *ahp = AH5212(ah); 12614779705SSam Leffler HAL_CHANNEL_INTERNAL *ichan = AH_NULL; 12714779705SSam Leffler const HAL_EEPROM *ee; 12814779705SSam Leffler uint32_t softLedCfg, softLedState; 12914779705SSam Leffler uint32_t saveFrameSeqCount, saveDefAntenna, saveLedState; 13014779705SSam Leffler uint32_t macStaId1, synthDelay, txFrm2TxDStart; 13114779705SSam Leffler uint16_t rfXpdGain[MAX_NUM_PDGAINS_PER_CHANNEL]; 13214779705SSam Leffler int16_t cckOfdmPwrDelta = 0; 13314779705SSam Leffler u_int modesIndex, freqIndex; 13414779705SSam Leffler HAL_STATUS ecode; 13514779705SSam Leffler int i, regWrites; 13614779705SSam Leffler uint32_t testReg, powerVal; 13714779705SSam Leffler int8_t twiceAntennaGain, twiceAntennaReduction; 13814779705SSam Leffler uint32_t ackTpcPow, ctsTpcPow, chirpTpcPow; 13914779705SSam Leffler HAL_BOOL isBmode = AH_FALSE; 14014779705SSam Leffler 14114779705SSam Leffler HALASSERT(ah->ah_magic == AR5212_MAGIC); 14214779705SSam Leffler ee = AH_PRIVATE(ah)->ah_eeprom; 14314779705SSam Leffler 14414779705SSam Leffler OS_MARK(ah, AH_MARK_RESET, bChannelChange); 14514779705SSam Leffler 14614779705SSam Leffler /* Bring out of sleep mode */ 14714779705SSam Leffler if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 14814779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip did not wakeup\n", 14914779705SSam Leffler __func__); 15014779705SSam Leffler FAIL(HAL_EIO); 15114779705SSam Leffler } 15214779705SSam Leffler 15314779705SSam Leffler /* 15414779705SSam Leffler * Map public channel to private. 15514779705SSam Leffler */ 15614779705SSam Leffler ichan = ath_hal_checkchannel(ah, chan); 15759efa8b5SSam Leffler if (ichan == AH_NULL) 15814779705SSam Leffler FAIL(HAL_EINVAL); 15914779705SSam Leffler switch (opmode) { 16014779705SSam Leffler case HAL_M_STA: 16114779705SSam Leffler case HAL_M_IBSS: 16214779705SSam Leffler case HAL_M_HOSTAP: 16314779705SSam Leffler case HAL_M_MONITOR: 16414779705SSam Leffler break; 16514779705SSam Leffler default: 16614779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n", 16714779705SSam Leffler __func__, opmode); 16814779705SSam Leffler FAIL(HAL_EINVAL); 16914779705SSam Leffler break; 17014779705SSam Leffler } 17114779705SSam Leffler HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3); 17214779705SSam Leffler 17314779705SSam Leffler SAVE_CCK(ah, chan, isBmode); 17414779705SSam Leffler 17514779705SSam Leffler /* Preserve certain DMA hardware registers on a channel change */ 17614779705SSam Leffler if (bChannelChange) { 17714779705SSam Leffler /* 17814779705SSam Leffler * On Venice, the TSF is almost preserved across a reset; 17914779705SSam Leffler * it requires doubling writes to the RESET_TSF 18014779705SSam Leffler * bit in the AR_BEACON register; it also has the quirk 18114779705SSam Leffler * of the TSF going back in time on the station (station 18214779705SSam Leffler * latches onto the last beacon's tsf during a reset 50% 18314779705SSam Leffler * of the times); the latter is not a problem for adhoc 18414779705SSam Leffler * stations since as long as the TSF is behind, it will 18514779705SSam Leffler * get resynchronized on receiving the next beacon; the 18614779705SSam Leffler * TSF going backwards in time could be a problem for the 18714779705SSam Leffler * sleep operation (supported on infrastructure stations 18814779705SSam Leffler * only) - the best and most general fix for this situation 18914779705SSam Leffler * is to resynchronize the various sleep/beacon timers on 19014779705SSam Leffler * the receipt of the next beacon i.e. when the TSF itself 19114779705SSam Leffler * gets resynchronized to the AP's TSF - power save is 19214779705SSam Leffler * needed to be temporarily disabled until that time 19314779705SSam Leffler * 19414779705SSam Leffler * Need to save the sequence number to restore it after 19514779705SSam Leffler * the reset! 19614779705SSam Leffler */ 19714779705SSam Leffler saveFrameSeqCount = OS_REG_READ(ah, AR_D_SEQNUM); 19814779705SSam Leffler } else 19914779705SSam Leffler saveFrameSeqCount = 0; /* NB: silence compiler */ 2006af85006SAdrian Chadd 2016af85006SAdrian Chadd /* Blank the channel survey statistics */ 202b0602becSAdrian Chadd ath_hal_survey_clear(ah); 203b0602becSAdrian Chadd 20414779705SSam Leffler #if 0 20514779705SSam Leffler /* 20614779705SSam Leffler * XXX disable for now; this appears to sometimes cause OFDM 20714779705SSam Leffler * XXX timing error floods when ani is enabled and bg scanning 20814779705SSam Leffler * XXX kicks in 20914779705SSam Leffler */ 21014779705SSam Leffler /* If the channel change is across the same mode - perform a fast channel change */ 21114779705SSam Leffler if (IS_2413(ah) || IS_5413(ah)) { 21214779705SSam Leffler /* 21314779705SSam Leffler * Fast channel change can only be used when: 21414779705SSam Leffler * -channel change requested - so it's not the initial reset. 21514779705SSam Leffler * -it's not a change to the current channel - 21614779705SSam Leffler * often called when switching modes on a channel 21714779705SSam Leffler * -the modes of the previous and requested channel are the 21814779705SSam Leffler * same 21914779705SSam Leffler * XXX opmode shouldn't change either? 22014779705SSam Leffler */ 22114779705SSam Leffler if (bChannelChange && 22214779705SSam Leffler (AH_PRIVATE(ah)->ah_curchan != AH_NULL) && 22359efa8b5SSam Leffler (chan->ic_freq != AH_PRIVATE(ah)->ah_curchan->ic_freq) && 22459efa8b5SSam Leffler ((chan->ic_flags & IEEE80211_CHAN_ALLTURBO) == 22559efa8b5SSam Leffler (AH_PRIVATE(ah)->ah_curchan->ic_flags & IEEE80211_CHAN_ALLTURBO))) { 22614779705SSam Leffler if (ar5212ChannelChange(ah, chan)) { 22714779705SSam Leffler /* If ChannelChange completed - skip the rest of reset */ 22814779705SSam Leffler /* XXX ani? */ 22959efa8b5SSam Leffler goto done; 23014779705SSam Leffler } 23114779705SSam Leffler } 23214779705SSam Leffler } 23314779705SSam Leffler #endif 23414779705SSam Leffler /* 23514779705SSam Leffler * Preserve the antenna on a channel change 23614779705SSam Leffler */ 23714779705SSam Leffler saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA); 23814779705SSam Leffler if (saveDefAntenna == 0) /* XXX magic constants */ 23914779705SSam Leffler saveDefAntenna = 1; 24014779705SSam Leffler 24114779705SSam Leffler /* Save hardware flag before chip reset clears the register */ 24214779705SSam Leffler macStaId1 = OS_REG_READ(ah, AR_STA_ID1) & 24314779705SSam Leffler (AR_STA_ID1_BASE_RATE_11B | AR_STA_ID1_USE_DEFANT); 24414779705SSam Leffler 24514779705SSam Leffler /* Save led state from pci config register */ 24614779705SSam Leffler saveLedState = OS_REG_READ(ah, AR_PCICFG) & 24714779705SSam Leffler (AR_PCICFG_LEDCTL | AR_PCICFG_LEDMODE | AR_PCICFG_LEDBLINK | 24814779705SSam Leffler AR_PCICFG_LEDSLOW); 24914779705SSam Leffler softLedCfg = OS_REG_READ(ah, AR_GPIOCR); 25014779705SSam Leffler softLedState = OS_REG_READ(ah, AR_GPIODO); 25114779705SSam Leffler 25214779705SSam Leffler ar5212RestoreClock(ah, opmode); /* move to refclk operation */ 25314779705SSam Leffler 25414779705SSam Leffler /* 25514779705SSam Leffler * Adjust gain parameters before reset if 25614779705SSam Leffler * there's an outstanding gain updated. 25714779705SSam Leffler */ 25814779705SSam Leffler (void) ar5212GetRfgain(ah); 25914779705SSam Leffler 26014779705SSam Leffler if (!ar5212ChipReset(ah, chan)) { 26114779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 26214779705SSam Leffler FAIL(HAL_EIO); 26314779705SSam Leffler } 26414779705SSam Leffler 26514779705SSam Leffler /* Setup the indices for the next set of register array writes */ 26659efa8b5SSam Leffler if (IEEE80211_IS_CHAN_2GHZ(chan)) { 26714779705SSam Leffler freqIndex = 2; 26859efa8b5SSam Leffler if (IEEE80211_IS_CHAN_108G(chan)) 26914779705SSam Leffler modesIndex = 5; 27059efa8b5SSam Leffler else if (IEEE80211_IS_CHAN_G(chan)) 27159efa8b5SSam Leffler modesIndex = 4; 27259efa8b5SSam Leffler else if (IEEE80211_IS_CHAN_B(chan)) 27359efa8b5SSam Leffler modesIndex = 3; 27459efa8b5SSam Leffler else { 27559efa8b5SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, 27659efa8b5SSam Leffler "%s: invalid channel %u/0x%x\n", 27759efa8b5SSam Leffler __func__, chan->ic_freq, chan->ic_flags); 27814779705SSam Leffler FAIL(HAL_EINVAL); 27914779705SSam Leffler } 28059efa8b5SSam Leffler } else { 28159efa8b5SSam Leffler freqIndex = 1; 28259efa8b5SSam Leffler if (IEEE80211_IS_CHAN_TURBO(chan)) 28359efa8b5SSam Leffler modesIndex = 2; 28459efa8b5SSam Leffler else if (IEEE80211_IS_CHAN_A(chan)) 28559efa8b5SSam Leffler modesIndex = 1; 28659efa8b5SSam Leffler else { 28759efa8b5SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, 28859efa8b5SSam Leffler "%s: invalid channel %u/0x%x\n", 28959efa8b5SSam Leffler __func__, chan->ic_freq, chan->ic_flags); 29059efa8b5SSam Leffler FAIL(HAL_EINVAL); 29159efa8b5SSam Leffler } 29259efa8b5SSam Leffler } 29314779705SSam Leffler 29414779705SSam Leffler OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 29514779705SSam Leffler 29614779705SSam Leffler /* Set correct Baseband to analog shift setting to access analog chips. */ 29714779705SSam Leffler OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 29814779705SSam Leffler 29914779705SSam Leffler regWrites = ath_hal_ini_write(ah, &ahp->ah_ini_modes, modesIndex, 0); 30014779705SSam Leffler regWrites = write_common(ah, &ahp->ah_ini_common, bChannelChange, 30114779705SSam Leffler regWrites); 302bc391cb2SWarner Losh #ifdef AH_RXCFG_SDMAMW_4BYTES 303bc391cb2SWarner Losh /* 304bc391cb2SWarner Losh * Nala doesn't work with 128 byte bursts on pb42(hydra) (ar71xx), 305bc391cb2SWarner Losh * use 4 instead. Enabling it on all platforms would hurt performance, 306bc391cb2SWarner Losh * so we only enable it on the ones that are affected by it. 307bc391cb2SWarner Losh */ 308bc391cb2SWarner Losh OS_REG_WRITE(ah, AR_RXCFG, 0); 309bc391cb2SWarner Losh #endif 31014779705SSam Leffler ahp->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 31114779705SSam Leffler 31214779705SSam Leffler OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 31314779705SSam Leffler 31459efa8b5SSam Leffler if (IEEE80211_IS_CHAN_HALF(chan) || IEEE80211_IS_CHAN_QUARTER(chan)) { 31514779705SSam Leffler ar5212SetIFSTiming(ah, chan); 31614779705SSam Leffler if (IS_5413(ah)) { 31714779705SSam Leffler /* 31814779705SSam Leffler * Force window_length for 1/2 and 1/4 rate channels, 31914779705SSam Leffler * the ini file sets this to zero otherwise. 32014779705SSam Leffler */ 32114779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, 32214779705SSam Leffler AR_PHY_FRAME_CTL_WINLEN, 3); 32314779705SSam Leffler } 32414779705SSam Leffler } 32514779705SSam Leffler 32614779705SSam Leffler /* Overwrite INI values for revised chipsets */ 32714779705SSam Leffler if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_2) { 32814779705SSam Leffler /* ADC_CTL */ 32914779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_ADC_CTL, 33014779705SSam Leffler SM(2, AR_PHY_ADC_CTL_OFF_INBUFGAIN) | 33114779705SSam Leffler SM(2, AR_PHY_ADC_CTL_ON_INBUFGAIN) | 33214779705SSam Leffler AR_PHY_ADC_CTL_OFF_PWDDAC | 33314779705SSam Leffler AR_PHY_ADC_CTL_OFF_PWDADC); 33414779705SSam Leffler 33514779705SSam Leffler /* TX_PWR_ADJ */ 33659efa8b5SSam Leffler if (ichan->channel == 2484) { 33714779705SSam Leffler cckOfdmPwrDelta = SCALE_OC_DELTA( 33814779705SSam Leffler ee->ee_cckOfdmPwrDelta - 33914779705SSam Leffler ee->ee_scaledCh14FilterCckDelta); 34014779705SSam Leffler } else { 34114779705SSam Leffler cckOfdmPwrDelta = SCALE_OC_DELTA( 34214779705SSam Leffler ee->ee_cckOfdmPwrDelta); 34314779705SSam Leffler } 34414779705SSam Leffler 34559efa8b5SSam Leffler if (IEEE80211_IS_CHAN_G(chan)) { 34614779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_TXPWRADJ, 34714779705SSam Leffler SM((ee->ee_cckOfdmPwrDelta*-1), 34814779705SSam Leffler AR_PHY_TXPWRADJ_CCK_GAIN_DELTA) | 34914779705SSam Leffler SM((cckOfdmPwrDelta*-1), 35014779705SSam Leffler AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX)); 35114779705SSam Leffler } else { 35214779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_TXPWRADJ, 0); 35314779705SSam Leffler } 35414779705SSam Leffler 35514779705SSam Leffler /* Add barker RSSI thresh enable as disabled */ 35614779705SSam Leffler OS_REG_CLR_BIT(ah, AR_PHY_DAG_CTRLCCK, 35714779705SSam Leffler AR_PHY_DAG_CTRLCCK_EN_RSSI_THR); 35814779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_DAG_CTRLCCK, 35914779705SSam Leffler AR_PHY_DAG_CTRLCCK_RSSI_THR, 2); 36014779705SSam Leffler 36114779705SSam Leffler /* Set the mute mask to the correct default */ 36214779705SSam Leffler OS_REG_WRITE(ah, AR_SEQ_MASK, 0x0000000F); 36314779705SSam Leffler } 36414779705SSam Leffler 36514779705SSam Leffler if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_3) { 36614779705SSam Leffler /* Clear reg to alllow RX_CLEAR line debug */ 36714779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_BLUETOOTH, 0); 36814779705SSam Leffler } 36914779705SSam Leffler if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_4) { 37014779705SSam Leffler #ifdef notyet 37114779705SSam Leffler /* Enable burst prefetch for the data queues */ 37214779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_D_FPCTL, ... ); 37314779705SSam Leffler /* Enable double-buffering */ 37414779705SSam Leffler OS_REG_CLR_BIT(ah, AR_TXCFG, AR_TXCFG_DBL_BUF_DIS); 37514779705SSam Leffler #endif 37614779705SSam Leffler } 37714779705SSam Leffler 37814779705SSam Leffler /* Set ADC/DAC select values */ 37914779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e); 38014779705SSam Leffler 38114779705SSam Leffler if (IS_5413(ah) || IS_2417(ah)) { 38214779705SSam Leffler uint32_t newReg = 1; 38359efa8b5SSam Leffler if (IS_DISABLE_FAST_ADC_CHAN(ichan->channel)) 38414779705SSam Leffler newReg = 0; 38514779705SSam Leffler /* As it's a clock changing register, only write when the value needs to be changed */ 38614779705SSam Leffler if (OS_REG_READ(ah, AR_PHY_FAST_ADC) != newReg) 38714779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_FAST_ADC, newReg); 38814779705SSam Leffler } 38914779705SSam Leffler 39014779705SSam Leffler /* Setup the transmit power values. */ 39159efa8b5SSam Leffler if (!ar5212SetTransmitPower(ah, chan, rfXpdGain)) { 39214779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, 39314779705SSam Leffler "%s: error init'ing transmit power\n", __func__); 39414779705SSam Leffler FAIL(HAL_EIO); 39514779705SSam Leffler } 39614779705SSam Leffler 39714779705SSam Leffler /* Write the analog registers */ 39859efa8b5SSam Leffler if (!ahp->ah_rfHal->setRfRegs(ah, chan, modesIndex, rfXpdGain)) { 39914779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5212SetRfRegs failed\n", 40014779705SSam Leffler __func__); 40114779705SSam Leffler FAIL(HAL_EIO); 40214779705SSam Leffler } 40314779705SSam Leffler 40414779705SSam Leffler /* Write delta slope for OFDM enabled modes (A, G, Turbo) */ 40559efa8b5SSam Leffler if (IEEE80211_IS_CHAN_OFDM(chan)) { 40659efa8b5SSam Leffler if (IS_5413(ah) || 40759efa8b5SSam Leffler AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3) 40859efa8b5SSam Leffler ar5212SetSpurMitigation(ah, chan); 40914779705SSam Leffler ar5212SetDeltaSlope(ah, chan); 41014779705SSam Leffler } 41114779705SSam Leffler 41214779705SSam Leffler /* Setup board specific options for EEPROM version 3 */ 41359efa8b5SSam Leffler if (!ar5212SetBoardValues(ah, chan)) { 41414779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, 41514779705SSam Leffler "%s: error setting board options\n", __func__); 41614779705SSam Leffler FAIL(HAL_EIO); 41714779705SSam Leffler } 41814779705SSam Leffler 41914779705SSam Leffler /* Restore certain DMA hardware registers on a channel change */ 42014779705SSam Leffler if (bChannelChange) 42114779705SSam Leffler OS_REG_WRITE(ah, AR_D_SEQNUM, saveFrameSeqCount); 42214779705SSam Leffler 42314779705SSam Leffler OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 42414779705SSam Leffler 42514779705SSam Leffler OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr)); 42614779705SSam Leffler OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4) 42714779705SSam Leffler | macStaId1 42814779705SSam Leffler | AR_STA_ID1_RTS_USE_DEF 42914779705SSam Leffler | ahp->ah_staId1Defaults 43014779705SSam Leffler ); 43114779705SSam Leffler ar5212SetOperatingMode(ah, opmode); 43214779705SSam Leffler 43314779705SSam Leffler /* Set Venice BSSID mask according to current state */ 43414779705SSam Leffler OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask)); 43514779705SSam Leffler OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4)); 43614779705SSam Leffler 43714779705SSam Leffler /* Restore previous led state */ 43814779705SSam Leffler OS_REG_WRITE(ah, AR_PCICFG, OS_REG_READ(ah, AR_PCICFG) | saveLedState); 43914779705SSam Leffler 44014779705SSam Leffler /* Restore soft Led state to GPIO */ 44114779705SSam Leffler OS_REG_WRITE(ah, AR_GPIOCR, softLedCfg); 44214779705SSam Leffler OS_REG_WRITE(ah, AR_GPIODO, softLedState); 44314779705SSam Leffler 44414779705SSam Leffler /* Restore previous antenna */ 44514779705SSam Leffler OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 44614779705SSam Leffler 4470047ff70SAdrian Chadd /* then our BSSID and associate id */ 44814779705SSam Leffler OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); 4490047ff70SAdrian Chadd OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) | 4500047ff70SAdrian Chadd (ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S); 45114779705SSam Leffler 45214779705SSam Leffler /* Restore bmiss rssi & count thresholds */ 45314779705SSam Leffler OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr); 45414779705SSam Leffler 45514779705SSam Leffler OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */ 45614779705SSam Leffler 45759efa8b5SSam Leffler if (!ar5212SetChannel(ah, chan)) 45814779705SSam Leffler FAIL(HAL_EIO); 45914779705SSam Leffler 46014779705SSam Leffler OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 46114779705SSam Leffler 46214779705SSam Leffler ar5212SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1); 46314779705SSam Leffler 46414779705SSam Leffler ar5212SetRateDurationTable(ah, chan); 46514779705SSam Leffler 46614779705SSam Leffler /* Set Tx frame start to tx data start delay */ 46714779705SSam Leffler if (IS_RAD5112_ANY(ah) && 46859efa8b5SSam Leffler (IEEE80211_IS_CHAN_HALF(chan) || IEEE80211_IS_CHAN_QUARTER(chan))) { 46914779705SSam Leffler txFrm2TxDStart = 47059efa8b5SSam Leffler IEEE80211_IS_CHAN_HALF(chan) ? 47114779705SSam Leffler TX_FRAME_D_START_HALF_RATE: 47214779705SSam Leffler TX_FRAME_D_START_QUARTER_RATE; 47314779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_TX_CTL, 47414779705SSam Leffler AR_PHY_TX_FRAME_TO_TX_DATA_START, txFrm2TxDStart); 47514779705SSam Leffler } 47614779705SSam Leffler 47714779705SSam Leffler /* 47814779705SSam Leffler * Setup fast diversity. 47914779705SSam Leffler * Fast diversity can be enabled or disabled via regadd.txt. 48014779705SSam Leffler * Default is enabled. 48114779705SSam Leffler * For reference, 48214779705SSam Leffler * Disable: reg val 48314779705SSam Leffler * 0x00009860 0x00009d18 (if 11a / 11g, else no change) 48414779705SSam Leffler * 0x00009970 0x192bb514 48514779705SSam Leffler * 0x0000a208 0xd03e4648 48614779705SSam Leffler * 48714779705SSam Leffler * Enable: 0x00009860 0x00009d10 (if 11a / 11g, else no change) 48814779705SSam Leffler * 0x00009970 0x192fb514 48914779705SSam Leffler * 0x0000a208 0xd03e6788 49014779705SSam Leffler */ 49114779705SSam Leffler 49214779705SSam Leffler /* XXX Setup pre PHY ENABLE EAR additions */ 49314779705SSam Leffler /* 49414779705SSam Leffler * Wait for the frequency synth to settle (synth goes on 49514779705SSam Leffler * via AR_PHY_ACTIVE_EN). Read the phy active delay register. 49614779705SSam Leffler * Value is in 100ns increments. 49714779705SSam Leffler */ 49814779705SSam Leffler synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 49959efa8b5SSam Leffler if (IEEE80211_IS_CHAN_B(chan)) { 50014779705SSam Leffler synthDelay = (4 * synthDelay) / 22; 50114779705SSam Leffler } else { 50214779705SSam Leffler synthDelay /= 10; 50314779705SSam Leffler } 50414779705SSam Leffler 50514779705SSam Leffler /* Activate the PHY (includes baseband activate and synthesizer on) */ 50614779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 50714779705SSam Leffler 50814779705SSam Leffler /* 50914779705SSam Leffler * There is an issue if the AP starts the calibration before 51014779705SSam Leffler * the base band timeout completes. This could result in the 51114779705SSam Leffler * rx_clear false triggering. As a workaround we add delay an 51214779705SSam Leffler * extra BASE_ACTIVATE_DELAY usecs to ensure this condition 51314779705SSam Leffler * does not happen. 51414779705SSam Leffler */ 51559efa8b5SSam Leffler if (IEEE80211_IS_CHAN_HALF(chan)) { 51614779705SSam Leffler OS_DELAY((synthDelay << 1) + BASE_ACTIVATE_DELAY); 51759efa8b5SSam Leffler } else if (IEEE80211_IS_CHAN_QUARTER(chan)) { 51814779705SSam Leffler OS_DELAY((synthDelay << 2) + BASE_ACTIVATE_DELAY); 51914779705SSam Leffler } else { 52014779705SSam Leffler OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY); 52114779705SSam Leffler } 52214779705SSam Leffler 52314779705SSam Leffler /* 52414779705SSam Leffler * The udelay method is not reliable with notebooks. 52514779705SSam Leffler * Need to check to see if the baseband is ready 52614779705SSam Leffler */ 52714779705SSam Leffler testReg = OS_REG_READ(ah, AR_PHY_TESTCTRL); 52814779705SSam Leffler /* Selects the Tx hold */ 52914779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_TESTCTRL, AR_PHY_TESTCTRL_TXHOLD); 53014779705SSam Leffler i = 0; 53114779705SSam Leffler while ((i++ < 20) && 53214779705SSam Leffler (OS_REG_READ(ah, 0x9c24) & 0x10)) /* test if baseband not ready */ OS_DELAY(200); 53314779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_TESTCTRL, testReg); 53414779705SSam Leffler 53514779705SSam Leffler /* Calibrate the AGC and start a NF calculation */ 53614779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, 53714779705SSam Leffler OS_REG_READ(ah, AR_PHY_AGC_CONTROL) 53814779705SSam Leffler | AR_PHY_AGC_CONTROL_CAL 53914779705SSam Leffler | AR_PHY_AGC_CONTROL_NF); 54014779705SSam Leffler 54159efa8b5SSam Leffler if (!IEEE80211_IS_CHAN_B(chan) && ahp->ah_bIQCalibration != IQ_CAL_DONE) { 54214779705SSam Leffler /* Start IQ calibration w/ 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples */ 54314779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 54414779705SSam Leffler AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, 54514779705SSam Leffler INIT_IQCAL_LOG_COUNT_MAX); 54614779705SSam Leffler OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 54714779705SSam Leffler AR_PHY_TIMING_CTRL4_DO_IQCAL); 54814779705SSam Leffler ahp->ah_bIQCalibration = IQ_CAL_RUNNING; 54914779705SSam Leffler } else 55014779705SSam Leffler ahp->ah_bIQCalibration = IQ_CAL_INACTIVE; 55114779705SSam Leffler 55214779705SSam Leffler /* Setup compression registers */ 55314779705SSam Leffler ar5212SetCompRegs(ah); 55414779705SSam Leffler 55514779705SSam Leffler /* Set 1:1 QCU to DCU mapping for all queues */ 55614779705SSam Leffler for (i = 0; i < AR_NUM_DCU; i++) 55714779705SSam Leffler OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 55814779705SSam Leffler 55914779705SSam Leffler ahp->ah_intrTxqs = 0; 56014779705SSam Leffler for (i = 0; i < AH_PRIVATE(ah)->ah_caps.halTotalQueues; i++) 56114779705SSam Leffler ar5212ResetTxQueue(ah, i); 56214779705SSam Leffler 56314779705SSam Leffler /* 56414779705SSam Leffler * Setup interrupt handling. Note that ar5212ResetTxQueue 56514779705SSam Leffler * manipulates the secondary IMR's as queues are enabled 56614779705SSam Leffler * and disabled. This is done with RMW ops to insure the 56714779705SSam Leffler * settings we make here are preserved. 56814779705SSam Leffler */ 56914779705SSam Leffler ahp->ah_maskReg = AR_IMR_TXOK | AR_IMR_TXERR | AR_IMR_TXURN 57014779705SSam Leffler | AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXORN 57114779705SSam Leffler | AR_IMR_HIUERR 57214779705SSam Leffler ; 57314779705SSam Leffler if (opmode == HAL_M_HOSTAP) 57414779705SSam Leffler ahp->ah_maskReg |= AR_IMR_MIB; 57514779705SSam Leffler OS_REG_WRITE(ah, AR_IMR, ahp->ah_maskReg); 57614779705SSam Leffler /* Enable bus errors that are OR'd to set the HIUERR bit */ 57714779705SSam Leffler OS_REG_WRITE(ah, AR_IMR_S2, 57814779705SSam Leffler OS_REG_READ(ah, AR_IMR_S2) 57914779705SSam Leffler | AR_IMR_S2_MCABT | AR_IMR_S2_SSERR | AR_IMR_S2_DPERR); 58014779705SSam Leffler 58114779705SSam Leffler if (AH_PRIVATE(ah)->ah_rfkillEnabled) 58214779705SSam Leffler ar5212EnableRfKill(ah); 58314779705SSam Leffler 58414779705SSam Leffler if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) { 58514779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, 58614779705SSam Leffler "%s: offset calibration failed to complete in 1ms;" 58714779705SSam Leffler " noisy environment?\n", __func__); 58814779705SSam Leffler } 58914779705SSam Leffler 59014779705SSam Leffler /* 59114779705SSam Leffler * Set clocks back to 32kHz if they had been using refClk, then 59214779705SSam Leffler * use an external 32kHz crystal when sleeping, if one exists. 59314779705SSam Leffler */ 59414779705SSam Leffler ar5212SetupClock(ah, opmode); 59514779705SSam Leffler 59614779705SSam Leffler /* 59714779705SSam Leffler * Writing to AR_BEACON will start timers. Hence it should 59814779705SSam Leffler * be the last register to be written. Do not reset tsf, do 59914779705SSam Leffler * not enable beacons at this point, but preserve other values 60014779705SSam Leffler * like beaconInterval. 60114779705SSam Leffler */ 60214779705SSam Leffler OS_REG_WRITE(ah, AR_BEACON, 60314779705SSam Leffler (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_EN | AR_BEACON_RESET_TSF))); 60414779705SSam Leffler 60514779705SSam Leffler /* XXX Setup post reset EAR additions */ 60614779705SSam Leffler 60714779705SSam Leffler /* QoS support */ 60814779705SSam Leffler if (AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE || 60914779705SSam Leffler (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 61014779705SSam Leffler AH_PRIVATE(ah)->ah_macRev >= AR_SREV_GRIFFIN_LITE)) { 61114779705SSam Leffler OS_REG_WRITE(ah, AR_QOS_CONTROL, 0x100aa); /* XXX magic */ 61214779705SSam Leffler OS_REG_WRITE(ah, AR_QOS_SELECT, 0x3210); /* XXX magic */ 61314779705SSam Leffler } 61414779705SSam Leffler 61514779705SSam Leffler /* Turn on NOACK Support for QoS packets */ 61614779705SSam Leffler OS_REG_WRITE(ah, AR_NOACK, 61714779705SSam Leffler SM(2, AR_NOACK_2BIT_VALUE) | 61814779705SSam Leffler SM(5, AR_NOACK_BIT_OFFSET) | 61914779705SSam Leffler SM(0, AR_NOACK_BYTE_OFFSET)); 62014779705SSam Leffler 62114779705SSam Leffler /* Get Antenna Gain reduction */ 62259efa8b5SSam Leffler if (IEEE80211_IS_CHAN_5GHZ(chan)) { 62314779705SSam Leffler ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_5, &twiceAntennaGain); 62414779705SSam Leffler } else { 62514779705SSam Leffler ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_2, &twiceAntennaGain); 62614779705SSam Leffler } 62714779705SSam Leffler twiceAntennaReduction = 62814779705SSam Leffler ath_hal_getantennareduction(ah, chan, twiceAntennaGain); 62914779705SSam Leffler 63014779705SSam Leffler /* TPC for self-generated frames */ 63114779705SSam Leffler 63214779705SSam Leffler ackTpcPow = MS(ahp->ah_macTPC, AR_TPC_ACK); 63359efa8b5SSam Leffler if ((ackTpcPow-ahp->ah_txPowerIndexOffset) > chan->ic_maxpower) 63459efa8b5SSam Leffler ackTpcPow = chan->ic_maxpower+ahp->ah_txPowerIndexOffset; 63514779705SSam Leffler 63659efa8b5SSam Leffler if (ackTpcPow > (2*chan->ic_maxregpower - twiceAntennaReduction)) 63759efa8b5SSam Leffler ackTpcPow = (2*chan->ic_maxregpower - twiceAntennaReduction) 63814779705SSam Leffler + ahp->ah_txPowerIndexOffset; 63914779705SSam Leffler 64014779705SSam Leffler ctsTpcPow = MS(ahp->ah_macTPC, AR_TPC_CTS); 64159efa8b5SSam Leffler if ((ctsTpcPow-ahp->ah_txPowerIndexOffset) > chan->ic_maxpower) 64259efa8b5SSam Leffler ctsTpcPow = chan->ic_maxpower+ahp->ah_txPowerIndexOffset; 64314779705SSam Leffler 64459efa8b5SSam Leffler if (ctsTpcPow > (2*chan->ic_maxregpower - twiceAntennaReduction)) 64559efa8b5SSam Leffler ctsTpcPow = (2*chan->ic_maxregpower - twiceAntennaReduction) 64614779705SSam Leffler + ahp->ah_txPowerIndexOffset; 64714779705SSam Leffler 64814779705SSam Leffler chirpTpcPow = MS(ahp->ah_macTPC, AR_TPC_CHIRP); 64959efa8b5SSam Leffler if ((chirpTpcPow-ahp->ah_txPowerIndexOffset) > chan->ic_maxpower) 65059efa8b5SSam Leffler chirpTpcPow = chan->ic_maxpower+ahp->ah_txPowerIndexOffset; 65114779705SSam Leffler 65259efa8b5SSam Leffler if (chirpTpcPow > (2*chan->ic_maxregpower - twiceAntennaReduction)) 65359efa8b5SSam Leffler chirpTpcPow = (2*chan->ic_maxregpower - twiceAntennaReduction) 65414779705SSam Leffler + ahp->ah_txPowerIndexOffset; 65514779705SSam Leffler 65614779705SSam Leffler if (ackTpcPow > 63) 65714779705SSam Leffler ackTpcPow = 63; 65814779705SSam Leffler if (ctsTpcPow > 63) 65914779705SSam Leffler ctsTpcPow = 63; 66014779705SSam Leffler if (chirpTpcPow > 63) 66114779705SSam Leffler chirpTpcPow = 63; 66214779705SSam Leffler 66314779705SSam Leffler powerVal = SM(ackTpcPow, AR_TPC_ACK) | 66414779705SSam Leffler SM(ctsTpcPow, AR_TPC_CTS) | 66514779705SSam Leffler SM(chirpTpcPow, AR_TPC_CHIRP); 66614779705SSam Leffler 66714779705SSam Leffler OS_REG_WRITE(ah, AR_TPC, powerVal); 66814779705SSam Leffler 66914779705SSam Leffler /* Restore user-specified settings */ 67014779705SSam Leffler if (ahp->ah_miscMode != 0) 67114779705SSam Leffler OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode); 67214779705SSam Leffler if (ahp->ah_sifstime != (u_int) -1) 67314779705SSam Leffler ar5212SetSifsTime(ah, ahp->ah_sifstime); 67414779705SSam Leffler if (ahp->ah_slottime != (u_int) -1) 67514779705SSam Leffler ar5212SetSlotTime(ah, ahp->ah_slottime); 67614779705SSam Leffler if (ahp->ah_acktimeout != (u_int) -1) 67714779705SSam Leffler ar5212SetAckTimeout(ah, ahp->ah_acktimeout); 67814779705SSam Leffler if (ahp->ah_ctstimeout != (u_int) -1) 67914779705SSam Leffler ar5212SetCTSTimeout(ah, ahp->ah_ctstimeout); 68014779705SSam Leffler if (AH_PRIVATE(ah)->ah_diagreg != 0) 68114779705SSam Leffler OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); 68214779705SSam Leffler 68314779705SSam Leffler AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */ 68459efa8b5SSam Leffler #if 0 68559efa8b5SSam Leffler done: 68659efa8b5SSam Leffler #endif 68759efa8b5SSam Leffler if (bChannelChange && !IEEE80211_IS_CHAN_DFS(chan)) 68859efa8b5SSam Leffler chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT; 68914779705SSam Leffler 69014779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__); 69114779705SSam Leffler 69214779705SSam Leffler RESTORE_CCK(ah, chan, isBmode); 69314779705SSam Leffler 69414779705SSam Leffler OS_MARK(ah, AH_MARK_RESET_DONE, 0); 69514779705SSam Leffler 69614779705SSam Leffler return AH_TRUE; 69714779705SSam Leffler bad: 69814779705SSam Leffler RESTORE_CCK(ah, chan, isBmode); 69914779705SSam Leffler 70014779705SSam Leffler OS_MARK(ah, AH_MARK_RESET_DONE, ecode); 7018698ea65SSam Leffler if (status != AH_NULL) 70214779705SSam Leffler *status = ecode; 70314779705SSam Leffler return AH_FALSE; 70414779705SSam Leffler #undef FAIL 70514779705SSam Leffler #undef N 70614779705SSam Leffler } 70714779705SSam Leffler 70814779705SSam Leffler /* 70914779705SSam Leffler * Call the rf backend to change the channel. 71014779705SSam Leffler */ 71114779705SSam Leffler HAL_BOOL 71259efa8b5SSam Leffler ar5212SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan) 71314779705SSam Leffler { 71414779705SSam Leffler struct ath_hal_5212 *ahp = AH5212(ah); 71514779705SSam Leffler 71614779705SSam Leffler /* Change the synth */ 71714779705SSam Leffler if (!ahp->ah_rfHal->setChannel(ah, chan)) 71814779705SSam Leffler return AH_FALSE; 71914779705SSam Leffler return AH_TRUE; 72014779705SSam Leffler } 72114779705SSam Leffler 72214779705SSam Leffler /* 72314779705SSam Leffler * This channel change evaluates whether the selected hardware can 72414779705SSam Leffler * perform a synthesizer-only channel change (no reset). If the 72514779705SSam Leffler * TX is not stopped, or the RFBus cannot be granted in the given 72614779705SSam Leffler * time, the function returns false as a reset is necessary 72714779705SSam Leffler */ 72814779705SSam Leffler HAL_BOOL 72959efa8b5SSam Leffler ar5212ChannelChange(struct ath_hal *ah, const struct ieee80211_channel *chan) 73014779705SSam Leffler { 73114779705SSam Leffler uint32_t ulCount; 73214779705SSam Leffler uint32_t data, synthDelay, qnum; 73314779705SSam Leffler uint16_t rfXpdGain[MAX_NUM_PDGAINS_PER_CHANNEL]; 73414779705SSam Leffler HAL_BOOL txStopped = AH_TRUE; 73514779705SSam Leffler HAL_CHANNEL_INTERNAL *ichan; 73614779705SSam Leffler 73714779705SSam Leffler /* 73814779705SSam Leffler * Map public channel to private. 73914779705SSam Leffler */ 74014779705SSam Leffler ichan = ath_hal_checkchannel(ah, chan); 74114779705SSam Leffler 74214779705SSam Leffler /* TX must be stopped or RF Bus grant will not work */ 74314779705SSam Leffler for (qnum = 0; qnum < AH_PRIVATE(ah)->ah_caps.halTotalQueues; qnum++) { 74414779705SSam Leffler if (ar5212NumTxPending(ah, qnum)) { 74514779705SSam Leffler txStopped = AH_FALSE; 74614779705SSam Leffler break; 74714779705SSam Leffler } 74814779705SSam Leffler } 74914779705SSam Leffler if (!txStopped) 75014779705SSam Leffler return AH_FALSE; 75114779705SSam Leffler 75214779705SSam Leffler /* Kill last Baseband Rx Frame */ 75314779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_REQUEST); /* Request analog bus grant */ 75414779705SSam Leffler for (ulCount = 0; ulCount < 100; ulCount++) { 75514779705SSam Leffler if (OS_REG_READ(ah, AR_PHY_RFBUS_GNT)) 75614779705SSam Leffler break; 75714779705SSam Leffler OS_DELAY(5); 75814779705SSam Leffler } 75914779705SSam Leffler if (ulCount >= 100) 76014779705SSam Leffler return AH_FALSE; 76114779705SSam Leffler 76214779705SSam Leffler /* Change the synth */ 76359efa8b5SSam Leffler if (!ar5212SetChannel(ah, chan)) 76414779705SSam Leffler return AH_FALSE; 76514779705SSam Leffler 76614779705SSam Leffler /* 76714779705SSam Leffler * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN). 76814779705SSam Leffler * Read the phy active delay register. Value is in 100ns increments. 76914779705SSam Leffler */ 77014779705SSam Leffler data = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 77159efa8b5SSam Leffler if (IEEE80211_IS_CHAN_B(chan)) { 77214779705SSam Leffler synthDelay = (4 * data) / 22; 77314779705SSam Leffler } else { 77414779705SSam Leffler synthDelay = data / 10; 77514779705SSam Leffler } 77614779705SSam Leffler OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY); 77714779705SSam Leffler 77814779705SSam Leffler /* Setup the transmit power values. */ 77959efa8b5SSam Leffler if (!ar5212SetTransmitPower(ah, chan, rfXpdGain)) { 78014779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, 78114779705SSam Leffler "%s: error init'ing transmit power\n", __func__); 78214779705SSam Leffler return AH_FALSE; 78314779705SSam Leffler } 78414779705SSam Leffler 78514779705SSam Leffler /* Write delta slope for OFDM enabled modes (A, G, Turbo) */ 78659efa8b5SSam Leffler if (IEEE80211_IS_CHAN_OFDM(chan)) { 78759efa8b5SSam Leffler if (IS_5413(ah) || 78859efa8b5SSam Leffler AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3) 78959efa8b5SSam Leffler ar5212SetSpurMitigation(ah, chan); 79014779705SSam Leffler ar5212SetDeltaSlope(ah, chan); 79114779705SSam Leffler } 79214779705SSam Leffler 79314779705SSam Leffler /* Release the RFBus Grant */ 79414779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 79514779705SSam Leffler 79614779705SSam Leffler /* Start Noise Floor Cal */ 79714779705SSam Leffler OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 79814779705SSam Leffler return AH_TRUE; 79914779705SSam Leffler } 80014779705SSam Leffler 80114779705SSam Leffler void 80214779705SSam Leffler ar5212SetOperatingMode(struct ath_hal *ah, int opmode) 80314779705SSam Leffler { 80414779705SSam Leffler uint32_t val; 80514779705SSam Leffler 80614779705SSam Leffler val = OS_REG_READ(ah, AR_STA_ID1); 80714779705SSam Leffler val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC); 80814779705SSam Leffler switch (opmode) { 80914779705SSam Leffler case HAL_M_HOSTAP: 81014779705SSam Leffler OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP 81114779705SSam Leffler | AR_STA_ID1_KSRCH_MODE); 81214779705SSam Leffler OS_REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 81314779705SSam Leffler break; 81414779705SSam Leffler case HAL_M_IBSS: 81514779705SSam Leffler OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC 81614779705SSam Leffler | AR_STA_ID1_KSRCH_MODE); 81714779705SSam Leffler OS_REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 81814779705SSam Leffler break; 81914779705SSam Leffler case HAL_M_STA: 82014779705SSam Leffler case HAL_M_MONITOR: 82114779705SSam Leffler OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); 82214779705SSam Leffler break; 82314779705SSam Leffler } 82414779705SSam Leffler } 82514779705SSam Leffler 82614779705SSam Leffler /* 82714779705SSam Leffler * Places the PHY and Radio chips into reset. A full reset 82814779705SSam Leffler * must be called to leave this state. The PCI/MAC/PCU are 82914779705SSam Leffler * not placed into reset as we must receive interrupt to 83014779705SSam Leffler * re-enable the hardware. 83114779705SSam Leffler */ 83214779705SSam Leffler HAL_BOOL 83314779705SSam Leffler ar5212PhyDisable(struct ath_hal *ah) 83414779705SSam Leffler { 83514779705SSam Leffler return ar5212SetResetReg(ah, AR_RC_BB); 83614779705SSam Leffler } 83714779705SSam Leffler 83814779705SSam Leffler /* 83914779705SSam Leffler * Places all of hardware into reset 84014779705SSam Leffler */ 84114779705SSam Leffler HAL_BOOL 84214779705SSam Leffler ar5212Disable(struct ath_hal *ah) 84314779705SSam Leffler { 84414779705SSam Leffler if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 84514779705SSam Leffler return AH_FALSE; 84614779705SSam Leffler /* 84714779705SSam Leffler * Reset the HW - PCI must be reset after the rest of the 84814779705SSam Leffler * device has been reset. 84914779705SSam Leffler */ 85014779705SSam Leffler return ar5212SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI); 85114779705SSam Leffler } 85214779705SSam Leffler 85314779705SSam Leffler /* 85414779705SSam Leffler * Places the hardware into reset and then pulls it out of reset 85514779705SSam Leffler * 85614779705SSam Leffler * TODO: Only write the PLL if we're changing to or from CCK mode 85714779705SSam Leffler * 85814779705SSam Leffler * WARNING: The order of the PLL and mode registers must be correct. 85914779705SSam Leffler */ 86014779705SSam Leffler HAL_BOOL 86159efa8b5SSam Leffler ar5212ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan) 86214779705SSam Leffler { 86314779705SSam Leffler 86459efa8b5SSam Leffler OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->ic_freq : 0); 86514779705SSam Leffler 86614779705SSam Leffler /* 86714779705SSam Leffler * Reset the HW - PCI must be reset after the rest of the 86814779705SSam Leffler * device has been reset 86914779705SSam Leffler */ 87014779705SSam Leffler if (!ar5212SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI)) 87114779705SSam Leffler return AH_FALSE; 87214779705SSam Leffler 87314779705SSam Leffler /* Bring out of sleep mode (AGAIN) */ 87414779705SSam Leffler if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 87514779705SSam Leffler return AH_FALSE; 87614779705SSam Leffler 87714779705SSam Leffler /* Clear warm reset register */ 87814779705SSam Leffler if (!ar5212SetResetReg(ah, 0)) 87914779705SSam Leffler return AH_FALSE; 88014779705SSam Leffler 88114779705SSam Leffler /* 88214779705SSam Leffler * Perform warm reset before the mode/PLL/turbo registers 88314779705SSam Leffler * are changed in order to deactivate the radio. Mode changes 88414779705SSam Leffler * with an active radio can result in corrupted shifts to the 88514779705SSam Leffler * radio device. 88614779705SSam Leffler */ 88714779705SSam Leffler 88814779705SSam Leffler /* 88914779705SSam Leffler * Set CCK and Turbo modes correctly. 89014779705SSam Leffler */ 89114779705SSam Leffler if (chan != AH_NULL) { /* NB: can be null during attach */ 89214779705SSam Leffler uint32_t rfMode, phyPLL = 0, curPhyPLL, turbo; 89314779705SSam Leffler 89414779705SSam Leffler if (IS_5413(ah)) { /* NB: =>'s 5424 also */ 89514779705SSam Leffler rfMode = AR_PHY_MODE_AR5112; 89659efa8b5SSam Leffler if (IEEE80211_IS_CHAN_HALF(chan)) 89714779705SSam Leffler rfMode |= AR_PHY_MODE_HALF; 89859efa8b5SSam Leffler else if (IEEE80211_IS_CHAN_QUARTER(chan)) 89914779705SSam Leffler rfMode |= AR_PHY_MODE_QUARTER; 90014779705SSam Leffler 90159efa8b5SSam Leffler if (IEEE80211_IS_CHAN_CCK(chan)) 90214779705SSam Leffler phyPLL = AR_PHY_PLL_CTL_44_5112; 90314779705SSam Leffler else 90414779705SSam Leffler phyPLL = AR_PHY_PLL_CTL_40_5413; 90514779705SSam Leffler } else if (IS_RAD5111(ah)) { 90614779705SSam Leffler rfMode = AR_PHY_MODE_AR5111; 90759efa8b5SSam Leffler if (IEEE80211_IS_CHAN_CCK(chan)) 90814779705SSam Leffler phyPLL = AR_PHY_PLL_CTL_44; 90914779705SSam Leffler else 91014779705SSam Leffler phyPLL = AR_PHY_PLL_CTL_40; 91159efa8b5SSam Leffler if (IEEE80211_IS_CHAN_HALF(chan)) 91214779705SSam Leffler phyPLL = AR_PHY_PLL_CTL_HALF; 91359efa8b5SSam Leffler else if (IEEE80211_IS_CHAN_QUARTER(chan)) 91414779705SSam Leffler phyPLL = AR_PHY_PLL_CTL_QUARTER; 91514779705SSam Leffler } else { /* 5112, 2413, 2316, 2317 */ 91614779705SSam Leffler rfMode = AR_PHY_MODE_AR5112; 91759efa8b5SSam Leffler if (IEEE80211_IS_CHAN_CCK(chan)) 91814779705SSam Leffler phyPLL = AR_PHY_PLL_CTL_44_5112; 91914779705SSam Leffler else 92014779705SSam Leffler phyPLL = AR_PHY_PLL_CTL_40_5112; 92159efa8b5SSam Leffler if (IEEE80211_IS_CHAN_HALF(chan)) 92214779705SSam Leffler phyPLL |= AR_PHY_PLL_CTL_HALF; 92359efa8b5SSam Leffler else if (IEEE80211_IS_CHAN_QUARTER(chan)) 92414779705SSam Leffler phyPLL |= AR_PHY_PLL_CTL_QUARTER; 92514779705SSam Leffler } 92659efa8b5SSam Leffler if (IEEE80211_IS_CHAN_G(chan)) 92714779705SSam Leffler rfMode |= AR_PHY_MODE_DYNAMIC; 92859efa8b5SSam Leffler else if (IEEE80211_IS_CHAN_OFDM(chan)) 92914779705SSam Leffler rfMode |= AR_PHY_MODE_OFDM; 93014779705SSam Leffler else 93114779705SSam Leffler rfMode |= AR_PHY_MODE_CCK; 93259efa8b5SSam Leffler if (IEEE80211_IS_CHAN_5GHZ(chan)) 93314779705SSam Leffler rfMode |= AR_PHY_MODE_RF5GHZ; 93414779705SSam Leffler else 93514779705SSam Leffler rfMode |= AR_PHY_MODE_RF2GHZ; 93659efa8b5SSam Leffler turbo = IEEE80211_IS_CHAN_TURBO(chan) ? 93714779705SSam Leffler (AR_PHY_FC_TURBO_MODE | AR_PHY_FC_TURBO_SHORT) : 0; 93814779705SSam Leffler curPhyPLL = OS_REG_READ(ah, AR_PHY_PLL_CTL); 93914779705SSam Leffler /* 94014779705SSam Leffler * PLL, Mode, and Turbo values must be written in the correct 94114779705SSam Leffler * order to ensure: 94214779705SSam Leffler * - The PLL cannot be set to 44 unless the CCK or DYNAMIC 94314779705SSam Leffler * mode bit is set 94414779705SSam Leffler * - Turbo cannot be set at the same time as CCK or DYNAMIC 94514779705SSam Leffler */ 94659efa8b5SSam Leffler if (IEEE80211_IS_CHAN_CCK(chan)) { 94714779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_TURBO, turbo); 94814779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_MODE, rfMode); 94914779705SSam Leffler if (curPhyPLL != phyPLL) { 95014779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_PLL_CTL, phyPLL); 95114779705SSam Leffler /* Wait for the PLL to settle */ 95214779705SSam Leffler OS_DELAY(PLL_SETTLE_DELAY); 95314779705SSam Leffler } 95414779705SSam Leffler } else { 95514779705SSam Leffler if (curPhyPLL != phyPLL) { 95614779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_PLL_CTL, phyPLL); 95714779705SSam Leffler /* Wait for the PLL to settle */ 95814779705SSam Leffler OS_DELAY(PLL_SETTLE_DELAY); 95914779705SSam Leffler } 96014779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_TURBO, turbo); 96114779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_MODE, rfMode); 96214779705SSam Leffler } 96314779705SSam Leffler } 96414779705SSam Leffler return AH_TRUE; 96514779705SSam Leffler } 96614779705SSam Leffler 96714779705SSam Leffler /* 96814779705SSam Leffler * Recalibrate the lower PHY chips to account for temperature/environment 96914779705SSam Leffler * changes. 97014779705SSam Leffler */ 97114779705SSam Leffler HAL_BOOL 97259efa8b5SSam Leffler ar5212PerCalibrationN(struct ath_hal *ah, 97359efa8b5SSam Leffler struct ieee80211_channel *chan, 97459efa8b5SSam Leffler u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone) 97514779705SSam Leffler { 97614779705SSam Leffler #define IQ_CAL_TRIES 10 97714779705SSam Leffler struct ath_hal_5212 *ahp = AH5212(ah); 97814779705SSam Leffler HAL_CHANNEL_INTERNAL *ichan; 97914779705SSam Leffler int32_t qCoff, qCoffDenom; 98014779705SSam Leffler int32_t iqCorrMeas, iCoff, iCoffDenom; 98114779705SSam Leffler uint32_t powerMeasQ, powerMeasI; 98255a2313aSSam Leffler HAL_BOOL isBmode = AH_FALSE; 98314779705SSam Leffler 98459efa8b5SSam Leffler OS_MARK(ah, AH_MARK_PERCAL, chan->ic_freq); 98514779705SSam Leffler *isCalDone = AH_FALSE; 98614779705SSam Leffler ichan = ath_hal_checkchannel(ah, chan); 98714779705SSam Leffler if (ichan == AH_NULL) { 98814779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, 98914779705SSam Leffler "%s: invalid channel %u/0x%x; no mapping\n", 99059efa8b5SSam Leffler __func__, chan->ic_freq, chan->ic_flags); 99114779705SSam Leffler return AH_FALSE; 99214779705SSam Leffler } 99314779705SSam Leffler SAVE_CCK(ah, chan, isBmode); 99414779705SSam Leffler 99514779705SSam Leffler if (ahp->ah_bIQCalibration == IQ_CAL_DONE || 99614779705SSam Leffler ahp->ah_bIQCalibration == IQ_CAL_INACTIVE) 99714779705SSam Leffler *isCalDone = AH_TRUE; 99814779705SSam Leffler 99914779705SSam Leffler /* IQ calibration in progress. Check to see if it has finished. */ 100014779705SSam Leffler if (ahp->ah_bIQCalibration == IQ_CAL_RUNNING && 100114779705SSam Leffler !(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_IQCAL)) { 100214779705SSam Leffler int i; 100314779705SSam Leffler 100414779705SSam Leffler /* IQ Calibration has finished. */ 100514779705SSam Leffler ahp->ah_bIQCalibration = IQ_CAL_INACTIVE; 100614779705SSam Leffler *isCalDone = AH_TRUE; 100714779705SSam Leffler 100814779705SSam Leffler /* workaround for misgated IQ Cal results */ 100914779705SSam Leffler i = 0; 101014779705SSam Leffler do { 101114779705SSam Leffler /* Read calibration results. */ 101214779705SSam Leffler powerMeasI = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_I); 101314779705SSam Leffler powerMeasQ = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_Q); 101414779705SSam Leffler iqCorrMeas = OS_REG_READ(ah, AR_PHY_IQCAL_RES_IQ_CORR_MEAS); 101514779705SSam Leffler if (powerMeasI && powerMeasQ) 101614779705SSam Leffler break; 101714779705SSam Leffler /* Do we really need this??? */ 10185c5b75f9SSam Leffler OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 101914779705SSam Leffler AR_PHY_TIMING_CTRL4_DO_IQCAL); 102014779705SSam Leffler } while (++i < IQ_CAL_TRIES); 102114779705SSam Leffler 10225b1e30afSSam Leffler HALDEBUG(ah, HAL_DEBUG_PERCAL, 10235b1e30afSSam Leffler "%s: IQ cal finished: %d tries\n", __func__, i); 10245b1e30afSSam Leffler HALDEBUG(ah, HAL_DEBUG_PERCAL, 10255b1e30afSSam Leffler "%s: powerMeasI %u powerMeasQ %u iqCorrMeas %d\n", 10265b1e30afSSam Leffler __func__, powerMeasI, powerMeasQ, iqCorrMeas); 10275b1e30afSSam Leffler 102814779705SSam Leffler /* 102914779705SSam Leffler * Prescale these values to remove 64-bit operation 103014779705SSam Leffler * requirement at the loss of a little precision. 103114779705SSam Leffler */ 103214779705SSam Leffler iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128; 103314779705SSam Leffler qCoffDenom = powerMeasQ / 128; 103414779705SSam Leffler 103514779705SSam Leffler /* Protect against divide-by-0 and loss of sign bits. */ 103614779705SSam Leffler if (iCoffDenom != 0 && qCoffDenom >= 2) { 103714779705SSam Leffler iCoff = (int8_t)(-iqCorrMeas) / iCoffDenom; 103814779705SSam Leffler /* IQCORR_Q_I_COFF is a signed 6 bit number */ 103914779705SSam Leffler if (iCoff < -32) { 104014779705SSam Leffler iCoff = -32; 104114779705SSam Leffler } else if (iCoff > 31) { 104214779705SSam Leffler iCoff = 31; 104314779705SSam Leffler } 104414779705SSam Leffler 104514779705SSam Leffler /* IQCORR_Q_Q_COFF is a signed 5 bit number */ 104614779705SSam Leffler qCoff = (powerMeasI / qCoffDenom) - 128; 104714779705SSam Leffler if (qCoff < -16) { 104814779705SSam Leffler qCoff = -16; 104914779705SSam Leffler } else if (qCoff > 15) { 105014779705SSam Leffler qCoff = 15; 105114779705SSam Leffler } 105214779705SSam Leffler 105314779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_PERCAL, 10545b1e30afSSam Leffler "%s: iCoff %d qCoff %d\n", __func__, iCoff, qCoff); 105514779705SSam Leffler 105614779705SSam Leffler /* Write values and enable correction */ 105714779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 105814779705SSam Leffler AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, iCoff); 105914779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 106014779705SSam Leffler AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, qCoff); 106114779705SSam Leffler OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 106214779705SSam Leffler AR_PHY_TIMING_CTRL4_IQCORR_ENABLE); 106314779705SSam Leffler 106414779705SSam Leffler ahp->ah_bIQCalibration = IQ_CAL_DONE; 106559efa8b5SSam Leffler ichan->privFlags |= CHANNEL_IQVALID; 106614779705SSam Leffler ichan->iCoff = iCoff; 106714779705SSam Leffler ichan->qCoff = qCoff; 106814779705SSam Leffler } 10693b00bfe1SSam Leffler } else if (!IEEE80211_IS_CHAN_B(chan) && 10703b00bfe1SSam Leffler ahp->ah_bIQCalibration == IQ_CAL_DONE && 107159efa8b5SSam Leffler (ichan->privFlags & CHANNEL_IQVALID) == 0) { 107214779705SSam Leffler /* 107314779705SSam Leffler * Start IQ calibration if configured channel has changed. 107414779705SSam Leffler * Use a magic number of 15 based on default value. 107514779705SSam Leffler */ 107614779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 107714779705SSam Leffler AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, 107814779705SSam Leffler INIT_IQCAL_LOG_COUNT_MAX); 107914779705SSam Leffler OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 108014779705SSam Leffler AR_PHY_TIMING_CTRL4_DO_IQCAL); 108114779705SSam Leffler ahp->ah_bIQCalibration = IQ_CAL_RUNNING; 108214779705SSam Leffler } 108314779705SSam Leffler /* XXX EAR */ 108414779705SSam Leffler 108514779705SSam Leffler if (longCal) { 108614779705SSam Leffler /* Check noise floor results */ 108759efa8b5SSam Leffler ar5212GetNf(ah, chan); 108859efa8b5SSam Leffler if (!IEEE80211_IS_CHAN_CWINT(chan)) { 108914779705SSam Leffler /* Perform cal for 5Ghz channels and any OFDM on 5112 */ 109059efa8b5SSam Leffler if (IEEE80211_IS_CHAN_5GHZ(chan) || 109159efa8b5SSam Leffler (IS_RAD5112(ah) && IEEE80211_IS_CHAN_OFDM(chan))) 109214779705SSam Leffler ar5212RequestRfgain(ah); 109314779705SSam Leffler } 109414779705SSam Leffler } 109514779705SSam Leffler RESTORE_CCK(ah, chan, isBmode); 109614779705SSam Leffler 109714779705SSam Leffler return AH_TRUE; 109814779705SSam Leffler #undef IQ_CAL_TRIES 109914779705SSam Leffler } 110014779705SSam Leffler 110114779705SSam Leffler HAL_BOOL 110259efa8b5SSam Leffler ar5212PerCalibration(struct ath_hal *ah, struct ieee80211_channel *chan, 110359efa8b5SSam Leffler HAL_BOOL *isIQdone) 110414779705SSam Leffler { 110514779705SSam Leffler return ar5212PerCalibrationN(ah, chan, 0x1, AH_TRUE, isIQdone); 110614779705SSam Leffler } 110714779705SSam Leffler 110814779705SSam Leffler HAL_BOOL 110959efa8b5SSam Leffler ar5212ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *chan) 111014779705SSam Leffler { 11114d5c4f2aSSam Leffler HAL_CHANNEL_INTERNAL *ichan; 11124d5c4f2aSSam Leffler 11134d5c4f2aSSam Leffler ichan = ath_hal_checkchannel(ah, chan); 11144d5c4f2aSSam Leffler if (ichan == AH_NULL) { 11154d5c4f2aSSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, 11164d5c4f2aSSam Leffler "%s: invalid channel %u/0x%x; no mapping\n", 11174d5c4f2aSSam Leffler __func__, chan->ic_freq, chan->ic_flags); 11184d5c4f2aSSam Leffler return AH_FALSE; 11194d5c4f2aSSam Leffler } 11204d5c4f2aSSam Leffler ichan->privFlags &= ~CHANNEL_IQVALID; 112114779705SSam Leffler return AH_TRUE; 112214779705SSam Leffler } 112314779705SSam Leffler 11240cbbe870SAdrian Chadd /************************************************************** 11250cbbe870SAdrian Chadd * ar5212MacStop 11260cbbe870SAdrian Chadd * 11270cbbe870SAdrian Chadd * Disables all active QCUs and ensure that the mac is in a 11280cbbe870SAdrian Chadd * quiessence state. 11290cbbe870SAdrian Chadd */ 11300cbbe870SAdrian Chadd static HAL_BOOL 11310cbbe870SAdrian Chadd ar5212MacStop(struct ath_hal *ah) 11320cbbe870SAdrian Chadd { 11330cbbe870SAdrian Chadd HAL_BOOL status; 11340cbbe870SAdrian Chadd uint32_t count; 11350cbbe870SAdrian Chadd uint32_t pendFrameCount; 11360cbbe870SAdrian Chadd uint32_t macStateFlag; 11370cbbe870SAdrian Chadd uint32_t queue; 11380cbbe870SAdrian Chadd 11390cbbe870SAdrian Chadd status = AH_FALSE; 11400cbbe870SAdrian Chadd 11410cbbe870SAdrian Chadd /* Disable Rx Operation ***********************************/ 11420cbbe870SAdrian Chadd OS_REG_SET_BIT(ah, AR_CR, AR_CR_RXD); 11430cbbe870SAdrian Chadd 11440cbbe870SAdrian Chadd /* Disable TX Operation ***********************************/ 11450cbbe870SAdrian Chadd #ifdef NOT_YET 11460cbbe870SAdrian Chadd ar5212SetTxdpInvalid(ah); 11470cbbe870SAdrian Chadd #endif 11480cbbe870SAdrian Chadd OS_REG_SET_BIT(ah, AR_Q_TXD, AR_Q_TXD_M); 11490cbbe870SAdrian Chadd 11500cbbe870SAdrian Chadd /* Polling operation for completion of disable ************/ 11510cbbe870SAdrian Chadd macStateFlag = TX_ENABLE_CHECK | RX_ENABLE_CHECK; 11520cbbe870SAdrian Chadd 11530cbbe870SAdrian Chadd for (count = 0; count < MAX_RESET_WAIT; count++) { 11540cbbe870SAdrian Chadd if (macStateFlag & RX_ENABLE_CHECK) { 11550cbbe870SAdrian Chadd if (!OS_REG_IS_BIT_SET(ah, AR_CR, AR_CR_RXE)) { 11560cbbe870SAdrian Chadd macStateFlag &= ~RX_ENABLE_CHECK; 11570cbbe870SAdrian Chadd } 11580cbbe870SAdrian Chadd } 11590cbbe870SAdrian Chadd 11600cbbe870SAdrian Chadd if (macStateFlag & TX_ENABLE_CHECK) { 11610cbbe870SAdrian Chadd if (!OS_REG_IS_BIT_SET(ah, AR_Q_TXE, AR_Q_TXE_M)) { 11620cbbe870SAdrian Chadd macStateFlag &= ~TX_ENABLE_CHECK; 11630cbbe870SAdrian Chadd macStateFlag |= TX_QUEUEPEND_CHECK; 11640cbbe870SAdrian Chadd } 11650cbbe870SAdrian Chadd } 11660cbbe870SAdrian Chadd if (macStateFlag & TX_QUEUEPEND_CHECK) { 11670cbbe870SAdrian Chadd pendFrameCount = 0; 11680cbbe870SAdrian Chadd for (queue = 0; queue < AR_NUM_DCU; queue++) { 11690cbbe870SAdrian Chadd pendFrameCount += OS_REG_READ(ah, 11700cbbe870SAdrian Chadd AR_Q0_STS + (queue * 4)) & 11710cbbe870SAdrian Chadd AR_Q_STS_PEND_FR_CNT; 11720cbbe870SAdrian Chadd } 11730cbbe870SAdrian Chadd if (pendFrameCount == 0) { 11740cbbe870SAdrian Chadd macStateFlag &= ~TX_QUEUEPEND_CHECK; 11750cbbe870SAdrian Chadd } 11760cbbe870SAdrian Chadd } 11770cbbe870SAdrian Chadd if (macStateFlag == 0) { 11780cbbe870SAdrian Chadd status = AH_TRUE; 11790cbbe870SAdrian Chadd break; 11800cbbe870SAdrian Chadd } 11810cbbe870SAdrian Chadd OS_DELAY(50); 11820cbbe870SAdrian Chadd } 11830cbbe870SAdrian Chadd 11840cbbe870SAdrian Chadd if (status != AH_TRUE) { 11850cbbe870SAdrian Chadd HALDEBUG(ah, HAL_DEBUG_RESET, 11860cbbe870SAdrian Chadd "%s:Failed to stop the MAC state 0x%x\n", 11870cbbe870SAdrian Chadd __func__, macStateFlag); 11880cbbe870SAdrian Chadd } 11890cbbe870SAdrian Chadd 11900cbbe870SAdrian Chadd return status; 11910cbbe870SAdrian Chadd } 11920cbbe870SAdrian Chadd 11930cbbe870SAdrian Chadd 119414779705SSam Leffler /* 119514779705SSam Leffler * Write the given reset bit mask into the reset register 119614779705SSam Leffler */ 119714779705SSam Leffler static HAL_BOOL 119814779705SSam Leffler ar5212SetResetReg(struct ath_hal *ah, uint32_t resetMask) 119914779705SSam Leffler { 120014779705SSam Leffler uint32_t mask = resetMask ? resetMask : ~0; 120114779705SSam Leffler HAL_BOOL rt; 120214779705SSam Leffler 12030cbbe870SAdrian Chadd /* Never reset the PCIE core */ 120444834ea4SSam Leffler if (AH_PRIVATE(ah)->ah_ispcie) { 120514779705SSam Leffler resetMask &= ~AR_RC_PCI; 120614779705SSam Leffler } 120714779705SSam Leffler 12080cbbe870SAdrian Chadd if (resetMask & (AR_RC_MAC | AR_RC_PCI)) { 12090cbbe870SAdrian Chadd /* 12100cbbe870SAdrian Chadd * To ensure that the driver can reset the 12110cbbe870SAdrian Chadd * MAC, wake up the chip 12120cbbe870SAdrian Chadd */ 12130cbbe870SAdrian Chadd rt = ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE); 12140cbbe870SAdrian Chadd 12150cbbe870SAdrian Chadd if (rt != AH_TRUE) { 12160cbbe870SAdrian Chadd return rt; 12170cbbe870SAdrian Chadd } 12180cbbe870SAdrian Chadd 12190cbbe870SAdrian Chadd /* 12200cbbe870SAdrian Chadd * Disable interrupts 12210cbbe870SAdrian Chadd */ 12220cbbe870SAdrian Chadd OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE); 12230cbbe870SAdrian Chadd OS_REG_READ(ah, AR_IER); 12240cbbe870SAdrian Chadd 12250cbbe870SAdrian Chadd if (ar5212MacStop(ah) != AH_TRUE) { 12260cbbe870SAdrian Chadd /* 12270cbbe870SAdrian Chadd * Failed to stop the MAC gracefully; let's be more forceful then 12280cbbe870SAdrian Chadd */ 12290cbbe870SAdrian Chadd 12300cbbe870SAdrian Chadd /* need some delay before flush any pending MMR writes */ 12310cbbe870SAdrian Chadd OS_DELAY(15); 12320cbbe870SAdrian Chadd OS_REG_READ(ah, AR_RXDP); 12330cbbe870SAdrian Chadd 12340cbbe870SAdrian Chadd resetMask |= AR_RC_MAC | AR_RC_BB; 12350cbbe870SAdrian Chadd /* _Never_ reset PCI Express core */ 12360cbbe870SAdrian Chadd if (! AH_PRIVATE(ah)->ah_ispcie) { 12370cbbe870SAdrian Chadd resetMask |= AR_RC_PCI; 12380cbbe870SAdrian Chadd } 12390cbbe870SAdrian Chadd #if 0 12400cbbe870SAdrian Chadd /* 12410cbbe870SAdrian Chadd * Flush the park address of the PCI controller 12420cbbe870SAdrian Chadd */ 12430cbbe870SAdrian Chadd /* Read PCI slot information less than Hainan revision */ 12440cbbe870SAdrian Chadd if (AH_PRIVATE(ah)->ah_bustype == HAL_BUS_TYPE_PCI) { 12450cbbe870SAdrian Chadd if (!IS_5112_REV5_UP(ah)) { 12460cbbe870SAdrian Chadd #define PCI_COMMON_CONFIG_STATUS 0x06 12470cbbe870SAdrian Chadd u_int32_t i; 12480cbbe870SAdrian Chadd u_int16_t reg16; 12490cbbe870SAdrian Chadd 12500cbbe870SAdrian Chadd for (i = 0; i < 32; i++) { 12510cbbe870SAdrian Chadd ath_hal_read_pci_config_space(ah, 12520cbbe870SAdrian Chadd PCI_COMMON_CONFIG_STATUS, 12530cbbe870SAdrian Chadd ®16, sizeof(reg16)); 12540cbbe870SAdrian Chadd } 12550cbbe870SAdrian Chadd } 12560cbbe870SAdrian Chadd #undef PCI_COMMON_CONFIG_STATUS 12570cbbe870SAdrian Chadd } 12580cbbe870SAdrian Chadd #endif 12590cbbe870SAdrian Chadd } else { 12600cbbe870SAdrian Chadd /* 12610cbbe870SAdrian Chadd * MAC stopped gracefully; no need to warm-reset the PCI bus 12620cbbe870SAdrian Chadd */ 12630cbbe870SAdrian Chadd 12640cbbe870SAdrian Chadd resetMask &= ~AR_RC_PCI; 12650cbbe870SAdrian Chadd 12660cbbe870SAdrian Chadd /* need some delay before flush any pending MMR writes */ 12670cbbe870SAdrian Chadd OS_DELAY(15); 12680cbbe870SAdrian Chadd OS_REG_READ(ah, AR_RXDP); 12690cbbe870SAdrian Chadd } 12700cbbe870SAdrian Chadd } 12710cbbe870SAdrian Chadd 127214779705SSam Leffler (void) OS_REG_READ(ah, AR_RXDP);/* flush any pending MMR writes */ 127314779705SSam Leffler OS_REG_WRITE(ah, AR_RC, resetMask); 127414779705SSam Leffler OS_DELAY(15); /* need to wait at least 128 clocks 127514779705SSam Leffler when reseting PCI before read */ 127614779705SSam Leffler mask &= (AR_RC_MAC | AR_RC_BB); 127714779705SSam Leffler resetMask &= (AR_RC_MAC | AR_RC_BB); 127814779705SSam Leffler rt = ath_hal_wait(ah, AR_RC, mask, resetMask); 127914779705SSam Leffler if ((resetMask & AR_RC_MAC) == 0) { 128014779705SSam Leffler if (isBigEndian()) { 128114779705SSam Leffler /* 1282a47f39daSAdrian Chadd * Set CFG, little-endian for descriptor accesses. 128314779705SSam Leffler */ 1284a47f39daSAdrian Chadd mask = INIT_CONFIG_STATUS | AR_CFG_SWRD; 128514779705SSam Leffler #ifndef AH_NEED_DESC_SWAP 128614779705SSam Leffler mask |= AR_CFG_SWTD; 128714779705SSam Leffler #endif 1288a47f39daSAdrian Chadd OS_REG_WRITE(ah, AR_CFG, mask); 128914779705SSam Leffler } else 129014779705SSam Leffler OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS); 129114779705SSam Leffler if (ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 129214779705SSam Leffler (void) OS_REG_READ(ah, AR_ISR_RAC); 129314779705SSam Leffler } 129414779705SSam Leffler 129514779705SSam Leffler /* track PHY power state so we don't try to r/w BB registers */ 129614779705SSam Leffler AH5212(ah)->ah_phyPowerOn = ((resetMask & AR_RC_BB) == 0); 129714779705SSam Leffler return rt; 129814779705SSam Leffler } 129914779705SSam Leffler 130014779705SSam Leffler int16_t 130114779705SSam Leffler ar5212GetNoiseFloor(struct ath_hal *ah) 130214779705SSam Leffler { 130314779705SSam Leffler int16_t nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff; 130414779705SSam Leffler if (nf & 0x100) 130514779705SSam Leffler nf = 0 - ((nf ^ 0x1ff) + 1); 130614779705SSam Leffler return nf; 130714779705SSam Leffler } 130814779705SSam Leffler 130914779705SSam Leffler static HAL_BOOL 131059efa8b5SSam Leffler getNoiseFloorThresh(struct ath_hal *ah, const struct ieee80211_channel *chan, 131114779705SSam Leffler int16_t *nft) 131214779705SSam Leffler { 131314779705SSam Leffler const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 131414779705SSam Leffler 131514779705SSam Leffler HALASSERT(ah->ah_magic == AR5212_MAGIC); 131614779705SSam Leffler 131759efa8b5SSam Leffler switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) { 131859efa8b5SSam Leffler case IEEE80211_CHAN_A: 131914779705SSam Leffler *nft = ee->ee_noiseFloorThresh[headerInfo11A]; 132014779705SSam Leffler break; 132159efa8b5SSam Leffler case IEEE80211_CHAN_B: 132214779705SSam Leffler *nft = ee->ee_noiseFloorThresh[headerInfo11B]; 132314779705SSam Leffler break; 132459efa8b5SSam Leffler case IEEE80211_CHAN_G: 132559efa8b5SSam Leffler case IEEE80211_CHAN_PUREG: /* NB: really 108G */ 132614779705SSam Leffler *nft = ee->ee_noiseFloorThresh[headerInfo11G]; 132714779705SSam Leffler break; 132814779705SSam Leffler default: 132959efa8b5SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, 133059efa8b5SSam Leffler "%s: invalid channel flags %u/0x%x\n", 133159efa8b5SSam Leffler __func__, chan->ic_freq, chan->ic_flags); 133214779705SSam Leffler return AH_FALSE; 133314779705SSam Leffler } 133414779705SSam Leffler return AH_TRUE; 133514779705SSam Leffler } 133614779705SSam Leffler 133714779705SSam Leffler /* 133814779705SSam Leffler * Setup the noise floor cal history buffer. 133914779705SSam Leffler */ 134014779705SSam Leffler void 134114779705SSam Leffler ar5212InitNfCalHistBuffer(struct ath_hal *ah) 134214779705SSam Leffler { 134314779705SSam Leffler struct ath_hal_5212 *ahp = AH5212(ah); 134414779705SSam Leffler int i; 134514779705SSam Leffler 134614779705SSam Leffler ahp->ah_nfCalHist.first_run = 1; 134714779705SSam Leffler ahp->ah_nfCalHist.currIndex = 0; 134814779705SSam Leffler ahp->ah_nfCalHist.privNF = AR5212_CCA_MAX_GOOD_VALUE; 134914779705SSam Leffler ahp->ah_nfCalHist.invalidNFcount = AR512_NF_CAL_HIST_MAX; 135014779705SSam Leffler for (i = 0; i < AR512_NF_CAL_HIST_MAX; i ++) 135114779705SSam Leffler ahp->ah_nfCalHist.nfCalBuffer[i] = AR5212_CCA_MAX_GOOD_VALUE; 135214779705SSam Leffler } 135314779705SSam Leffler 135414779705SSam Leffler /* 135514779705SSam Leffler * Add a noise floor value to the ring buffer. 135614779705SSam Leffler */ 135714779705SSam Leffler static __inline void 135814779705SSam Leffler updateNFHistBuff(struct ar5212NfCalHist *h, int16_t nf) 135914779705SSam Leffler { 136014779705SSam Leffler h->nfCalBuffer[h->currIndex] = nf; 136114779705SSam Leffler if (++h->currIndex >= AR512_NF_CAL_HIST_MAX) 136214779705SSam Leffler h->currIndex = 0; 136314779705SSam Leffler } 136414779705SSam Leffler 136514779705SSam Leffler /* 136614779705SSam Leffler * Return the median noise floor value in the ring buffer. 136714779705SSam Leffler */ 136814779705SSam Leffler int16_t 136914779705SSam Leffler ar5212GetNfHistMid(const int16_t calData[AR512_NF_CAL_HIST_MAX]) 137014779705SSam Leffler { 137114779705SSam Leffler int16_t sort[AR512_NF_CAL_HIST_MAX]; 137214779705SSam Leffler int i, j; 137314779705SSam Leffler 137414779705SSam Leffler OS_MEMCPY(sort, calData, AR512_NF_CAL_HIST_MAX*sizeof(int16_t)); 137514779705SSam Leffler for (i = 0; i < AR512_NF_CAL_HIST_MAX-1; i ++) { 137614779705SSam Leffler for (j = 1; j < AR512_NF_CAL_HIST_MAX-i; j ++) { 137714779705SSam Leffler if (sort[j] > sort[j-1]) { 137814779705SSam Leffler int16_t nf = sort[j]; 137914779705SSam Leffler sort[j] = sort[j-1]; 138014779705SSam Leffler sort[j-1] = nf; 138114779705SSam Leffler } 138214779705SSam Leffler } 138314779705SSam Leffler } 138414779705SSam Leffler return sort[(AR512_NF_CAL_HIST_MAX-1)>>1]; 138514779705SSam Leffler } 138614779705SSam Leffler 138714779705SSam Leffler /* 1388f6b6084bSPedro F. Giffuni * Read the NF and check it against the noise floor threshold 138914779705SSam Leffler */ 139014779705SSam Leffler int16_t 139159efa8b5SSam Leffler ar5212GetNf(struct ath_hal *ah, struct ieee80211_channel *chan) 139214779705SSam Leffler { 139314779705SSam Leffler struct ath_hal_5212 *ahp = AH5212(ah); 139414779705SSam Leffler struct ar5212NfCalHist *h = &ahp->ah_nfCalHist; 139559efa8b5SSam Leffler HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 139614779705SSam Leffler int16_t nf, nfThresh; 139714779705SSam Leffler int32_t val; 139814779705SSam Leffler 139914779705SSam Leffler if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { 140014779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, 140114779705SSam Leffler "%s: NF did not complete in calibration window\n", __func__); 140259efa8b5SSam Leffler ichan->rawNoiseFloor = h->privNF; /* most recent value */ 140359efa8b5SSam Leffler return ichan->rawNoiseFloor; 140414779705SSam Leffler } 140514779705SSam Leffler 140614779705SSam Leffler /* 140714779705SSam Leffler * Finished NF cal, check against threshold. 140814779705SSam Leffler */ 140914779705SSam Leffler nf = ar5212GetNoiseFloor(ah); 141014779705SSam Leffler if (getNoiseFloorThresh(ah, chan, &nfThresh)) { 141114779705SSam Leffler if (nf > nfThresh) { 141214779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, 141314779705SSam Leffler "%s: noise floor failed detected; detected %u, " 141414779705SSam Leffler "threshold %u\n", __func__, nf, nfThresh); 141514779705SSam Leffler /* 141614779705SSam Leffler * NB: Don't discriminate 2.4 vs 5Ghz, if this 141714779705SSam Leffler * happens it indicates a problem regardless 141814779705SSam Leffler * of the band. 141914779705SSam Leffler */ 142059efa8b5SSam Leffler chan->ic_state |= IEEE80211_CHANSTATE_CWINT; 142114779705SSam Leffler nf = 0; 142214779705SSam Leffler } 142314779705SSam Leffler } else 142414779705SSam Leffler nf = 0; 142514779705SSam Leffler 142614779705SSam Leffler /* 142714779705SSam Leffler * Pass through histogram and write median value as 142814779705SSam Leffler * calculated from the accrued window. We require a 142914779705SSam Leffler * full window of in-range values to be seen before we 143014779705SSam Leffler * start using the history. 143114779705SSam Leffler */ 143214779705SSam Leffler updateNFHistBuff(h, nf); 143314779705SSam Leffler if (h->first_run) { 143414779705SSam Leffler if (nf < AR5212_CCA_MIN_BAD_VALUE || 143514779705SSam Leffler nf > AR5212_CCA_MAX_HIGH_VALUE) { 143614779705SSam Leffler nf = AR5212_CCA_MAX_GOOD_VALUE; 143714779705SSam Leffler h->invalidNFcount = AR512_NF_CAL_HIST_MAX; 143814779705SSam Leffler } else if (--(h->invalidNFcount) == 0) { 143914779705SSam Leffler h->first_run = 0; 144014779705SSam Leffler h->privNF = nf = ar5212GetNfHistMid(h->nfCalBuffer); 144114779705SSam Leffler } else { 144214779705SSam Leffler nf = AR5212_CCA_MAX_GOOD_VALUE; 144314779705SSam Leffler } 144414779705SSam Leffler } else { 144514779705SSam Leffler h->privNF = nf = ar5212GetNfHistMid(h->nfCalBuffer); 144614779705SSam Leffler } 144714779705SSam Leffler 144814779705SSam Leffler val = OS_REG_READ(ah, AR_PHY(25)); 144914779705SSam Leffler val &= 0xFFFFFE00; 145014779705SSam Leffler val |= (((uint32_t)nf << 1) & 0x1FF); 145114779705SSam Leffler OS_REG_WRITE(ah, AR_PHY(25), val); 145214779705SSam Leffler OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); 145314779705SSam Leffler OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); 145414779705SSam Leffler OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 145514779705SSam Leffler 145614779705SSam Leffler if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF, 0)) { 145714779705SSam Leffler #ifdef AH_DEBUG 145814779705SSam Leffler ath_hal_printf(ah, "%s: AGC not ready AGC_CONTROL 0x%x\n", 145914779705SSam Leffler __func__, OS_REG_READ(ah, AR_PHY_AGC_CONTROL)); 146014779705SSam Leffler #endif 146114779705SSam Leffler } 146214779705SSam Leffler 146314779705SSam Leffler /* 146414779705SSam Leffler * Now load a high maxCCAPower value again so that we're 146514779705SSam Leffler * not capped by the median we just loaded 146614779705SSam Leffler */ 146714779705SSam Leffler val &= 0xFFFFFE00; 146814779705SSam Leffler val |= (((uint32_t)(-50) << 1) & 0x1FF); 146914779705SSam Leffler OS_REG_WRITE(ah, AR_PHY(25), val); 147014779705SSam Leffler OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); 147114779705SSam Leffler OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); 147214779705SSam Leffler OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 147314779705SSam Leffler 147459efa8b5SSam Leffler return (ichan->rawNoiseFloor = nf); 147514779705SSam Leffler } 147614779705SSam Leffler 147714779705SSam Leffler /* 147814779705SSam Leffler * Set up compression configuration registers 147914779705SSam Leffler */ 148014779705SSam Leffler void 148114779705SSam Leffler ar5212SetCompRegs(struct ath_hal *ah) 148214779705SSam Leffler { 148314779705SSam Leffler struct ath_hal_5212 *ahp = AH5212(ah); 148414779705SSam Leffler int i; 148514779705SSam Leffler 148614779705SSam Leffler /* Check if h/w supports compression */ 148714779705SSam Leffler if (!AH_PRIVATE(ah)->ah_caps.halCompressSupport) 148814779705SSam Leffler return; 148914779705SSam Leffler 149014779705SSam Leffler OS_REG_WRITE(ah, AR_DCCFG, 1); 149114779705SSam Leffler 149214779705SSam Leffler OS_REG_WRITE(ah, AR_CCFG, 149314779705SSam Leffler (AR_COMPRESSION_WINDOW_SIZE >> 8) & AR_CCFG_WIN_M); 149414779705SSam Leffler 149514779705SSam Leffler OS_REG_WRITE(ah, AR_CCFG, 149614779705SSam Leffler OS_REG_READ(ah, AR_CCFG) | AR_CCFG_MIB_INT_EN); 149714779705SSam Leffler OS_REG_WRITE(ah, AR_CCUCFG, 149814779705SSam Leffler AR_CCUCFG_RESET_VAL | AR_CCUCFG_CATCHUP_EN); 149914779705SSam Leffler 150014779705SSam Leffler OS_REG_WRITE(ah, AR_CPCOVF, 0); 150114779705SSam Leffler 150214779705SSam Leffler /* reset decompression mask */ 150314779705SSam Leffler for (i = 0; i < HAL_DECOMP_MASK_SIZE; i++) { 150414779705SSam Leffler OS_REG_WRITE(ah, AR_DCM_A, i); 150514779705SSam Leffler OS_REG_WRITE(ah, AR_DCM_D, ahp->ah_decompMask[i]); 150614779705SSam Leffler } 150714779705SSam Leffler } 150814779705SSam Leffler 150914779705SSam Leffler HAL_BOOL 151014779705SSam Leffler ar5212SetAntennaSwitchInternal(struct ath_hal *ah, HAL_ANT_SETTING settings, 151159efa8b5SSam Leffler const struct ieee80211_channel *chan) 151214779705SSam Leffler { 151314779705SSam Leffler #define ANT_SWITCH_TABLE1 AR_PHY(88) 151414779705SSam Leffler #define ANT_SWITCH_TABLE2 AR_PHY(89) 151514779705SSam Leffler struct ath_hal_5212 *ahp = AH5212(ah); 151614779705SSam Leffler const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 151714779705SSam Leffler uint32_t antSwitchA, antSwitchB; 151814779705SSam Leffler int ix; 151914779705SSam Leffler 152014779705SSam Leffler HALASSERT(ah->ah_magic == AR5212_MAGIC); 152114779705SSam Leffler HALASSERT(ahp->ah_phyPowerOn); 152214779705SSam Leffler 152359efa8b5SSam Leffler switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) { 152459efa8b5SSam Leffler case IEEE80211_CHAN_A: 152559efa8b5SSam Leffler ix = 0; 152659efa8b5SSam Leffler break; 152759efa8b5SSam Leffler case IEEE80211_CHAN_G: 152859efa8b5SSam Leffler case IEEE80211_CHAN_PUREG: /* NB: 108G */ 152959efa8b5SSam Leffler ix = 2; 153059efa8b5SSam Leffler break; 153159efa8b5SSam Leffler case IEEE80211_CHAN_B: 153259efa8b5SSam Leffler if (IS_2425(ah) || IS_2417(ah)) { 153359efa8b5SSam Leffler /* NB: Nala/Swan: 11b is handled using 11g */ 153459efa8b5SSam Leffler ix = 2; 153559efa8b5SSam Leffler } else 153659efa8b5SSam Leffler ix = 1; 153759efa8b5SSam Leffler break; 153814779705SSam Leffler default: 153914779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n", 154059efa8b5SSam Leffler __func__, chan->ic_flags); 154114779705SSam Leffler return AH_FALSE; 154214779705SSam Leffler } 154314779705SSam Leffler 154414779705SSam Leffler antSwitchA = ee->ee_antennaControl[1][ix] 154514779705SSam Leffler | (ee->ee_antennaControl[2][ix] << 6) 154614779705SSam Leffler | (ee->ee_antennaControl[3][ix] << 12) 154714779705SSam Leffler | (ee->ee_antennaControl[4][ix] << 18) 154814779705SSam Leffler | (ee->ee_antennaControl[5][ix] << 24) 154914779705SSam Leffler ; 155014779705SSam Leffler antSwitchB = ee->ee_antennaControl[6][ix] 155114779705SSam Leffler | (ee->ee_antennaControl[7][ix] << 6) 155214779705SSam Leffler | (ee->ee_antennaControl[8][ix] << 12) 155314779705SSam Leffler | (ee->ee_antennaControl[9][ix] << 18) 155414779705SSam Leffler | (ee->ee_antennaControl[10][ix] << 24) 155514779705SSam Leffler ; 155614779705SSam Leffler /* 155714779705SSam Leffler * For fixed antenna, give the same setting for both switch banks 155814779705SSam Leffler */ 155914779705SSam Leffler switch (settings) { 156014779705SSam Leffler case HAL_ANT_FIXED_A: 156114779705SSam Leffler antSwitchB = antSwitchA; 156214779705SSam Leffler break; 156314779705SSam Leffler case HAL_ANT_FIXED_B: 156414779705SSam Leffler antSwitchA = antSwitchB; 156514779705SSam Leffler break; 156614779705SSam Leffler case HAL_ANT_VARIABLE: 156714779705SSam Leffler break; 156814779705SSam Leffler default: 156914779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad antenna setting %u\n", 157014779705SSam Leffler __func__, settings); 157114779705SSam Leffler return AH_FALSE; 157214779705SSam Leffler } 157314779705SSam Leffler if (antSwitchB == antSwitchA) { 157414779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_RFPARAM, 157514779705SSam Leffler "%s: Setting fast diversity off.\n", __func__); 157614779705SSam Leffler OS_REG_CLR_BIT(ah,AR_PHY_CCK_DETECT, 157714779705SSam Leffler AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 157814779705SSam Leffler ahp->ah_diversity = AH_FALSE; 157914779705SSam Leffler } else { 158014779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_RFPARAM, 158114779705SSam Leffler "%s: Setting fast diversity on.\n", __func__); 158214779705SSam Leffler OS_REG_SET_BIT(ah,AR_PHY_CCK_DETECT, 158314779705SSam Leffler AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 158414779705SSam Leffler ahp->ah_diversity = AH_TRUE; 158514779705SSam Leffler } 158614779705SSam Leffler ahp->ah_antControl = settings; 158714779705SSam Leffler 158814779705SSam Leffler OS_REG_WRITE(ah, ANT_SWITCH_TABLE1, antSwitchA); 158914779705SSam Leffler OS_REG_WRITE(ah, ANT_SWITCH_TABLE2, antSwitchB); 159014779705SSam Leffler 159114779705SSam Leffler return AH_TRUE; 159214779705SSam Leffler #undef ANT_SWITCH_TABLE2 159314779705SSam Leffler #undef ANT_SWITCH_TABLE1 159414779705SSam Leffler } 159514779705SSam Leffler 159614779705SSam Leffler HAL_BOOL 159759efa8b5SSam Leffler ar5212IsSpurChannel(struct ath_hal *ah, const struct ieee80211_channel *chan) 159814779705SSam Leffler { 159959efa8b5SSam Leffler uint16_t freq = ath_hal_gethwchannel(ah, chan); 160014779705SSam Leffler uint32_t clockFreq = 160114779705SSam Leffler ((IS_5413(ah) || IS_RAD5112_ANY(ah) || IS_2417(ah)) ? 40 : 32); 160259efa8b5SSam Leffler return ( ((freq % clockFreq) != 0) 160359efa8b5SSam Leffler && (((freq % clockFreq) < 10) 160459efa8b5SSam Leffler || (((freq) % clockFreq) > 22)) ); 160514779705SSam Leffler } 160614779705SSam Leffler 160714779705SSam Leffler /* 160814779705SSam Leffler * Read EEPROM header info and program the device for correct operation 160914779705SSam Leffler * given the channel value. 161014779705SSam Leffler */ 161114779705SSam Leffler HAL_BOOL 161259efa8b5SSam Leffler ar5212SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan) 161314779705SSam Leffler { 161414779705SSam Leffler #define NO_FALSE_DETECT_BACKOFF 2 161514779705SSam Leffler #define CB22_FALSE_DETECT_BACKOFF 6 161614779705SSam Leffler #define AR_PHY_BIS(_ah, _reg, _mask, _val) \ 161714779705SSam Leffler OS_REG_WRITE(_ah, AR_PHY(_reg), \ 161814779705SSam Leffler (OS_REG_READ(_ah, AR_PHY(_reg)) & _mask) | (_val)); 161914779705SSam Leffler struct ath_hal_5212 *ahp = AH5212(ah); 162014779705SSam Leffler const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 162114779705SSam Leffler int arrayMode, falseDectectBackoff; 162259efa8b5SSam Leffler int is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 162359efa8b5SSam Leffler HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 162414779705SSam Leffler int8_t adcDesiredSize, pgaDesiredSize; 162514779705SSam Leffler uint16_t switchSettling, txrxAtten, rxtxMargin; 162614779705SSam Leffler int iCoff, qCoff; 162714779705SSam Leffler 162814779705SSam Leffler HALASSERT(ah->ah_magic == AR5212_MAGIC); 162914779705SSam Leffler 163059efa8b5SSam Leffler switch (chan->ic_flags & IEEE80211_CHAN_ALLTURBOFULL) { 163159efa8b5SSam Leffler case IEEE80211_CHAN_A: 163259efa8b5SSam Leffler case IEEE80211_CHAN_ST: 163314779705SSam Leffler arrayMode = headerInfo11A; 163414779705SSam Leffler if (!IS_RAD5112_ANY(ah) && !IS_2413(ah) && !IS_5413(ah)) 163514779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, 163614779705SSam Leffler AR_PHY_FRAME_CTL_TX_CLIP, 163714779705SSam Leffler ahp->ah_gainValues.currStep->paramVal[GP_TXCLIP]); 163814779705SSam Leffler break; 163959efa8b5SSam Leffler case IEEE80211_CHAN_B: 164014779705SSam Leffler arrayMode = headerInfo11B; 164114779705SSam Leffler break; 164259efa8b5SSam Leffler case IEEE80211_CHAN_G: 164359efa8b5SSam Leffler case IEEE80211_CHAN_108G: 164414779705SSam Leffler arrayMode = headerInfo11G; 164514779705SSam Leffler break; 164614779705SSam Leffler default: 164714779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n", 164859efa8b5SSam Leffler __func__, chan->ic_flags); 164914779705SSam Leffler return AH_FALSE; 165014779705SSam Leffler } 165114779705SSam Leffler 165214779705SSam Leffler /* Set the antenna register(s) correctly for the chip revision */ 165314779705SSam Leffler AR_PHY_BIS(ah, 68, 0xFFFFFC06, 165414779705SSam Leffler (ee->ee_antennaControl[0][arrayMode] << 4) | 0x1); 165514779705SSam Leffler 165614779705SSam Leffler ar5212SetAntennaSwitchInternal(ah, ahp->ah_antControl, chan); 165714779705SSam Leffler 165814779705SSam Leffler /* Set the Noise Floor Thresh on ar5211 devices */ 165914779705SSam Leffler OS_REG_WRITE(ah, AR_PHY(90), 166014779705SSam Leffler (ee->ee_noiseFloorThresh[arrayMode] & 0x1FF) 166114779705SSam Leffler | (1 << 9)); 166214779705SSam Leffler 166359efa8b5SSam Leffler if (ee->ee_version >= AR_EEPROM_VER5_0 && IEEE80211_IS_CHAN_TURBO(chan)) { 166414779705SSam Leffler switchSettling = ee->ee_switchSettlingTurbo[is2GHz]; 166514779705SSam Leffler adcDesiredSize = ee->ee_adcDesiredSizeTurbo[is2GHz]; 166614779705SSam Leffler pgaDesiredSize = ee->ee_pgaDesiredSizeTurbo[is2GHz]; 166714779705SSam Leffler txrxAtten = ee->ee_txrxAttenTurbo[is2GHz]; 166814779705SSam Leffler rxtxMargin = ee->ee_rxtxMarginTurbo[is2GHz]; 166914779705SSam Leffler } else { 167014779705SSam Leffler switchSettling = ee->ee_switchSettling[arrayMode]; 167114779705SSam Leffler adcDesiredSize = ee->ee_adcDesiredSize[arrayMode]; 167214779705SSam Leffler pgaDesiredSize = ee->ee_pgaDesiredSize[is2GHz]; 167314779705SSam Leffler txrxAtten = ee->ee_txrxAtten[is2GHz]; 167414779705SSam Leffler rxtxMargin = ee->ee_rxtxMargin[is2GHz]; 167514779705SSam Leffler } 167614779705SSam Leffler 167714779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, 167814779705SSam Leffler AR_PHY_SETTLING_SWITCH, switchSettling); 167914779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, 168014779705SSam Leffler AR_PHY_DESIRED_SZ_ADC, adcDesiredSize); 168114779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, 168214779705SSam Leffler AR_PHY_DESIRED_SZ_PGA, pgaDesiredSize); 168314779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 168414779705SSam Leffler AR_PHY_RXGAIN_TXRX_ATTEN, txrxAtten); 168514779705SSam Leffler OS_REG_WRITE(ah, AR_PHY(13), 168614779705SSam Leffler (ee->ee_txEndToXPAOff[arrayMode] << 24) 168714779705SSam Leffler | (ee->ee_txEndToXPAOff[arrayMode] << 16) 168814779705SSam Leffler | (ee->ee_txFrameToXPAOn[arrayMode] << 8) 168914779705SSam Leffler | ee->ee_txFrameToXPAOn[arrayMode]); 169014779705SSam Leffler AR_PHY_BIS(ah, 10, 0xFFFF00FF, 169114779705SSam Leffler ee->ee_txEndToXLNAOn[arrayMode] << 8); 169214779705SSam Leffler AR_PHY_BIS(ah, 25, 0xFFF80FFF, 169314779705SSam Leffler (ee->ee_thresh62[arrayMode] << 12) & 0x7F000); 169414779705SSam Leffler 169514779705SSam Leffler /* 169614779705SSam Leffler * False detect backoff - suspected 32 MHz spur causes false 169714779705SSam Leffler * detects in OFDM, causing Tx Hangs. Decrease weak signal 169814779705SSam Leffler * sensitivity for this card. 169914779705SSam Leffler */ 170014779705SSam Leffler falseDectectBackoff = NO_FALSE_DETECT_BACKOFF; 170114779705SSam Leffler if (ee->ee_version < AR_EEPROM_VER3_3) { 170214779705SSam Leffler /* XXX magic number */ 170314779705SSam Leffler if (AH_PRIVATE(ah)->ah_subvendorid == 0x1022 && 170459efa8b5SSam Leffler IEEE80211_IS_CHAN_OFDM(chan)) 170514779705SSam Leffler falseDectectBackoff += CB22_FALSE_DETECT_BACKOFF; 170614779705SSam Leffler } else { 170759efa8b5SSam Leffler if (ar5212IsSpurChannel(ah, chan)) 170814779705SSam Leffler falseDectectBackoff += ee->ee_falseDetectBackoff[arrayMode]; 170914779705SSam Leffler } 171014779705SSam Leffler AR_PHY_BIS(ah, 73, 0xFFFFFF01, (falseDectectBackoff << 1) & 0xFE); 171114779705SSam Leffler 171259efa8b5SSam Leffler if (ichan->privFlags & CHANNEL_IQVALID) { 171359efa8b5SSam Leffler iCoff = ichan->iCoff; 171459efa8b5SSam Leffler qCoff = ichan->qCoff; 171514779705SSam Leffler } else { 171614779705SSam Leffler iCoff = ee->ee_iqCalI[is2GHz]; 171714779705SSam Leffler qCoff = ee->ee_iqCalQ[is2GHz]; 171814779705SSam Leffler } 171914779705SSam Leffler 172014779705SSam Leffler /* write previous IQ results */ 172114779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 172214779705SSam Leffler AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, iCoff); 172314779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 172414779705SSam Leffler AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, qCoff); 172514779705SSam Leffler OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 172614779705SSam Leffler AR_PHY_TIMING_CTRL4_IQCORR_ENABLE); 172714779705SSam Leffler 172814779705SSam Leffler if (ee->ee_version >= AR_EEPROM_VER4_1) { 172959efa8b5SSam Leffler if (!IEEE80211_IS_CHAN_108G(chan) || ee->ee_version >= AR_EEPROM_VER5_0) 173014779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 173114779705SSam Leffler AR_PHY_GAIN_2GHZ_RXTX_MARGIN, rxtxMargin); 173214779705SSam Leffler } 173314779705SSam Leffler if (ee->ee_version >= AR_EEPROM_VER5_1) { 173414779705SSam Leffler /* for now always disabled */ 173514779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_HEAVY_CLIP_ENABLE, 0); 173614779705SSam Leffler } 173714779705SSam Leffler 173814779705SSam Leffler return AH_TRUE; 173914779705SSam Leffler #undef AR_PHY_BIS 174014779705SSam Leffler #undef NO_FALSE_DETECT_BACKOFF 174114779705SSam Leffler #undef CB22_FALSE_DETECT_BACKOFF 174214779705SSam Leffler } 174314779705SSam Leffler 174414779705SSam Leffler /* 174514779705SSam Leffler * Apply Spur Immunity to Boards that require it. 174614779705SSam Leffler * Applies only to OFDM RX operation. 174714779705SSam Leffler */ 174814779705SSam Leffler 174914779705SSam Leffler void 175059efa8b5SSam Leffler ar5212SetSpurMitigation(struct ath_hal *ah, 175159efa8b5SSam Leffler const struct ieee80211_channel *chan) 175214779705SSam Leffler { 175314779705SSam Leffler uint32_t pilotMask[2] = {0, 0}, binMagMask[4] = {0, 0, 0 , 0}; 175414779705SSam Leffler uint16_t i, finalSpur, curChanAsSpur, binWidth = 0, spurDetectWidth, spurChan; 175514779705SSam Leffler int32_t spurDeltaPhase = 0, spurFreqSd = 0, spurOffset, binOffsetNumT16, curBinOffset; 175614779705SSam Leffler int16_t numBinOffsets; 175714779705SSam Leffler static const uint16_t magMapFor4[4] = {1, 2, 2, 1}; 175814779705SSam Leffler static const uint16_t magMapFor3[3] = {1, 2, 1}; 175914779705SSam Leffler const uint16_t *pMagMap; 176059efa8b5SSam Leffler HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 176159efa8b5SSam Leffler HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 176214779705SSam Leffler uint32_t val; 176314779705SSam Leffler 176414779705SSam Leffler #define CHAN_TO_SPUR(_f, _freq) ( ((_freq) - ((_f) ? 2300 : 4900)) * 10 ) 176514779705SSam Leffler if (IS_2417(ah)) { 176614779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: no spur mitigation\n", 176714779705SSam Leffler __func__); 176814779705SSam Leffler return; 176914779705SSam Leffler } 177014779705SSam Leffler 177114779705SSam Leffler curChanAsSpur = CHAN_TO_SPUR(is2GHz, ichan->channel); 177214779705SSam Leffler 177314779705SSam Leffler if (ichan->mainSpur) { 177414779705SSam Leffler /* Pull out the saved spur value */ 177514779705SSam Leffler finalSpur = ichan->mainSpur; 177614779705SSam Leffler } else { 177714779705SSam Leffler /* 177814779705SSam Leffler * Check if spur immunity should be performed for this channel 177914779705SSam Leffler * Should only be performed once per channel and then saved 178014779705SSam Leffler */ 178114779705SSam Leffler finalSpur = AR_NO_SPUR; 178214779705SSam Leffler spurDetectWidth = HAL_SPUR_CHAN_WIDTH; 178359efa8b5SSam Leffler if (IEEE80211_IS_CHAN_TURBO(chan)) 178414779705SSam Leffler spurDetectWidth *= 2; 178514779705SSam Leffler 178614779705SSam Leffler /* Decide if any spur affects the current channel */ 178714779705SSam Leffler for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 178814779705SSam Leffler spurChan = ath_hal_getSpurChan(ah, i, is2GHz); 178914779705SSam Leffler if (spurChan == AR_NO_SPUR) { 179014779705SSam Leffler break; 179114779705SSam Leffler } 179214779705SSam Leffler if ((curChanAsSpur - spurDetectWidth <= (spurChan & HAL_SPUR_VAL_MASK)) && 179314779705SSam Leffler (curChanAsSpur + spurDetectWidth >= (spurChan & HAL_SPUR_VAL_MASK))) { 179414779705SSam Leffler finalSpur = spurChan & HAL_SPUR_VAL_MASK; 179514779705SSam Leffler break; 179614779705SSam Leffler } 179714779705SSam Leffler } 179814779705SSam Leffler /* Save detected spur (or no spur) for this channel */ 179914779705SSam Leffler ichan->mainSpur = finalSpur; 180014779705SSam Leffler } 180114779705SSam Leffler 180214779705SSam Leffler /* Write spur immunity data */ 180314779705SSam Leffler if (finalSpur == AR_NO_SPUR) { 180414779705SSam Leffler /* Disable Spur Immunity Regs if they appear set */ 180514779705SSam Leffler if (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER) { 180614779705SSam Leffler /* Clear Spur Delta Phase, Spur Freq, and enable bits */ 180714779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_RATE, 0); 180814779705SSam Leffler val = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4); 180914779705SSam Leffler val &= ~(AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 181014779705SSam Leffler AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 181114779705SSam Leffler AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 181214779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_MASK_CTL, val); 181314779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_TIMING11, 0); 181414779705SSam Leffler 181514779705SSam Leffler /* Clear pilot masks */ 181614779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_TIMING7, 0); 181714779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_TIMING8, AR_PHY_TIMING8_PILOT_MASK_2, 0); 181814779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_TIMING9, 0); 181914779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_TIMING10, AR_PHY_TIMING10_PILOT_MASK_2, 0); 182014779705SSam Leffler 182114779705SSam Leffler /* Clear magnitude masks */ 182214779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, 0); 182314779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, 0); 182414779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, 0); 182514779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_MASK_4, 0); 182614779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, 0); 182714779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, 0); 182814779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, 0); 182914779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_BIN_MASK2_4, AR_PHY_BIN_MASK2_4_MASK_4, 0); 183014779705SSam Leffler } 183114779705SSam Leffler } else { 183214779705SSam Leffler spurOffset = finalSpur - curChanAsSpur; 183314779705SSam Leffler /* 183414779705SSam Leffler * Spur calculations: 183514779705SSam Leffler * spurDeltaPhase is (spurOffsetIn100KHz / chipFrequencyIn100KHz) << 21 183614779705SSam Leffler * spurFreqSd is (spurOffsetIn100KHz / sampleFrequencyIn100KHz) << 11 183714779705SSam Leffler */ 183859efa8b5SSam Leffler if (IEEE80211_IS_CHAN_TURBO(chan)) { 183959efa8b5SSam Leffler /* Chip Frequency & sampleFrequency are 80 MHz */ 184014779705SSam Leffler spurDeltaPhase = (spurOffset << 16) / 25; 184114779705SSam Leffler spurFreqSd = spurDeltaPhase >> 10; 184214779705SSam Leffler binWidth = HAL_BIN_WIDTH_TURBO_100HZ; 184359efa8b5SSam Leffler } else if (IEEE80211_IS_CHAN_G(chan)) { 184459efa8b5SSam Leffler /* Chip Frequency is 44MHz, sampleFrequency is 40 MHz */ 184559efa8b5SSam Leffler spurFreqSd = (spurOffset << 8) / 55; 184659efa8b5SSam Leffler spurDeltaPhase = (spurOffset << 17) / 25; 184759efa8b5SSam Leffler binWidth = HAL_BIN_WIDTH_BASE_100HZ; 184859efa8b5SSam Leffler } else { 184959efa8b5SSam Leffler HALASSERT(!IEEE80211_IS_CHAN_B(chan)); 185059efa8b5SSam Leffler /* Chip Frequency & sampleFrequency are 40 MHz */ 185159efa8b5SSam Leffler spurDeltaPhase = (spurOffset << 17) / 25; 185259efa8b5SSam Leffler spurFreqSd = spurDeltaPhase >> 10; 185359efa8b5SSam Leffler binWidth = HAL_BIN_WIDTH_BASE_100HZ; 185414779705SSam Leffler } 185514779705SSam Leffler 185614779705SSam Leffler /* Compute Pilot Mask */ 185714779705SSam Leffler binOffsetNumT16 = ((spurOffset * 1000) << 4) / binWidth; 185814779705SSam Leffler /* The spur is on a bin if it's remainder at times 16 is 0 */ 185914779705SSam Leffler if (binOffsetNumT16 & 0xF) { 186014779705SSam Leffler numBinOffsets = 4; 186114779705SSam Leffler pMagMap = magMapFor4; 186214779705SSam Leffler } else { 186314779705SSam Leffler numBinOffsets = 3; 186414779705SSam Leffler pMagMap = magMapFor3; 186514779705SSam Leffler } 186614779705SSam Leffler for (i = 0; i < numBinOffsets; i++) { 186714779705SSam Leffler if ((binOffsetNumT16 >> 4) > HAL_MAX_BINS_ALLOWED) { 186814779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, 186914779705SSam Leffler "Too man bins in spur mitigation\n"); 187014779705SSam Leffler return; 187114779705SSam Leffler } 187214779705SSam Leffler 187314779705SSam Leffler /* Get Pilot Mask values */ 187414779705SSam Leffler curBinOffset = (binOffsetNumT16 >> 4) + i + 25; 187514779705SSam Leffler if ((curBinOffset >= 0) && (curBinOffset <= 32)) { 187614779705SSam Leffler if (curBinOffset <= 25) 187714779705SSam Leffler pilotMask[0] |= 1 << curBinOffset; 187814779705SSam Leffler else if (curBinOffset >= 27) 187914779705SSam Leffler pilotMask[0] |= 1 << (curBinOffset - 1); 188014779705SSam Leffler } else if ((curBinOffset >= 33) && (curBinOffset <= 52)) 188114779705SSam Leffler pilotMask[1] |= 1 << (curBinOffset - 33); 188214779705SSam Leffler 188314779705SSam Leffler /* Get viterbi values */ 188414779705SSam Leffler if ((curBinOffset >= -1) && (curBinOffset <= 14)) 188514779705SSam Leffler binMagMask[0] |= pMagMap[i] << (curBinOffset + 1) * 2; 188614779705SSam Leffler else if ((curBinOffset >= 15) && (curBinOffset <= 30)) 188714779705SSam Leffler binMagMask[1] |= pMagMap[i] << (curBinOffset - 15) * 2; 188814779705SSam Leffler else if ((curBinOffset >= 31) && (curBinOffset <= 46)) 188914779705SSam Leffler binMagMask[2] |= pMagMap[i] << (curBinOffset -31) * 2; 189014779705SSam Leffler else if((curBinOffset >= 47) && (curBinOffset <= 53)) 189114779705SSam Leffler binMagMask[3] |= pMagMap[i] << (curBinOffset -47) * 2; 189214779705SSam Leffler } 189314779705SSam Leffler 189414779705SSam Leffler /* Write Spur Delta Phase, Spur Freq, and enable bits */ 189514779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_RATE, 0xFF); 189614779705SSam Leffler val = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4); 189714779705SSam Leffler val |= (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 189814779705SSam Leffler AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 189914779705SSam Leffler AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 190014779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, val); 190114779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_TIMING11, AR_PHY_TIMING11_USE_SPUR_IN_AGC | 190214779705SSam Leffler SM(spurFreqSd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 190314779705SSam Leffler SM(spurDeltaPhase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 190414779705SSam Leffler 190514779705SSam Leffler /* Write pilot masks */ 190614779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_TIMING7, pilotMask[0]); 190714779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_TIMING8, AR_PHY_TIMING8_PILOT_MASK_2, pilotMask[1]); 190814779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_TIMING9, pilotMask[0]); 190914779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_TIMING10, AR_PHY_TIMING10_PILOT_MASK_2, pilotMask[1]); 191014779705SSam Leffler 191114779705SSam Leffler /* Write magnitude masks */ 191214779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, binMagMask[0]); 191314779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, binMagMask[1]); 191414779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, binMagMask[2]); 191514779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_MASK_4, binMagMask[3]); 191614779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, binMagMask[0]); 191714779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, binMagMask[1]); 191814779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, binMagMask[2]); 191914779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_BIN_MASK2_4, AR_PHY_BIN_MASK2_4_MASK_4, binMagMask[3]); 192014779705SSam Leffler } 192114779705SSam Leffler #undef CHAN_TO_SPUR 192214779705SSam Leffler } 192314779705SSam Leffler 192414779705SSam Leffler 192514779705SSam Leffler /* 192614779705SSam Leffler * Delta slope coefficient computation. 192714779705SSam Leffler * Required for OFDM operation. 192814779705SSam Leffler */ 192914779705SSam Leffler void 193059efa8b5SSam Leffler ar5212SetDeltaSlope(struct ath_hal *ah, const struct ieee80211_channel *chan) 193114779705SSam Leffler { 193214779705SSam Leffler #define COEF_SCALE_S 24 193314779705SSam Leffler #define INIT_CLOCKMHZSCALED 0x64000000 193459efa8b5SSam Leffler uint16_t freq = ath_hal_gethwchannel(ah, chan); 193514779705SSam Leffler unsigned long coef_scaled, coef_exp, coef_man, ds_coef_exp, ds_coef_man; 193614779705SSam Leffler unsigned long clockMhzScaled = INIT_CLOCKMHZSCALED; 193714779705SSam Leffler 193859efa8b5SSam Leffler if (IEEE80211_IS_CHAN_TURBO(chan)) 193914779705SSam Leffler clockMhzScaled *= 2; 194014779705SSam Leffler /* half and quarter rate can divide the scaled clock by 2 or 4 respectively */ 194114779705SSam Leffler /* scale for selected channel bandwidth */ 194259efa8b5SSam Leffler if (IEEE80211_IS_CHAN_HALF(chan)) { 194314779705SSam Leffler clockMhzScaled = clockMhzScaled >> 1; 194459efa8b5SSam Leffler } else if (IEEE80211_IS_CHAN_QUARTER(chan)) { 194514779705SSam Leffler clockMhzScaled = clockMhzScaled >> 2; 194614779705SSam Leffler } 194714779705SSam Leffler 194814779705SSam Leffler /* 194914779705SSam Leffler * ALGO -> coef = 1e8/fcarrier*fclock/40; 195014779705SSam Leffler * scaled coef to provide precision for this floating calculation 195114779705SSam Leffler */ 195259efa8b5SSam Leffler coef_scaled = clockMhzScaled / freq; 195314779705SSam Leffler 195414779705SSam Leffler /* 195514779705SSam Leffler * ALGO -> coef_exp = 14-floor(log2(coef)); 195614779705SSam Leffler * floor(log2(x)) is the highest set bit position 195714779705SSam Leffler */ 195814779705SSam Leffler for (coef_exp = 31; coef_exp > 0; coef_exp--) 195914779705SSam Leffler if ((coef_scaled >> coef_exp) & 0x1) 196014779705SSam Leffler break; 196114779705SSam Leffler /* A coef_exp of 0 is a legal bit position but an unexpected coef_exp */ 196214779705SSam Leffler HALASSERT(coef_exp); 196314779705SSam Leffler coef_exp = 14 - (coef_exp - COEF_SCALE_S); 196414779705SSam Leffler 196514779705SSam Leffler /* 196614779705SSam Leffler * ALGO -> coef_man = floor(coef* 2^coef_exp+0.5); 196714779705SSam Leffler * The coefficient is already shifted up for scaling 196814779705SSam Leffler */ 196914779705SSam Leffler coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 197014779705SSam Leffler ds_coef_man = coef_man >> (COEF_SCALE_S - coef_exp); 197114779705SSam Leffler ds_coef_exp = coef_exp - 16; 197214779705SSam Leffler 197314779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, 197414779705SSam Leffler AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 197514779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, 197614779705SSam Leffler AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 197714779705SSam Leffler #undef INIT_CLOCKMHZSCALED 197814779705SSam Leffler #undef COEF_SCALE_S 197914779705SSam Leffler } 198014779705SSam Leffler 198114779705SSam Leffler /* 198214779705SSam Leffler * Set a limit on the overall output power. Used for dynamic 198314779705SSam Leffler * transmit power control and the like. 198414779705SSam Leffler * 198514779705SSam Leffler * NB: limit is in units of 0.5 dbM. 198614779705SSam Leffler */ 198714779705SSam Leffler HAL_BOOL 198814779705SSam Leffler ar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit) 198914779705SSam Leffler { 199059efa8b5SSam Leffler /* XXX blech, construct local writable copy */ 199159efa8b5SSam Leffler struct ieee80211_channel dummy = *AH_PRIVATE(ah)->ah_curchan; 199214779705SSam Leffler uint16_t dummyXpdGains[2]; 199359efa8b5SSam Leffler HAL_BOOL isBmode; 199414779705SSam Leffler 199559efa8b5SSam Leffler SAVE_CCK(ah, &dummy, isBmode); 199614779705SSam Leffler AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER); 199759efa8b5SSam Leffler return ar5212SetTransmitPower(ah, &dummy, dummyXpdGains); 199814779705SSam Leffler } 199914779705SSam Leffler 200014779705SSam Leffler /* 200114779705SSam Leffler * Set the transmit power in the baseband for the given 200214779705SSam Leffler * operating channel and mode. 200314779705SSam Leffler */ 200414779705SSam Leffler HAL_BOOL 200559efa8b5SSam Leffler ar5212SetTransmitPower(struct ath_hal *ah, 200659efa8b5SSam Leffler const struct ieee80211_channel *chan, uint16_t *rfXpdGain) 200714779705SSam Leffler { 200814779705SSam Leffler #define POW_OFDM(_r, _s) (((0 & 1)<< ((_s)+6)) | (((_r) & 0x3f) << (_s))) 200914779705SSam Leffler #define POW_CCK(_r, _s) (((_r) & 0x3f) << (_s)) 201014779705SSam Leffler #define N(a) (sizeof (a) / sizeof (a[0])) 201114779705SSam Leffler static const uint16_t tpcScaleReductionTable[5] = 201214779705SSam Leffler { 0, 3, 6, 9, MAX_RATE_POWER }; 201314779705SSam Leffler struct ath_hal_5212 *ahp = AH5212(ah); 201459efa8b5SSam Leffler uint16_t freq = ath_hal_gethwchannel(ah, chan); 201514779705SSam Leffler const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 201614779705SSam Leffler int16_t minPower, maxPower, tpcInDb, powerLimit; 201714779705SSam Leffler int i; 201814779705SSam Leffler 201914779705SSam Leffler HALASSERT(ah->ah_magic == AR5212_MAGIC); 202014779705SSam Leffler 202114779705SSam Leffler OS_MEMZERO(ahp->ah_pcdacTable, ahp->ah_pcdacTableSize); 202214779705SSam Leffler OS_MEMZERO(ahp->ah_ratesArray, sizeof(ahp->ah_ratesArray)); 202314779705SSam Leffler 202414779705SSam Leffler powerLimit = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 202514779705SSam Leffler if (powerLimit >= MAX_RATE_POWER || powerLimit == 0) 202614779705SSam Leffler tpcInDb = tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale]; 202714779705SSam Leffler else 202814779705SSam Leffler tpcInDb = 0; 202959efa8b5SSam Leffler if (!ar5212SetRateTable(ah, chan, tpcInDb, powerLimit, 203014779705SSam Leffler AH_TRUE, &minPower, &maxPower)) { 203114779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set rate table\n", 203214779705SSam Leffler __func__); 203314779705SSam Leffler return AH_FALSE; 203414779705SSam Leffler } 203514779705SSam Leffler if (!ahp->ah_rfHal->setPowerTable(ah, 203614779705SSam Leffler &minPower, &maxPower, chan, rfXpdGain)) { 203714779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n", 203814779705SSam Leffler __func__); 203914779705SSam Leffler return AH_FALSE; 204014779705SSam Leffler } 204114779705SSam Leffler 204214779705SSam Leffler /* 204314779705SSam Leffler * Adjust XR power/rate up by 2 dB to account for greater peak 204414779705SSam Leffler * to avg ratio - except in newer avg power designs 204514779705SSam Leffler */ 204614779705SSam Leffler if (!IS_2413(ah) && !IS_5413(ah)) 204714779705SSam Leffler ahp->ah_ratesArray[15] += 4; 204814779705SSam Leffler /* 204914779705SSam Leffler * txPowerIndexOffset is set by the SetPowerTable() call - 205014779705SSam Leffler * adjust the rate table 205114779705SSam Leffler */ 205214779705SSam Leffler for (i = 0; i < N(ahp->ah_ratesArray); i++) { 205314779705SSam Leffler ahp->ah_ratesArray[i] += ahp->ah_txPowerIndexOffset; 205414779705SSam Leffler if (ahp->ah_ratesArray[i] > 63) 205514779705SSam Leffler ahp->ah_ratesArray[i] = 63; 205614779705SSam Leffler } 205714779705SSam Leffler 205814779705SSam Leffler if (ee->ee_eepMap < 2) { 205914779705SSam Leffler /* 206014779705SSam Leffler * Correct gain deltas for 5212 G operation - 206114779705SSam Leffler * Removed with revised chipset 206214779705SSam Leffler */ 206314779705SSam Leffler if (AH_PRIVATE(ah)->ah_phyRev < AR_PHY_CHIP_ID_REV_2 && 206459efa8b5SSam Leffler IEEE80211_IS_CHAN_G(chan)) { 206514779705SSam Leffler uint16_t cckOfdmPwrDelta; 206614779705SSam Leffler 206759efa8b5SSam Leffler if (freq == 2484) 206814779705SSam Leffler cckOfdmPwrDelta = SCALE_OC_DELTA( 206914779705SSam Leffler ee->ee_cckOfdmPwrDelta - 207014779705SSam Leffler ee->ee_scaledCh14FilterCckDelta); 207114779705SSam Leffler else 207214779705SSam Leffler cckOfdmPwrDelta = SCALE_OC_DELTA( 207314779705SSam Leffler ee->ee_cckOfdmPwrDelta); 207414779705SSam Leffler ar5212CorrectGainDelta(ah, cckOfdmPwrDelta); 207514779705SSam Leffler } 207614779705SSam Leffler /* 207714779705SSam Leffler * Finally, write the power values into the 207814779705SSam Leffler * baseband power table 207914779705SSam Leffler */ 208014779705SSam Leffler for (i = 0; i < (PWR_TABLE_SIZE/2); i++) { 208114779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_PCDAC_TX_POWER(i), 208214779705SSam Leffler ((((ahp->ah_pcdacTable[2*i + 1] << 8) | 0xff) & 0xffff) << 16) 208314779705SSam Leffler | (((ahp->ah_pcdacTable[2*i] << 8) | 0xff) & 0xffff) 208414779705SSam Leffler ); 208514779705SSam Leffler } 208614779705SSam Leffler } 208714779705SSam Leffler 208814779705SSam Leffler /* Write the OFDM power per rate set */ 208914779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 209014779705SSam Leffler POW_OFDM(ahp->ah_ratesArray[3], 24) 209114779705SSam Leffler | POW_OFDM(ahp->ah_ratesArray[2], 16) 209214779705SSam Leffler | POW_OFDM(ahp->ah_ratesArray[1], 8) 209314779705SSam Leffler | POW_OFDM(ahp->ah_ratesArray[0], 0) 209414779705SSam Leffler ); 209514779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, 209614779705SSam Leffler POW_OFDM(ahp->ah_ratesArray[7], 24) 209714779705SSam Leffler | POW_OFDM(ahp->ah_ratesArray[6], 16) 209814779705SSam Leffler | POW_OFDM(ahp->ah_ratesArray[5], 8) 209914779705SSam Leffler | POW_OFDM(ahp->ah_ratesArray[4], 0) 210014779705SSam Leffler ); 210114779705SSam Leffler 210214779705SSam Leffler /* Write the CCK power per rate set */ 210314779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, 210414779705SSam Leffler POW_CCK(ahp->ah_ratesArray[10], 24) 210514779705SSam Leffler | POW_CCK(ahp->ah_ratesArray[9], 16) 210614779705SSam Leffler | POW_CCK(ahp->ah_ratesArray[15], 8) /* XR target power */ 210714779705SSam Leffler | POW_CCK(ahp->ah_ratesArray[8], 0) 210814779705SSam Leffler ); 210914779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, 211014779705SSam Leffler POW_CCK(ahp->ah_ratesArray[14], 24) 211114779705SSam Leffler | POW_CCK(ahp->ah_ratesArray[13], 16) 211214779705SSam Leffler | POW_CCK(ahp->ah_ratesArray[12], 8) 211314779705SSam Leffler | POW_CCK(ahp->ah_ratesArray[11], 0) 211414779705SSam Leffler ); 211514779705SSam Leffler 211614779705SSam Leffler /* 211714779705SSam Leffler * Set max power to 30 dBm and, optionally, 211814779705SSam Leffler * enable TPC in tx descriptors. 211914779705SSam Leffler */ 212014779705SSam Leffler OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, MAX_RATE_POWER | 212114779705SSam Leffler (ahp->ah_tpcEnabled ? AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE : 0)); 212214779705SSam Leffler 212314779705SSam Leffler return AH_TRUE; 212414779705SSam Leffler #undef N 212514779705SSam Leffler #undef POW_CCK 212614779705SSam Leffler #undef POW_OFDM 212714779705SSam Leffler } 212814779705SSam Leffler 212914779705SSam Leffler /* 213014779705SSam Leffler * Sets the transmit power in the baseband for the given 213114779705SSam Leffler * operating channel and mode. 213214779705SSam Leffler */ 213314779705SSam Leffler static HAL_BOOL 213459efa8b5SSam Leffler ar5212SetRateTable(struct ath_hal *ah, const struct ieee80211_channel *chan, 213514779705SSam Leffler int16_t tpcScaleReduction, int16_t powerLimit, HAL_BOOL commit, 213614779705SSam Leffler int16_t *pMinPower, int16_t *pMaxPower) 213714779705SSam Leffler { 213814779705SSam Leffler struct ath_hal_5212 *ahp = AH5212(ah); 213959efa8b5SSam Leffler uint16_t freq = ath_hal_gethwchannel(ah, chan); 214014779705SSam Leffler const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 214114779705SSam Leffler uint16_t *rpow = ahp->ah_ratesArray; 214214779705SSam Leffler uint16_t twiceMaxEdgePower = MAX_RATE_POWER; 214314779705SSam Leffler uint16_t twiceMaxEdgePowerCck = MAX_RATE_POWER; 214414779705SSam Leffler uint16_t twiceMaxRDPower = MAX_RATE_POWER; 214514779705SSam Leffler int i; 214614779705SSam Leffler uint8_t cfgCtl; 214714779705SSam Leffler int8_t twiceAntennaGain, twiceAntennaReduction; 214814779705SSam Leffler const RD_EDGES_POWER *rep; 214914779705SSam Leffler TRGT_POWER_INFO targetPowerOfdm, targetPowerCck; 215014779705SSam Leffler int16_t scaledPower, maxAvailPower = 0; 215114779705SSam Leffler int16_t r13, r9, r7, r0; 215214779705SSam Leffler 215314779705SSam Leffler HALASSERT(ah->ah_magic == AR5212_MAGIC); 215414779705SSam Leffler 215559efa8b5SSam Leffler twiceMaxRDPower = chan->ic_maxregpower * 2; 215614779705SSam Leffler *pMaxPower = -MAX_RATE_POWER; 215714779705SSam Leffler *pMinPower = MAX_RATE_POWER; 215814779705SSam Leffler 215914779705SSam Leffler /* Get conformance test limit maximum for this channel */ 216014779705SSam Leffler cfgCtl = ath_hal_getctl(ah, chan); 216114779705SSam Leffler for (i = 0; i < ee->ee_numCtls; i++) { 216214779705SSam Leffler uint16_t twiceMinEdgePower; 216314779705SSam Leffler 216414779705SSam Leffler if (ee->ee_ctl[i] == 0) 216514779705SSam Leffler continue; 216614779705SSam Leffler if (ee->ee_ctl[i] == cfgCtl || 216714779705SSam Leffler cfgCtl == ((ee->ee_ctl[i] & CTL_MODE_M) | SD_NO_CTL)) { 216814779705SSam Leffler rep = &ee->ee_rdEdgesPower[i * NUM_EDGES]; 216959efa8b5SSam Leffler twiceMinEdgePower = ar5212GetMaxEdgePower(freq, rep); 217014779705SSam Leffler if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 217114779705SSam Leffler /* Find the minimum of all CTL edge powers that apply to this channel */ 217214779705SSam Leffler twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower); 217314779705SSam Leffler } else { 217414779705SSam Leffler twiceMaxEdgePower = twiceMinEdgePower; 217514779705SSam Leffler break; 217614779705SSam Leffler } 217714779705SSam Leffler } 217814779705SSam Leffler } 217914779705SSam Leffler 218059efa8b5SSam Leffler if (IEEE80211_IS_CHAN_G(chan)) { 218114779705SSam Leffler /* Check for a CCK CTL for 11G CCK powers */ 218214779705SSam Leffler cfgCtl = (cfgCtl & ~CTL_MODE_M) | CTL_11B; 218314779705SSam Leffler for (i = 0; i < ee->ee_numCtls; i++) { 218414779705SSam Leffler uint16_t twiceMinEdgePowerCck; 218514779705SSam Leffler 218614779705SSam Leffler if (ee->ee_ctl[i] == 0) 218714779705SSam Leffler continue; 218814779705SSam Leffler if (ee->ee_ctl[i] == cfgCtl || 218914779705SSam Leffler cfgCtl == ((ee->ee_ctl[i] & CTL_MODE_M) | SD_NO_CTL)) { 219014779705SSam Leffler rep = &ee->ee_rdEdgesPower[i * NUM_EDGES]; 219159efa8b5SSam Leffler twiceMinEdgePowerCck = ar5212GetMaxEdgePower(freq, rep); 219214779705SSam Leffler if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 219314779705SSam Leffler /* Find the minimum of all CTL edge powers that apply to this channel */ 219414779705SSam Leffler twiceMaxEdgePowerCck = AH_MIN(twiceMaxEdgePowerCck, twiceMinEdgePowerCck); 219514779705SSam Leffler } else { 219614779705SSam Leffler twiceMaxEdgePowerCck = twiceMinEdgePowerCck; 219714779705SSam Leffler break; 219814779705SSam Leffler } 219914779705SSam Leffler } 220014779705SSam Leffler } 220114779705SSam Leffler } else { 220214779705SSam Leffler /* Set the 11B cck edge power to the one found before */ 220314779705SSam Leffler twiceMaxEdgePowerCck = twiceMaxEdgePower; 220414779705SSam Leffler } 220514779705SSam Leffler 220614779705SSam Leffler /* Get Antenna Gain reduction */ 220759efa8b5SSam Leffler if (IEEE80211_IS_CHAN_5GHZ(chan)) { 220814779705SSam Leffler ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_5, &twiceAntennaGain); 220914779705SSam Leffler } else { 221014779705SSam Leffler ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_2, &twiceAntennaGain); 221114779705SSam Leffler } 221214779705SSam Leffler twiceAntennaReduction = 221314779705SSam Leffler ath_hal_getantennareduction(ah, chan, twiceAntennaGain); 221414779705SSam Leffler 221559efa8b5SSam Leffler if (IEEE80211_IS_CHAN_OFDM(chan)) { 221614779705SSam Leffler /* Get final OFDM target powers */ 221759efa8b5SSam Leffler if (IEEE80211_IS_CHAN_2GHZ(chan)) { 221814779705SSam Leffler ar5212GetTargetPowers(ah, chan, ee->ee_trgtPwr_11g, 221914779705SSam Leffler ee->ee_numTargetPwr_11g, &targetPowerOfdm); 222014779705SSam Leffler } else { 222114779705SSam Leffler ar5212GetTargetPowers(ah, chan, ee->ee_trgtPwr_11a, 222214779705SSam Leffler ee->ee_numTargetPwr_11a, &targetPowerOfdm); 222314779705SSam Leffler } 222414779705SSam Leffler 222514779705SSam Leffler /* Get Maximum OFDM power */ 222614779705SSam Leffler /* Minimum of target and edge powers */ 222714779705SSam Leffler scaledPower = AH_MIN(twiceMaxEdgePower, 222814779705SSam Leffler twiceMaxRDPower - twiceAntennaReduction); 222914779705SSam Leffler 223014779705SSam Leffler /* 223114779705SSam Leffler * If turbo is set, reduce power to keep power 223214779705SSam Leffler * consumption under 2 Watts. Note that we always do 223314779705SSam Leffler * this unless specially configured. Then we limit 223414779705SSam Leffler * power only for non-AP operation. 223514779705SSam Leffler */ 223659efa8b5SSam Leffler if (IEEE80211_IS_CHAN_TURBO(chan) 223714779705SSam Leffler #ifdef AH_ENABLE_AP_SUPPORT 223814779705SSam Leffler && AH_PRIVATE(ah)->ah_opmode != HAL_M_HOSTAP 223914779705SSam Leffler #endif 224014779705SSam Leffler ) { 224114779705SSam Leffler /* 224214779705SSam Leffler * If turbo is set, reduce power to keep power 224314779705SSam Leffler * consumption under 2 Watts 224414779705SSam Leffler */ 224514779705SSam Leffler if (ee->ee_version >= AR_EEPROM_VER3_1) 224614779705SSam Leffler scaledPower = AH_MIN(scaledPower, 224714779705SSam Leffler ee->ee_turbo2WMaxPower5); 224814779705SSam Leffler /* 224914779705SSam Leffler * EEPROM version 4.0 added an additional 225014779705SSam Leffler * constraint on 2.4GHz channels. 225114779705SSam Leffler */ 225214779705SSam Leffler if (ee->ee_version >= AR_EEPROM_VER4_0 && 225359efa8b5SSam Leffler IEEE80211_IS_CHAN_2GHZ(chan)) 225414779705SSam Leffler scaledPower = AH_MIN(scaledPower, 225514779705SSam Leffler ee->ee_turbo2WMaxPower2); 225614779705SSam Leffler } 225714779705SSam Leffler 225814779705SSam Leffler maxAvailPower = AH_MIN(scaledPower, 225914779705SSam Leffler targetPowerOfdm.twicePwr6_24); 226014779705SSam Leffler 226114779705SSam Leffler /* Reduce power by max regulatory domain allowed restrictions */ 226214779705SSam Leffler scaledPower = maxAvailPower - (tpcScaleReduction * 2); 226314779705SSam Leffler scaledPower = (scaledPower < 0) ? 0 : scaledPower; 226414779705SSam Leffler scaledPower = AH_MIN(scaledPower, powerLimit); 226514779705SSam Leffler 226614779705SSam Leffler if (commit) { 226714779705SSam Leffler /* Set OFDM rates 9, 12, 18, 24 */ 226814779705SSam Leffler r0 = rpow[0] = rpow[1] = rpow[2] = rpow[3] = rpow[4] = scaledPower; 226914779705SSam Leffler 227014779705SSam Leffler /* Set OFDM rates 36, 48, 54, XR */ 227114779705SSam Leffler rpow[5] = AH_MIN(rpow[0], targetPowerOfdm.twicePwr36); 227214779705SSam Leffler rpow[6] = AH_MIN(rpow[0], targetPowerOfdm.twicePwr48); 227314779705SSam Leffler r7 = rpow[7] = AH_MIN(rpow[0], targetPowerOfdm.twicePwr54); 227414779705SSam Leffler 227514779705SSam Leffler if (ee->ee_version >= AR_EEPROM_VER4_0) { 227614779705SSam Leffler /* Setup XR target power from EEPROM */ 227759efa8b5SSam Leffler rpow[15] = AH_MIN(scaledPower, IEEE80211_IS_CHAN_2GHZ(chan) ? 227814779705SSam Leffler ee->ee_xrTargetPower2 : ee->ee_xrTargetPower5); 227914779705SSam Leffler } else { 228014779705SSam Leffler /* XR uses 6mb power */ 228114779705SSam Leffler rpow[15] = rpow[0]; 228214779705SSam Leffler } 228314779705SSam Leffler ahp->ah_ofdmTxPower = *pMaxPower; 228414779705SSam Leffler 228514779705SSam Leffler } else { 228614779705SSam Leffler r0 = scaledPower; 228714779705SSam Leffler r7 = AH_MIN(r0, targetPowerOfdm.twicePwr54); 228814779705SSam Leffler } 228914779705SSam Leffler *pMinPower = r7; 229014779705SSam Leffler *pMaxPower = r0; 229114779705SSam Leffler 229214779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_RFPARAM, 229314779705SSam Leffler "%s: MaxRD: %d TurboMax: %d MaxCTL: %d " 229414779705SSam Leffler "TPC_Reduction %d chan=%d (0x%x) maxAvailPower=%d pwr6_24=%d, maxPower=%d\n", 229514779705SSam Leffler __func__, twiceMaxRDPower, ee->ee_turbo2WMaxPower5, 229614779705SSam Leffler twiceMaxEdgePower, tpcScaleReduction * 2, 229759efa8b5SSam Leffler chan->ic_freq, chan->ic_flags, 229814779705SSam Leffler maxAvailPower, targetPowerOfdm.twicePwr6_24, *pMaxPower); 229914779705SSam Leffler } 230014779705SSam Leffler 230159efa8b5SSam Leffler if (IEEE80211_IS_CHAN_CCK(chan)) { 230214779705SSam Leffler /* Get final CCK target powers */ 230314779705SSam Leffler ar5212GetTargetPowers(ah, chan, ee->ee_trgtPwr_11b, 230414779705SSam Leffler ee->ee_numTargetPwr_11b, &targetPowerCck); 230514779705SSam Leffler 230614779705SSam Leffler /* Reduce power by max regulatory domain allowed restrictions */ 230714779705SSam Leffler scaledPower = AH_MIN(twiceMaxEdgePowerCck, 230814779705SSam Leffler twiceMaxRDPower - twiceAntennaReduction); 230914779705SSam Leffler if (maxAvailPower < AH_MIN(scaledPower, targetPowerCck.twicePwr6_24)) 231014779705SSam Leffler maxAvailPower = AH_MIN(scaledPower, targetPowerCck.twicePwr6_24); 231114779705SSam Leffler 231214779705SSam Leffler /* Reduce power by user selection */ 231314779705SSam Leffler scaledPower = AH_MIN(scaledPower, targetPowerCck.twicePwr6_24) - (tpcScaleReduction * 2); 231414779705SSam Leffler scaledPower = (scaledPower < 0) ? 0 : scaledPower; 231514779705SSam Leffler scaledPower = AH_MIN(scaledPower, powerLimit); 231614779705SSam Leffler 231714779705SSam Leffler if (commit) { 231814779705SSam Leffler /* Set CCK rates 2L, 2S, 5.5L, 5.5S, 11L, 11S */ 231914779705SSam Leffler rpow[8] = AH_MIN(scaledPower, targetPowerCck.twicePwr6_24); 232014779705SSam Leffler r9 = rpow[9] = AH_MIN(scaledPower, targetPowerCck.twicePwr36); 232114779705SSam Leffler rpow[10] = rpow[9]; 232214779705SSam Leffler rpow[11] = AH_MIN(scaledPower, targetPowerCck.twicePwr48); 232314779705SSam Leffler rpow[12] = rpow[11]; 232414779705SSam Leffler r13 = rpow[13] = AH_MIN(scaledPower, targetPowerCck.twicePwr54); 232514779705SSam Leffler rpow[14] = rpow[13]; 232614779705SSam Leffler } else { 232714779705SSam Leffler r9 = AH_MIN(scaledPower, targetPowerCck.twicePwr36); 232814779705SSam Leffler r13 = AH_MIN(scaledPower, targetPowerCck.twicePwr54); 232914779705SSam Leffler } 233014779705SSam Leffler 233114779705SSam Leffler /* Set min/max power based off OFDM values or initialization */ 233214779705SSam Leffler if (r13 < *pMinPower) 233314779705SSam Leffler *pMinPower = r13; 233414779705SSam Leffler if (r9 > *pMaxPower) 233514779705SSam Leffler *pMaxPower = r9; 233614779705SSam Leffler 233714779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_RFPARAM, 233814779705SSam Leffler "%s: cck: MaxRD: %d MaxCTL: %d " 233914779705SSam Leffler "TPC_Reduction %d chan=%d (0x%x) maxAvailPower=%d pwr6_24=%d, maxPower=%d\n", 234014779705SSam Leffler __func__, twiceMaxRDPower, twiceMaxEdgePowerCck, 234159efa8b5SSam Leffler tpcScaleReduction * 2, chan->ic_freq, chan->ic_flags, 234214779705SSam Leffler maxAvailPower, targetPowerCck.twicePwr6_24, *pMaxPower); 234314779705SSam Leffler } 234414779705SSam Leffler if (commit) { 234514779705SSam Leffler ahp->ah_tx6PowerInHalfDbm = *pMaxPower; 234614779705SSam Leffler AH_PRIVATE(ah)->ah_maxPowerLevel = ahp->ah_tx6PowerInHalfDbm; 234714779705SSam Leffler } 234814779705SSam Leffler return AH_TRUE; 234914779705SSam Leffler } 235014779705SSam Leffler 235114779705SSam Leffler HAL_BOOL 235259efa8b5SSam Leffler ar5212GetChipPowerLimits(struct ath_hal *ah, struct ieee80211_channel *chan) 235314779705SSam Leffler { 235414779705SSam Leffler struct ath_hal_5212 *ahp = AH5212(ah); 235559efa8b5SSam Leffler #if 0 235614779705SSam Leffler static const uint16_t tpcScaleReductionTable[5] = 235714779705SSam Leffler { 0, 3, 6, 9, MAX_RATE_POWER }; 235859efa8b5SSam Leffler int16_t tpcInDb, powerLimit; 235959efa8b5SSam Leffler #endif 236059efa8b5SSam Leffler int16_t minPower, maxPower; 236114779705SSam Leffler 236214779705SSam Leffler /* 236314779705SSam Leffler * Get Pier table max and min powers. 236414779705SSam Leffler */ 236514779705SSam Leffler if (ahp->ah_rfHal->getChannelMaxMinPower(ah, chan, &maxPower, &minPower)) { 236614779705SSam Leffler /* NB: rf code returns 1/4 dBm units, convert */ 236759efa8b5SSam Leffler chan->ic_maxpower = maxPower / 2; 236859efa8b5SSam Leffler chan->ic_minpower = minPower / 2; 236914779705SSam Leffler } else { 237014779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, 237114779705SSam Leffler "%s: no min/max power for %u/0x%x\n", 237259efa8b5SSam Leffler __func__, chan->ic_freq, chan->ic_flags); 237359efa8b5SSam Leffler chan->ic_maxpower = MAX_RATE_POWER; 237459efa8b5SSam Leffler chan->ic_minpower = 0; 237514779705SSam Leffler } 237659efa8b5SSam Leffler #if 0 237714779705SSam Leffler /* 237814779705SSam Leffler * Now adjust to reflect any global scale and/or CTL's. 237914779705SSam Leffler * (XXX is that correct?) 238014779705SSam Leffler */ 238114779705SSam Leffler powerLimit = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 238214779705SSam Leffler if (powerLimit >= MAX_RATE_POWER || powerLimit == 0) 238314779705SSam Leffler tpcInDb = tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale]; 238414779705SSam Leffler else 238514779705SSam Leffler tpcInDb = 0; 238659efa8b5SSam Leffler if (!ar5212SetRateTable(ah, chan, tpcInDb, powerLimit, 238714779705SSam Leffler AH_FALSE, &minPower, &maxPower)) { 238814779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_ANY, 238914779705SSam Leffler "%s: unable to find max/min power\n",__func__); 239014779705SSam Leffler return AH_FALSE; 239114779705SSam Leffler } 239259efa8b5SSam Leffler if (maxPower < chan->ic_maxpower) 239359efa8b5SSam Leffler chan->ic_maxpower = maxPower; 239459efa8b5SSam Leffler if (minPower < chan->ic_minpower) 239559efa8b5SSam Leffler chan->ic_minpower = minPower; 239614779705SSam Leffler HALDEBUG(ah, HAL_DEBUG_RESET, 239714779705SSam Leffler "Chan %d: MaxPow = %d MinPow = %d\n", 239859efa8b5SSam Leffler chan->ic_freq, chan->ic_maxpower, chans->ic_minpower); 239914779705SSam Leffler #endif 240014779705SSam Leffler return AH_TRUE; 240114779705SSam Leffler } 240214779705SSam Leffler 240314779705SSam Leffler /* 240414779705SSam Leffler * Correct for the gain-delta between ofdm and cck mode target 240514779705SSam Leffler * powers. Write the results to the rate table and the power table. 240614779705SSam Leffler * 240714779705SSam Leffler * Conventions : 240814779705SSam Leffler * 1. rpow[ii] is the integer value of 2*(desired power 240914779705SSam Leffler * for the rate ii in dBm) to provide 0.5dB resolution. rate 241014779705SSam Leffler * mapping is as following : 241114779705SSam Leffler * [0..7] --> ofdm 6, 9, .. 48, 54 241214779705SSam Leffler * [8..14] --> cck 1L, 2L, 2S, .. 11L, 11S 241314779705SSam Leffler * [15] --> XR (all rates get the same power) 241414779705SSam Leffler * 2. powv[ii] is the pcdac corresponding to ii/2 dBm. 241514779705SSam Leffler */ 241614779705SSam Leffler static void 241714779705SSam Leffler ar5212CorrectGainDelta(struct ath_hal *ah, int twiceOfdmCckDelta) 241814779705SSam Leffler { 241914779705SSam Leffler #define N(_a) (sizeof(_a) / sizeof(_a[0])) 242014779705SSam Leffler struct ath_hal_5212 *ahp = AH5212(ah); 242114779705SSam Leffler const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 242214779705SSam Leffler int16_t ratesIndex[N(ahp->ah_ratesArray)]; 242314779705SSam Leffler uint16_t ii, jj, iter; 242414779705SSam Leffler int32_t cckIndex; 242514779705SSam Leffler int16_t gainDeltaAdjust; 242614779705SSam Leffler 242714779705SSam Leffler HALASSERT(ah->ah_magic == AR5212_MAGIC); 242814779705SSam Leffler 242914779705SSam Leffler gainDeltaAdjust = ee->ee_cckOfdmGainDelta; 243014779705SSam Leffler 243114779705SSam Leffler /* make a local copy of desired powers as initial indices */ 243214779705SSam Leffler OS_MEMCPY(ratesIndex, ahp->ah_ratesArray, sizeof(ratesIndex)); 243314779705SSam Leffler 243414779705SSam Leffler /* fix only the CCK indices */ 243514779705SSam Leffler for (ii = 8; ii < 15; ii++) { 243614779705SSam Leffler /* apply a gain_delta correction of -15 for CCK */ 243714779705SSam Leffler ratesIndex[ii] -= gainDeltaAdjust; 243814779705SSam Leffler 243914779705SSam Leffler /* Now check for contention with all ofdm target powers */ 244014779705SSam Leffler jj = 0; 244114779705SSam Leffler iter = 0; 244214779705SSam Leffler /* indicates not all ofdm rates checked forcontention yet */ 244314779705SSam Leffler while (jj < 16) { 244414779705SSam Leffler if (ratesIndex[ii] < 0) 244514779705SSam Leffler ratesIndex[ii] = 0; 244614779705SSam Leffler if (jj == 8) { /* skip CCK rates */ 244714779705SSam Leffler jj = 15; 244814779705SSam Leffler continue; 244914779705SSam Leffler } 245014779705SSam Leffler if (ratesIndex[ii] == ahp->ah_ratesArray[jj]) { 245114779705SSam Leffler if (ahp->ah_ratesArray[jj] == 0) 245214779705SSam Leffler ratesIndex[ii]++; 245314779705SSam Leffler else if (iter > 50) { 245414779705SSam Leffler /* 245514779705SSam Leffler * To avoid pathological case of of 245614779705SSam Leffler * dm target powers 0 and 0.5dBm 245714779705SSam Leffler */ 245814779705SSam Leffler ratesIndex[ii]++; 245914779705SSam Leffler } else 246014779705SSam Leffler ratesIndex[ii]--; 246114779705SSam Leffler /* check with all rates again */ 246214779705SSam Leffler jj = 0; 246314779705SSam Leffler iter++; 246414779705SSam Leffler } else 246514779705SSam Leffler jj++; 246614779705SSam Leffler } 246714779705SSam Leffler if (ratesIndex[ii] >= PWR_TABLE_SIZE) 246814779705SSam Leffler ratesIndex[ii] = PWR_TABLE_SIZE -1; 246914779705SSam Leffler cckIndex = ahp->ah_ratesArray[ii] - twiceOfdmCckDelta; 247014779705SSam Leffler if (cckIndex < 0) 247114779705SSam Leffler cckIndex = 0; 247214779705SSam Leffler 247314779705SSam Leffler /* 247414779705SSam Leffler * Validate that the indexes for the powv are not 247514779705SSam Leffler * out of bounds. 247614779705SSam Leffler */ 247714779705SSam Leffler HALASSERT(cckIndex < PWR_TABLE_SIZE); 247814779705SSam Leffler HALASSERT(ratesIndex[ii] < PWR_TABLE_SIZE); 247914779705SSam Leffler ahp->ah_pcdacTable[ratesIndex[ii]] = 248014779705SSam Leffler ahp->ah_pcdacTable[cckIndex]; 248114779705SSam Leffler } 248214779705SSam Leffler /* Override rate per power table with new values */ 248314779705SSam Leffler for (ii = 8; ii < 15; ii++) 248414779705SSam Leffler ahp->ah_ratesArray[ii] = ratesIndex[ii]; 248514779705SSam Leffler #undef N 248614779705SSam Leffler } 248714779705SSam Leffler 248814779705SSam Leffler /* 248914779705SSam Leffler * Find the maximum conformance test limit for the given channel and CTL info 249014779705SSam Leffler */ 249114779705SSam Leffler static uint16_t 249214779705SSam Leffler ar5212GetMaxEdgePower(uint16_t channel, const RD_EDGES_POWER *pRdEdgesPower) 249314779705SSam Leffler { 249414779705SSam Leffler /* temp array for holding edge channels */ 249514779705SSam Leffler uint16_t tempChannelList[NUM_EDGES]; 249614779705SSam Leffler uint16_t clo, chi, twiceMaxEdgePower; 249714779705SSam Leffler int i, numEdges; 249814779705SSam Leffler 249914779705SSam Leffler /* Get the edge power */ 250014779705SSam Leffler for (i = 0; i < NUM_EDGES; i++) { 250114779705SSam Leffler if (pRdEdgesPower[i].rdEdge == 0) 250214779705SSam Leffler break; 250314779705SSam Leffler tempChannelList[i] = pRdEdgesPower[i].rdEdge; 250414779705SSam Leffler } 250514779705SSam Leffler numEdges = i; 250614779705SSam Leffler 250714779705SSam Leffler ar5212GetLowerUpperValues(channel, tempChannelList, 250814779705SSam Leffler numEdges, &clo, &chi); 250914779705SSam Leffler /* Get the index for the lower channel */ 251014779705SSam Leffler for (i = 0; i < numEdges && clo != tempChannelList[i]; i++) 251114779705SSam Leffler ; 251214779705SSam Leffler /* Is lower channel ever outside the rdEdge? */ 251314779705SSam Leffler HALASSERT(i != numEdges); 251414779705SSam Leffler 251514779705SSam Leffler if ((clo == chi && clo == channel) || (pRdEdgesPower[i].flag)) { 251614779705SSam Leffler /* 251714779705SSam Leffler * If there's an exact channel match or an inband flag set 251814779705SSam Leffler * on the lower channel use the given rdEdgePower 251914779705SSam Leffler */ 252014779705SSam Leffler twiceMaxEdgePower = pRdEdgesPower[i].twice_rdEdgePower; 252114779705SSam Leffler HALASSERT(twiceMaxEdgePower > 0); 252214779705SSam Leffler } else 252314779705SSam Leffler twiceMaxEdgePower = MAX_RATE_POWER; 252414779705SSam Leffler return twiceMaxEdgePower; 252514779705SSam Leffler } 252614779705SSam Leffler 252714779705SSam Leffler /* 252814779705SSam Leffler * Returns interpolated or the scaled up interpolated value 252914779705SSam Leffler */ 253014779705SSam Leffler static uint16_t 253114779705SSam Leffler interpolate(uint16_t target, uint16_t srcLeft, uint16_t srcRight, 253214779705SSam Leffler uint16_t targetLeft, uint16_t targetRight) 253314779705SSam Leffler { 253414779705SSam Leffler uint16_t rv; 253514779705SSam Leffler int16_t lRatio; 253614779705SSam Leffler 253714779705SSam Leffler /* to get an accurate ratio, always scale, if want to scale, then don't scale back down */ 253814779705SSam Leffler if ((targetLeft * targetRight) == 0) 253914779705SSam Leffler return 0; 254014779705SSam Leffler 254114779705SSam Leffler if (srcRight != srcLeft) { 254214779705SSam Leffler /* 254314779705SSam Leffler * Note the ratio always need to be scaled, 254414779705SSam Leffler * since it will be a fraction. 254514779705SSam Leffler */ 254614779705SSam Leffler lRatio = (target - srcLeft) * EEP_SCALE / (srcRight - srcLeft); 254714779705SSam Leffler if (lRatio < 0) { 254814779705SSam Leffler /* Return as Left target if value would be negative */ 254914779705SSam Leffler rv = targetLeft; 255014779705SSam Leffler } else if (lRatio > EEP_SCALE) { 255114779705SSam Leffler /* Return as Right target if Ratio is greater than 100% (SCALE) */ 255214779705SSam Leffler rv = targetRight; 255314779705SSam Leffler } else { 255414779705SSam Leffler rv = (lRatio * targetRight + (EEP_SCALE - lRatio) * 255514779705SSam Leffler targetLeft) / EEP_SCALE; 255614779705SSam Leffler } 255714779705SSam Leffler } else { 255814779705SSam Leffler rv = targetLeft; 255914779705SSam Leffler } 256014779705SSam Leffler return rv; 256114779705SSam Leffler } 256214779705SSam Leffler 256314779705SSam Leffler /* 256414779705SSam Leffler * Return the four rates of target power for the given target power table 256514779705SSam Leffler * channel, and number of channels 256614779705SSam Leffler */ 256714779705SSam Leffler static void 256859efa8b5SSam Leffler ar5212GetTargetPowers(struct ath_hal *ah, const struct ieee80211_channel *chan, 256914779705SSam Leffler const TRGT_POWER_INFO *powInfo, 257014779705SSam Leffler uint16_t numChannels, TRGT_POWER_INFO *pNewPower) 257114779705SSam Leffler { 257259efa8b5SSam Leffler uint16_t freq = ath_hal_gethwchannel(ah, chan); 257314779705SSam Leffler /* temp array for holding target power channels */ 257414779705SSam Leffler uint16_t tempChannelList[NUM_TEST_FREQUENCIES]; 257514779705SSam Leffler uint16_t clo, chi, ixlo, ixhi; 257614779705SSam Leffler int i; 257714779705SSam Leffler 257814779705SSam Leffler /* Copy the target powers into the temp channel list */ 257914779705SSam Leffler for (i = 0; i < numChannels; i++) 258014779705SSam Leffler tempChannelList[i] = powInfo[i].testChannel; 258114779705SSam Leffler 258259efa8b5SSam Leffler ar5212GetLowerUpperValues(freq, tempChannelList, 258314779705SSam Leffler numChannels, &clo, &chi); 258414779705SSam Leffler 258514779705SSam Leffler /* Get the indices for the channel */ 258614779705SSam Leffler ixlo = ixhi = 0; 258714779705SSam Leffler for (i = 0; i < numChannels; i++) { 258814779705SSam Leffler if (clo == tempChannelList[i]) { 258914779705SSam Leffler ixlo = i; 259014779705SSam Leffler } 259114779705SSam Leffler if (chi == tempChannelList[i]) { 259214779705SSam Leffler ixhi = i; 259314779705SSam Leffler break; 259414779705SSam Leffler } 259514779705SSam Leffler } 259614779705SSam Leffler 259714779705SSam Leffler /* 259814779705SSam Leffler * Get the lower and upper channels, target powers, 259914779705SSam Leffler * and interpolate between them. 260014779705SSam Leffler */ 260159efa8b5SSam Leffler pNewPower->twicePwr6_24 = interpolate(freq, clo, chi, 260214779705SSam Leffler powInfo[ixlo].twicePwr6_24, powInfo[ixhi].twicePwr6_24); 260359efa8b5SSam Leffler pNewPower->twicePwr36 = interpolate(freq, clo, chi, 260414779705SSam Leffler powInfo[ixlo].twicePwr36, powInfo[ixhi].twicePwr36); 260559efa8b5SSam Leffler pNewPower->twicePwr48 = interpolate(freq, clo, chi, 260614779705SSam Leffler powInfo[ixlo].twicePwr48, powInfo[ixhi].twicePwr48); 260759efa8b5SSam Leffler pNewPower->twicePwr54 = interpolate(freq, clo, chi, 260814779705SSam Leffler powInfo[ixlo].twicePwr54, powInfo[ixhi].twicePwr54); 260914779705SSam Leffler } 261014779705SSam Leffler 2611d41b89ccSDimitry Andric static uint32_t 2612d41b89ccSDimitry Andric udiff(uint32_t u, uint32_t v) 2613d41b89ccSDimitry Andric { 2614d41b89ccSDimitry Andric return (u >= v ? u - v : v - u); 2615d41b89ccSDimitry Andric } 2616d41b89ccSDimitry Andric 261714779705SSam Leffler /* 261814779705SSam Leffler * Search a list for a specified value v that is within 261914779705SSam Leffler * EEP_DELTA of the search values. Return the closest 262014779705SSam Leffler * values in the list above and below the desired value. 262114779705SSam Leffler * EEP_DELTA is a factional value; everything is scaled 262214779705SSam Leffler * so only integer arithmetic is used. 262314779705SSam Leffler * 262414779705SSam Leffler * NB: the input list is assumed to be sorted in ascending order 262514779705SSam Leffler */ 262614779705SSam Leffler void 262714779705SSam Leffler ar5212GetLowerUpperValues(uint16_t v, uint16_t *lp, uint16_t listSize, 262814779705SSam Leffler uint16_t *vlo, uint16_t *vhi) 262914779705SSam Leffler { 263014779705SSam Leffler uint32_t target = v * EEP_SCALE; 263114779705SSam Leffler uint16_t *ep = lp+listSize; 263214779705SSam Leffler 263314779705SSam Leffler /* 263414779705SSam Leffler * Check first and last elements for out-of-bounds conditions. 263514779705SSam Leffler */ 263614779705SSam Leffler if (target < (uint32_t)(lp[0] * EEP_SCALE - EEP_DELTA)) { 263714779705SSam Leffler *vlo = *vhi = lp[0]; 263814779705SSam Leffler return; 263914779705SSam Leffler } 264014779705SSam Leffler if (target > (uint32_t)(ep[-1] * EEP_SCALE + EEP_DELTA)) { 264114779705SSam Leffler *vlo = *vhi = ep[-1]; 264214779705SSam Leffler return; 264314779705SSam Leffler } 264414779705SSam Leffler 264514779705SSam Leffler /* look for value being near or between 2 values in list */ 264614779705SSam Leffler for (; lp < ep; lp++) { 264714779705SSam Leffler /* 264814779705SSam Leffler * If value is close to the current value of the list 264914779705SSam Leffler * then target is not between values, it is one of the values 265014779705SSam Leffler */ 2651d41b89ccSDimitry Andric if (udiff(lp[0] * EEP_SCALE, target) < EEP_DELTA) { 265214779705SSam Leffler *vlo = *vhi = lp[0]; 265314779705SSam Leffler return; 265414779705SSam Leffler } 265514779705SSam Leffler /* 265614779705SSam Leffler * Look for value being between current value and next value 265714779705SSam Leffler * if so return these 2 values 265814779705SSam Leffler */ 265914779705SSam Leffler if (target < (uint32_t)(lp[1] * EEP_SCALE - EEP_DELTA)) { 266014779705SSam Leffler *vlo = lp[0]; 266114779705SSam Leffler *vhi = lp[1]; 266214779705SSam Leffler return; 266314779705SSam Leffler } 266414779705SSam Leffler } 266514779705SSam Leffler HALASSERT(AH_FALSE); /* should not reach here */ 266614779705SSam Leffler } 266714779705SSam Leffler 266814779705SSam Leffler /* 266914779705SSam Leffler * Perform analog "swizzling" of parameters into their location 267014779705SSam Leffler * 267114779705SSam Leffler * NB: used by RF backends 267214779705SSam Leffler */ 267314779705SSam Leffler void 267414779705SSam Leffler ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32, uint32_t numBits, 267514779705SSam Leffler uint32_t firstBit, uint32_t column) 267614779705SSam Leffler { 267714779705SSam Leffler #define MAX_ANALOG_START 319 /* XXX */ 267814779705SSam Leffler uint32_t tmp32, mask, arrayEntry, lastBit; 267914779705SSam Leffler int32_t bitPosition, bitsLeft; 268014779705SSam Leffler 268114779705SSam Leffler HALASSERT(column <= 3); 268214779705SSam Leffler HALASSERT(numBits <= 32); 268314779705SSam Leffler HALASSERT(firstBit + numBits <= MAX_ANALOG_START); 268414779705SSam Leffler 268514779705SSam Leffler tmp32 = ath_hal_reverseBits(reg32, numBits); 268614779705SSam Leffler arrayEntry = (firstBit - 1) / 8; 268714779705SSam Leffler bitPosition = (firstBit - 1) % 8; 268814779705SSam Leffler bitsLeft = numBits; 268914779705SSam Leffler while (bitsLeft > 0) { 269014779705SSam Leffler lastBit = (bitPosition + bitsLeft > 8) ? 269114779705SSam Leffler 8 : bitPosition + bitsLeft; 269214779705SSam Leffler mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) << 269314779705SSam Leffler (column * 8); 269414779705SSam Leffler rfBuf[arrayEntry] &= ~mask; 269514779705SSam Leffler rfBuf[arrayEntry] |= ((tmp32 << bitPosition) << 269614779705SSam Leffler (column * 8)) & mask; 269714779705SSam Leffler bitsLeft -= 8 - bitPosition; 269814779705SSam Leffler tmp32 = tmp32 >> (8 - bitPosition); 269914779705SSam Leffler bitPosition = 0; 270014779705SSam Leffler arrayEntry++; 270114779705SSam Leffler } 270214779705SSam Leffler #undef MAX_ANALOG_START 270314779705SSam Leffler } 270414779705SSam Leffler 270514779705SSam Leffler /* 270614779705SSam Leffler * Sets the rate to duration values in MAC - used for multi- 270714779705SSam Leffler * rate retry. 270814779705SSam Leffler * The rate duration table needs to cover all valid rate codes; 270914779705SSam Leffler * the 11g table covers all ofdm rates, while the 11b table 271014779705SSam Leffler * covers all cck rates => all valid rates get covered between 271114779705SSam Leffler * these two mode's ratetables! 271214779705SSam Leffler * But if we're turbo, the ofdm phy is replaced by the turbo phy 271314779705SSam Leffler * and cck is not valid with turbo => all rates get covered 271414779705SSam Leffler * by the turbo ratetable only 271514779705SSam Leffler */ 271614779705SSam Leffler void 271759efa8b5SSam Leffler ar5212SetRateDurationTable(struct ath_hal *ah, 271859efa8b5SSam Leffler const struct ieee80211_channel *chan) 271914779705SSam Leffler { 272014779705SSam Leffler const HAL_RATE_TABLE *rt; 272114779705SSam Leffler int i; 272214779705SSam Leffler 272314779705SSam Leffler /* NB: band doesn't matter for 1/2 and 1/4 rate */ 272459efa8b5SSam Leffler if (IEEE80211_IS_CHAN_HALF(chan)) { 272514779705SSam Leffler rt = ar5212GetRateTable(ah, HAL_MODE_11A_HALF_RATE); 272659efa8b5SSam Leffler } else if (IEEE80211_IS_CHAN_QUARTER(chan)) { 272714779705SSam Leffler rt = ar5212GetRateTable(ah, HAL_MODE_11A_QUARTER_RATE); 272814779705SSam Leffler } else { 272914779705SSam Leffler rt = ar5212GetRateTable(ah, 273059efa8b5SSam Leffler IEEE80211_IS_CHAN_TURBO(chan) ? HAL_MODE_TURBO : HAL_MODE_11G); 273114779705SSam Leffler } 273214779705SSam Leffler 273314779705SSam Leffler for (i = 0; i < rt->rateCount; ++i) 273414779705SSam Leffler OS_REG_WRITE(ah, 273514779705SSam Leffler AR_RATE_DURATION(rt->info[i].rateCode), 273614779705SSam Leffler ath_hal_computetxtime(ah, rt, 273714779705SSam Leffler WLAN_CTRL_FRAME_SIZE, 27387ff1939dSAdrian Chadd rt->info[i].controlRate, AH_FALSE, AH_TRUE)); 273959efa8b5SSam Leffler if (!IEEE80211_IS_CHAN_TURBO(chan)) { 274014779705SSam Leffler /* 11g Table is used to cover the CCK rates. */ 274114779705SSam Leffler rt = ar5212GetRateTable(ah, HAL_MODE_11G); 274214779705SSam Leffler for (i = 0; i < rt->rateCount; ++i) { 274314779705SSam Leffler uint32_t reg = AR_RATE_DURATION(rt->info[i].rateCode); 274414779705SSam Leffler 274514779705SSam Leffler if (rt->info[i].phy != IEEE80211_T_CCK) 274614779705SSam Leffler continue; 274714779705SSam Leffler 274814779705SSam Leffler OS_REG_WRITE(ah, reg, 274914779705SSam Leffler ath_hal_computetxtime(ah, rt, 275014779705SSam Leffler WLAN_CTRL_FRAME_SIZE, 27517ff1939dSAdrian Chadd rt->info[i].controlRate, AH_FALSE, 27527ff1939dSAdrian Chadd AH_TRUE)); 275314779705SSam Leffler /* cck rates have short preamble option also */ 275414779705SSam Leffler if (rt->info[i].shortPreamble) { 275514779705SSam Leffler reg += rt->info[i].shortPreamble << 2; 275614779705SSam Leffler OS_REG_WRITE(ah, reg, 275714779705SSam Leffler ath_hal_computetxtime(ah, rt, 275814779705SSam Leffler WLAN_CTRL_FRAME_SIZE, 275914779705SSam Leffler rt->info[i].controlRate, 27607ff1939dSAdrian Chadd AH_TRUE, AH_TRUE)); 276114779705SSam Leffler } 276214779705SSam Leffler } 276314779705SSam Leffler } 276414779705SSam Leffler } 276514779705SSam Leffler 276614779705SSam Leffler /* Adjust various register settings based on half/quarter rate clock setting. 276714779705SSam Leffler * This includes: +USEC, TX/RX latency, 276814779705SSam Leffler * + IFS params: slot, eifs, misc etc. 276914779705SSam Leffler */ 277014779705SSam Leffler void 277159efa8b5SSam Leffler ar5212SetIFSTiming(struct ath_hal *ah, const struct ieee80211_channel *chan) 277214779705SSam Leffler { 277314779705SSam Leffler uint32_t txLat, rxLat, usec, slot, refClock, eifs, init_usec; 277414779705SSam Leffler 277559efa8b5SSam Leffler HALASSERT(IEEE80211_IS_CHAN_HALF(chan) || 277659efa8b5SSam Leffler IEEE80211_IS_CHAN_QUARTER(chan)); 277714779705SSam Leffler 277814779705SSam Leffler refClock = OS_REG_READ(ah, AR_USEC) & AR_USEC_USEC32; 277959efa8b5SSam Leffler if (IEEE80211_IS_CHAN_HALF(chan)) { 278014779705SSam Leffler slot = IFS_SLOT_HALF_RATE; 278114779705SSam Leffler rxLat = RX_NON_FULL_RATE_LATENCY << AR5212_USEC_RX_LAT_S; 278214779705SSam Leffler txLat = TX_HALF_RATE_LATENCY << AR5212_USEC_TX_LAT_S; 278314779705SSam Leffler usec = HALF_RATE_USEC; 278414779705SSam Leffler eifs = IFS_EIFS_HALF_RATE; 278514779705SSam Leffler init_usec = INIT_USEC >> 1; 278614779705SSam Leffler } else { /* quarter rate */ 278714779705SSam Leffler slot = IFS_SLOT_QUARTER_RATE; 278814779705SSam Leffler rxLat = RX_NON_FULL_RATE_LATENCY << AR5212_USEC_RX_LAT_S; 278914779705SSam Leffler txLat = TX_QUARTER_RATE_LATENCY << AR5212_USEC_TX_LAT_S; 279014779705SSam Leffler usec = QUARTER_RATE_USEC; 279114779705SSam Leffler eifs = IFS_EIFS_QUARTER_RATE; 279214779705SSam Leffler init_usec = INIT_USEC >> 2; 279314779705SSam Leffler } 279414779705SSam Leffler 279514779705SSam Leffler OS_REG_WRITE(ah, AR_USEC, (usec | refClock | txLat | rxLat)); 279614779705SSam Leffler OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, slot); 279714779705SSam Leffler OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, eifs); 279814779705SSam Leffler OS_REG_RMW_FIELD(ah, AR_D_GBL_IFS_MISC, 279914779705SSam Leffler AR_D_GBL_IFS_MISC_USEC_DURATION, init_usec); 280014779705SSam Leffler } 2801