1 /* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 #include "ah_devid.h" 24 25 #include "ah_eeprom_v14.h" 26 27 #include "ar5416/ar5416.h" 28 #include "ar5416/ar5416reg.h" 29 #include "ar5416/ar5416phy.h" 30 31 #include "ar5416/ar5416.ini" 32 33 static void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 34 static void ar5416WriteIni(struct ath_hal *ah, 35 const struct ieee80211_channel *chan); 36 static void ar5416SpurMitigate(struct ath_hal *ah, 37 const struct ieee80211_channel *chan); 38 39 static void 40 ar5416AniSetup(struct ath_hal *ah) 41 { 42 static const struct ar5212AniParams aniparams = { 43 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 44 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 45 .coarseHigh = { -14, -14, -14, -14, -12 }, 46 .coarseLow = { -64, -64, -64, -64, -70 }, 47 .firpwr = { -78, -78, -78, -78, -80 }, 48 .maxSpurImmunityLevel = 2, 49 .cycPwrThr1 = { 2, 4, 6 }, 50 .maxFirstepLevel = 2, /* levels 0..2 */ 51 .firstep = { 0, 4, 8 }, 52 .ofdmTrigHigh = 500, 53 .ofdmTrigLow = 200, 54 .cckTrigHigh = 200, 55 .cckTrigLow = 100, 56 .rssiThrHigh = 40, 57 .rssiThrLow = 7, 58 .period = 100, 59 }; 60 /* NB: ANI is not enabled yet */ 61 ar5416AniAttach(ah, &aniparams, &aniparams, AH_FALSE); 62 } 63 64 /* 65 * AR5416 doesn't do OLC or temperature compensation. 66 */ 67 static void 68 ar5416olcInit(struct ath_hal *ah) 69 { 70 } 71 72 static void 73 ar5416olcTempCompensation(struct ath_hal *ah) 74 { 75 } 76 77 /* 78 * Attach for an AR5416 part. 79 */ 80 void 81 ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc, 82 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 83 { 84 struct ath_hal_5212 *ahp; 85 struct ath_hal *ah; 86 87 ahp = &ahp5416->ah_5212; 88 ar5212InitState(ahp, devid, sc, st, sh, status); 89 ah = &ahp->ah_priv.h; 90 91 /* override 5212 methods for our needs */ 92 ah->ah_magic = AR5416_MAGIC; 93 ah->ah_getRateTable = ar5416GetRateTable; 94 ah->ah_detach = ar5416Detach; 95 96 /* Reset functions */ 97 ah->ah_reset = ar5416Reset; 98 ah->ah_phyDisable = ar5416PhyDisable; 99 ah->ah_disable = ar5416Disable; 100 ah->ah_configPCIE = ar5416ConfigPCIE; 101 ah->ah_perCalibration = ar5416PerCalibration; 102 ah->ah_perCalibrationN = ar5416PerCalibrationN, 103 ah->ah_resetCalValid = ar5416ResetCalValid, 104 ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit; 105 ah->ah_setTxPower = ar5416SetTransmitPower; 106 ah->ah_setBoardValues = ar5416SetBoardValues; 107 108 /* Transmit functions */ 109 ah->ah_stopTxDma = ar5416StopTxDma; 110 ah->ah_setupTxDesc = ar5416SetupTxDesc; 111 ah->ah_setupXTxDesc = ar5416SetupXTxDesc; 112 ah->ah_fillTxDesc = ar5416FillTxDesc; 113 ah->ah_procTxDesc = ar5416ProcTxDesc; 114 ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates; 115 ah->ah_setupTxQueue = ar5416SetupTxQueue; 116 ah->ah_resetTxQueue = ar5416ResetTxQueue; 117 118 /* Receive Functions */ 119 ah->ah_startPcuReceive = ar5416StartPcuReceive; 120 ah->ah_stopPcuReceive = ar5416StopPcuReceive; 121 ah->ah_setupRxDesc = ar5416SetupRxDesc; 122 ah->ah_procRxDesc = ar5416ProcRxDesc; 123 ah->ah_rxMonitor = ar5416RxMonitor; 124 ah->ah_aniPoll = ar5416AniPoll; 125 ah->ah_procMibEvent = ar5416ProcessMibIntr; 126 127 /* Misc Functions */ 128 ah->ah_getCapability = ar5416GetCapability; 129 ah->ah_getDiagState = ar5416GetDiagState; 130 ah->ah_setLedState = ar5416SetLedState; 131 ah->ah_gpioCfgOutput = ar5416GpioCfgOutput; 132 ah->ah_gpioCfgInput = ar5416GpioCfgInput; 133 ah->ah_gpioGet = ar5416GpioGet; 134 ah->ah_gpioSet = ar5416GpioSet; 135 ah->ah_gpioSetIntr = ar5416GpioSetIntr; 136 ah->ah_resetTsf = ar5416ResetTsf; 137 ah->ah_getRfGain = ar5416GetRfgain; 138 ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch; 139 ah->ah_setDecompMask = ar5416SetDecompMask; 140 ah->ah_setCoverageClass = ar5416SetCoverageClass; 141 142 ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry; 143 ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry; 144 145 /* Power Management Functions */ 146 ah->ah_setPowerMode = ar5416SetPowerMode; 147 148 /* Beacon Management Functions */ 149 ah->ah_setBeaconTimers = ar5416SetBeaconTimers; 150 ah->ah_beaconInit = ar5416BeaconInit; 151 ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers; 152 ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers; 153 154 /* 802.11n Functions */ 155 ah->ah_chainTxDesc = ar5416ChainTxDesc; 156 ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc; 157 ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc; 158 ah->ah_set11nRateScenario = ar5416Set11nRateScenario; 159 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle; 160 ah->ah_clr11nAggr = ar5416Clr11nAggr; 161 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration; 162 ah->ah_get11nExtBusy = ar5416Get11nExtBusy; 163 ah->ah_set11nMac2040 = ar5416Set11nMac2040; 164 ah->ah_get11nRxClear = ar5416Get11nRxClear; 165 ah->ah_set11nRxClear = ar5416Set11nRxClear; 166 167 /* Interrupt functions */ 168 ah->ah_isInterruptPending = ar5416IsInterruptPending; 169 ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts; 170 ah->ah_setInterrupts = ar5416SetInterrupts; 171 172 ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes; 173 ahp->ah_priv.ah_eepromRead = ar5416EepromRead; 174 #ifdef AH_SUPPORT_WRITE_EEPROM 175 ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite; 176 #endif 177 ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits; 178 179 /* Internal ops */ 180 AH5416(ah)->ah_writeIni = ar5416WriteIni; 181 AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate; 182 183 /* Internal calibration ops */ 184 AH5416(ah)->ah_cal_initcal = ar5416InitCalHardware; 185 186 /* Internal TX power control related operations */ 187 AH5416(ah)->ah_olcInit = ar5416olcInit; 188 AH5416(ah)->ah_olcTempCompensation = ar5416olcTempCompensation; 189 AH5416(ah)->ah_setPowerCalTable = ar5416SetPowerCalTable; 190 191 /* 192 * Start by setting all Owl devices to 2x2 193 */ 194 AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK; 195 AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK; 196 197 /* Enable all ANI functions to begin with */ 198 AH5416(ah)->ah_ani_function = HAL_ANI_ALL; 199 } 200 201 uint32_t 202 ar5416GetRadioRev(struct ath_hal *ah) 203 { 204 uint32_t val; 205 int i; 206 207 /* Read Radio Chip Rev Extract */ 208 OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 209 for (i = 0; i < 8; i++) 210 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 211 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 212 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 213 return ath_hal_reverseBits(val, 8); 214 } 215 216 /* 217 * Attach for an AR5416 part. 218 */ 219 static struct ath_hal * 220 ar5416Attach(uint16_t devid, HAL_SOFTC sc, 221 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 222 HAL_STATUS *status) 223 { 224 struct ath_hal_5416 *ahp5416; 225 struct ath_hal_5212 *ahp; 226 struct ath_hal *ah; 227 uint32_t val; 228 HAL_STATUS ecode; 229 HAL_BOOL rfStatus; 230 231 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 232 __func__, sc, (void*) st, (void*) sh); 233 234 /* NB: memory is returned zero'd */ 235 ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) + 236 /* extra space for Owl 2.1/2.2 WAR */ 237 sizeof(ar5416Addac) 238 ); 239 if (ahp5416 == AH_NULL) { 240 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 241 "%s: cannot allocate memory for state block\n", __func__); 242 *status = HAL_ENOMEM; 243 return AH_NULL; 244 } 245 ar5416InitState(ahp5416, devid, sc, st, sh, status); 246 ahp = &ahp5416->ah_5212; 247 ah = &ahp->ah_priv.h; 248 249 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 250 /* reset chip */ 251 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__); 252 ecode = HAL_EIO; 253 goto bad; 254 } 255 256 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 257 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__); 258 ecode = HAL_EIO; 259 goto bad; 260 } 261 /* Read Revisions from Chips before taking out of reset */ 262 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 263 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 264 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 265 AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE); 266 267 /* setup common ini data; rf backends handle remainder */ 268 HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6); 269 HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2); 270 271 HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3); 272 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2); 273 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2); 274 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2); 275 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3); 276 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3); 277 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2); 278 HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2); 279 280 if (!IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */ 281 struct ini { 282 uint32_t *data; /* NB: !const */ 283 int rows, cols; 284 }; 285 /* override CLKDRV value */ 286 OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac)); 287 AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1]; 288 HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0; 289 } 290 291 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2); 292 ar5416AttachPCIE(ah); 293 294 ecode = ath_hal_v14EepromAttach(ah); 295 if (ecode != HAL_OK) 296 goto bad; 297 298 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 299 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", 300 __func__); 301 ecode = HAL_EIO; 302 goto bad; 303 } 304 305 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 306 307 if (!ar5212ChipTest(ah)) { 308 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 309 __func__); 310 ecode = HAL_ESELFTEST; 311 goto bad; 312 } 313 314 /* 315 * Set correct Baseband to analog shift 316 * setting to access analog chips. 317 */ 318 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 319 320 /* Read Radio Chip Rev Extract */ 321 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 322 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 323 case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */ 324 case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */ 325 case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */ 326 case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */ 327 break; 328 default: 329 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 330 /* 331 * When RF_Silen is used the analog chip is reset. 332 * So when the system boots with radio switch off 333 * the RF chip rev reads back as zero and we need 334 * to use the mac+phy revs to set the radio rev. 335 */ 336 AH_PRIVATE(ah)->ah_analog5GhzRev = 337 AR_RAD5133_SREV_MAJOR; 338 break; 339 } 340 /* NB: silently accept anything in release code per Atheros */ 341 #ifdef AH_DEBUG 342 HALDEBUG(ah, HAL_DEBUG_ANY, 343 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 344 "this driver\n", __func__, 345 AH_PRIVATE(ah)->ah_analog5GhzRev); 346 ecode = HAL_ENOTSUPP; 347 goto bad; 348 #endif 349 } 350 351 /* 352 * Got everything we need now to setup the capabilities. 353 */ 354 if (!ar5416FillCapabilityInfo(ah)) { 355 ecode = HAL_EEREAD; 356 goto bad; 357 } 358 359 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 360 if (ecode != HAL_OK) { 361 HALDEBUG(ah, HAL_DEBUG_ANY, 362 "%s: error getting mac address from EEPROM\n", __func__); 363 goto bad; 364 } 365 /* XXX How about the serial number ? */ 366 /* Read Reg Domain */ 367 AH_PRIVATE(ah)->ah_currentRD = 368 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 369 370 /* 371 * ah_miscMode is populated by ar5416FillCapabilityInfo() 372 * starting from griffin. Set here to make sure that 373 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 374 * placed into hardware. 375 */ 376 if (ahp->ah_miscMode != 0) 377 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 378 379 rfStatus = ar2133RfAttach(ah, &ecode); 380 if (!rfStatus) { 381 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 382 __func__, ecode); 383 goto bad; 384 } 385 386 ar5416AniSetup(ah); /* Anti Noise Immunity */ 387 388 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 389 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 390 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 391 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 392 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 393 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 394 395 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 396 397 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 398 399 return ah; 400 bad: 401 if (ahp) 402 ar5416Detach((struct ath_hal *) ahp); 403 if (status) 404 *status = ecode; 405 return AH_NULL; 406 } 407 408 void 409 ar5416Detach(struct ath_hal *ah) 410 { 411 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 412 413 HALASSERT(ah != AH_NULL); 414 HALASSERT(ah->ah_magic == AR5416_MAGIC); 415 416 ar5416AniDetach(ah); 417 ar5212RfDetach(ah); 418 ah->ah_disable(ah); 419 ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 420 ath_hal_eepromDetach(ah); 421 ath_hal_free(ah); 422 } 423 424 void 425 ar5416AttachPCIE(struct ath_hal *ah) 426 { 427 if (AH_PRIVATE(ah)->ah_ispcie) 428 ath_hal_configPCIE(ah, AH_FALSE); 429 else 430 ath_hal_disablePCIE(ah); 431 } 432 433 static void 434 ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 435 { 436 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 437 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 438 OS_DELAY(1000); 439 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 440 OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 441 } 442 } 443 444 static void 445 ar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 446 { 447 u_int modesIndex, freqIndex; 448 int regWrites = 0; 449 450 /* Setup the indices for the next set of register array writes */ 451 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 452 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 453 freqIndex = 2; 454 if (IEEE80211_IS_CHAN_HT40(chan)) 455 modesIndex = 3; 456 else if (IEEE80211_IS_CHAN_108G(chan)) 457 modesIndex = 5; 458 else 459 modesIndex = 4; 460 } else { 461 freqIndex = 1; 462 if (IEEE80211_IS_CHAN_HT40(chan) || 463 IEEE80211_IS_CHAN_TURBO(chan)) 464 modesIndex = 2; 465 else 466 modesIndex = 1; 467 } 468 469 /* Set correct Baseband to analog shift setting to access analog chips. */ 470 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 471 472 /* 473 * Write addac shifts 474 */ 475 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 476 #if 0 477 /* NB: only required for Sowl */ 478 ar5416EepromSetAddac(ah, chan); 479 #endif 480 regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1, 481 regWrites); 482 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 483 484 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 485 modesIndex, regWrites); 486 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 487 1, regWrites); 488 489 /* XXX updated regWrites? */ 490 AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 491 } 492 493 /* 494 * Convert to baseband spur frequency given input channel frequency 495 * and compute register settings below. 496 */ 497 498 static void 499 ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 500 { 501 uint16_t freq = ath_hal_gethwchannel(ah, chan); 502 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 503 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 504 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 505 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 506 static const int inc[4] = { 0, 100, 0, 0 }; 507 508 int bb_spur = AR_NO_SPUR; 509 int bin, cur_bin; 510 int spur_freq_sd; 511 int spur_delta_phase; 512 int denominator; 513 int upper, lower, cur_vit_mask; 514 int tmp, new; 515 int i; 516 517 int8_t mask_m[123]; 518 int8_t mask_p[123]; 519 int8_t mask_amt; 520 int tmp_mask; 521 int cur_bb_spur; 522 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 523 524 OS_MEMZERO(mask_m, sizeof(mask_m)); 525 OS_MEMZERO(mask_p, sizeof(mask_p)); 526 527 /* 528 * Need to verify range +/- 9.5 for static ht20, otherwise spur 529 * is out-of-band and can be ignored. 530 */ 531 /* XXX ath9k changes */ 532 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 533 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 534 if (AR_NO_SPUR == cur_bb_spur) 535 break; 536 cur_bb_spur = cur_bb_spur - (freq * 10); 537 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 538 bb_spur = cur_bb_spur; 539 break; 540 } 541 } 542 if (AR_NO_SPUR == bb_spur) 543 return; 544 545 bin = bb_spur * 32; 546 547 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 548 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 549 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 550 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 551 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 552 553 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new); 554 555 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 556 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 557 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 558 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 559 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 560 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new); 561 /* 562 * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz 563 * config, no offset for HT20. 564 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 565 * /80 for dyn2040. 566 */ 567 spur_delta_phase = ((bb_spur * 524288) / 100) & 568 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 569 /* 570 * in 11A mode the denominator of spur_freq_sd should be 40 and 571 * it should be 44 in 11G 572 */ 573 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400; 574 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 575 576 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 577 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 578 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 579 OS_REG_WRITE(ah, AR_PHY_TIMING11, new); 580 581 582 /* 583 * ============================================ 584 * pilot mask 1 [31:0] = +6..-26, no 0 bin 585 * pilot mask 2 [19:0] = +26..+7 586 * 587 * channel mask 1 [31:0] = +6..-26, no 0 bin 588 * channel mask 2 [19:0] = +26..+7 589 */ 590 //cur_bin = -26; 591 cur_bin = -6000; 592 upper = bin + 100; 593 lower = bin - 100; 594 595 for (i = 0; i < 4; i++) { 596 int pilot_mask = 0; 597 int chan_mask = 0; 598 int bp = 0; 599 for (bp = 0; bp < 30; bp++) { 600 if ((cur_bin > lower) && (cur_bin < upper)) { 601 pilot_mask = pilot_mask | 0x1 << bp; 602 chan_mask = chan_mask | 0x1 << bp; 603 } 604 cur_bin += 100; 605 } 606 cur_bin += inc[i]; 607 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 608 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 609 } 610 611 /* ================================================= 612 * viterbi mask 1 based on channel magnitude 613 * four levels 0-3 614 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 615 * [1 2 2 1] for -9.6 or [1 2 1] for +16 616 * - enable_mask_ppm, all bins move with freq 617 * 618 * - mask_select, 8 bits for rates (reg 67,0x990c) 619 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 620 * choose which mask to use mask or mask2 621 */ 622 623 /* 624 * viterbi mask 2 2nd set for per data rate puncturing 625 * four levels 0-3 626 * - mask_select, 8 bits for rates (reg 67) 627 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 628 * [1 2 2 1] for -9.6 or [1 2 1] for +16 629 */ 630 cur_vit_mask = 6100; 631 upper = bin + 120; 632 lower = bin - 120; 633 634 for (i = 0; i < 123; i++) { 635 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 636 if ((abs(cur_vit_mask - bin)) < 75) { 637 mask_amt = 1; 638 } else { 639 mask_amt = 0; 640 } 641 if (cur_vit_mask < 0) { 642 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 643 } else { 644 mask_p[cur_vit_mask / 100] = mask_amt; 645 } 646 } 647 cur_vit_mask -= 100; 648 } 649 650 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 651 | (mask_m[48] << 26) | (mask_m[49] << 24) 652 | (mask_m[50] << 22) | (mask_m[51] << 20) 653 | (mask_m[52] << 18) | (mask_m[53] << 16) 654 | (mask_m[54] << 14) | (mask_m[55] << 12) 655 | (mask_m[56] << 10) | (mask_m[57] << 8) 656 | (mask_m[58] << 6) | (mask_m[59] << 4) 657 | (mask_m[60] << 2) | (mask_m[61] << 0); 658 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 659 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 660 661 tmp_mask = (mask_m[31] << 28) 662 | (mask_m[32] << 26) | (mask_m[33] << 24) 663 | (mask_m[34] << 22) | (mask_m[35] << 20) 664 | (mask_m[36] << 18) | (mask_m[37] << 16) 665 | (mask_m[48] << 14) | (mask_m[39] << 12) 666 | (mask_m[40] << 10) | (mask_m[41] << 8) 667 | (mask_m[42] << 6) | (mask_m[43] << 4) 668 | (mask_m[44] << 2) | (mask_m[45] << 0); 669 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 670 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 671 672 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 673 | (mask_m[18] << 26) | (mask_m[18] << 24) 674 | (mask_m[20] << 22) | (mask_m[20] << 20) 675 | (mask_m[22] << 18) | (mask_m[22] << 16) 676 | (mask_m[24] << 14) | (mask_m[24] << 12) 677 | (mask_m[25] << 10) | (mask_m[26] << 8) 678 | (mask_m[27] << 6) | (mask_m[28] << 4) 679 | (mask_m[29] << 2) | (mask_m[30] << 0); 680 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 681 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 682 683 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 684 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 685 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 686 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 687 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 688 | (mask_m[10] << 10) | (mask_m[11] << 8) 689 | (mask_m[12] << 6) | (mask_m[13] << 4) 690 | (mask_m[14] << 2) | (mask_m[15] << 0); 691 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 692 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 693 694 tmp_mask = (mask_p[15] << 28) 695 | (mask_p[14] << 26) | (mask_p[13] << 24) 696 | (mask_p[12] << 22) | (mask_p[11] << 20) 697 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 698 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 699 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 700 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 701 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 702 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 703 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 704 705 tmp_mask = (mask_p[30] << 28) 706 | (mask_p[29] << 26) | (mask_p[28] << 24) 707 | (mask_p[27] << 22) | (mask_p[26] << 20) 708 | (mask_p[25] << 18) | (mask_p[24] << 16) 709 | (mask_p[23] << 14) | (mask_p[22] << 12) 710 | (mask_p[21] << 10) | (mask_p[20] << 8) 711 | (mask_p[19] << 6) | (mask_p[18] << 4) 712 | (mask_p[17] << 2) | (mask_p[16] << 0); 713 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 714 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 715 716 tmp_mask = (mask_p[45] << 28) 717 | (mask_p[44] << 26) | (mask_p[43] << 24) 718 | (mask_p[42] << 22) | (mask_p[41] << 20) 719 | (mask_p[40] << 18) | (mask_p[39] << 16) 720 | (mask_p[38] << 14) | (mask_p[37] << 12) 721 | (mask_p[36] << 10) | (mask_p[35] << 8) 722 | (mask_p[34] << 6) | (mask_p[33] << 4) 723 | (mask_p[32] << 2) | (mask_p[31] << 0); 724 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 725 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 726 727 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 728 | (mask_p[59] << 26) | (mask_p[58] << 24) 729 | (mask_p[57] << 22) | (mask_p[56] << 20) 730 | (mask_p[55] << 18) | (mask_p[54] << 16) 731 | (mask_p[53] << 14) | (mask_p[52] << 12) 732 | (mask_p[51] << 10) | (mask_p[50] << 8) 733 | (mask_p[49] << 6) | (mask_p[48] << 4) 734 | (mask_p[47] << 2) | (mask_p[46] << 0); 735 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 736 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 737 } 738 739 /* 740 * Fill all software cached or static hardware state information. 741 * Return failure if capabilities are to come from EEPROM and 742 * cannot be read. 743 */ 744 HAL_BOOL 745 ar5416FillCapabilityInfo(struct ath_hal *ah) 746 { 747 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 748 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 749 uint16_t val; 750 751 /* Construct wireless mode from EEPROM */ 752 pCap->halWirelessModes = 0; 753 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 754 pCap->halWirelessModes |= HAL_MODE_11A 755 | HAL_MODE_11NA_HT20 756 | HAL_MODE_11NA_HT40PLUS 757 | HAL_MODE_11NA_HT40MINUS 758 ; 759 } 760 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) { 761 pCap->halWirelessModes |= HAL_MODE_11G 762 | HAL_MODE_11NG_HT20 763 | HAL_MODE_11NG_HT40PLUS 764 | HAL_MODE_11NG_HT40MINUS 765 ; 766 pCap->halWirelessModes |= HAL_MODE_11A 767 | HAL_MODE_11NA_HT20 768 | HAL_MODE_11NA_HT40PLUS 769 | HAL_MODE_11NA_HT40MINUS 770 ; 771 } 772 773 pCap->halLow2GhzChan = 2312; 774 pCap->halHigh2GhzChan = 2732; 775 776 pCap->halLow5GhzChan = 4915; 777 pCap->halHigh5GhzChan = 6100; 778 779 pCap->halCipherCkipSupport = AH_FALSE; 780 pCap->halCipherTkipSupport = AH_TRUE; 781 pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 782 783 pCap->halMicCkipSupport = AH_FALSE; 784 pCap->halMicTkipSupport = AH_TRUE; 785 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 786 /* 787 * Starting with Griffin TX+RX mic keys can be combined 788 * in one key cache slot. 789 */ 790 pCap->halTkipMicTxRxKeySupport = AH_TRUE; 791 pCap->halChanSpreadSupport = AH_TRUE; 792 pCap->halSleepAfterBeaconBroken = AH_TRUE; 793 794 pCap->halCompressSupport = AH_FALSE; 795 pCap->halBurstSupport = AH_TRUE; 796 pCap->halFastFramesSupport = AH_FALSE; /* XXX? */ 797 pCap->halChapTuningSupport = AH_TRUE; 798 pCap->halTurboPrimeSupport = AH_TRUE; 799 800 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 801 802 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 803 pCap->halVEOLSupport = AH_TRUE; 804 pCap->halBssIdMaskSupport = AH_TRUE; 805 pCap->halMcastKeySrchSupport = AH_FALSE; 806 pCap->halTsfAddSupport = AH_TRUE; 807 808 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 809 pCap->halTotalQueues = val; 810 else 811 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 812 813 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 814 pCap->halKeyCacheSize = val; 815 else 816 pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE; 817 818 /* XXX not needed */ 819 pCap->halChanHalfRate = AH_FALSE; /* XXX ? */ 820 pCap->halChanQuarterRate = AH_FALSE; /* XXX ? */ 821 822 pCap->halTstampPrecision = 32; 823 pCap->halHwPhyCounterSupport = AH_TRUE; 824 pCap->halIntrMask = HAL_INT_COMMON 825 | HAL_INT_RX 826 | HAL_INT_TX 827 | HAL_INT_FATAL 828 | HAL_INT_BNR 829 | HAL_INT_BMISC 830 | HAL_INT_DTIMSYNC 831 | HAL_INT_TSFOOR 832 | HAL_INT_CST 833 | HAL_INT_GTT 834 ; 835 836 pCap->halFastCCSupport = AH_TRUE; 837 pCap->halNumGpioPins = 6; 838 pCap->halWowSupport = AH_FALSE; 839 pCap->halWowMatchPatternExact = AH_FALSE; 840 pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */ 841 pCap->halAutoSleepSupport = AH_FALSE; 842 pCap->hal4kbSplitTransSupport = AH_TRUE; 843 #if 0 /* XXX not yet */ 844 pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ); 845 pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ); 846 #endif 847 pCap->halHTSupport = AH_TRUE; 848 pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL); 849 /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */ 850 pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL); 851 /* AR5416 may have 3 antennas but is a 2x2 stream device */ 852 pCap->halTxStreams = 2; 853 pCap->halRxStreams = 2; 854 pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */ 855 pCap->halMbssidAggrSupport = AH_TRUE; 856 pCap->halForcePpmSupport = AH_TRUE; 857 pCap->halEnhancedPmSupport = AH_TRUE; 858 pCap->halBssidMatchSupport = AH_TRUE; 859 860 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 861 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 862 /* NB: enabled by default */ 863 ahpriv->ah_rfkillEnabled = AH_TRUE; 864 pCap->halRfSilentSupport = AH_TRUE; 865 } 866 867 ahpriv->ah_rxornIsFatal = AH_FALSE; 868 869 return AH_TRUE; 870 } 871 872 static const char* 873 ar5416Probe(uint16_t vendorid, uint16_t devid) 874 { 875 if (vendorid == ATHEROS_VENDOR_ID && 876 (devid == AR5416_DEVID_PCI || devid == AR5416_DEVID_PCIE)) 877 return "Atheros 5416"; 878 return AH_NULL; 879 } 880 AH_CHIP(AR5416, ar5416Probe, ar5416Attach); 881