1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD$ 20 */ 21 #include "opt_ah.h" 22 23 #include "ah.h" 24 #include "ah_internal.h" 25 #include "ah_devid.h" 26 27 #include "ah_eeprom_v14.h" 28 29 #include "ar5416/ar5416.h" 30 #include "ar5416/ar5416reg.h" 31 #include "ar5416/ar5416phy.h" 32 33 /* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */ 34 #define EEP_MINOR(_ah) \ 35 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) 36 #define IS_EEP_MINOR_V2(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2) 37 #define IS_EEP_MINOR_V3(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_3) 38 39 /* Additional Time delay to wait after activiting the Base band */ 40 #define BASE_ACTIVATE_DELAY 100 /* 100 usec */ 41 #define PLL_SETTLE_DELAY 300 /* 300 usec */ 42 #define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */ 43 44 static void ar5416InitDMA(struct ath_hal *ah); 45 static void ar5416InitBB(struct ath_hal *ah, const struct ieee80211_channel *); 46 static void ar5416InitIMR(struct ath_hal *ah, HAL_OPMODE opmode); 47 static void ar5416InitQoS(struct ath_hal *ah); 48 static void ar5416InitUserSettings(struct ath_hal *ah); 49 static void ar5416OverrideIni(struct ath_hal *ah, const struct ieee80211_channel *); 50 51 #if 0 52 static HAL_BOOL ar5416ChannelChange(struct ath_hal *, const struct ieee80211_channel *); 53 #endif 54 static void ar5416SetDeltaSlope(struct ath_hal *, const struct ieee80211_channel *); 55 56 static HAL_BOOL ar5416SetResetPowerOn(struct ath_hal *ah); 57 static HAL_BOOL ar5416SetReset(struct ath_hal *ah, int type); 58 static HAL_BOOL ar5416SetPowerPerRateTable(struct ath_hal *ah, 59 struct ar5416eeprom *pEepData, 60 const struct ieee80211_channel *chan, int16_t *ratesArray, 61 uint16_t cfgCtl, uint16_t AntennaReduction, 62 uint16_t twiceMaxRegulatoryPower, 63 uint16_t powerLimit); 64 static void ar5416Set11nRegs(struct ath_hal *ah, const struct ieee80211_channel *chan); 65 static void ar5416MarkPhyInactive(struct ath_hal *ah); 66 static void ar5416SetIFSTiming(struct ath_hal *ah, 67 const struct ieee80211_channel *chan); 68 69 /* 70 * Places the device in and out of reset and then places sane 71 * values in the registers based on EEPROM config, initialization 72 * vectors (as determined by the mode), and station configuration 73 * 74 * bChannelChange is used to preserve DMA/PCU registers across 75 * a HW Reset during channel change. 76 */ 77 HAL_BOOL 78 ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode, 79 struct ieee80211_channel *chan, 80 HAL_BOOL bChannelChange, 81 HAL_RESET_TYPE resetType, 82 HAL_STATUS *status) 83 { 84 #define N(a) (sizeof (a) / sizeof (a[0])) 85 #define FAIL(_code) do { ecode = _code; goto bad; } while (0) 86 struct ath_hal_5212 *ahp = AH5212(ah); 87 HAL_CHANNEL_INTERNAL *ichan; 88 uint32_t saveDefAntenna, saveLedState; 89 uint32_t macStaId1; 90 uint16_t rfXpdGain[2]; 91 HAL_STATUS ecode; 92 uint32_t powerVal, rssiThrReg; 93 uint32_t ackTpcPow, ctsTpcPow, chirpTpcPow; 94 int i; 95 uint64_t tsf = 0; 96 97 OS_MARK(ah, AH_MARK_RESET, bChannelChange); 98 99 /* Bring out of sleep mode */ 100 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 101 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip did not wakeup\n", 102 __func__); 103 FAIL(HAL_EIO); 104 } 105 106 /* 107 * Map public channel to private. 108 */ 109 ichan = ath_hal_checkchannel(ah, chan); 110 if (ichan == AH_NULL) 111 FAIL(HAL_EINVAL); 112 switch (opmode) { 113 case HAL_M_STA: 114 case HAL_M_IBSS: 115 case HAL_M_HOSTAP: 116 case HAL_M_MONITOR: 117 break; 118 default: 119 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n", 120 __func__, opmode); 121 FAIL(HAL_EINVAL); 122 break; 123 } 124 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); 125 126 /* Blank the channel survey statistics */ 127 ath_hal_survey_clear(ah); 128 129 /* XXX Turn on fast channel change for 5416 */ 130 131 /* 132 * Preserve the bmiss rssi threshold and count threshold 133 * across resets 134 */ 135 rssiThrReg = OS_REG_READ(ah, AR_RSSI_THR); 136 /* If reg is zero, first time thru set to default val */ 137 if (rssiThrReg == 0) 138 rssiThrReg = INIT_RSSI_THR; 139 140 /* 141 * Preserve the antenna on a channel change 142 */ 143 saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA); 144 145 /* 146 * Don't do this for the AR9285 - it breaks RX for single 147 * antenna designs when diversity is disabled. 148 * 149 * I'm not sure what this was working around; it may be 150 * something to do with the AR5416. Certainly this register 151 * isn't supposed to be used by the MIMO chips for anything 152 * except for defining the default antenna when an external 153 * phase array / smart antenna is connected. 154 * 155 * See PR: kern/179269 . 156 */ 157 if ((! AR_SREV_KITE(ah)) && saveDefAntenna == 0) /* XXX magic constants */ 158 saveDefAntenna = 1; 159 160 /* Save hardware flag before chip reset clears the register */ 161 macStaId1 = OS_REG_READ(ah, AR_STA_ID1) & 162 (AR_STA_ID1_BASE_RATE_11B | AR_STA_ID1_USE_DEFANT); 163 164 /* Save led state from pci config register */ 165 saveLedState = OS_REG_READ(ah, AR_MAC_LED) & 166 (AR_MAC_LED_ASSOC | AR_MAC_LED_MODE | 167 AR_MAC_LED_BLINK_THRESH_SEL | AR_MAC_LED_BLINK_SLOW); 168 169 /* For chips on which the RTC reset is done, save TSF before it gets cleared */ 170 if (AR_SREV_HOWL(ah) || 171 (AR_SREV_MERLIN(ah) && 172 ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) || 173 (resetType == HAL_RESET_FORCE_COLD) || 174 (resetType == HAL_RESET_BBPANIC) || 175 (ah->ah_config.ah_force_full_reset)) 176 tsf = ar5416GetTsf64(ah); 177 178 /* Mark PHY as inactive; marked active in ar5416InitBB() */ 179 ar5416MarkPhyInactive(ah); 180 181 if (!ar5416ChipReset(ah, chan, resetType)) { 182 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 183 FAIL(HAL_EIO); 184 } 185 186 /* Restore TSF */ 187 if (tsf) 188 ar5416SetTsf64(ah, tsf); 189 190 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 191 if (AR_SREV_MERLIN_10_OR_LATER(ah)) 192 OS_REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 193 194 AH5416(ah)->ah_writeIni(ah, chan); 195 196 if(AR_SREV_KIWI_13_OR_LATER(ah) ) { 197 /* Enable ASYNC FIFO */ 198 OS_REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, 199 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL); 200 OS_REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO); 201 OS_REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, 202 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); 203 OS_REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, 204 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); 205 } 206 207 /* Override ini values (that can be overriden in this fashion) */ 208 ar5416OverrideIni(ah, chan); 209 210 /* Setup 11n MAC/Phy mode registers */ 211 ar5416Set11nRegs(ah, chan); 212 213 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 214 215 /* 216 * Some AR91xx SoC devices frequently fail to accept TSF writes 217 * right after the chip reset. When that happens, write a new 218 * value after the initvals have been applied, with an offset 219 * based on measured time difference 220 */ 221 if (AR_SREV_HOWL(ah) && (ar5416GetTsf64(ah) < tsf)) { 222 tsf += 1500; 223 ar5416SetTsf64(ah, tsf); 224 } 225 226 HALDEBUG(ah, HAL_DEBUG_RESET, ">>>2 %s: AR_PHY_DAG_CTRLCCK=0x%x\n", 227 __func__, OS_REG_READ(ah,AR_PHY_DAG_CTRLCCK)); 228 HALDEBUG(ah, HAL_DEBUG_RESET, ">>>2 %s: AR_PHY_ADC_CTL=0x%x\n", 229 __func__, OS_REG_READ(ah,AR_PHY_ADC_CTL)); 230 231 /* 232 * This routine swaps the analog chains - it should be done 233 * before any radio register twiddling is done. 234 */ 235 ar5416InitChainMasks(ah); 236 237 /* Setup the open-loop power calibration if required */ 238 if (ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) { 239 AH5416(ah)->ah_olcInit(ah); 240 AH5416(ah)->ah_olcTempCompensation(ah); 241 } 242 243 /* Setup the transmit power values. */ 244 if (!ah->ah_setTxPower(ah, chan, rfXpdGain)) { 245 HALDEBUG(ah, HAL_DEBUG_ANY, 246 "%s: error init'ing transmit power\n", __func__); 247 FAIL(HAL_EIO); 248 } 249 250 /* Write the analog registers */ 251 if (!ahp->ah_rfHal->setRfRegs(ah, chan, 252 IEEE80211_IS_CHAN_2GHZ(chan) ? 2: 1, rfXpdGain)) { 253 HALDEBUG(ah, HAL_DEBUG_ANY, 254 "%s: ar5212SetRfRegs failed\n", __func__); 255 FAIL(HAL_EIO); 256 } 257 258 /* Write delta slope for OFDM enabled modes (A, G, Turbo) */ 259 if (IEEE80211_IS_CHAN_OFDM(chan)|| IEEE80211_IS_CHAN_HT(chan)) 260 ar5416SetDeltaSlope(ah, chan); 261 262 AH5416(ah)->ah_spurMitigate(ah, chan); 263 264 /* Setup board specific options for EEPROM version 3 */ 265 if (!ah->ah_setBoardValues(ah, chan)) { 266 HALDEBUG(ah, HAL_DEBUG_ANY, 267 "%s: error setting board options\n", __func__); 268 FAIL(HAL_EIO); 269 } 270 271 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 272 273 OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr)); 274 OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4) 275 | macStaId1 276 | AR_STA_ID1_RTS_USE_DEF 277 | ahp->ah_staId1Defaults 278 ); 279 ar5212SetOperatingMode(ah, opmode); 280 281 /* Set Venice BSSID mask according to current state */ 282 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask)); 283 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4)); 284 285 /* Restore previous led state */ 286 if (AR_SREV_HOWL(ah)) 287 OS_REG_WRITE(ah, AR_MAC_LED, 288 AR_MAC_LED_ASSOC_ACTIVE | AR_CFG_SCLK_32KHZ); 289 else 290 OS_REG_WRITE(ah, AR_MAC_LED, OS_REG_READ(ah, AR_MAC_LED) | 291 saveLedState); 292 293 /* Start TSF2 for generic timer 8-15 */ 294 #ifdef NOTYET 295 if (AR_SREV_KIWI(ah)) 296 ar5416StartTsf2(ah); 297 #endif 298 299 /* 300 * Enable Bluetooth Coexistence if it's enabled. 301 */ 302 if (AH5416(ah)->ah_btCoexConfigType != HAL_BT_COEX_CFG_NONE) 303 ar5416InitBTCoex(ah); 304 305 /* Restore previous antenna */ 306 OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 307 308 /* then our BSSID and associate id */ 309 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); 310 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) | 311 (ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S); 312 313 /* Restore bmiss rssi & count thresholds */ 314 OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr); 315 316 OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */ 317 318 /* Restore bmiss rssi & count thresholds */ 319 OS_REG_WRITE(ah, AR_RSSI_THR, rssiThrReg); 320 321 if (!ar5212SetChannel(ah, chan)) 322 FAIL(HAL_EIO); 323 324 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 325 326 /* Set 1:1 QCU to DCU mapping for all queues */ 327 for (i = 0; i < AR_NUM_DCU; i++) 328 OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 329 330 ahp->ah_intrTxqs = 0; 331 for (i = 0; i < AH_PRIVATE(ah)->ah_caps.halTotalQueues; i++) 332 ah->ah_resetTxQueue(ah, i); 333 334 ar5416InitIMR(ah, opmode); 335 ar5416SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1); 336 ar5416InitQoS(ah); 337 /* This may override the AR_DIAG_SW register */ 338 ar5416InitUserSettings(ah); 339 340 /* XXX this won't work for AR9287! */ 341 if (IEEE80211_IS_CHAN_HALF(chan) || IEEE80211_IS_CHAN_QUARTER(chan)) { 342 ar5416SetIFSTiming(ah, chan); 343 #if 0 344 /* 345 * AR5413? 346 * Force window_length for 1/2 and 1/4 rate channels, 347 * the ini file sets this to zero otherwise. 348 */ 349 OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, 350 AR_PHY_FRAME_CTL_WINLEN, 3); 351 } 352 #endif 353 } 354 355 if (AR_SREV_KIWI_13_OR_LATER(ah)) { 356 /* 357 * Enable ASYNC FIFO 358 * 359 * If Async FIFO is enabled, the following counters change 360 * as MAC now runs at 117 Mhz instead of 88/44MHz when 361 * async FIFO is disabled. 362 * 363 * Overwrite the delay/timeouts initialized in ProcessIni() 364 * above. 365 */ 366 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 367 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR); 368 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, 369 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR); 370 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 371 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR); 372 373 OS_REG_WRITE(ah, AR_TIME_OUT, 374 AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR); 375 OS_REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR); 376 377 OS_REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 378 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 379 OS_REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 380 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 381 } 382 383 if (AR_SREV_KIWI_13_OR_LATER(ah)) { 384 /* Enable AGGWEP to accelerate encryption engine */ 385 OS_REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 386 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 387 } 388 389 390 /* 391 * disable seq number generation in hw 392 */ 393 OS_REG_WRITE(ah, AR_STA_ID1, 394 OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); 395 396 ar5416InitDMA(ah); 397 398 /* 399 * program OBS bus to see MAC interrupts 400 */ 401 OS_REG_WRITE(ah, AR_OBS, 8); 402 403 /* 404 * Disable the "general" TX/RX mitigation timers. 405 */ 406 OS_REG_WRITE(ah, AR_MIRT, 0); 407 408 #ifdef AH_AR5416_INTERRUPT_MITIGATION 409 /* 410 * This initialises the RX interrupt mitigation timers. 411 * 412 * The mitigation timers begin at idle and are triggered 413 * upon the RXOK of a single frame (or sub-frame, for A-MPDU.) 414 * Then, the RX mitigation interrupt will fire: 415 * 416 * + 250uS after the last RX'ed frame, or 417 * + 700uS after the first RX'ed frame 418 * 419 * Thus, the LAST field dictates the extra latency 420 * induced by the RX mitigation method and the FIRST 421 * field dictates how long to delay before firing an 422 * RX mitigation interrupt. 423 * 424 * Please note this only seems to be for RXOK frames; 425 * not CRC or PHY error frames. 426 * 427 */ 428 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 250); 429 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 700); 430 #endif 431 ar5416InitBB(ah, chan); 432 433 /* Setup compression registers */ 434 ar5212SetCompRegs(ah); /* XXX not needed? */ 435 436 /* 437 * 5416 baseband will check the per rate power table 438 * and select the lower of the two 439 */ 440 ackTpcPow = 63; 441 ctsTpcPow = 63; 442 chirpTpcPow = 63; 443 powerVal = SM(ackTpcPow, AR_TPC_ACK) | 444 SM(ctsTpcPow, AR_TPC_CTS) | 445 SM(chirpTpcPow, AR_TPC_CHIRP); 446 OS_REG_WRITE(ah, AR_TPC, powerVal); 447 448 if (!ar5416InitCal(ah, chan)) 449 FAIL(HAL_ESELFTEST); 450 451 ar5416RestoreChainMask(ah); 452 453 AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */ 454 455 if (bChannelChange && !IEEE80211_IS_CHAN_DFS(chan)) 456 chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT; 457 458 if (AR_SREV_HOWL(ah)) { 459 /* 460 * Enable the MBSSID block-ack fix for HOWL. 461 * This feature is only supported on Howl 1.4, but it is safe to 462 * set bit 22 of STA_ID1 on other Howl revisions (1.1, 1.2, 1.3), 463 * since bit 22 is unused in those Howl revisions. 464 */ 465 unsigned int reg; 466 reg = (OS_REG_READ(ah, AR_STA_ID1) | (1<<22)); 467 OS_REG_WRITE(ah,AR_STA_ID1, reg); 468 ath_hal_printf(ah, "MBSSID Set bit 22 of AR_STA_ID 0x%x\n", reg); 469 } 470 471 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__); 472 473 OS_MARK(ah, AH_MARK_RESET_DONE, 0); 474 475 return AH_TRUE; 476 bad: 477 OS_MARK(ah, AH_MARK_RESET_DONE, ecode); 478 if (status != AH_NULL) 479 *status = ecode; 480 return AH_FALSE; 481 #undef FAIL 482 #undef N 483 } 484 485 #if 0 486 /* 487 * This channel change evaluates whether the selected hardware can 488 * perform a synthesizer-only channel change (no reset). If the 489 * TX is not stopped, or the RFBus cannot be granted in the given 490 * time, the function returns false as a reset is necessary 491 */ 492 HAL_BOOL 493 ar5416ChannelChange(struct ath_hal *ah, const structu ieee80211_channel *chan) 494 { 495 uint32_t ulCount; 496 uint32_t data, synthDelay, qnum; 497 uint16_t rfXpdGain[4]; 498 struct ath_hal_5212 *ahp = AH5212(ah); 499 HAL_CHANNEL_INTERNAL *ichan; 500 501 /* 502 * Map public channel to private. 503 */ 504 ichan = ath_hal_checkchannel(ah, chan); 505 506 /* TX must be stopped or RF Bus grant will not work */ 507 for (qnum = 0; qnum < AH_PRIVATE(ah)->ah_caps.halTotalQueues; qnum++) { 508 if (ar5212NumTxPending(ah, qnum)) { 509 HALDEBUG(ah, HAL_DEBUG_ANY, 510 "%s: frames pending on queue %d\n", __func__, qnum); 511 return AH_FALSE; 512 } 513 } 514 515 /* 516 * Kill last Baseband Rx Frame - Request analog bus grant 517 */ 518 OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_REQUEST); 519 if (!ath_hal_wait(ah, AR_PHY_RFBUS_GNT, AR_PHY_RFBUS_GRANT_EN, AR_PHY_RFBUS_GRANT_EN)) { 520 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: could not kill baseband rx\n", 521 __func__); 522 return AH_FALSE; 523 } 524 525 ar5416Set11nRegs(ah, chan); /* NB: setup 5416-specific regs */ 526 527 /* Change the synth */ 528 if (!ar5212SetChannel(ah, chan)) 529 return AH_FALSE; 530 531 /* Setup the transmit power values. */ 532 if (!ah->ah_setTxPower(ah, chan, rfXpdGain)) { 533 HALDEBUG(ah, HAL_DEBUG_ANY, 534 "%s: error init'ing transmit power\n", __func__); 535 return AH_FALSE; 536 } 537 538 /* 539 * Wait for the frequency synth to settle (synth goes on 540 * via PHY_ACTIVE_EN). Read the phy active delay register. 541 * Value is in 100ns increments. 542 */ 543 data = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 544 if (IS_CHAN_CCK(ichan)) { 545 synthDelay = (4 * data) / 22; 546 } else { 547 synthDelay = data / 10; 548 } 549 550 OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY); 551 552 /* Release the RFBus Grant */ 553 OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 554 555 /* Write delta slope for OFDM enabled modes (A, G, Turbo) */ 556 if (IEEE80211_IS_CHAN_OFDM(ichan)|| IEEE80211_IS_CHAN_HT(chan)) { 557 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3); 558 ar5212SetSpurMitigation(ah, chan); 559 ar5416SetDeltaSlope(ah, chan); 560 } 561 562 /* XXX spur mitigation for Melin */ 563 564 if (!IEEE80211_IS_CHAN_DFS(chan)) 565 chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT; 566 567 ichan->channel_time = 0; 568 ichan->tsf_last = ar5416GetTsf64(ah); 569 ar5212TxEnable(ah, AH_TRUE); 570 return AH_TRUE; 571 } 572 #endif 573 574 static void 575 ar5416InitDMA(struct ath_hal *ah) 576 { 577 struct ath_hal_5212 *ahp = AH5212(ah); 578 579 /* 580 * set AHB_MODE not to do cacheline prefetches 581 */ 582 OS_REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 583 584 /* 585 * let mac dma reads be in 128 byte chunks 586 */ 587 OS_REG_WRITE(ah, AR_TXCFG, 588 (OS_REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK) | AR_TXCFG_DMASZ_128B); 589 590 /* 591 * let mac dma writes be in 128 byte chunks 592 */ 593 /* 594 * XXX If you change this, you must change the headroom 595 * assigned in ah_maxTxTrigLev - see ar5416InitState(). 596 */ 597 OS_REG_WRITE(ah, AR_RXCFG, 598 (OS_REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK) | AR_RXCFG_DMASZ_128B); 599 600 /* restore TX trigger level */ 601 OS_REG_WRITE(ah, AR_TXCFG, 602 (OS_REG_READ(ah, AR_TXCFG) &~ AR_FTRIG) | 603 SM(ahp->ah_txTrigLev, AR_FTRIG)); 604 605 /* 606 * Setup receive FIFO threshold to hold off TX activities 607 */ 608 OS_REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 609 610 /* 611 * reduce the number of usable entries in PCU TXBUF to avoid 612 * wrap around. 613 */ 614 if (AR_SREV_KITE(ah)) 615 /* 616 * For AR9285 the number of Fifos are reduced to half. 617 * So set the usable tx buf size also to half to 618 * avoid data/delimiter underruns 619 */ 620 OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL, AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); 621 else 622 OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL, AR_PCU_TXBUF_CTRL_USABLE_SIZE); 623 } 624 625 static void 626 ar5416InitBB(struct ath_hal *ah, const struct ieee80211_channel *chan) 627 { 628 uint32_t synthDelay; 629 630 /* 631 * Wait for the frequency synth to settle (synth goes on 632 * via AR_PHY_ACTIVE_EN). Read the phy active delay register. 633 * Value is in 100ns increments. 634 */ 635 synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 636 if (IEEE80211_IS_CHAN_CCK(chan)) { 637 synthDelay = (4 * synthDelay) / 22; 638 } else { 639 synthDelay /= 10; 640 } 641 642 /* Turn on PLL on 5416 */ 643 HALDEBUG(ah, HAL_DEBUG_RESET, "%s %s channel\n", 644 __func__, IEEE80211_IS_CHAN_5GHZ(chan) ? "5GHz" : "2GHz"); 645 646 /* Activate the PHY (includes baseband activate and synthesizer on) */ 647 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 648 649 /* 650 * If the AP starts the calibration before the base band timeout 651 * completes we could get rx_clear false triggering. Add an 652 * extra BASE_ACTIVATE_DELAY usecs to ensure this condition 653 * does not happen. 654 */ 655 if (IEEE80211_IS_CHAN_HALF(chan)) { 656 OS_DELAY((synthDelay << 1) + BASE_ACTIVATE_DELAY); 657 } else if (IEEE80211_IS_CHAN_QUARTER(chan)) { 658 OS_DELAY((synthDelay << 2) + BASE_ACTIVATE_DELAY); 659 } else { 660 OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY); 661 } 662 } 663 664 static void 665 ar5416InitIMR(struct ath_hal *ah, HAL_OPMODE opmode) 666 { 667 struct ath_hal_5212 *ahp = AH5212(ah); 668 669 /* 670 * Setup interrupt handling. Note that ar5212ResetTxQueue 671 * manipulates the secondary IMR's as queues are enabled 672 * and disabled. This is done with RMW ops to insure the 673 * settings we make here are preserved. 674 */ 675 ahp->ah_maskReg = AR_IMR_TXERR | AR_IMR_TXURN 676 | AR_IMR_RXERR | AR_IMR_RXORN 677 | AR_IMR_BCNMISC; 678 679 #ifdef AH_AR5416_INTERRUPT_MITIGATION 680 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 681 #else 682 ahp->ah_maskReg |= AR_IMR_RXOK; 683 #endif 684 ahp->ah_maskReg |= AR_IMR_TXOK; 685 686 if (opmode == HAL_M_HOSTAP) 687 ahp->ah_maskReg |= AR_IMR_MIB; 688 OS_REG_WRITE(ah, AR_IMR, ahp->ah_maskReg); 689 690 #ifdef ADRIAN_NOTYET 691 /* This is straight from ath9k */ 692 if (! AR_SREV_HOWL(ah)) { 693 OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 694 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); 695 OS_REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 696 } 697 #endif 698 699 /* Enable bus errors that are OR'd to set the HIUERR bit */ 700 #if 0 701 OS_REG_WRITE(ah, AR_IMR_S2, 702 OS_REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT | AR_IMR_S2_CST); 703 #endif 704 } 705 706 static void 707 ar5416InitQoS(struct ath_hal *ah) 708 { 709 /* QoS support */ 710 OS_REG_WRITE(ah, AR_QOS_CONTROL, 0x100aa); /* XXX magic */ 711 OS_REG_WRITE(ah, AR_QOS_SELECT, 0x3210); /* XXX magic */ 712 713 /* Turn on NOACK Support for QoS packets */ 714 OS_REG_WRITE(ah, AR_NOACK, 715 SM(2, AR_NOACK_2BIT_VALUE) | 716 SM(5, AR_NOACK_BIT_OFFSET) | 717 SM(0, AR_NOACK_BYTE_OFFSET)); 718 719 /* 720 * initialize TXOP for all TIDs 721 */ 722 OS_REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 723 OS_REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 724 OS_REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 725 OS_REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 726 OS_REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 727 } 728 729 static void 730 ar5416InitUserSettings(struct ath_hal *ah) 731 { 732 struct ath_hal_5212 *ahp = AH5212(ah); 733 734 /* Restore user-specified settings */ 735 if (ahp->ah_miscMode != 0) 736 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) 737 | ahp->ah_miscMode); 738 if (ahp->ah_sifstime != (u_int) -1) 739 ar5212SetSifsTime(ah, ahp->ah_sifstime); 740 if (ahp->ah_slottime != (u_int) -1) 741 ar5212SetSlotTime(ah, ahp->ah_slottime); 742 if (ahp->ah_acktimeout != (u_int) -1) 743 ar5212SetAckTimeout(ah, ahp->ah_acktimeout); 744 if (ahp->ah_ctstimeout != (u_int) -1) 745 ar5212SetCTSTimeout(ah, ahp->ah_ctstimeout); 746 if (AH_PRIVATE(ah)->ah_diagreg != 0) 747 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); 748 if (AH5416(ah)->ah_globaltxtimeout != (u_int) -1) 749 ar5416SetGlobalTxTimeout(ah, AH5416(ah)->ah_globaltxtimeout); 750 } 751 752 static void 753 ar5416SetRfMode(struct ath_hal *ah, const struct ieee80211_channel *chan) 754 { 755 uint32_t rfMode; 756 757 if (chan == AH_NULL) 758 return; 759 760 /* treat channel B as channel G , no B mode suport in owl */ 761 rfMode = IEEE80211_IS_CHAN_CCK(chan) ? 762 AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; 763 764 if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { 765 /* phy mode bits for 5GHz channels require Fast Clock */ 766 rfMode |= AR_PHY_MODE_DYNAMIC 767 | AR_PHY_MODE_DYN_CCK_DISABLE; 768 } else if (!AR_SREV_MERLIN_10_OR_LATER(ah)) { 769 rfMode |= IEEE80211_IS_CHAN_5GHZ(chan) ? 770 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ; 771 } 772 773 OS_REG_WRITE(ah, AR_PHY_MODE, rfMode); 774 } 775 776 /* 777 * Places the hardware into reset and then pulls it out of reset 778 */ 779 HAL_BOOL 780 ar5416ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan, 781 HAL_RESET_TYPE resetType) 782 { 783 OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->ic_freq : 0); 784 /* 785 * Warm reset is optimistic for open-loop TX power control. 786 */ 787 if (AR_SREV_MERLIN(ah) && 788 ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) { 789 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) 790 return AH_FALSE; 791 } else if (ah->ah_config.ah_force_full_reset) { 792 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) 793 return AH_FALSE; 794 } else if ((resetType == HAL_RESET_FORCE_COLD) || 795 (resetType == HAL_RESET_BBPANIC)) { 796 HALDEBUG(ah, HAL_DEBUG_RESET, 797 "%s: full reset; resetType=%d\n", 798 __func__, resetType); 799 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) 800 return AH_FALSE; 801 } else { 802 if (!ar5416SetResetReg(ah, HAL_RESET_WARM)) 803 return AH_FALSE; 804 } 805 806 /* Bring out of sleep mode (AGAIN) */ 807 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 808 return AH_FALSE; 809 810 #ifdef notyet 811 ahp->ah_chipFullSleep = AH_FALSE; 812 #endif 813 814 AH5416(ah)->ah_initPLL(ah, chan); 815 816 /* 817 * Perform warm reset before the mode/PLL/turbo registers 818 * are changed in order to deactivate the radio. Mode changes 819 * with an active radio can result in corrupted shifts to the 820 * radio device. 821 */ 822 ar5416SetRfMode(ah, chan); 823 824 return AH_TRUE; 825 } 826 827 /* 828 * Delta slope coefficient computation. 829 * Required for OFDM operation. 830 */ 831 static void 832 ar5416GetDeltaSlopeValues(struct ath_hal *ah, uint32_t coef_scaled, 833 uint32_t *coef_mantissa, uint32_t *coef_exponent) 834 { 835 #define COEF_SCALE_S 24 836 uint32_t coef_exp, coef_man; 837 /* 838 * ALGO -> coef_exp = 14-floor(log2(coef)); 839 * floor(log2(x)) is the highest set bit position 840 */ 841 for (coef_exp = 31; coef_exp > 0; coef_exp--) 842 if ((coef_scaled >> coef_exp) & 0x1) 843 break; 844 /* A coef_exp of 0 is a legal bit position but an unexpected coef_exp */ 845 HALASSERT(coef_exp); 846 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 847 848 /* 849 * ALGO -> coef_man = floor(coef* 2^coef_exp+0.5); 850 * The coefficient is already shifted up for scaling 851 */ 852 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 853 854 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 855 *coef_exponent = coef_exp - 16; 856 857 #undef COEF_SCALE_S 858 } 859 860 void 861 ar5416SetDeltaSlope(struct ath_hal *ah, const struct ieee80211_channel *chan) 862 { 863 #define INIT_CLOCKMHZSCALED 0x64000000 864 uint32_t coef_scaled, ds_coef_exp, ds_coef_man; 865 uint32_t clockMhzScaled; 866 867 CHAN_CENTERS centers; 868 869 /* half and quarter rate can divide the scaled clock by 2 or 4 respectively */ 870 /* scale for selected channel bandwidth */ 871 clockMhzScaled = INIT_CLOCKMHZSCALED; 872 if (IEEE80211_IS_CHAN_TURBO(chan)) 873 clockMhzScaled <<= 1; 874 else if (IEEE80211_IS_CHAN_HALF(chan)) 875 clockMhzScaled >>= 1; 876 else if (IEEE80211_IS_CHAN_QUARTER(chan)) 877 clockMhzScaled >>= 2; 878 879 /* 880 * ALGO -> coef = 1e8/fcarrier*fclock/40; 881 * scaled coef to provide precision for this floating calculation 882 */ 883 ar5416GetChannelCenters(ah, chan, ¢ers); 884 coef_scaled = clockMhzScaled / centers.synth_center; 885 886 ar5416GetDeltaSlopeValues(ah, coef_scaled, &ds_coef_man, &ds_coef_exp); 887 888 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, 889 AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 890 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, 891 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 892 893 /* 894 * For Short GI, 895 * scaled coeff is 9/10 that of normal coeff 896 */ 897 coef_scaled = (9 * coef_scaled)/10; 898 899 ar5416GetDeltaSlopeValues(ah, coef_scaled, &ds_coef_man, &ds_coef_exp); 900 901 /* for short gi */ 902 OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI, 903 AR_PHY_HALFGI_DSC_MAN, ds_coef_man); 904 OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI, 905 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); 906 #undef INIT_CLOCKMHZSCALED 907 } 908 909 /* 910 * Set a limit on the overall output power. Used for dynamic 911 * transmit power control and the like. 912 * 913 * NB: limit is in units of 0.5 dbM. 914 */ 915 HAL_BOOL 916 ar5416SetTxPowerLimit(struct ath_hal *ah, uint32_t limit) 917 { 918 uint16_t dummyXpdGains[2]; 919 920 AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER); 921 return ah->ah_setTxPower(ah, AH_PRIVATE(ah)->ah_curchan, 922 dummyXpdGains); 923 } 924 925 HAL_BOOL 926 ar5416GetChipPowerLimits(struct ath_hal *ah, 927 struct ieee80211_channel *chan) 928 { 929 struct ath_hal_5212 *ahp = AH5212(ah); 930 int16_t minPower, maxPower; 931 932 /* 933 * Get Pier table max and min powers. 934 */ 935 if (ahp->ah_rfHal->getChannelMaxMinPower(ah, chan, &maxPower, &minPower)) { 936 /* NB: rf code returns 1/4 dBm units, convert */ 937 chan->ic_maxpower = maxPower / 2; 938 chan->ic_minpower = minPower / 2; 939 } else { 940 HALDEBUG(ah, HAL_DEBUG_ANY, 941 "%s: no min/max power for %u/0x%x\n", 942 __func__, chan->ic_freq, chan->ic_flags); 943 chan->ic_maxpower = AR5416_MAX_RATE_POWER; 944 chan->ic_minpower = 0; 945 } 946 HALDEBUG(ah, HAL_DEBUG_RESET, 947 "Chan %d: MaxPow = %d MinPow = %d\n", 948 chan->ic_freq, chan->ic_maxpower, chan->ic_minpower); 949 return AH_TRUE; 950 } 951 952 /************************************************************** 953 * ar5416WriteTxPowerRateRegisters 954 * 955 * Write the TX power rate registers from the raw values given 956 * in ratesArray[]. 957 * 958 * The CCK and HT40 rate registers are only written if needed. 959 * HT20 and 11g/11a OFDM rate registers are always written. 960 * 961 * The values written are raw values which should be written 962 * to the registers - so it's up to the caller to pre-adjust 963 * them (eg CCK power offset value, or Merlin TX power offset, 964 * etc.) 965 */ 966 void 967 ar5416WriteTxPowerRateRegisters(struct ath_hal *ah, 968 const struct ieee80211_channel *chan, const int16_t ratesArray[]) 969 { 970 #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) 971 972 /* Write the OFDM power per rate set */ 973 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 974 POW_SM(ratesArray[rate18mb], 24) 975 | POW_SM(ratesArray[rate12mb], 16) 976 | POW_SM(ratesArray[rate9mb], 8) 977 | POW_SM(ratesArray[rate6mb], 0) 978 ); 979 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, 980 POW_SM(ratesArray[rate54mb], 24) 981 | POW_SM(ratesArray[rate48mb], 16) 982 | POW_SM(ratesArray[rate36mb], 8) 983 | POW_SM(ratesArray[rate24mb], 0) 984 ); 985 986 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 987 /* Write the CCK power per rate set */ 988 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, 989 POW_SM(ratesArray[rate2s], 24) 990 | POW_SM(ratesArray[rate2l], 16) 991 | POW_SM(ratesArray[rateXr], 8) /* XR target power */ 992 | POW_SM(ratesArray[rate1l], 0) 993 ); 994 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, 995 POW_SM(ratesArray[rate11s], 24) 996 | POW_SM(ratesArray[rate11l], 16) 997 | POW_SM(ratesArray[rate5_5s], 8) 998 | POW_SM(ratesArray[rate5_5l], 0) 999 ); 1000 HALDEBUG(ah, HAL_DEBUG_RESET, 1001 "%s AR_PHY_POWER_TX_RATE3=0x%x AR_PHY_POWER_TX_RATE4=0x%x\n", 1002 __func__, OS_REG_READ(ah,AR_PHY_POWER_TX_RATE3), 1003 OS_REG_READ(ah,AR_PHY_POWER_TX_RATE4)); 1004 } 1005 1006 /* Write the HT20 power per rate set */ 1007 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, 1008 POW_SM(ratesArray[rateHt20_3], 24) 1009 | POW_SM(ratesArray[rateHt20_2], 16) 1010 | POW_SM(ratesArray[rateHt20_1], 8) 1011 | POW_SM(ratesArray[rateHt20_0], 0) 1012 ); 1013 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, 1014 POW_SM(ratesArray[rateHt20_7], 24) 1015 | POW_SM(ratesArray[rateHt20_6], 16) 1016 | POW_SM(ratesArray[rateHt20_5], 8) 1017 | POW_SM(ratesArray[rateHt20_4], 0) 1018 ); 1019 1020 if (IEEE80211_IS_CHAN_HT40(chan)) { 1021 /* Write the HT40 power per rate set */ 1022 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, 1023 POW_SM(ratesArray[rateHt40_3], 24) 1024 | POW_SM(ratesArray[rateHt40_2], 16) 1025 | POW_SM(ratesArray[rateHt40_1], 8) 1026 | POW_SM(ratesArray[rateHt40_0], 0) 1027 ); 1028 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, 1029 POW_SM(ratesArray[rateHt40_7], 24) 1030 | POW_SM(ratesArray[rateHt40_6], 16) 1031 | POW_SM(ratesArray[rateHt40_5], 8) 1032 | POW_SM(ratesArray[rateHt40_4], 0) 1033 ); 1034 /* Write the Dup/Ext 40 power per rate set */ 1035 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, 1036 POW_SM(ratesArray[rateExtOfdm], 24) 1037 | POW_SM(ratesArray[rateExtCck], 16) 1038 | POW_SM(ratesArray[rateDupOfdm], 8) 1039 | POW_SM(ratesArray[rateDupCck], 0) 1040 ); 1041 } 1042 1043 /* 1044 * Set max power to 30 dBm and, optionally, 1045 * enable TPC in tx descriptors. 1046 */ 1047 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, MAX_RATE_POWER | 1048 (AH5212(ah)->ah_tpcEnabled ? AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE : 0)); 1049 #undef POW_SM 1050 } 1051 1052 1053 /************************************************************** 1054 * ar5416SetTransmitPower 1055 * 1056 * Set the transmit power in the baseband for the given 1057 * operating channel and mode. 1058 */ 1059 HAL_BOOL 1060 ar5416SetTransmitPower(struct ath_hal *ah, 1061 const struct ieee80211_channel *chan, uint16_t *rfXpdGain) 1062 { 1063 #define N(a) (sizeof (a) / sizeof (a[0])) 1064 #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) 1065 1066 MODAL_EEP_HEADER *pModal; 1067 struct ath_hal_5212 *ahp = AH5212(ah); 1068 int16_t txPowerIndexOffset = 0; 1069 int i; 1070 1071 uint16_t cfgCtl; 1072 uint16_t powerLimit; 1073 uint16_t twiceAntennaReduction; 1074 uint16_t twiceMaxRegulatoryPower; 1075 int16_t maxPower; 1076 HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom; 1077 struct ar5416eeprom *pEepData = &ee->ee_base; 1078 1079 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); 1080 1081 /* 1082 * Default to 2, is overridden based on the EEPROM version / value. 1083 */ 1084 AH5416(ah)->ah_ht40PowerIncForPdadc = 2; 1085 1086 /* Setup info for the actual eeprom */ 1087 OS_MEMZERO(AH5416(ah)->ah_ratesArray, sizeof(AH5416(ah)->ah_ratesArray)); 1088 cfgCtl = ath_hal_getctl(ah, chan); 1089 powerLimit = chan->ic_maxregpower * 2; 1090 twiceAntennaReduction = chan->ic_maxantgain; 1091 twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 1092 pModal = &pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)]; 1093 HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n", 1094 __func__,chan->ic_freq, cfgCtl ); 1095 1096 if (IS_EEP_MINOR_V2(ah)) { 1097 AH5416(ah)->ah_ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; 1098 } 1099 1100 if (!ar5416SetPowerPerRateTable(ah, pEepData, chan, 1101 &AH5416(ah)->ah_ratesArray[0], 1102 cfgCtl, 1103 twiceAntennaReduction, 1104 twiceMaxRegulatoryPower, powerLimit)) { 1105 HALDEBUG(ah, HAL_DEBUG_ANY, 1106 "%s: unable to set tx power per rate table\n", __func__); 1107 return AH_FALSE; 1108 } 1109 1110 if (!AH5416(ah)->ah_setPowerCalTable(ah, pEepData, chan, &txPowerIndexOffset)) { 1111 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n", 1112 __func__); 1113 return AH_FALSE; 1114 } 1115 1116 maxPower = AH_MAX(AH5416(ah)->ah_ratesArray[rate6mb], 1117 AH5416(ah)->ah_ratesArray[rateHt20_0]); 1118 1119 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 1120 maxPower = AH_MAX(maxPower, AH5416(ah)->ah_ratesArray[rate1l]); 1121 } 1122 1123 if (IEEE80211_IS_CHAN_HT40(chan)) { 1124 maxPower = AH_MAX(maxPower, AH5416(ah)->ah_ratesArray[rateHt40_0]); 1125 } 1126 1127 ahp->ah_tx6PowerInHalfDbm = maxPower; 1128 AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower; 1129 ahp->ah_txPowerIndexOffset = txPowerIndexOffset; 1130 1131 /* 1132 * txPowerIndexOffset is set by the SetPowerTable() call - 1133 * adjust the rate table (0 offset if rates EEPROM not loaded) 1134 */ 1135 for (i = 0; i < N(AH5416(ah)->ah_ratesArray); i++) { 1136 AH5416(ah)->ah_ratesArray[i] = 1137 (int16_t)(txPowerIndexOffset + AH5416(ah)->ah_ratesArray[i]); 1138 if (AH5416(ah)->ah_ratesArray[i] > AR5416_MAX_RATE_POWER) 1139 AH5416(ah)->ah_ratesArray[i] = AR5416_MAX_RATE_POWER; 1140 } 1141 1142 #ifdef AH_EEPROM_DUMP 1143 /* 1144 * Dump the rate array whilst it represents the intended dBm*2 1145 * values versus what's being adjusted before being programmed 1146 * in. Keep this in mind if you code up this function and enable 1147 * this debugging; the values won't necessarily be what's being 1148 * programmed into the hardware. 1149 */ 1150 ar5416PrintPowerPerRate(ah, AH5416(ah)->ah_ratesArray); 1151 #endif 1152 1153 /* 1154 * Merlin and later have a power offset, so subtract 1155 * pwr_table_offset * 2 from each value. The default 1156 * power offset is -5 dBm - ie, a register value of 0 1157 * equates to a TX power of -5 dBm. 1158 */ 1159 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 1160 int8_t pwr_table_offset; 1161 1162 (void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, 1163 &pwr_table_offset); 1164 /* Underflow power gets clamped at raw value 0 */ 1165 /* Overflow power gets camped at AR5416_MAX_RATE_POWER */ 1166 for (i = 0; i < N(AH5416(ah)->ah_ratesArray); i++) { 1167 /* 1168 * + pwr_table_offset is in dBm 1169 * + ratesArray is in 1/2 dBm 1170 */ 1171 AH5416(ah)->ah_ratesArray[i] -= (pwr_table_offset * 2); 1172 if (AH5416(ah)->ah_ratesArray[i] < 0) 1173 AH5416(ah)->ah_ratesArray[i] = 0; 1174 else if (AH5416(ah)->ah_ratesArray[i] > AR5416_MAX_RATE_POWER) 1175 AH5416(ah)->ah_ratesArray[i] = AR5416_MAX_RATE_POWER; 1176 } 1177 } 1178 1179 /* 1180 * Adjust rates for OLC where needed 1181 * 1182 * The following CCK rates need adjusting when doing 2.4ghz 1183 * CCK transmission. 1184 * 1185 * + rate2s, rate2l, rate1l, rate11s, rate11l, rate5_5s, rate5_5l 1186 * + rateExtCck, rateDupCck 1187 * 1188 * They're adjusted here regardless. The hardware then gets 1189 * programmed as needed. 5GHz operation doesn't program in CCK 1190 * rates for legacy mode but they seem to be initialised for 1191 * HT40 regardless of channel type. 1192 */ 1193 if (AR_SREV_MERLIN_20_OR_LATER(ah) && 1194 ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) { 1195 int adj[] = { 1196 rate2s, rate2l, rate1l, rate11s, rate11l, 1197 rate5_5s, rate5_5l, rateExtCck, rateDupCck 1198 }; 1199 int cck_ofdm_delta = 2; 1200 int i; 1201 for (i = 0; i < N(adj); i++) { 1202 AH5416(ah)->ah_ratesArray[adj[i]] -= cck_ofdm_delta; 1203 if (AH5416(ah)->ah_ratesArray[adj[i]] < 0) 1204 AH5416(ah)->ah_ratesArray[adj[i]] = 0; 1205 } 1206 } 1207 1208 /* 1209 * Adjust the HT40 power to meet the correct target TX power 1210 * for 40MHz mode, based on TX power curves that are established 1211 * for 20MHz mode. 1212 * 1213 * XXX handle overflow/too high power level? 1214 */ 1215 if (IEEE80211_IS_CHAN_HT40(chan)) { 1216 AH5416(ah)->ah_ratesArray[rateHt40_0] += 1217 AH5416(ah)->ah_ht40PowerIncForPdadc; 1218 AH5416(ah)->ah_ratesArray[rateHt40_1] += 1219 AH5416(ah)->ah_ht40PowerIncForPdadc; 1220 AH5416(ah)->ah_ratesArray[rateHt40_2] += AH5416(ah)->ah_ht40PowerIncForPdadc; 1221 AH5416(ah)->ah_ratesArray[rateHt40_3] += AH5416(ah)->ah_ht40PowerIncForPdadc; 1222 AH5416(ah)->ah_ratesArray[rateHt40_4] += AH5416(ah)->ah_ht40PowerIncForPdadc; 1223 AH5416(ah)->ah_ratesArray[rateHt40_5] += AH5416(ah)->ah_ht40PowerIncForPdadc; 1224 AH5416(ah)->ah_ratesArray[rateHt40_6] += AH5416(ah)->ah_ht40PowerIncForPdadc; 1225 AH5416(ah)->ah_ratesArray[rateHt40_7] += AH5416(ah)->ah_ht40PowerIncForPdadc; 1226 } 1227 1228 /* Write the TX power rate registers */ 1229 ar5416WriteTxPowerRateRegisters(ah, chan, AH5416(ah)->ah_ratesArray); 1230 1231 /* Write the Power subtraction for dynamic chain changing, for per-packet powertx */ 1232 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, 1233 POW_SM(pModal->pwrDecreaseFor3Chain, 6) 1234 | POW_SM(pModal->pwrDecreaseFor2Chain, 0) 1235 ); 1236 return AH_TRUE; 1237 #undef POW_SM 1238 #undef N 1239 } 1240 1241 /* 1242 * Exported call to check for a recent gain reading and return 1243 * the current state of the thermal calibration gain engine. 1244 */ 1245 HAL_RFGAIN 1246 ar5416GetRfgain(struct ath_hal *ah) 1247 { 1248 1249 return (HAL_RFGAIN_INACTIVE); 1250 } 1251 1252 /* 1253 * Places all of hardware into reset 1254 */ 1255 HAL_BOOL 1256 ar5416Disable(struct ath_hal *ah) 1257 { 1258 1259 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 1260 return AH_FALSE; 1261 if (! ar5416SetResetReg(ah, HAL_RESET_COLD)) 1262 return AH_FALSE; 1263 1264 AH5416(ah)->ah_initPLL(ah, AH_NULL); 1265 return (AH_TRUE); 1266 } 1267 1268 /* 1269 * Places the PHY and Radio chips into reset. A full reset 1270 * must be called to leave this state. The PCI/MAC/PCU are 1271 * not placed into reset as we must receive interrupt to 1272 * re-enable the hardware. 1273 */ 1274 HAL_BOOL 1275 ar5416PhyDisable(struct ath_hal *ah) 1276 { 1277 1278 if (! ar5416SetResetReg(ah, HAL_RESET_WARM)) 1279 return AH_FALSE; 1280 1281 AH5416(ah)->ah_initPLL(ah, AH_NULL); 1282 return (AH_TRUE); 1283 } 1284 1285 /* 1286 * Write the given reset bit mask into the reset register 1287 */ 1288 HAL_BOOL 1289 ar5416SetResetReg(struct ath_hal *ah, uint32_t type) 1290 { 1291 /* 1292 * Set force wake 1293 */ 1294 OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1295 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1296 1297 switch (type) { 1298 case HAL_RESET_POWER_ON: 1299 return ar5416SetResetPowerOn(ah); 1300 case HAL_RESET_WARM: 1301 case HAL_RESET_COLD: 1302 return ar5416SetReset(ah, type); 1303 default: 1304 HALASSERT(AH_FALSE); 1305 return AH_FALSE; 1306 } 1307 } 1308 1309 static HAL_BOOL 1310 ar5416SetResetPowerOn(struct ath_hal *ah) 1311 { 1312 /* Power On Reset (Hard Reset) */ 1313 1314 /* 1315 * Set force wake 1316 * 1317 * If the MAC was running, previously calling 1318 * reset will wake up the MAC but it may go back to sleep 1319 * before we can start polling. 1320 * Set force wake stops that 1321 * This must be called before initiating a hard reset. 1322 */ 1323 OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1324 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1325 1326 /* 1327 * PowerOn reset can be used in open loop power control or failure recovery. 1328 * If we do RTC reset while DMA is still running, hardware may corrupt memory. 1329 * Therefore, we need to reset AHB first to stop DMA. 1330 */ 1331 if (! AR_SREV_HOWL(ah)) 1332 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB); 1333 /* 1334 * RTC reset and clear 1335 */ 1336 OS_REG_WRITE(ah, AR_RTC_RESET, 0); 1337 OS_DELAY(20); 1338 1339 if (! AR_SREV_HOWL(ah)) 1340 OS_REG_WRITE(ah, AR_RC, 0); 1341 1342 OS_REG_WRITE(ah, AR_RTC_RESET, 1); 1343 1344 /* 1345 * Poll till RTC is ON 1346 */ 1347 if (!ath_hal_wait(ah, AR_RTC_STATUS, AR_RTC_PM_STATUS_M, AR_RTC_STATUS_ON)) { 1348 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RTC not waking up\n", __func__); 1349 return AH_FALSE; 1350 } 1351 1352 return ar5416SetReset(ah, HAL_RESET_COLD); 1353 } 1354 1355 static HAL_BOOL 1356 ar5416SetReset(struct ath_hal *ah, int type) 1357 { 1358 uint32_t tmpReg, mask; 1359 uint32_t rst_flags; 1360 1361 #ifdef AH_SUPPORT_AR9130 /* Because of the AR9130 specific registers */ 1362 if (AR_SREV_HOWL(ah)) { 1363 HALDEBUG(ah, HAL_DEBUG_ANY, "[ath] HOWL: Fiddling with derived clk!\n"); 1364 uint32_t val = OS_REG_READ(ah, AR_RTC_DERIVED_CLK); 1365 val &= ~AR_RTC_DERIVED_CLK_PERIOD; 1366 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD); 1367 OS_REG_WRITE(ah, AR_RTC_DERIVED_CLK, val); 1368 (void) OS_REG_READ(ah, AR_RTC_DERIVED_CLK); 1369 } 1370 #endif /* AH_SUPPORT_AR9130 */ 1371 1372 /* 1373 * Force wake 1374 */ 1375 OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1376 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1377 1378 #ifdef AH_SUPPORT_AR9130 1379 if (AR_SREV_HOWL(ah)) { 1380 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1381 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1382 } else { 1383 #endif /* AH_SUPPORT_AR9130 */ 1384 /* 1385 * Reset AHB 1386 * 1387 * (In case the last interrupt source was a bus timeout.) 1388 * XXX TODO: this is not the way to do it! It should be recorded 1389 * XXX by the interrupt handler and passed _into_ the 1390 * XXX reset path routine so this occurs. 1391 */ 1392 tmpReg = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE); 1393 if (tmpReg & (AR_INTR_SYNC_LOCAL_TIMEOUT|AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1394 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1395 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB|AR_RC_HOSTIF); 1396 } else { 1397 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB); 1398 } 1399 rst_flags = AR_RTC_RC_MAC_WARM; 1400 if (type == HAL_RESET_COLD) 1401 rst_flags |= AR_RTC_RC_MAC_COLD; 1402 #ifdef AH_SUPPORT_AR9130 1403 } 1404 #endif /* AH_SUPPORT_AR9130 */ 1405 1406 OS_REG_WRITE(ah, AR_RTC_RC, rst_flags); 1407 1408 if (AR_SREV_HOWL(ah)) 1409 OS_DELAY(10000); 1410 else 1411 OS_DELAY(100); 1412 1413 /* 1414 * Clear resets and force wakeup 1415 */ 1416 OS_REG_WRITE(ah, AR_RTC_RC, 0); 1417 if (!ath_hal_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0)) { 1418 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RTC stuck in MAC reset\n", __func__); 1419 return AH_FALSE; 1420 } 1421 1422 /* Clear AHB reset */ 1423 if (! AR_SREV_HOWL(ah)) 1424 OS_REG_WRITE(ah, AR_RC, 0); 1425 1426 if (AR_SREV_HOWL(ah)) 1427 OS_DELAY(50); 1428 1429 if (AR_SREV_HOWL(ah)) { 1430 uint32_t mask; 1431 mask = OS_REG_READ(ah, AR_CFG); 1432 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1433 HALDEBUG(ah, HAL_DEBUG_RESET, 1434 "CFG Byte Swap Set 0x%x\n", mask); 1435 } else { 1436 mask = 1437 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1438 OS_REG_WRITE(ah, AR_CFG, mask); 1439 HALDEBUG(ah, HAL_DEBUG_RESET, 1440 "Setting CFG 0x%x\n", OS_REG_READ(ah, AR_CFG)); 1441 } 1442 } else { 1443 if (type == HAL_RESET_COLD) { 1444 if (isBigEndian()) { 1445 /* 1446 * Set CFG, little-endian for descriptor accesses. 1447 */ 1448 mask = INIT_CONFIG_STATUS | AR_CFG_SWRD; 1449 #ifndef AH_NEED_DESC_SWAP 1450 mask |= AR_CFG_SWTD; 1451 #endif 1452 HALDEBUG(ah, HAL_DEBUG_RESET, 1453 "%s Applying descriptor swap\n", __func__); 1454 OS_REG_WRITE(ah, AR_CFG, mask); 1455 } else 1456 OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS); 1457 } 1458 } 1459 1460 return AH_TRUE; 1461 } 1462 1463 void 1464 ar5416InitChainMasks(struct ath_hal *ah) 1465 { 1466 int rx_chainmask = AH5416(ah)->ah_rx_chainmask; 1467 1468 /* Flip this for this chainmask regardless of chip */ 1469 if (rx_chainmask == 0x5) 1470 OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN); 1471 1472 /* 1473 * Workaround for OWL 1.0 calibration failure; enable multi-chain; 1474 * then set true mask after calibration. 1475 */ 1476 if (IS_5416V1(ah) && (rx_chainmask == 0x5 || rx_chainmask == 0x3)) { 1477 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); 1478 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); 1479 } else { 1480 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, AH5416(ah)->ah_rx_chainmask); 1481 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, AH5416(ah)->ah_rx_chainmask); 1482 } 1483 OS_REG_WRITE(ah, AR_SELFGEN_MASK, AH5416(ah)->ah_tx_chainmask); 1484 1485 if (AH5416(ah)->ah_tx_chainmask == 0x5) 1486 OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN); 1487 1488 if (AR_SREV_HOWL(ah)) { 1489 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 1490 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); 1491 } 1492 } 1493 1494 /* 1495 * Work-around for Owl 1.0 calibration failure. 1496 * 1497 * ar5416InitChainMasks sets the RX chainmask to 0x7 if it's Owl 1.0 1498 * due to init calibration failures. ar5416RestoreChainMask restores 1499 * these registers to the correct setting. 1500 */ 1501 void 1502 ar5416RestoreChainMask(struct ath_hal *ah) 1503 { 1504 int rx_chainmask = AH5416(ah)->ah_rx_chainmask; 1505 1506 if (IS_5416V1(ah) && (rx_chainmask == 0x5 || rx_chainmask == 0x3)) { 1507 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 1508 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 1509 } 1510 } 1511 1512 void 1513 ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan) 1514 { 1515 uint32_t pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 1516 if (chan != AH_NULL) { 1517 if (IEEE80211_IS_CHAN_HALF(chan)) 1518 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); 1519 else if (IEEE80211_IS_CHAN_QUARTER(chan)) 1520 pll |= SM(0x2, AR_RTC_PLL_CLKSEL); 1521 1522 if (IEEE80211_IS_CHAN_5GHZ(chan)) 1523 pll |= SM(0xa, AR_RTC_PLL_DIV); 1524 else 1525 pll |= SM(0xb, AR_RTC_PLL_DIV); 1526 } else 1527 pll |= SM(0xb, AR_RTC_PLL_DIV); 1528 1529 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 1530 1531 /* TODO: 1532 * For multi-band owl, switch between bands by reiniting the PLL. 1533 */ 1534 1535 OS_DELAY(RTC_PLL_SETTLE_DELAY); 1536 1537 OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK); 1538 } 1539 1540 static void 1541 ar5416SetDefGainValues(struct ath_hal *ah, 1542 const MODAL_EEP_HEADER *pModal, 1543 const struct ar5416eeprom *eep, 1544 uint8_t txRxAttenLocal, int regChainOffset, int i) 1545 { 1546 1547 if (IS_EEP_MINOR_V3(ah)) { 1548 txRxAttenLocal = pModal->txRxAttenCh[i]; 1549 1550 if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 1551 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1552 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 1553 pModal->bswMargin[i]); 1554 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1555 AR_PHY_GAIN_2GHZ_XATTEN1_DB, 1556 pModal->bswAtten[i]); 1557 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1558 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 1559 pModal->xatten2Margin[i]); 1560 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1561 AR_PHY_GAIN_2GHZ_XATTEN2_DB, 1562 pModal->xatten2Db[i]); 1563 } else { 1564 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1565 AR_PHY_GAIN_2GHZ_BSW_MARGIN, 1566 pModal->bswMargin[i]); 1567 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1568 AR_PHY_GAIN_2GHZ_BSW_ATTEN, 1569 pModal->bswAtten[i]); 1570 } 1571 } 1572 1573 if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 1574 OS_REG_RMW_FIELD(ah, 1575 AR_PHY_RXGAIN + regChainOffset, 1576 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 1577 OS_REG_RMW_FIELD(ah, 1578 AR_PHY_RXGAIN + regChainOffset, 1579 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]); 1580 } else { 1581 OS_REG_RMW_FIELD(ah, 1582 AR_PHY_RXGAIN + regChainOffset, 1583 AR_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 1584 OS_REG_RMW_FIELD(ah, 1585 AR_PHY_GAIN_2GHZ + regChainOffset, 1586 AR_PHY_GAIN_2GHZ_RXTX_MARGIN, pModal->rxTxMarginCh[i]); 1587 } 1588 } 1589 1590 /* 1591 * Get the register chain offset for the given chain. 1592 * 1593 * Take into account the register chain swapping with AR5416 v2.0. 1594 * 1595 * XXX make sure that the reg chain swapping is only done for 1596 * XXX AR5416 v2.0 or greater, and not later chips? 1597 */ 1598 int 1599 ar5416GetRegChainOffset(struct ath_hal *ah, int i) 1600 { 1601 int regChainOffset; 1602 1603 if (AR_SREV_5416_V20_OR_LATER(ah) && 1604 (AH5416(ah)->ah_rx_chainmask == 0x5 || 1605 AH5416(ah)->ah_tx_chainmask == 0x5) && (i != 0)) { 1606 /* Regs are swapped from chain 2 to 1 for 5416 2_0 with 1607 * only chains 0 and 2 populated 1608 */ 1609 regChainOffset = (i == 1) ? 0x2000 : 0x1000; 1610 } else { 1611 regChainOffset = i * 0x1000; 1612 } 1613 1614 return regChainOffset; 1615 } 1616 1617 /* 1618 * Read EEPROM header info and program the device for correct operation 1619 * given the channel value. 1620 */ 1621 HAL_BOOL 1622 ar5416SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan) 1623 { 1624 const HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom; 1625 const struct ar5416eeprom *eep = &ee->ee_base; 1626 const MODAL_EEP_HEADER *pModal; 1627 int i, regChainOffset; 1628 uint8_t txRxAttenLocal; /* workaround for eeprom versions <= 14.2 */ 1629 1630 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); 1631 pModal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)]; 1632 1633 /* NB: workaround for eeprom versions <= 14.2 */ 1634 txRxAttenLocal = IEEE80211_IS_CHAN_2GHZ(chan) ? 23 : 44; 1635 1636 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon); 1637 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 1638 if (AR_SREV_MERLIN(ah)) { 1639 if (i >= 2) break; 1640 } 1641 regChainOffset = ar5416GetRegChainOffset(ah, i); 1642 1643 OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, pModal->antCtrlChain[i]); 1644 1645 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4 + regChainOffset, 1646 (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4 + regChainOffset) & 1647 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | 1648 SM(pModal->iqCalICh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | 1649 SM(pModal->iqCalQCh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 1650 1651 /* 1652 * Large signal upgrade, 1653 * If 14.3 or later EEPROM, use 1654 * txRxAttenLocal = pModal->txRxAttenCh[i] 1655 * else txRxAttenLocal is fixed value above. 1656 */ 1657 1658 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) 1659 ar5416SetDefGainValues(ah, pModal, eep, txRxAttenLocal, regChainOffset, i); 1660 1661 } 1662 1663 if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 1664 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 1665 OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH0, AR_AN_RF2G1_CH0_OB, pModal->ob); 1666 OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH0, AR_AN_RF2G1_CH0_DB, pModal->db); 1667 OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH1, AR_AN_RF2G1_CH1_OB, pModal->ob_ch1); 1668 OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH1, AR_AN_RF2G1_CH1_DB, pModal->db_ch1); 1669 } else { 1670 OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH0, AR_AN_RF5G1_CH0_OB5, pModal->ob); 1671 OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH0, AR_AN_RF5G1_CH0_DB5, pModal->db); 1672 OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH1, AR_AN_RF5G1_CH1_OB5, pModal->ob_ch1); 1673 OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH1, AR_AN_RF5G1_CH1_DB5, pModal->db_ch1); 1674 } 1675 OS_A_REG_RMW_FIELD(ah, AR_AN_TOP2, AR_AN_TOP2_XPABIAS_LVL, pModal->xpaBiasLvl); 1676 OS_A_REG_RMW_FIELD(ah, AR_AN_TOP2, AR_AN_TOP2_LOCALBIAS, 1677 !!(pModal->flagBits & AR5416_EEP_FLAG_LOCALBIAS)); 1678 OS_A_REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG, 1679 !!(pModal->flagBits & AR5416_EEP_FLAG_FORCEXPAON)); 1680 } 1681 1682 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->switchSettling); 1683 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize); 1684 1685 if (! AR_SREV_MERLIN_10_OR_LATER(ah)) 1686 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_PGA, pModal->pgaDesiredSize); 1687 1688 OS_REG_WRITE(ah, AR_PHY_RF_CTL4, 1689 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) 1690 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) 1691 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) 1692 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); 1693 1694 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, 1695 pModal->txEndToRxOn); 1696 1697 if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 1698 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, 1699 pModal->thresh62); 1700 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, 1701 pModal->thresh62); 1702 } else { 1703 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62, 1704 pModal->thresh62); 1705 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, AR_PHY_EXT_CCA_THRESH62, 1706 pModal->thresh62); 1707 } 1708 1709 /* Minor Version Specific application */ 1710 if (IS_EEP_MINOR_V2(ah)) { 1711 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START, 1712 pModal->txFrameToDataStart); 1713 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON, 1714 pModal->txFrameToPaOn); 1715 } 1716 1717 if (IS_EEP_MINOR_V3(ah) && IEEE80211_IS_CHAN_HT40(chan)) 1718 /* Overwrite switch settling with HT40 value */ 1719 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, 1720 pModal->swSettleHt40); 1721 1722 if (AR_SREV_MERLIN_20_OR_LATER(ah) && EEP_MINOR(ah) >= AR5416_EEP_MINOR_VER_19) 1723 OS_REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL, AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK, pModal->miscBits); 1724 1725 if (AR_SREV_MERLIN_20(ah) && EEP_MINOR(ah) >= AR5416_EEP_MINOR_VER_20) { 1726 if (IEEE80211_IS_CHAN_2GHZ(chan)) 1727 OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 1728 eep->baseEepHeader.dacLpMode); 1729 else if (eep->baseEepHeader.dacHiPwrMode_5G) 1730 OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0); 1731 else 1732 OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 1733 eep->baseEepHeader.dacLpMode); 1734 1735 OS_DELAY(100); 1736 1737 OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP, 1738 pModal->miscBits >> 2); 1739 OS_REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9, AR_PHY_TX_DESIRED_SCALE_CCK, 1740 eep->baseEepHeader.desiredScaleCCK); 1741 } 1742 1743 return (AH_TRUE); 1744 } 1745 1746 /* 1747 * Helper functions common for AP/CB/XB 1748 */ 1749 1750 /* 1751 * Set the target power array "ratesArray" from the 1752 * given set of target powers. 1753 * 1754 * This is used by the various chipset/EEPROM TX power 1755 * setup routines. 1756 */ 1757 void 1758 ar5416SetRatesArrayFromTargetPower(struct ath_hal *ah, 1759 const struct ieee80211_channel *chan, 1760 int16_t *ratesArray, 1761 const CAL_TARGET_POWER_LEG *targetPowerCck, 1762 const CAL_TARGET_POWER_LEG *targetPowerCckExt, 1763 const CAL_TARGET_POWER_LEG *targetPowerOfdm, 1764 const CAL_TARGET_POWER_LEG *targetPowerOfdmExt, 1765 const CAL_TARGET_POWER_HT *targetPowerHt20, 1766 const CAL_TARGET_POWER_HT *targetPowerHt40) 1767 { 1768 #define N(a) (sizeof(a)/sizeof(a[0])) 1769 int i; 1770 1771 /* Blank the rates array, to be consistent */ 1772 for (i = 0; i < Ar5416RateSize; i++) 1773 ratesArray[i] = 0; 1774 1775 /* Set rates Array from collected data */ 1776 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = 1777 ratesArray[rate18mb] = ratesArray[rate24mb] = 1778 targetPowerOfdm->tPow2x[0]; 1779 ratesArray[rate36mb] = targetPowerOfdm->tPow2x[1]; 1780 ratesArray[rate48mb] = targetPowerOfdm->tPow2x[2]; 1781 ratesArray[rate54mb] = targetPowerOfdm->tPow2x[3]; 1782 ratesArray[rateXr] = targetPowerOfdm->tPow2x[0]; 1783 1784 for (i = 0; i < N(targetPowerHt20->tPow2x); i++) { 1785 ratesArray[rateHt20_0 + i] = targetPowerHt20->tPow2x[i]; 1786 } 1787 1788 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 1789 ratesArray[rate1l] = targetPowerCck->tPow2x[0]; 1790 ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck->tPow2x[1]; 1791 ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck->tPow2x[2]; 1792 ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck->tPow2x[3]; 1793 } 1794 if (IEEE80211_IS_CHAN_HT40(chan)) { 1795 for (i = 0; i < N(targetPowerHt40->tPow2x); i++) { 1796 ratesArray[rateHt40_0 + i] = targetPowerHt40->tPow2x[i]; 1797 } 1798 ratesArray[rateDupOfdm] = targetPowerHt40->tPow2x[0]; 1799 ratesArray[rateDupCck] = targetPowerHt40->tPow2x[0]; 1800 ratesArray[rateExtOfdm] = targetPowerOfdmExt->tPow2x[0]; 1801 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 1802 ratesArray[rateExtCck] = targetPowerCckExt->tPow2x[0]; 1803 } 1804 } 1805 #undef N 1806 } 1807 1808 /* 1809 * ar5416SetPowerPerRateTable 1810 * 1811 * Sets the transmit power in the baseband for the given 1812 * operating channel and mode. 1813 */ 1814 static HAL_BOOL 1815 ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData, 1816 const struct ieee80211_channel *chan, 1817 int16_t *ratesArray, uint16_t cfgCtl, 1818 uint16_t AntennaReduction, 1819 uint16_t twiceMaxRegulatoryPower, 1820 uint16_t powerLimit) 1821 { 1822 #define N(a) (sizeof(a)/sizeof(a[0])) 1823 /* Local defines to distinguish between extension and control CTL's */ 1824 #define EXT_ADDITIVE (0x8000) 1825 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) 1826 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) 1827 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) 1828 1829 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 1830 int i; 1831 int16_t twiceLargestAntenna; 1832 CAL_CTL_DATA *rep; 1833 CAL_TARGET_POWER_LEG targetPowerOfdm, targetPowerCck = {0, {0, 0, 0, 0}}; 1834 CAL_TARGET_POWER_LEG targetPowerOfdmExt = {0, {0, 0, 0, 0}}, targetPowerCckExt = {0, {0, 0, 0, 0}}; 1835 CAL_TARGET_POWER_HT targetPowerHt20, targetPowerHt40 = {0, {0, 0, 0, 0}}; 1836 int16_t scaledPower, minCtlPower; 1837 1838 #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */ 1839 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */ 1840 static const uint16_t ctlModesFor11a[] = { 1841 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 1842 }; 1843 static const uint16_t ctlModesFor11g[] = { 1844 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40 1845 }; 1846 const uint16_t *pCtlMode; 1847 uint16_t numCtlModes, ctlMode, freq; 1848 CHAN_CENTERS centers; 1849 1850 ar5416GetChannelCenters(ah, chan, ¢ers); 1851 1852 /* Compute TxPower reduction due to Antenna Gain */ 1853 1854 twiceLargestAntenna = AH_MAX(AH_MAX( 1855 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[0], 1856 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[1]), 1857 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[2]); 1858 #if 0 1859 /* Turn it back on if we need to calculate per chain antenna gain reduction */ 1860 /* Use only if the expected gain > 6dbi */ 1861 /* Chain 0 is always used */ 1862 twiceLargestAntenna = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[0]; 1863 1864 /* Look at antenna gains of Chains 1 and 2 if the TX mask is set */ 1865 if (ahp->ah_tx_chainmask & 0x2) 1866 twiceLargestAntenna = AH_MAX(twiceLargestAntenna, 1867 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[1]); 1868 1869 if (ahp->ah_tx_chainmask & 0x4) 1870 twiceLargestAntenna = AH_MAX(twiceLargestAntenna, 1871 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[2]); 1872 #endif 1873 twiceLargestAntenna = (int16_t)AH_MIN((AntennaReduction) - twiceLargestAntenna, 0); 1874 1875 /* XXX setup for 5212 use (really used?) */ 1876 ath_hal_eepromSet(ah, 1877 IEEE80211_IS_CHAN_2GHZ(chan) ? AR_EEP_ANTGAINMAX_2 : AR_EEP_ANTGAINMAX_5, 1878 twiceLargestAntenna); 1879 1880 /* 1881 * scaledPower is the minimum of the user input power level and 1882 * the regulatory allowed power level 1883 */ 1884 scaledPower = AH_MIN(powerLimit, twiceMaxRegulatoryPower + twiceLargestAntenna); 1885 1886 /* Reduce scaled Power by number of chains active to get to per chain tx power level */ 1887 /* TODO: better value than these? */ 1888 switch (owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask)) { 1889 case 1: 1890 break; 1891 case 2: 1892 scaledPower -= pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pwrDecreaseFor2Chain; 1893 break; 1894 case 3: 1895 scaledPower -= pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pwrDecreaseFor3Chain; 1896 break; 1897 default: 1898 return AH_FALSE; /* Unsupported number of chains */ 1899 } 1900 1901 scaledPower = AH_MAX(0, scaledPower); 1902 1903 /* Get target powers from EEPROM - our baseline for TX Power */ 1904 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 1905 /* Setup for CTL modes */ 1906 numCtlModes = N(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; /* CTL_11B, CTL_11G, CTL_2GHT20 */ 1907 pCtlMode = ctlModesFor11g; 1908 1909 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, 1910 AR5416_NUM_2G_CCK_TARGET_POWERS, &targetPowerCck, 4, AH_FALSE); 1911 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, 1912 AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE); 1913 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20, 1914 AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE); 1915 1916 if (IEEE80211_IS_CHAN_HT40(chan)) { 1917 numCtlModes = N(ctlModesFor11g); /* All 2G CTL's */ 1918 1919 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40, 1920 AR5416_NUM_2G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE); 1921 /* Get target powers for extension channels */ 1922 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, 1923 AR5416_NUM_2G_CCK_TARGET_POWERS, &targetPowerCckExt, 4, AH_TRUE); 1924 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, 1925 AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE); 1926 } 1927 } else { 1928 /* Setup for CTL modes */ 1929 numCtlModes = N(ctlModesFor11a) - SUB_NUM_CTL_MODES_AT_5G_40; /* CTL_11A, CTL_5GHT20 */ 1930 pCtlMode = ctlModesFor11a; 1931 1932 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower5G, 1933 AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE); 1934 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower5GHT20, 1935 AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE); 1936 1937 if (IEEE80211_IS_CHAN_HT40(chan)) { 1938 numCtlModes = N(ctlModesFor11a); /* All 5G CTL's */ 1939 1940 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower5GHT40, 1941 AR5416_NUM_5G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE); 1942 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower5G, 1943 AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE); 1944 } 1945 } 1946 1947 /* 1948 * For MIMO, need to apply regulatory caps individually across dynamically 1949 * running modes: CCK, OFDM, HT20, HT40 1950 * 1951 * The outer loop walks through each possible applicable runtime mode. 1952 * The inner loop walks through each ctlIndex entry in EEPROM. 1953 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode. 1954 * 1955 */ 1956 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { 1957 HAL_BOOL isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || 1958 (pCtlMode[ctlMode] == CTL_2GHT40); 1959 if (isHt40CtlMode) { 1960 freq = centers.ctl_center; 1961 } else if (pCtlMode[ctlMode] & EXT_ADDITIVE) { 1962 freq = centers.ext_center; 1963 } else { 1964 freq = centers.ctl_center; 1965 } 1966 1967 /* walk through each CTL index stored in EEPROM */ 1968 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { 1969 uint16_t twiceMinEdgePower; 1970 1971 /* compare test group from regulatory channel list with test mode from pCtlMode list */ 1972 if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == pEepData->ctlIndex[i]) || 1973 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == 1974 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) { 1975 rep = &(pEepData->ctlData[i]); 1976 twiceMinEdgePower = ar5416GetMaxEdgePower(freq, 1977 rep->ctlEdges[owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1], 1978 IEEE80211_IS_CHAN_2GHZ(chan)); 1979 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 1980 /* Find the minimum of all CTL edge powers that apply to this channel */ 1981 twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower); 1982 } else { 1983 /* specific */ 1984 twiceMaxEdgePower = twiceMinEdgePower; 1985 break; 1986 } 1987 } 1988 } 1989 minCtlPower = (uint8_t)AH_MIN(twiceMaxEdgePower, scaledPower); 1990 /* Apply ctl mode to correct target power set */ 1991 switch(pCtlMode[ctlMode]) { 1992 case CTL_11B: 1993 for (i = 0; i < N(targetPowerCck.tPow2x); i++) { 1994 targetPowerCck.tPow2x[i] = (uint8_t)AH_MIN(targetPowerCck.tPow2x[i], minCtlPower); 1995 } 1996 break; 1997 case CTL_11A: 1998 case CTL_11G: 1999 for (i = 0; i < N(targetPowerOfdm.tPow2x); i++) { 2000 targetPowerOfdm.tPow2x[i] = (uint8_t)AH_MIN(targetPowerOfdm.tPow2x[i], minCtlPower); 2001 } 2002 break; 2003 case CTL_5GHT20: 2004 case CTL_2GHT20: 2005 for (i = 0; i < N(targetPowerHt20.tPow2x); i++) { 2006 targetPowerHt20.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt20.tPow2x[i], minCtlPower); 2007 } 2008 break; 2009 case CTL_11B_EXT: 2010 targetPowerCckExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerCckExt.tPow2x[0], minCtlPower); 2011 break; 2012 case CTL_11A_EXT: 2013 case CTL_11G_EXT: 2014 targetPowerOfdmExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerOfdmExt.tPow2x[0], minCtlPower); 2015 break; 2016 case CTL_5GHT40: 2017 case CTL_2GHT40: 2018 for (i = 0; i < N(targetPowerHt40.tPow2x); i++) { 2019 targetPowerHt40.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt40.tPow2x[i], minCtlPower); 2020 } 2021 break; 2022 default: 2023 return AH_FALSE; 2024 break; 2025 } 2026 } /* end ctl mode checking */ 2027 2028 /* Set rates Array from collected data */ 2029 ar5416SetRatesArrayFromTargetPower(ah, chan, ratesArray, 2030 &targetPowerCck, 2031 &targetPowerCckExt, 2032 &targetPowerOfdm, 2033 &targetPowerOfdmExt, 2034 &targetPowerHt20, 2035 &targetPowerHt40); 2036 return AH_TRUE; 2037 #undef EXT_ADDITIVE 2038 #undef CTL_11A_EXT 2039 #undef CTL_11G_EXT 2040 #undef CTL_11B_EXT 2041 #undef SUB_NUM_CTL_MODES_AT_5G_40 2042 #undef SUB_NUM_CTL_MODES_AT_2G_40 2043 #undef N 2044 } 2045 2046 /************************************************************************** 2047 * fbin2freq 2048 * 2049 * Get channel value from binary representation held in eeprom 2050 * RETURNS: the frequency in MHz 2051 */ 2052 static uint16_t 2053 fbin2freq(uint8_t fbin, HAL_BOOL is2GHz) 2054 { 2055 /* 2056 * Reserved value 0xFF provides an empty definition both as 2057 * an fbin and as a frequency - do not convert 2058 */ 2059 if (fbin == AR5416_BCHAN_UNUSED) { 2060 return fbin; 2061 } 2062 2063 return (uint16_t)((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin)); 2064 } 2065 2066 /* 2067 * ar5416GetMaxEdgePower 2068 * 2069 * Find the maximum conformance test limit for the given channel and CTL info 2070 */ 2071 uint16_t 2072 ar5416GetMaxEdgePower(uint16_t freq, CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz) 2073 { 2074 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 2075 int i; 2076 2077 /* Get the edge power */ 2078 for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED) ; i++) { 2079 /* 2080 * If there's an exact channel match or an inband flag set 2081 * on the lower channel use the given rdEdgePower 2082 */ 2083 if (freq == fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) { 2084 twiceMaxEdgePower = MS(pRdEdgesPower[i].tPowerFlag, CAL_CTL_EDGES_POWER); 2085 break; 2086 } else if ((i > 0) && (freq < fbin2freq(pRdEdgesPower[i].bChannel, is2GHz))) { 2087 if (fbin2freq(pRdEdgesPower[i - 1].bChannel, is2GHz) < freq && (pRdEdgesPower[i - 1].tPowerFlag & CAL_CTL_EDGES_FLAG) != 0) { 2088 twiceMaxEdgePower = MS(pRdEdgesPower[i - 1].tPowerFlag, CAL_CTL_EDGES_POWER); 2089 } 2090 /* Leave loop - no more affecting edges possible in this monotonic increasing list */ 2091 break; 2092 } 2093 } 2094 HALASSERT(twiceMaxEdgePower > 0); 2095 return twiceMaxEdgePower; 2096 } 2097 2098 /************************************************************** 2099 * ar5416GetTargetPowers 2100 * 2101 * Return the rates of target power for the given target power table 2102 * channel, and number of channels 2103 */ 2104 void 2105 ar5416GetTargetPowers(struct ath_hal *ah, const struct ieee80211_channel *chan, 2106 CAL_TARGET_POWER_HT *powInfo, uint16_t numChannels, 2107 CAL_TARGET_POWER_HT *pNewPower, uint16_t numRates, 2108 HAL_BOOL isHt40Target) 2109 { 2110 uint16_t clo, chi; 2111 int i; 2112 int matchIndex = -1, lowIndex = -1; 2113 uint16_t freq; 2114 CHAN_CENTERS centers; 2115 2116 ar5416GetChannelCenters(ah, chan, ¢ers); 2117 freq = isHt40Target ? centers.synth_center : centers.ctl_center; 2118 2119 /* Copy the target powers into the temp channel list */ 2120 if (freq <= fbin2freq(powInfo[0].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) { 2121 matchIndex = 0; 2122 } else { 2123 for (i = 0; (i < numChannels) && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { 2124 if (freq == fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) { 2125 matchIndex = i; 2126 break; 2127 } else if ((freq < fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) && 2128 (freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)))) 2129 { 2130 lowIndex = i - 1; 2131 break; 2132 } 2133 } 2134 if ((matchIndex == -1) && (lowIndex == -1)) { 2135 HALASSERT(freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))); 2136 matchIndex = i - 1; 2137 } 2138 } 2139 2140 if (matchIndex != -1) { 2141 OS_MEMCPY(pNewPower, &powInfo[matchIndex], sizeof(*pNewPower)); 2142 } else { 2143 HALASSERT(lowIndex != -1); 2144 /* 2145 * Get the lower and upper channels, target powers, 2146 * and interpolate between them. 2147 */ 2148 clo = fbin2freq(powInfo[lowIndex].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)); 2149 chi = fbin2freq(powInfo[lowIndex + 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)); 2150 2151 for (i = 0; i < numRates; i++) { 2152 pNewPower->tPow2x[i] = (uint8_t)ath_ee_interpolate(freq, clo, chi, 2153 powInfo[lowIndex].tPow2x[i], powInfo[lowIndex + 1].tPow2x[i]); 2154 } 2155 } 2156 } 2157 /************************************************************** 2158 * ar5416GetTargetPowersLeg 2159 * 2160 * Return the four rates of target power for the given target power table 2161 * channel, and number of channels 2162 */ 2163 void 2164 ar5416GetTargetPowersLeg(struct ath_hal *ah, 2165 const struct ieee80211_channel *chan, 2166 CAL_TARGET_POWER_LEG *powInfo, uint16_t numChannels, 2167 CAL_TARGET_POWER_LEG *pNewPower, uint16_t numRates, 2168 HAL_BOOL isExtTarget) 2169 { 2170 uint16_t clo, chi; 2171 int i; 2172 int matchIndex = -1, lowIndex = -1; 2173 uint16_t freq; 2174 CHAN_CENTERS centers; 2175 2176 ar5416GetChannelCenters(ah, chan, ¢ers); 2177 freq = (isExtTarget) ? centers.ext_center :centers.ctl_center; 2178 2179 /* Copy the target powers into the temp channel list */ 2180 if (freq <= fbin2freq(powInfo[0].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) { 2181 matchIndex = 0; 2182 } else { 2183 for (i = 0; (i < numChannels) && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { 2184 if (freq == fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) { 2185 matchIndex = i; 2186 break; 2187 } else if ((freq < fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) && 2188 (freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)))) 2189 { 2190 lowIndex = i - 1; 2191 break; 2192 } 2193 } 2194 if ((matchIndex == -1) && (lowIndex == -1)) { 2195 HALASSERT(freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))); 2196 matchIndex = i - 1; 2197 } 2198 } 2199 2200 if (matchIndex != -1) { 2201 OS_MEMCPY(pNewPower, &powInfo[matchIndex], sizeof(*pNewPower)); 2202 } else { 2203 HALASSERT(lowIndex != -1); 2204 /* 2205 * Get the lower and upper channels, target powers, 2206 * and interpolate between them. 2207 */ 2208 clo = fbin2freq(powInfo[lowIndex].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)); 2209 chi = fbin2freq(powInfo[lowIndex + 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)); 2210 2211 for (i = 0; i < numRates; i++) { 2212 pNewPower->tPow2x[i] = (uint8_t)ath_ee_interpolate(freq, clo, chi, 2213 powInfo[lowIndex].tPow2x[i], powInfo[lowIndex + 1].tPow2x[i]); 2214 } 2215 } 2216 } 2217 2218 /* 2219 * Set the gain boundaries for the given radio chain. 2220 * 2221 * The gain boundaries tell the hardware at what point in the 2222 * PDADC array to "switch over" from one PD gain setting 2223 * to another. There's also a gain overlap between two 2224 * PDADC array gain curves where there's valid PD values 2225 * for 2 gain settings. 2226 * 2227 * The hardware uses the gain overlap and gain boundaries 2228 * to determine which gain curve to use for the given 2229 * target TX power. 2230 */ 2231 void 2232 ar5416SetGainBoundariesClosedLoop(struct ath_hal *ah, int i, 2233 uint16_t pdGainOverlap_t2, uint16_t gainBoundaries[]) 2234 { 2235 int regChainOffset; 2236 2237 regChainOffset = ar5416GetRegChainOffset(ah, i); 2238 2239 HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: chain %d: gainOverlap_t2: %d," 2240 " gainBoundaries: %d, %d, %d, %d\n", __func__, i, pdGainOverlap_t2, 2241 gainBoundaries[0], gainBoundaries[1], gainBoundaries[2], 2242 gainBoundaries[3]); 2243 OS_REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset, 2244 SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | 2245 SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) | 2246 SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) | 2247 SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) | 2248 SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); 2249 } 2250 2251 /* 2252 * Get the gain values and the number of gain levels given 2253 * in xpdMask. 2254 * 2255 * The EEPROM xpdMask determines which power detector gain 2256 * levels were used during calibration. Each of these mask 2257 * bits maps to a fixed gain level in hardware. 2258 */ 2259 uint16_t 2260 ar5416GetXpdGainValues(struct ath_hal *ah, uint16_t xpdMask, 2261 uint16_t xpdGainValues[]) 2262 { 2263 int i; 2264 uint16_t numXpdGain = 0; 2265 2266 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { 2267 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { 2268 if (numXpdGain >= AR5416_NUM_PD_GAINS) { 2269 HALASSERT(0); 2270 break; 2271 } 2272 xpdGainValues[numXpdGain] = (uint16_t)(AR5416_PD_GAINS_IN_MASK - i); 2273 numXpdGain++; 2274 } 2275 } 2276 return numXpdGain; 2277 } 2278 2279 /* 2280 * Write the detector gain and biases. 2281 * 2282 * There are four power detector gain levels. The xpdMask in the EEPROM 2283 * determines which power detector gain levels have TX power calibration 2284 * data associated with them. This function writes the number of 2285 * PD gain levels and their values into the hardware. 2286 * 2287 * This is valid for all TX chains - the calibration data itself however 2288 * will likely differ per-chain. 2289 */ 2290 void 2291 ar5416WriteDetectorGainBiases(struct ath_hal *ah, uint16_t numXpdGain, 2292 uint16_t xpdGainValues[]) 2293 { 2294 HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: numXpdGain: %d," 2295 " xpdGainValues: %d, %d, %d\n", __func__, numXpdGain, 2296 xpdGainValues[0], xpdGainValues[1], xpdGainValues[2]); 2297 2298 OS_REG_WRITE(ah, AR_PHY_TPCRG1, (OS_REG_READ(ah, AR_PHY_TPCRG1) & 2299 ~(AR_PHY_TPCRG1_NUM_PD_GAIN | AR_PHY_TPCRG1_PD_GAIN_1 | 2300 AR_PHY_TPCRG1_PD_GAIN_2 | AR_PHY_TPCRG1_PD_GAIN_3)) | 2301 SM(numXpdGain - 1, AR_PHY_TPCRG1_NUM_PD_GAIN) | 2302 SM(xpdGainValues[0], AR_PHY_TPCRG1_PD_GAIN_1 ) | 2303 SM(xpdGainValues[1], AR_PHY_TPCRG1_PD_GAIN_2) | 2304 SM(xpdGainValues[2], AR_PHY_TPCRG1_PD_GAIN_3)); 2305 } 2306 2307 /* 2308 * Write the PDADC array to the given radio chain i. 2309 * 2310 * The 32 PDADC registers are written without any care about 2311 * their contents - so if various chips treat values as "special", 2312 * this routine will not care. 2313 */ 2314 void 2315 ar5416WritePdadcValues(struct ath_hal *ah, int i, uint8_t pdadcValues[]) 2316 { 2317 int regOffset, regChainOffset; 2318 int j; 2319 int reg32; 2320 2321 regChainOffset = ar5416GetRegChainOffset(ah, i); 2322 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; 2323 2324 for (j = 0; j < 32; j++) { 2325 reg32 = ((pdadcValues[4*j + 0] & 0xFF) << 0) | 2326 ((pdadcValues[4*j + 1] & 0xFF) << 8) | 2327 ((pdadcValues[4*j + 2] & 0xFF) << 16) | 2328 ((pdadcValues[4*j + 3] & 0xFF) << 24) ; 2329 OS_REG_WRITE(ah, regOffset, reg32); 2330 HALDEBUG(ah, HAL_DEBUG_EEPROM, "PDADC: Chain %d |" 2331 " PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d" 2332 " Value %3d | PDADC %3d Value %3d |\n", 2333 i, 2334 4*j, pdadcValues[4*j], 2335 4*j+1, pdadcValues[4*j + 1], 2336 4*j+2, pdadcValues[4*j + 2], 2337 4*j+3, pdadcValues[4*j + 3]); 2338 regOffset += 4; 2339 } 2340 } 2341 2342 /************************************************************** 2343 * ar5416SetPowerCalTable 2344 * 2345 * Pull the PDADC piers from cal data and interpolate them across the given 2346 * points as well as from the nearest pier(s) to get a power detector 2347 * linear voltage to power level table. 2348 */ 2349 HAL_BOOL 2350 ar5416SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData, 2351 const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset) 2352 { 2353 CAL_DATA_PER_FREQ *pRawDataset; 2354 uint8_t *pCalBChans = AH_NULL; 2355 uint16_t pdGainOverlap_t2; 2356 static uint8_t pdadcValues[AR5416_NUM_PDADC_VALUES]; 2357 uint16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK]; 2358 uint16_t numPiers, i; 2359 int16_t tMinCalPower; 2360 uint16_t numXpdGain, xpdMask; 2361 uint16_t xpdGainValues[AR5416_NUM_PD_GAINS]; 2362 uint32_t regChainOffset; 2363 2364 OS_MEMZERO(xpdGainValues, sizeof(xpdGainValues)); 2365 2366 xpdMask = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].xpdGain; 2367 2368 if (IS_EEP_MINOR_V2(ah)) { 2369 pdGainOverlap_t2 = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pdGainOverlap; 2370 } else { 2371 pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); 2372 } 2373 2374 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 2375 pCalBChans = pEepData->calFreqPier2G; 2376 numPiers = AR5416_NUM_2G_CAL_PIERS; 2377 } else { 2378 pCalBChans = pEepData->calFreqPier5G; 2379 numPiers = AR5416_NUM_5G_CAL_PIERS; 2380 } 2381 2382 /* Calculate the value of xpdgains from the xpdGain Mask */ 2383 numXpdGain = ar5416GetXpdGainValues(ah, xpdMask, xpdGainValues); 2384 2385 /* Write the detector gain biases and their number */ 2386 ar5416WriteDetectorGainBiases(ah, numXpdGain, xpdGainValues); 2387 2388 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 2389 regChainOffset = ar5416GetRegChainOffset(ah, i); 2390 2391 if (pEepData->baseEepHeader.txMask & (1 << i)) { 2392 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 2393 pRawDataset = pEepData->calPierData2G[i]; 2394 } else { 2395 pRawDataset = pEepData->calPierData5G[i]; 2396 } 2397 2398 /* Fetch the gain boundaries and the PDADC values */ 2399 ar5416GetGainBoundariesAndPdadcs(ah, chan, pRawDataset, 2400 pCalBChans, numPiers, 2401 pdGainOverlap_t2, 2402 &tMinCalPower, gainBoundaries, 2403 pdadcValues, numXpdGain); 2404 2405 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { 2406 ar5416SetGainBoundariesClosedLoop(ah, i, pdGainOverlap_t2, 2407 gainBoundaries); 2408 } 2409 2410 /* Write the power values into the baseband power table */ 2411 ar5416WritePdadcValues(ah, i, pdadcValues); 2412 } 2413 } 2414 *pTxPowerIndexOffset = 0; 2415 2416 return AH_TRUE; 2417 } 2418 2419 /************************************************************** 2420 * ar5416GetGainBoundariesAndPdadcs 2421 * 2422 * Uses the data points read from EEPROM to reconstruct the pdadc power table 2423 * Called by ar5416SetPowerCalTable only. 2424 */ 2425 void 2426 ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah, 2427 const struct ieee80211_channel *chan, 2428 CAL_DATA_PER_FREQ *pRawDataSet, 2429 uint8_t * bChans, uint16_t availPiers, 2430 uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries, 2431 uint8_t * pPDADCValues, uint16_t numXpdGains) 2432 { 2433 2434 int i, j, k; 2435 int16_t ss; /* potentially -ve index for taking care of pdGainOverlap */ 2436 uint16_t idxL, idxR, numPiers; /* Pier indexes */ 2437 2438 /* filled out Vpd table for all pdGains (chanL) */ 2439 static uint8_t vpdTableL[AR5416_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 2440 2441 /* filled out Vpd table for all pdGains (chanR) */ 2442 static uint8_t vpdTableR[AR5416_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 2443 2444 /* filled out Vpd table for all pdGains (interpolated) */ 2445 static uint8_t vpdTableI[AR5416_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 2446 2447 uint8_t *pVpdL, *pVpdR, *pPwrL, *pPwrR; 2448 uint8_t minPwrT4[AR5416_NUM_PD_GAINS]; 2449 uint8_t maxPwrT4[AR5416_NUM_PD_GAINS]; 2450 int16_t vpdStep; 2451 int16_t tmpVal; 2452 uint16_t sizeCurrVpdTable, maxIndex, tgtIndex; 2453 HAL_BOOL match; 2454 int16_t minDelta = 0; 2455 CHAN_CENTERS centers; 2456 2457 ar5416GetChannelCenters(ah, chan, ¢ers); 2458 2459 /* Trim numPiers for the number of populated channel Piers */ 2460 for (numPiers = 0; numPiers < availPiers; numPiers++) { 2461 if (bChans[numPiers] == AR5416_BCHAN_UNUSED) { 2462 break; 2463 } 2464 } 2465 2466 /* Find pier indexes around the current channel */ 2467 match = ath_ee_getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center, 2468 IEEE80211_IS_CHAN_2GHZ(chan)), bChans, numPiers, &idxL, &idxR); 2469 2470 if (match) { 2471 /* Directly fill both vpd tables from the matching index */ 2472 for (i = 0; i < numXpdGains; i++) { 2473 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; 2474 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; 2475 ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], pRawDataSet[idxL].pwrPdg[i], 2476 pRawDataSet[idxL].vpdPdg[i], AR5416_PD_GAIN_ICEPTS, vpdTableI[i]); 2477 } 2478 } else { 2479 for (i = 0; i < numXpdGains; i++) { 2480 pVpdL = pRawDataSet[idxL].vpdPdg[i]; 2481 pPwrL = pRawDataSet[idxL].pwrPdg[i]; 2482 pVpdR = pRawDataSet[idxR].vpdPdg[i]; 2483 pPwrR = pRawDataSet[idxR].pwrPdg[i]; 2484 2485 /* Start Vpd interpolation from the max of the minimum powers */ 2486 minPwrT4[i] = AH_MAX(pPwrL[0], pPwrR[0]); 2487 2488 /* End Vpd interpolation from the min of the max powers */ 2489 maxPwrT4[i] = AH_MIN(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], pPwrR[AR5416_PD_GAIN_ICEPTS - 1]); 2490 HALASSERT(maxPwrT4[i] > minPwrT4[i]); 2491 2492 /* Fill pier Vpds */ 2493 ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrL, pVpdL, AR5416_PD_GAIN_ICEPTS, vpdTableL[i]); 2494 ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrR, pVpdR, AR5416_PD_GAIN_ICEPTS, vpdTableR[i]); 2495 2496 /* Interpolate the final vpd */ 2497 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { 2498 vpdTableI[i][j] = (uint8_t)(ath_ee_interpolate((uint16_t)FREQ2FBIN(centers.synth_center, 2499 IEEE80211_IS_CHAN_2GHZ(chan)), 2500 bChans[idxL], bChans[idxR], vpdTableL[i][j], vpdTableR[i][j])); 2501 } 2502 } 2503 } 2504 *pMinCalPower = (int16_t)(minPwrT4[0] / 2); 2505 2506 k = 0; /* index for the final table */ 2507 for (i = 0; i < numXpdGains; i++) { 2508 if (i == (numXpdGains - 1)) { 2509 pPdGainBoundaries[i] = (uint16_t)(maxPwrT4[i] / 2); 2510 } else { 2511 pPdGainBoundaries[i] = (uint16_t)((maxPwrT4[i] + minPwrT4[i+1]) / 4); 2512 } 2513 2514 pPdGainBoundaries[i] = (uint16_t)AH_MIN(AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); 2515 2516 /* NB: only applies to owl 1.0 */ 2517 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah) ) { 2518 /* 2519 * fix the gain delta, but get a delta that can be applied to min to 2520 * keep the upper power values accurate, don't think max needs to 2521 * be adjusted because should not be at that area of the table? 2522 */ 2523 minDelta = pPdGainBoundaries[0] - 23; 2524 pPdGainBoundaries[0] = 23; 2525 } 2526 else { 2527 minDelta = 0; 2528 } 2529 2530 /* Find starting index for this pdGain */ 2531 if (i == 0) { 2532 if (AR_SREV_MERLIN_10_OR_LATER(ah)) 2533 ss = (int16_t)(0 - (minPwrT4[i] / 2)); 2534 else 2535 ss = 0; /* for the first pdGain, start from index 0 */ 2536 } else { 2537 /* need overlap entries extrapolated below. */ 2538 ss = (int16_t)((pPdGainBoundaries[i-1] - (minPwrT4[i] / 2)) - tPdGainOverlap + 1 + minDelta); 2539 } 2540 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); 2541 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 2542 /* 2543 *-ve ss indicates need to extrapolate data below for this pdGain 2544 */ 2545 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 2546 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); 2547 pPDADCValues[k++] = (uint8_t)((tmpVal < 0) ? 0 : tmpVal); 2548 ss++; 2549 } 2550 2551 sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 +1); 2552 tgtIndex = (uint8_t)(pPdGainBoundaries[i] + tPdGainOverlap - (minPwrT4[i] / 2)); 2553 maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable; 2554 2555 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 2556 pPDADCValues[k++] = vpdTableI[i][ss++]; 2557 } 2558 2559 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - vpdTableI[i][sizeCurrVpdTable - 2]); 2560 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 2561 /* 2562 * for last gain, pdGainBoundary == Pmax_t2, so will 2563 * have to extrapolate 2564 */ 2565 if (tgtIndex >= maxIndex) { /* need to extrapolate above */ 2566 while ((ss <= tgtIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 2567 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] + 2568 (ss - maxIndex +1) * vpdStep)); 2569 pPDADCValues[k++] = (uint8_t)((tmpVal > 255) ? 255 : tmpVal); 2570 ss++; 2571 } 2572 } /* extrapolated above */ 2573 } /* for all pdGainUsed */ 2574 2575 /* Fill out pdGainBoundaries - only up to 2 allowed here, but hardware allows up to 4 */ 2576 while (i < AR5416_PD_GAINS_IN_MASK) { 2577 pPdGainBoundaries[i] = pPdGainBoundaries[i-1]; 2578 i++; 2579 } 2580 2581 while (k < AR5416_NUM_PDADC_VALUES) { 2582 pPDADCValues[k] = pPDADCValues[k-1]; 2583 k++; 2584 } 2585 return; 2586 } 2587 2588 /* 2589 * The linux ath9k driver and (from what I've been told) the reference 2590 * Atheros driver enables the 11n PHY by default whether or not it's 2591 * configured. 2592 */ 2593 static void 2594 ar5416Set11nRegs(struct ath_hal *ah, const struct ieee80211_channel *chan) 2595 { 2596 uint32_t phymode; 2597 uint32_t enableDacFifo = 0; 2598 HAL_HT_MACMODE macmode; /* MAC - 20/40 mode */ 2599 2600 if (AR_SREV_KITE_10_OR_LATER(ah)) 2601 enableDacFifo = (OS_REG_READ(ah, AR_PHY_TURBO) & AR_PHY_FC_ENABLE_DAC_FIFO); 2602 2603 /* Enable 11n HT, 20 MHz */ 2604 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 2605 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo; 2606 2607 /* Configure baseband for dynamic 20/40 operation */ 2608 if (IEEE80211_IS_CHAN_HT40(chan)) { 2609 phymode |= AR_PHY_FC_DYN2040_EN; 2610 2611 /* Configure control (primary) channel at +-10MHz */ 2612 if (IEEE80211_IS_CHAN_HT40U(chan)) 2613 phymode |= AR_PHY_FC_DYN2040_PRI_CH; 2614 #if 0 2615 /* Configure 20/25 spacing */ 2616 if (ht->ht_extprotspacing == HAL_HT_EXTPROTSPACING_25) 2617 phymode |= AR_PHY_FC_DYN2040_EXT_CH; 2618 #endif 2619 macmode = HAL_HT_MACMODE_2040; 2620 } else 2621 macmode = HAL_HT_MACMODE_20; 2622 OS_REG_WRITE(ah, AR_PHY_TURBO, phymode); 2623 2624 /* Configure MAC for 20/40 operation */ 2625 ar5416Set11nMac2040(ah, macmode); 2626 2627 /* global transmit timeout (25 TUs default)*/ 2628 /* XXX - put this elsewhere??? */ 2629 OS_REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S) ; 2630 2631 /* carrier sense timeout */ 2632 OS_REG_SET_BIT(ah, AR_GTTM, AR_GTTM_CST_USEC); 2633 OS_REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 2634 } 2635 2636 void 2637 ar5416GetChannelCenters(struct ath_hal *ah, 2638 const struct ieee80211_channel *chan, CHAN_CENTERS *centers) 2639 { 2640 uint16_t freq = ath_hal_gethwchannel(ah, chan); 2641 2642 centers->ctl_center = freq; 2643 centers->synth_center = freq; 2644 /* 2645 * In 20/40 phy mode, the center frequency is 2646 * "between" the control and extension channels. 2647 */ 2648 if (IEEE80211_IS_CHAN_HT40U(chan)) { 2649 centers->synth_center += HT40_CHANNEL_CENTER_SHIFT; 2650 centers->ext_center = 2651 centers->synth_center + HT40_CHANNEL_CENTER_SHIFT; 2652 } else if (IEEE80211_IS_CHAN_HT40D(chan)) { 2653 centers->synth_center -= HT40_CHANNEL_CENTER_SHIFT; 2654 centers->ext_center = 2655 centers->synth_center - HT40_CHANNEL_CENTER_SHIFT; 2656 } else { 2657 centers->ext_center = freq; 2658 } 2659 } 2660 2661 /* 2662 * Override the INI vals being programmed. 2663 */ 2664 static void 2665 ar5416OverrideIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 2666 { 2667 uint32_t val; 2668 2669 /* 2670 * Set the RX_ABORT and RX_DIS and clear if off only after 2671 * RXE is set for MAC. This prevents frames with corrupted 2672 * descriptor status. 2673 */ 2674 OS_REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 2675 2676 if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 2677 val = OS_REG_READ(ah, AR_PCU_MISC_MODE2); 2678 val &= (~AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE); 2679 if (!AR_SREV_9271(ah)) 2680 val &= ~AR_PCU_MISC_MODE2_HWWAR1; 2681 2682 if (AR_SREV_KIWI_10_OR_LATER(ah)) 2683 val = val & (~AR_PCU_MISC_MODE2_HWWAR2); 2684 2685 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, val); 2686 } 2687 2688 /* 2689 * Disable RIFS search on some chips to avoid baseband 2690 * hang issues. 2691 */ 2692 if (AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) 2693 (void) ar5416SetRifsDelay(ah, chan, AH_FALSE); 2694 2695 if (!AR_SREV_5416_V20_OR_LATER(ah) || AR_SREV_MERLIN(ah)) 2696 return; 2697 2698 /* 2699 * Disable BB clock gating 2700 * Necessary to avoid issues on AR5416 2.0 2701 */ 2702 OS_REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); 2703 } 2704 2705 struct ini { 2706 uint32_t *data; /* NB: !const */ 2707 int rows, cols; 2708 }; 2709 2710 /* 2711 * Override XPA bias level based on operating frequency. 2712 * This is a v14 EEPROM specific thing for the AR9160. 2713 */ 2714 void 2715 ar5416EepromSetAddac(struct ath_hal *ah, const struct ieee80211_channel *chan) 2716 { 2717 #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt]) 2718 MODAL_EEP_HEADER *pModal; 2719 HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom; 2720 struct ar5416eeprom *eep = &ee->ee_base; 2721 uint8_t biaslevel; 2722 2723 if (! AR_SREV_SOWL(ah)) 2724 return; 2725 2726 if (EEP_MINOR(ah) < AR5416_EEP_MINOR_VER_7) 2727 return; 2728 2729 pModal = &(eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)]); 2730 2731 if (pModal->xpaBiasLvl != 0xff) 2732 biaslevel = pModal->xpaBiasLvl; 2733 else { 2734 uint16_t resetFreqBin, freqBin, freqCount = 0; 2735 CHAN_CENTERS centers; 2736 2737 ar5416GetChannelCenters(ah, chan, ¢ers); 2738 2739 resetFreqBin = FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)); 2740 freqBin = XPA_LVL_FREQ(0) & 0xff; 2741 biaslevel = (uint8_t) (XPA_LVL_FREQ(0) >> 14); 2742 2743 freqCount++; 2744 2745 while (freqCount < 3) { 2746 if (XPA_LVL_FREQ(freqCount) == 0x0) 2747 break; 2748 2749 freqBin = XPA_LVL_FREQ(freqCount) & 0xff; 2750 if (resetFreqBin >= freqBin) 2751 biaslevel = (uint8_t)(XPA_LVL_FREQ(freqCount) >> 14); 2752 else 2753 break; 2754 freqCount++; 2755 } 2756 } 2757 2758 HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: overriding XPA bias level = %d\n", 2759 __func__, biaslevel); 2760 2761 /* 2762 * This is a dirty workaround for the const initval data, 2763 * which will upset multiple AR9160's on the same board. 2764 * 2765 * The HAL should likely just have a private copy of the addac 2766 * data per instance. 2767 */ 2768 if (IEEE80211_IS_CHAN_2GHZ(chan)) 2769 HAL_INI_VAL((struct ini *) &AH5416(ah)->ah_ini_addac, 7, 1) = 2770 (HAL_INI_VAL(&AH5416(ah)->ah_ini_addac, 7, 1) & (~0x18)) | biaslevel << 3; 2771 else 2772 HAL_INI_VAL((struct ini *) &AH5416(ah)->ah_ini_addac, 6, 1) = 2773 (HAL_INI_VAL(&AH5416(ah)->ah_ini_addac, 6, 1) & (~0xc0)) | biaslevel << 6; 2774 #undef XPA_LVL_FREQ 2775 } 2776 2777 static void 2778 ar5416MarkPhyInactive(struct ath_hal *ah) 2779 { 2780 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 2781 } 2782 2783 #define AR5416_IFS_SLOT_FULL_RATE_40 0x168 /* 9 us half, 40 MHz core clock (9*40) */ 2784 #define AR5416_IFS_SLOT_HALF_RATE_40 0x104 /* 13 us half, 20 MHz core clock (13*20) */ 2785 #define AR5416_IFS_SLOT_QUARTER_RATE_40 0xD2 /* 21 us quarter, 10 MHz core clock (21*10) */ 2786 2787 #define AR5416_IFS_EIFS_FULL_RATE_40 0xE60 /* (74 + (2 * 9)) * 40MHz core clock */ 2788 #define AR5416_IFS_EIFS_HALF_RATE_40 0xDAC /* (149 + (2 * 13)) * 20MHz core clock */ 2789 #define AR5416_IFS_EIFS_QUARTER_RATE_40 0xD48 /* (298 + (2 * 21)) * 10MHz core clock */ 2790 2791 #define AR5416_IFS_SLOT_FULL_RATE_44 0x18c /* 9 us half, 44 MHz core clock (9*44) */ 2792 #define AR5416_IFS_SLOT_HALF_RATE_44 0x11e /* 13 us half, 22 MHz core clock (13*22) */ 2793 #define AR5416_IFS_SLOT_QUARTER_RATE_44 0xe7 /* 21 us quarter, 11 MHz core clock (21*11) */ 2794 2795 #define AR5416_IFS_EIFS_FULL_RATE_44 0xfd0 /* (74 + (2 * 9)) * 44MHz core clock */ 2796 #define AR5416_IFS_EIFS_HALF_RATE_44 0xf0a /* (149 + (2 * 13)) * 22MHz core clock */ 2797 #define AR5416_IFS_EIFS_QUARTER_RATE_44 0xe9c /* (298 + (2 * 21)) * 11MHz core clock */ 2798 2799 #define AR5416_INIT_USEC_40 40 2800 #define AR5416_HALF_RATE_USEC_40 19 /* ((40 / 2) - 1 ) */ 2801 #define AR5416_QUARTER_RATE_USEC_40 9 /* ((40 / 4) - 1 ) */ 2802 2803 #define AR5416_INIT_USEC_44 44 2804 #define AR5416_HALF_RATE_USEC_44 21 /* ((44 / 2) - 1 ) */ 2805 #define AR5416_QUARTER_RATE_USEC_44 10 /* ((44 / 4) - 1 ) */ 2806 2807 2808 /* XXX What should these be for 40/44MHz clocks (and half/quarter) ? */ 2809 #define AR5416_RX_NON_FULL_RATE_LATENCY 63 2810 #define AR5416_TX_HALF_RATE_LATENCY 108 2811 #define AR5416_TX_QUARTER_RATE_LATENCY 216 2812 2813 /* 2814 * Adjust various register settings based on half/quarter rate clock setting. 2815 * This includes: 2816 * 2817 * + USEC, TX/RX latency, 2818 * + IFS params: slot, eifs, misc etc. 2819 * 2820 * TODO: 2821 * 2822 * + Verify which other registers need to be tweaked; 2823 * + Verify the behaviour of this for 5GHz fast and non-fast clock mode; 2824 * + This just plain won't work for long distance links - the coverage class 2825 * code isn't aware of the slot/ifs/ACK/RTS timeout values that need to 2826 * change; 2827 * + Verify whether the 32KHz USEC value needs to be kept for the 802.11n 2828 * series chips? 2829 * + Calculate/derive values for 2GHz, 5GHz, 5GHz fast clock 2830 */ 2831 static void 2832 ar5416SetIFSTiming(struct ath_hal *ah, const struct ieee80211_channel *chan) 2833 { 2834 uint32_t txLat, rxLat, usec, slot, refClock, eifs, init_usec; 2835 int clk_44 = 0; 2836 2837 HALASSERT(IEEE80211_IS_CHAN_HALF(chan) || 2838 IEEE80211_IS_CHAN_QUARTER(chan)); 2839 2840 /* 2GHz and 5GHz fast clock - 44MHz; else 40MHz */ 2841 if (IEEE80211_IS_CHAN_2GHZ(chan)) 2842 clk_44 = 1; 2843 else if (IEEE80211_IS_CHAN_5GHZ(chan) && 2844 IS_5GHZ_FAST_CLOCK_EN(ah, chan)) 2845 clk_44 = 1; 2846 2847 /* XXX does this need save/restoring for the 11n chips? */ 2848 /* 2849 * XXX TODO: should mask out the txlat/rxlat/usec values? 2850 */ 2851 refClock = OS_REG_READ(ah, AR_USEC) & AR_USEC_USEC32; 2852 2853 /* 2854 * XXX This really should calculate things, not use 2855 * hard coded values! Ew. 2856 */ 2857 if (IEEE80211_IS_CHAN_HALF(chan)) { 2858 if (clk_44) { 2859 slot = AR5416_IFS_SLOT_HALF_RATE_44; 2860 rxLat = AR5416_RX_NON_FULL_RATE_LATENCY << 2861 AR5416_USEC_RX_LAT_S; 2862 txLat = AR5416_TX_HALF_RATE_LATENCY << 2863 AR5416_USEC_TX_LAT_S; 2864 usec = AR5416_HALF_RATE_USEC_44; 2865 eifs = AR5416_IFS_EIFS_HALF_RATE_44; 2866 init_usec = AR5416_INIT_USEC_44 >> 1; 2867 } else { 2868 slot = AR5416_IFS_SLOT_HALF_RATE_40; 2869 rxLat = AR5416_RX_NON_FULL_RATE_LATENCY << 2870 AR5416_USEC_RX_LAT_S; 2871 txLat = AR5416_TX_HALF_RATE_LATENCY << 2872 AR5416_USEC_TX_LAT_S; 2873 usec = AR5416_HALF_RATE_USEC_40; 2874 eifs = AR5416_IFS_EIFS_HALF_RATE_40; 2875 init_usec = AR5416_INIT_USEC_40 >> 1; 2876 } 2877 } else { /* quarter rate */ 2878 if (clk_44) { 2879 slot = AR5416_IFS_SLOT_QUARTER_RATE_44; 2880 rxLat = AR5416_RX_NON_FULL_RATE_LATENCY << 2881 AR5416_USEC_RX_LAT_S; 2882 txLat = AR5416_TX_QUARTER_RATE_LATENCY << 2883 AR5416_USEC_TX_LAT_S; 2884 usec = AR5416_QUARTER_RATE_USEC_44; 2885 eifs = AR5416_IFS_EIFS_QUARTER_RATE_44; 2886 init_usec = AR5416_INIT_USEC_44 >> 2; 2887 } else { 2888 slot = AR5416_IFS_SLOT_QUARTER_RATE_40; 2889 rxLat = AR5416_RX_NON_FULL_RATE_LATENCY << 2890 AR5416_USEC_RX_LAT_S; 2891 txLat = AR5416_TX_QUARTER_RATE_LATENCY << 2892 AR5416_USEC_TX_LAT_S; 2893 usec = AR5416_QUARTER_RATE_USEC_40; 2894 eifs = AR5416_IFS_EIFS_QUARTER_RATE_40; 2895 init_usec = AR5416_INIT_USEC_40 >> 2; 2896 } 2897 } 2898 2899 /* XXX verify these! */ 2900 OS_REG_WRITE(ah, AR_USEC, (usec | refClock | txLat | rxLat)); 2901 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, slot); 2902 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, eifs); 2903 OS_REG_RMW_FIELD(ah, AR_D_GBL_IFS_MISC, 2904 AR_D_GBL_IFS_MISC_USEC_DURATION, init_usec); 2905 } 2906 2907