xref: /freebsd/sys/dev/ath/if_athioctl.h (revision 9768746b)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer,
12  *    without modification.
13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
15  *    redistribution must be conditioned upon including a substantially
16  *    similar Disclaimer requirement for further binary redistribution.
17  *
18  * NO WARRANTY
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
22  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
23  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
24  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
27  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
29  * THE POSSIBILITY OF SUCH DAMAGES.
30  *
31  * $FreeBSD$
32  */
33 
34 /*
35  * Ioctl-related defintions for the Atheros Wireless LAN controller driver.
36  */
37 #ifndef _DEV_ATH_ATHIOCTL_H
38 #define _DEV_ATH_ATHIOCTL_H
39 
40 struct ath_tx_aggr_stats {
41 	u_int32_t	aggr_pkts[64];
42 	u_int32_t	aggr_single_pkt;
43 	u_int32_t	aggr_nonbaw_pkt;
44 	u_int32_t	aggr_aggr_pkt;
45 	u_int32_t	aggr_baw_closed_single_pkt;
46 	u_int32_t	aggr_low_hwq_single_pkt;
47 	u_int32_t	aggr_sched_nopkt;
48 	u_int32_t	aggr_rts_aggr_limited;
49 };
50 
51 #define	ATH_IOCTL_INTR_NUM_SYNC_INTR		32
52 struct ath_intr_stats {
53 	u_int32_t	sync_intr[ATH_IOCTL_INTR_NUM_SYNC_INTR];
54 };
55 
56 #define	ATH_IOCTL_STATS_NUM_RX_PHYERR		64
57 #define	ATH_IOCTL_STATS_NUM_TX_ANTENNA		8
58 #define	ATH_IOCTL_STATS_NUM_RX_ANTENNA		8
59 struct ath_stats {
60 	u_int32_t	ast_watchdog;	/* device reset by watchdog */
61 	u_int32_t	ast_hardware;	/* fatal hardware error interrupts */
62 	u_int32_t	ast_bmiss;	/* beacon miss interrupts */
63 	u_int32_t	ast_bmiss_phantom;/* beacon miss interrupts */
64 	u_int32_t	ast_bstuck;	/* beacon stuck interrupts */
65 	u_int32_t	ast_rxorn;	/* rx overrun interrupts */
66 	u_int32_t	ast_rxeol;	/* rx eol interrupts */
67 	u_int32_t	ast_txurn;	/* tx underrun interrupts */
68 	u_int32_t	ast_mib;	/* mib interrupts */
69 	u_int32_t	ast_intrcoal;	/* interrupts coalesced */
70 	u_int32_t	ast_tx_packets;	/* packet sent on the interface */
71 	u_int32_t	ast_tx_mgmt;	/* management frames transmitted */
72 	u_int32_t	ast_tx_discard;	/* frames discarded prior to assoc */
73 	u_int32_t	ast_tx_qstop;	/* output stopped 'cuz no buffer */
74 	u_int32_t	ast_tx_encap;	/* tx encapsulation failed */
75 	u_int32_t	ast_tx_nonode;	/* tx failed 'cuz no node */
76 	u_int32_t	ast_tx_nombuf;	/* tx failed 'cuz no mbuf */
77 	u_int32_t	ast_tx_nomcl;	/* tx failed 'cuz no cluster */
78 	u_int32_t	ast_tx_linear;	/* tx linearized to cluster */
79 	u_int32_t	ast_tx_nodata;	/* tx discarded empty frame */
80 	u_int32_t	ast_tx_busdma;	/* tx failed for dma resrcs */
81 	u_int32_t	ast_tx_xretries;/* tx failed 'cuz too many retries */
82 	u_int32_t	ast_tx_fifoerr;	/* tx failed 'cuz FIFO underrun */
83 	u_int32_t	ast_tx_filtered;/* tx failed 'cuz xmit filtered */
84 	u_int32_t	ast_tx_shortretry;/* tx on-chip retries (short) */
85 	u_int32_t	ast_tx_longretry;/* tx on-chip retries (long) */
86 	u_int32_t	ast_tx_badrate;	/* tx failed 'cuz bogus xmit rate */
87 	u_int32_t	ast_tx_noack;	/* tx frames with no ack marked */
88 	u_int32_t	ast_tx_rts;	/* tx frames with rts enabled */
89 	u_int32_t	ast_tx_cts;	/* tx frames with cts enabled */
90 	u_int32_t	ast_tx_shortpre;/* tx frames with short preamble */
91 	u_int32_t	ast_tx_altrate;	/* tx frames with alternate rate */
92 	u_int32_t	ast_tx_protect;	/* tx frames with protection */
93 	u_int32_t	ast_tx_ctsburst;/* tx frames with cts and bursting */
94 	u_int32_t	ast_tx_ctsext;	/* tx frames with cts extension */
95 	u_int32_t	ast_rx_nombuf;	/* rx setup failed 'cuz no mbuf */
96 	u_int32_t	ast_rx_busdma;	/* rx setup failed for dma resrcs */
97 	u_int32_t	ast_rx_orn;	/* rx failed 'cuz of desc overrun */
98 	u_int32_t	ast_rx_crcerr;	/* rx failed 'cuz of bad CRC */
99 	u_int32_t	ast_rx_fifoerr;	/* rx failed 'cuz of FIFO overrun */
100 	u_int32_t	ast_rx_badcrypt;/* rx failed 'cuz decryption */
101 	u_int32_t	ast_rx_badmic;	/* rx failed 'cuz MIC failure */
102 	u_int32_t	ast_rx_phyerr;	/* rx failed 'cuz of PHY err */
103 	u_int32_t	ast_rx_phy[ATH_IOCTL_STATS_NUM_RX_PHYERR];
104 					/* rx PHY error per-code counts */
105 	u_int32_t	ast_rx_tooshort;/* rx discarded 'cuz frame too short */
106 	u_int32_t	ast_rx_toobig;	/* rx discarded 'cuz frame too large */
107 	u_int32_t	ast_rx_packets;	/* packet recv on the interface */
108 	u_int32_t	ast_rx_mgt;	/* management frames received */
109 	u_int32_t	ast_rx_ctl;	/* rx discarded 'cuz ctl frame */
110 	int8_t		ast_tx_rssi;	/* tx rssi of last ack */
111 	int8_t		ast_rx_rssi;	/* rx rssi from histogram */
112 	u_int8_t	ast_tx_rate;	/* IEEE rate of last unicast tx */
113 	u_int32_t	ast_be_xmit;	/* beacons transmitted */
114 	u_int32_t	ast_be_nombuf;	/* beacon setup failed 'cuz no mbuf */
115 	u_int32_t	ast_per_cal;	/* periodic calibration calls */
116 	u_int32_t	ast_per_calfail;/* periodic calibration failed */
117 	u_int32_t	ast_per_rfgain;	/* periodic calibration rfgain reset */
118 	u_int32_t	ast_rate_calls;	/* rate control checks */
119 	u_int32_t	ast_rate_raise;	/* rate control raised xmit rate */
120 	u_int32_t	ast_rate_drop;	/* rate control dropped xmit rate */
121 	u_int32_t	ast_ant_defswitch;/* rx/default antenna switches */
122 	u_int32_t	ast_ant_txswitch;/* tx antenna switches */
123 	u_int32_t	ast_ant_rx[ATH_IOCTL_STATS_NUM_RX_ANTENNA];
124 					/* rx frames with antenna */
125 	u_int32_t	ast_ant_tx[ATH_IOCTL_STATS_NUM_TX_ANTENNA];
126 					/* tx frames with antenna */
127 	u_int32_t	ast_cabq_xmit;	/* cabq frames transmitted */
128 	u_int32_t	ast_cabq_busy;	/* cabq found busy */
129 	u_int32_t	ast_tx_raw;	/* tx frames through raw api */
130 	u_int32_t	ast_ff_txok;	/* fast frames tx'd successfully */
131 	u_int32_t	ast_ff_txerr;	/* fast frames tx'd w/ error */
132 	u_int32_t	ast_ff_rx;	/* fast frames rx'd */
133 	u_int32_t	ast_ff_flush;	/* fast frames flushed from staging q */
134 	u_int32_t	ast_tx_qfull;	/* tx dropped 'cuz of queue limit */
135 	int8_t		ast_rx_noise;	/* rx noise floor */
136 	u_int32_t	ast_tx_nobuf;	/* tx dropped 'cuz no ath buffer */
137 	u_int32_t	ast_tdma_update;/* TDMA slot timing updates */
138 	u_int32_t	ast_tdma_timers;/* TDMA slot update set beacon timers */
139 	u_int32_t	ast_tdma_tsf;	/* TDMA slot update set TSF */
140 	u_int16_t	ast_tdma_tsfadjp;/* TDMA slot adjust+ (usec, smoothed)*/
141 	u_int16_t	ast_tdma_tsfadjm;/* TDMA slot adjust- (usec, smoothed)*/
142 	u_int32_t	ast_tdma_ack;	/* TDMA tx failed 'cuz ACK required */
143 	u_int32_t	ast_tx_raw_fail;/* raw tx failed 'cuz h/w down */
144 	u_int32_t	ast_tx_nofrag;	/* tx dropped 'cuz no ath frag buffer */
145 	u_int32_t	ast_be_missed;	/* missed beacons */
146 	u_int32_t	ast_ani_cal;	/* ANI calibrations performed */
147 	u_int32_t	ast_rx_agg;	/* number of aggregate frames RX'ed */
148 	u_int32_t	ast_rx_halfgi;	/* RX half-GI */
149 	u_int32_t	ast_rx_2040;	/* RX 40mhz frame */
150 	u_int32_t	ast_rx_pre_crc_err;	/* RX pre-delimiter CRC error */
151 	u_int32_t	ast_rx_post_crc_err;	/* RX post-delimiter CRC error */
152 	u_int32_t	ast_rx_decrypt_busy_err;	/* RX decrypt engine busy error */
153 	u_int32_t	ast_rx_hi_rx_chain;
154 	u_int32_t	ast_tx_htprotect;	/* HT tx frames with protection */
155 	u_int32_t	ast_rx_hitqueueend;	/* RX hit descr queue end */
156 	u_int32_t	ast_tx_timeout;		/* Global TX timeout */
157 	u_int32_t	ast_tx_cst;		/* Carrier sense timeout */
158 	u_int32_t	ast_tx_xtxop;	/* tx exceeded TXOP */
159 	u_int32_t	ast_tx_timerexpired;	/* tx exceeded TX_TIMER */
160 	u_int32_t	ast_tx_desccfgerr;	/* tx desc cfg error */
161 	u_int32_t	ast_tx_swretries;	/* software TX retries */
162 	u_int32_t	ast_tx_swretrymax;	/* software TX retry max limit reach */
163 	u_int32_t	ast_tx_data_underrun;
164 	u_int32_t	ast_tx_delim_underrun;
165 	u_int32_t	ast_tx_aggr_failall;	/* aggregate TX failed in its entirety */
166 	u_int32_t	ast_tx_getnobuf;
167 	u_int32_t	ast_tx_getbusybuf;
168 	u_int32_t	ast_tx_intr;
169 	u_int32_t	ast_rx_intr;
170 	u_int32_t	ast_tx_aggr_ok;		/* aggregate TX ok */
171 	u_int32_t	ast_tx_aggr_fail;	/* aggregate TX failed */
172 	u_int32_t	ast_tx_mcastq_overflow;	/* multicast queue overflow */
173 	u_int32_t	ast_rx_keymiss;
174 	u_int32_t	ast_tx_swfiltered;
175 	u_int32_t	ast_tx_node_psq_overflow;
176 	u_int32_t	ast_rx_stbc;		/* RX STBC frame */
177 	u_int32_t	ast_tx_nodeq_overflow;	/* node sw queue overflow */
178 	u_int32_t	ast_tx_ldpc;		/* TX LDPC frame */
179 	u_int32_t	ast_tx_stbc;		/* TX STBC frame */
180 	u_int32_t	ast_tsfoor;		/* TSFOOR interrupts */
181 	u_int32_t	ast_pad[10];
182 };
183 
184 #define	SIOCGATHSTATS	_IOWR('i', 137, struct ifreq)
185 #define	SIOCZATHSTATS	_IOWR('i', 139, struct ifreq)
186 #define	SIOCGATHAGSTATS	_IOWR('i', 141, struct ifreq)
187 
188 struct ath_diag {
189 	char	ad_name[IFNAMSIZ];	/* if name, e.g. "ath0" */
190 	u_int16_t ad_id;
191 #define	ATH_DIAG_DYN	0x8000		/* allocate buffer in caller */
192 #define	ATH_DIAG_IN	0x4000		/* copy in parameters */
193 #define	ATH_DIAG_OUT	0x0000		/* copy out results (always) */
194 #define	ATH_DIAG_ID	0x0fff
195 	u_int16_t ad_in_size;		/* pack to fit, yech */
196 	caddr_t	ad_in_data;
197 	caddr_t	ad_out_data;
198 	u_int	ad_out_size;
199 
200 };
201 #define	SIOCGATHDIAG	_IOWR('i', 138, struct ath_diag)
202 #define	SIOCGATHPHYERR	_IOWR('i', 140, struct ath_diag)
203 
204 /*
205  * The rate control ioctl has to support multiple potential rate
206  * control classes.  For now, instead of trying to support an
207  * abstraction for this in the API, let's just use a TLV
208  * representation for the payload and let userspace sort it out.
209  */
210 struct ath_rateioctl_tlv {
211 	uint16_t	tlv_id;
212 	uint16_t	tlv_len;	/* length excluding TLV header */
213 };
214 
215 /*
216  * This is purely the six byte MAC address.
217  */
218 #define	ATH_RATE_TLV_MACADDR		0xaab0
219 
220 /*
221  * The rate control modules may decide to push a mapping table
222  * of rix -> net80211 ratecode as part of the update.
223  */
224 #define	ATH_RATE_TLV_RATETABLE_NENTRIES	64
225 struct ath_rateioctl_rt {
226 	uint16_t	nentries;
227 	uint16_t	pad[1];
228 	uint8_t		ratecode[ATH_RATE_TLV_RATETABLE_NENTRIES];
229 };
230 #define	ATH_RATE_TLV_RATETABLE		0xaab1
231 
232 /*
233  * This is the sample node statistics structure.
234  * More in ath_rate/sample/sample.h.
235  */
236 #define	ATH_RATE_TLV_SAMPLENODE		0xaab2
237 
238 struct ath_rateioctl {
239 	char	if_name[IFNAMSIZ];	/* if name */
240 	union {
241 		uint8_t		macaddr[IEEE80211_ADDR_LEN];
242 		uint64_t	pad;
243 	} is_u;
244 	uint32_t		len;
245 	caddr_t			buf;
246 };
247 #define	SIOCGATHNODERATESTATS	_IOWR('i', 149, struct ath_rateioctl)
248 #define	SIOCGATHRATESTATS	_IOWR('i', 150, struct ath_rateioctl)
249 
250 /*
251  * Radio capture format.
252  */
253 #define ATH_RX_RADIOTAP_PRESENT_BASE (		\
254 	(1 << IEEE80211_RADIOTAP_TSFT)		| \
255 	(1 << IEEE80211_RADIOTAP_FLAGS)		| \
256 	(1 << IEEE80211_RADIOTAP_RATE)		| \
257 	(1 << IEEE80211_RADIOTAP_ANTENNA)	| \
258 	(1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL)	| \
259 	(1 << IEEE80211_RADIOTAP_DBM_ANTNOISE)	| \
260 	(1 << IEEE80211_RADIOTAP_XCHANNEL)	| \
261 	0)
262 
263 #ifdef	ATH_ENABLE_RADIOTAP_VENDOR_EXT
264 #define	ATH_RX_RADIOTAP_PRESENT \
265 	(ATH_RX_RADIOTAP_PRESENT_BASE		| \
266 	(1 << IEEE80211_RADIOTAP_VENDOREXT)	| \
267 	(1 << IEEE80211_RADIOTAP_EXT)		| \
268 	0)
269 #else
270 #define	ATH_RX_RADIOTAP_PRESENT	ATH_RX_RADIOTAP_PRESENT_BASE
271 #endif	/* ATH_ENABLE_RADIOTAP_PRESENT */
272 
273 #ifdef	ATH_ENABLE_RADIOTAP_VENDOR_EXT
274 /*
275  * This is higher than the vendor bitmap used inside
276  * the Atheros reference codebase.
277  */
278 
279 /* Bit 8 */
280 #define	ATH_RADIOTAP_VENDOR_HEADER	8
281 
282 /*
283  * Using four chains makes all the fields in the
284  * per-chain info header be 4-byte aligned.
285  */
286 #define	ATH_RADIOTAP_MAX_CHAINS		4
287 
288 /*
289  * AR9380 and later chips are 3x3, which requires
290  * 5 EVM DWORDs in HT40 mode.
291  */
292 #define	ATH_RADIOTAP_MAX_EVM		5
293 
294 /*
295  * The vendor radiotap header data needs to be:
296  *
297  * + Aligned to a 4 byte address
298  * + .. so all internal fields are 4 bytes aligned;
299  * + .. and no 64 bit fields are allowed.
300  *
301  * So padding is required to ensure this is the case.
302  *
303  * Note that because of the lack of alignment with the
304  * vendor header (6 bytes), the first field must be
305  * two bytes so it can be accessed by alignment-strict
306  * platform (eg MIPS.)
307  */
308 struct ath_radiotap_vendor_hdr {		/* 30 bytes */
309 	uint8_t		vh_version;		/* 1 */
310 	uint8_t		vh_rx_chainmask;	/* 1 */
311 
312 	/* At this point it should be 4 byte aligned */
313 	uint32_t	evm[ATH_RADIOTAP_MAX_EVM];	/* 5 * 4 = 20 */
314 
315 	uint8_t		rssi_ctl[ATH_RADIOTAP_MAX_CHAINS];	/* 4 * 4 = 16 */
316 	uint8_t		rssi_ext[ATH_RADIOTAP_MAX_CHAINS];	/* 4 * 4 = 16 */
317 
318 	uint8_t		vh_phyerr_code;	/* Phy error code, or 0xff */
319 	uint8_t		vh_rs_status;	/* RX status */
320 	uint8_t		vh_rssi;	/* Raw RSSI */
321 	uint8_t		vh_flags;	/* General flags */
322 #define	ATH_VENDOR_PKT_RX	0x01
323 #define	ATH_VENDOR_PKT_TX	0x02
324 #define	ATH_VENDOR_PKT_RXPHYERR	0x04
325 #define	ATH_VENDOR_PKT_ISAGGR	0x08
326 #define	ATH_VENDOR_PKT_MOREAGGR	0x10
327 
328 	uint8_t		vh_rx_hwrate;	/* hardware RX ratecode */
329 	uint8_t		vh_rs_flags;	/* RX HAL flags */
330 	uint8_t		vh_pad[2];	/* pad to DWORD boundary */
331 } __packed;
332 #endif	/* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
333 
334 struct ath_rx_radiotap_header {
335 	struct ieee80211_radiotap_header wr_ihdr;
336 
337 #ifdef	ATH_ENABLE_RADIOTAP_VENDOR_EXT
338 	/* Vendor extension header bitmap */
339 	uint32_t	wr_ext_bitmap;          /* 4 */
340 
341 	/*
342 	 * This padding is needed because:
343 	 * + the radiotap header is 8 bytes;
344 	 * + the extension bitmap is 4 bytes;
345 	 * + the tsf is 8 bytes, so it must start on an 8 byte
346 	 *   boundary.
347 	 */
348 	uint32_t	wr_pad1;
349 #endif	/* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
350 
351 	/* Normal radiotap fields */
352 	u_int64_t	wr_tsf;
353 	u_int8_t	wr_flags;
354 	u_int8_t	wr_rate;
355 	int8_t		wr_antsignal;
356 	int8_t		wr_antnoise;
357 	u_int8_t	wr_antenna;
358 	u_int8_t	wr_pad[3];
359 	u_int32_t	wr_chan_flags;
360 	u_int16_t	wr_chan_freq;
361 	u_int8_t	wr_chan_ieee;
362 	int8_t		wr_chan_maxpow;
363 
364 #ifdef	ATH_ENABLE_RADIOTAP_VENDOR_EXT
365 	/*
366 	 * Vendor header section, as required by the
367 	 * presence of the vendor extension bit and bitmap
368 	 * entry.
369 	 *
370 	 * XXX This must be aligned to a 4 byte address?
371 	 * XXX or 8 byte address?
372 	 */
373 	struct ieee80211_radiotap_vendor_header wr_vh;  /* 6 bytes */
374 
375 	/*
376 	 * Because of the lack of alignment enforced by the above
377 	 * header, this vendor section won't be aligned in any
378 	 * useful way.  So, this will include a two-byte version
379 	 * value which will force the structure to be 4-byte aligned.
380 	 */
381 	struct ath_radiotap_vendor_hdr wr_v;
382 #endif	/* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
383 } __packed __aligned(8);
384 
385 #define ATH_TX_RADIOTAP_PRESENT (		\
386 	(1 << IEEE80211_RADIOTAP_FLAGS)		| \
387 	(1 << IEEE80211_RADIOTAP_RATE)		| \
388 	(1 << IEEE80211_RADIOTAP_DBM_TX_POWER)	| \
389 	(1 << IEEE80211_RADIOTAP_ANTENNA)	| \
390 	(1 << IEEE80211_RADIOTAP_XCHANNEL)	| \
391 	0)
392 
393 struct ath_tx_radiotap_header {
394 	struct ieee80211_radiotap_header wt_ihdr;
395 	u_int8_t	wt_flags;
396 	u_int8_t	wt_rate;
397 	u_int8_t	wt_txpower;
398 	u_int8_t	wt_antenna;
399 	u_int32_t	wt_chan_flags;
400 	u_int16_t	wt_chan_freq;
401 	u_int8_t	wt_chan_ieee;
402 	int8_t		wt_chan_maxpow;
403 } __packed;
404 
405 /*
406  * DFS ioctl commands
407  */
408 
409 #define	DFS_SET_THRESH		2
410 #define	DFS_GET_THRESH		3
411 #define	DFS_RADARDETECTS	6
412 
413 /*
414  * DFS ioctl parameter types
415  */
416 #define DFS_PARAM_FIRPWR	1
417 #define DFS_PARAM_RRSSI		2
418 #define DFS_PARAM_HEIGHT	3
419 #define DFS_PARAM_PRSSI		4
420 #define DFS_PARAM_INBAND	5
421 #define DFS_PARAM_NOL		6	/* XXX not used in FreeBSD */
422 #define DFS_PARAM_RELSTEP_EN	7
423 #define DFS_PARAM_RELSTEP	8
424 #define DFS_PARAM_RELPWR_EN	9
425 #define DFS_PARAM_RELPWR	10
426 #define DFS_PARAM_MAXLEN	11
427 #define DFS_PARAM_USEFIR128	12
428 #define DFS_PARAM_BLOCKRADAR	13
429 #define DFS_PARAM_MAXRSSI_EN	14
430 
431 /* FreeBSD-specific start at 32 */
432 #define	DFS_PARAM_ENABLE	32
433 #define	DFS_PARAM_EN_EXTCH	33
434 
435 /*
436  * Spectral ioctl parameter types
437  */
438 #define	SPECTRAL_PARAM_FFT_PERIOD	1
439 #define	SPECTRAL_PARAM_SS_PERIOD	2
440 #define	SPECTRAL_PARAM_SS_COUNT		3
441 #define	SPECTRAL_PARAM_SS_SHORT_RPT	4
442 #define	SPECTRAL_PARAM_ENABLED		5
443 #define	SPECTRAL_PARAM_ACTIVE		6
444 #define	SPECTRAL_PARAM_SS_SPECTRAL_PRI	7
445 
446 /*
447  * Spectral control parameters
448  */
449 #define	SIOCGATHSPECTRAL	_IOWR('i', 151, struct ath_diag)
450 
451 #define	SPECTRAL_CONTROL_ENABLE		2
452 #define	SPECTRAL_CONTROL_DISABLE	3
453 #define	SPECTRAL_CONTROL_START		4
454 #define	SPECTRAL_CONTROL_STOP		5
455 #define	SPECTRAL_CONTROL_GET_PARAMS	6
456 #define	SPECTRAL_CONTROL_SET_PARAMS	7
457 #define	SPECTRAL_CONTROL_ENABLE_AT_RESET	8
458 #define	SPECTRAL_CONTROL_DISABLE_AT_RESET	9
459 
460 /*
461  * Bluetooth coexistence control parameters
462  */
463 #define	SIOCGATHBTCOEX		_IOWR('i', 152, struct ath_diag)
464 
465 #endif /* _DEV_ATH_ATHIOCTL_H */
466