1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69 #ifdef HAVE_KERNEL_OPTION_HEADERS 70 #include "opt_device_polling.h" 71 #endif 72 73 #include <sys/param.h> 74 #include <sys/endian.h> 75 #include <sys/systm.h> 76 #include <sys/sockio.h> 77 #include <sys/mbuf.h> 78 #include <sys/malloc.h> 79 #include <sys/kernel.h> 80 #include <sys/module.h> 81 #include <sys/socket.h> 82 #include <sys/sysctl.h> 83 84 #include <net/if.h> 85 #include <net/if_arp.h> 86 #include <net/ethernet.h> 87 #include <net/if_dl.h> 88 #include <net/if_media.h> 89 90 #include <net/bpf.h> 91 92 #include <net/if_types.h> 93 #include <net/if_vlan_var.h> 94 95 #include <netinet/in_systm.h> 96 #include <netinet/in.h> 97 #include <netinet/ip.h> 98 99 #include <machine/bus.h> 100 #include <machine/resource.h> 101 #include <sys/bus.h> 102 #include <sys/rman.h> 103 104 #include <dev/mii/mii.h> 105 #include <dev/mii/miivar.h> 106 #include "miidevs.h" 107 #include <dev/mii/brgphyreg.h> 108 109 #ifdef __sparc64__ 110 #include <dev/ofw/ofw_bus.h> 111 #include <dev/ofw/openfirm.h> 112 #include <machine/ofw_machdep.h> 113 #include <machine/ver.h> 114 #endif 115 116 #include <dev/pci/pcireg.h> 117 #include <dev/pci/pcivar.h> 118 119 #include <dev/bge/if_bgereg.h> 120 121 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 122 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 123 124 MODULE_DEPEND(bge, pci, 1, 1, 1); 125 MODULE_DEPEND(bge, ether, 1, 1, 1); 126 MODULE_DEPEND(bge, miibus, 1, 1, 1); 127 128 /* "device miibus" required. See GENERIC if you get errors here. */ 129 #include "miibus_if.h" 130 131 /* 132 * Various supported device vendors/types and their names. Note: the 133 * spec seems to indicate that the hardware still has Alteon's vendor 134 * ID burned into it, though it will always be overriden by the vendor 135 * ID in the EEPROM. Just to be safe, we cover all possibilities. 136 */ 137 static const struct bge_type { 138 uint16_t bge_vid; 139 uint16_t bge_did; 140 } bge_devs[] = { 141 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 142 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 143 144 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 145 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 147 148 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 149 150 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 151 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, 200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, 201 202 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 203 204 { TC_VENDORID, TC_DEVICEID_3C996 }, 205 206 { 0, 0 } 207 }; 208 209 static const struct bge_vendor { 210 uint16_t v_id; 211 const char *v_name; 212 } bge_vendors[] = { 213 { ALTEON_VENDORID, "Alteon" }, 214 { ALTIMA_VENDORID, "Altima" }, 215 { APPLE_VENDORID, "Apple" }, 216 { BCOM_VENDORID, "Broadcom" }, 217 { SK_VENDORID, "SysKonnect" }, 218 { TC_VENDORID, "3Com" }, 219 220 { 0, NULL } 221 }; 222 223 static const struct bge_revision { 224 uint32_t br_chipid; 225 const char *br_name; 226 } bge_revisions[] = { 227 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 228 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 229 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 230 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 231 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 232 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 233 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 234 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 235 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 236 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 237 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 238 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 239 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 240 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 241 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 242 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 243 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 244 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 245 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 246 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 247 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 248 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 249 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 250 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 251 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 252 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 253 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 254 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 255 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 256 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 257 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 258 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 259 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 260 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 261 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 262 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 263 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 264 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 265 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 266 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 267 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 268 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 269 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 270 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 271 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 272 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 273 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, 274 /* 5754 and 5787 share the same ASIC ID */ 275 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 276 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 277 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 278 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 279 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 280 281 { 0, NULL } 282 }; 283 284 /* 285 * Some defaults for major revisions, so that newer steppings 286 * that we don't know about have a shot at working. 287 */ 288 static const struct bge_revision bge_majorrevs[] = { 289 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 290 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 291 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 292 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 293 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 294 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 295 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 296 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 297 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 298 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 299 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 300 /* 5754 and 5787 share the same ASIC ID */ 301 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 302 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 303 304 { 0, NULL } 305 }; 306 307 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 308 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 309 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 310 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 311 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 312 313 const struct bge_revision * bge_lookup_rev(uint32_t); 314 const struct bge_vendor * bge_lookup_vendor(uint16_t); 315 316 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 317 318 static int bge_probe(device_t); 319 static int bge_attach(device_t); 320 static int bge_detach(device_t); 321 static int bge_suspend(device_t); 322 static int bge_resume(device_t); 323 static void bge_release_resources(struct bge_softc *); 324 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 325 static int bge_dma_alloc(device_t); 326 static void bge_dma_free(struct bge_softc *); 327 328 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]); 329 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 330 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 331 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 332 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 333 334 static void bge_txeof(struct bge_softc *); 335 static void bge_rxeof(struct bge_softc *); 336 337 static void bge_asf_driver_up (struct bge_softc *); 338 static void bge_tick(void *); 339 static void bge_stats_update(struct bge_softc *); 340 static void bge_stats_update_regs(struct bge_softc *); 341 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 342 343 static void bge_intr(void *); 344 static void bge_start_locked(struct ifnet *); 345 static void bge_start(struct ifnet *); 346 static int bge_ioctl(struct ifnet *, u_long, caddr_t); 347 static void bge_init_locked(struct bge_softc *); 348 static void bge_init(void *); 349 static void bge_stop(struct bge_softc *); 350 static void bge_watchdog(struct bge_softc *); 351 static void bge_shutdown(device_t); 352 static int bge_ifmedia_upd_locked(struct ifnet *); 353 static int bge_ifmedia_upd(struct ifnet *); 354 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 355 356 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 357 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 358 359 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 360 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 361 362 static void bge_setpromisc(struct bge_softc *); 363 static void bge_setmulti(struct bge_softc *); 364 static void bge_setvlan(struct bge_softc *); 365 366 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *); 367 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 368 static int bge_init_rx_ring_std(struct bge_softc *); 369 static void bge_free_rx_ring_std(struct bge_softc *); 370 static int bge_init_rx_ring_jumbo(struct bge_softc *); 371 static void bge_free_rx_ring_jumbo(struct bge_softc *); 372 static void bge_free_tx_ring(struct bge_softc *); 373 static int bge_init_tx_ring(struct bge_softc *); 374 375 static int bge_chipinit(struct bge_softc *); 376 static int bge_blockinit(struct bge_softc *); 377 378 static int bge_has_eaddr(struct bge_softc *); 379 static uint32_t bge_readmem_ind(struct bge_softc *, int); 380 static void bge_writemem_ind(struct bge_softc *, int, int); 381 static void bge_writembx(struct bge_softc *, int, int); 382 #ifdef notdef 383 static uint32_t bge_readreg_ind(struct bge_softc *, int); 384 #endif 385 static void bge_writemem_direct(struct bge_softc *, int, int); 386 static void bge_writereg_ind(struct bge_softc *, int, int); 387 388 static int bge_miibus_readreg(device_t, int, int); 389 static int bge_miibus_writereg(device_t, int, int, int); 390 static void bge_miibus_statchg(device_t); 391 #ifdef DEVICE_POLLING 392 static void bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 393 #endif 394 395 #define BGE_RESET_START 1 396 #define BGE_RESET_STOP 2 397 static void bge_sig_post_reset(struct bge_softc *, int); 398 static void bge_sig_legacy(struct bge_softc *, int); 399 static void bge_sig_pre_reset(struct bge_softc *, int); 400 static int bge_reset(struct bge_softc *); 401 static void bge_link_upd(struct bge_softc *); 402 403 /* 404 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 405 * leak information to untrusted users. It is also known to cause alignment 406 * traps on certain architectures. 407 */ 408 #ifdef BGE_REGISTER_DEBUG 409 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 410 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 411 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 412 #endif 413 static void bge_add_sysctls(struct bge_softc *); 414 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); 415 416 static device_method_t bge_methods[] = { 417 /* Device interface */ 418 DEVMETHOD(device_probe, bge_probe), 419 DEVMETHOD(device_attach, bge_attach), 420 DEVMETHOD(device_detach, bge_detach), 421 DEVMETHOD(device_shutdown, bge_shutdown), 422 DEVMETHOD(device_suspend, bge_suspend), 423 DEVMETHOD(device_resume, bge_resume), 424 425 /* bus interface */ 426 DEVMETHOD(bus_print_child, bus_generic_print_child), 427 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 428 429 /* MII interface */ 430 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 431 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 432 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 433 434 { 0, 0 } 435 }; 436 437 static driver_t bge_driver = { 438 "bge", 439 bge_methods, 440 sizeof(struct bge_softc) 441 }; 442 443 static devclass_t bge_devclass; 444 445 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 446 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 447 448 static int bge_allow_asf = 1; 449 450 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); 451 452 SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); 453 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0, 454 "Allow ASF mode if available"); 455 456 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500" 457 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2" 458 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500" 459 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3" 460 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" 461 462 static int 463 bge_has_eaddr(struct bge_softc *sc) 464 { 465 #ifdef __sparc64__ 466 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; 467 device_t dev; 468 uint32_t subvendor; 469 470 dev = sc->bge_dev; 471 472 /* 473 * The on-board BGEs found in sun4u machines aren't fitted with 474 * an EEPROM which means that we have to obtain the MAC address 475 * via OFW and that some tests will always fail. We distinguish 476 * such BGEs by the subvendor ID, which also has to be obtained 477 * from OFW instead of the PCI configuration space as the latter 478 * indicates Broadcom as the subvendor of the netboot interface. 479 * For early Blade 1500 and 2500 we even have to check the OFW 480 * device path as the subvendor ID always defaults to Broadcom 481 * there. 482 */ 483 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR, 484 &subvendor, sizeof(subvendor)) == sizeof(subvendor) && 485 subvendor == SUN_VENDORID) 486 return (0); 487 memset(buf, 0, sizeof(buf)); 488 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) { 489 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 && 490 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0) 491 return (0); 492 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 && 493 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0) 494 return (0); 495 } 496 #endif 497 return (1); 498 } 499 500 static uint32_t 501 bge_readmem_ind(struct bge_softc *sc, int off) 502 { 503 device_t dev; 504 uint32_t val; 505 506 dev = sc->bge_dev; 507 508 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 509 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 510 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 511 return (val); 512 } 513 514 static void 515 bge_writemem_ind(struct bge_softc *sc, int off, int val) 516 { 517 device_t dev; 518 519 dev = sc->bge_dev; 520 521 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 522 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 523 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 524 } 525 526 #ifdef notdef 527 static uint32_t 528 bge_readreg_ind(struct bge_softc *sc, int off) 529 { 530 device_t dev; 531 532 dev = sc->bge_dev; 533 534 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 535 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 536 } 537 #endif 538 539 static void 540 bge_writereg_ind(struct bge_softc *sc, int off, int val) 541 { 542 device_t dev; 543 544 dev = sc->bge_dev; 545 546 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 547 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 548 } 549 550 static void 551 bge_writemem_direct(struct bge_softc *sc, int off, int val) 552 { 553 CSR_WRITE_4(sc, off, val); 554 } 555 556 static void 557 bge_writembx(struct bge_softc *sc, int off, int val) 558 { 559 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 560 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 561 562 CSR_WRITE_4(sc, off, val); 563 } 564 565 /* 566 * Map a single buffer address. 567 */ 568 569 static void 570 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 571 { 572 struct bge_dmamap_arg *ctx; 573 574 if (error) 575 return; 576 577 ctx = arg; 578 579 if (nseg > ctx->bge_maxsegs) { 580 ctx->bge_maxsegs = 0; 581 return; 582 } 583 584 ctx->bge_busaddr = segs->ds_addr; 585 } 586 587 static uint8_t 588 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 589 { 590 uint32_t access, byte = 0; 591 int i; 592 593 /* Lock. */ 594 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 595 for (i = 0; i < 8000; i++) { 596 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 597 break; 598 DELAY(20); 599 } 600 if (i == 8000) 601 return (1); 602 603 /* Enable access. */ 604 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 605 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 606 607 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 608 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 609 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 610 DELAY(10); 611 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 612 DELAY(10); 613 break; 614 } 615 } 616 617 if (i == BGE_TIMEOUT * 10) { 618 if_printf(sc->bge_ifp, "nvram read timed out\n"); 619 return (1); 620 } 621 622 /* Get result. */ 623 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 624 625 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 626 627 /* Disable access. */ 628 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 629 630 /* Unlock. */ 631 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 632 CSR_READ_4(sc, BGE_NVRAM_SWARB); 633 634 return (0); 635 } 636 637 /* 638 * Read a sequence of bytes from NVRAM. 639 */ 640 static int 641 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 642 { 643 int err = 0, i; 644 uint8_t byte = 0; 645 646 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 647 return (1); 648 649 for (i = 0; i < cnt; i++) { 650 err = bge_nvram_getbyte(sc, off + i, &byte); 651 if (err) 652 break; 653 *(dest + i) = byte; 654 } 655 656 return (err ? 1 : 0); 657 } 658 659 /* 660 * Read a byte of data stored in the EEPROM at address 'addr.' The 661 * BCM570x supports both the traditional bitbang interface and an 662 * auto access interface for reading the EEPROM. We use the auto 663 * access method. 664 */ 665 static uint8_t 666 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 667 { 668 int i; 669 uint32_t byte = 0; 670 671 /* 672 * Enable use of auto EEPROM access so we can avoid 673 * having to use the bitbang method. 674 */ 675 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 676 677 /* Reset the EEPROM, load the clock period. */ 678 CSR_WRITE_4(sc, BGE_EE_ADDR, 679 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 680 DELAY(20); 681 682 /* Issue the read EEPROM command. */ 683 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 684 685 /* Wait for completion */ 686 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 687 DELAY(10); 688 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 689 break; 690 } 691 692 if (i == BGE_TIMEOUT * 10) { 693 device_printf(sc->bge_dev, "EEPROM read timed out\n"); 694 return (1); 695 } 696 697 /* Get result. */ 698 byte = CSR_READ_4(sc, BGE_EE_DATA); 699 700 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 701 702 return (0); 703 } 704 705 /* 706 * Read a sequence of bytes from the EEPROM. 707 */ 708 static int 709 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 710 { 711 int i, error = 0; 712 uint8_t byte = 0; 713 714 for (i = 0; i < cnt; i++) { 715 error = bge_eeprom_getbyte(sc, off + i, &byte); 716 if (error) 717 break; 718 *(dest + i) = byte; 719 } 720 721 return (error ? 1 : 0); 722 } 723 724 static int 725 bge_miibus_readreg(device_t dev, int phy, int reg) 726 { 727 struct bge_softc *sc; 728 uint32_t val, autopoll; 729 int i; 730 731 sc = device_get_softc(dev); 732 733 /* 734 * Broadcom's own driver always assumes the internal 735 * PHY is at GMII address 1. On some chips, the PHY responds 736 * to accesses at all addresses, which could cause us to 737 * bogusly attach the PHY 32 times at probe type. Always 738 * restricting the lookup to address 1 is simpler than 739 * trying to figure out which chips revisions should be 740 * special-cased. 741 */ 742 if (phy != 1) 743 return (0); 744 745 /* Reading with autopolling on may trigger PCI errors */ 746 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 747 if (autopoll & BGE_MIMODE_AUTOPOLL) { 748 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 749 DELAY(40); 750 } 751 752 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 753 BGE_MIPHY(phy) | BGE_MIREG(reg)); 754 755 for (i = 0; i < BGE_TIMEOUT; i++) { 756 DELAY(10); 757 val = CSR_READ_4(sc, BGE_MI_COMM); 758 if (!(val & BGE_MICOMM_BUSY)) 759 break; 760 } 761 762 if (i == BGE_TIMEOUT) { 763 device_printf(sc->bge_dev, 764 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", 765 phy, reg, val); 766 val = 0; 767 goto done; 768 } 769 770 DELAY(5); 771 val = CSR_READ_4(sc, BGE_MI_COMM); 772 773 done: 774 if (autopoll & BGE_MIMODE_AUTOPOLL) { 775 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 776 DELAY(40); 777 } 778 779 if (val & BGE_MICOMM_READFAIL) 780 return (0); 781 782 return (val & 0xFFFF); 783 } 784 785 static int 786 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 787 { 788 struct bge_softc *sc; 789 uint32_t autopoll; 790 int i; 791 792 sc = device_get_softc(dev); 793 794 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 795 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 796 return(0); 797 798 /* Reading with autopolling on may trigger PCI errors */ 799 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 800 if (autopoll & BGE_MIMODE_AUTOPOLL) { 801 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 802 DELAY(40); 803 } 804 805 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 806 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 807 808 for (i = 0; i < BGE_TIMEOUT; i++) { 809 DELAY(10); 810 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 811 DELAY(5); 812 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 813 break; 814 } 815 } 816 817 if (i == BGE_TIMEOUT) { 818 device_printf(sc->bge_dev, 819 "PHY write timed out (phy %d, reg %d, val %d)\n", 820 phy, reg, val); 821 return (0); 822 } 823 824 if (autopoll & BGE_MIMODE_AUTOPOLL) { 825 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 826 DELAY(40); 827 } 828 829 return (0); 830 } 831 832 static void 833 bge_miibus_statchg(device_t dev) 834 { 835 struct bge_softc *sc; 836 struct mii_data *mii; 837 sc = device_get_softc(dev); 838 mii = device_get_softc(sc->bge_miibus); 839 840 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 841 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 842 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 843 else 844 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 845 846 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 847 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 848 else 849 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 850 } 851 852 /* 853 * Intialize a standard receive ring descriptor. 854 */ 855 static int 856 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m) 857 { 858 struct mbuf *m_new = NULL; 859 struct bge_rx_bd *r; 860 struct bge_dmamap_arg ctx; 861 int error; 862 863 if (m == NULL) { 864 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 865 if (m_new == NULL) 866 return (ENOBUFS); 867 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 868 } else { 869 m_new = m; 870 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 871 m_new->m_data = m_new->m_ext.ext_buf; 872 } 873 874 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 875 m_adj(m_new, ETHER_ALIGN); 876 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 877 r = &sc->bge_ldata.bge_rx_std_ring[i]; 878 ctx.bge_maxsegs = 1; 879 ctx.sc = sc; 880 error = bus_dmamap_load(sc->bge_cdata.bge_mtag, 881 sc->bge_cdata.bge_rx_std_dmamap[i], mtod(m_new, void *), 882 m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 883 if (error || ctx.bge_maxsegs == 0) { 884 if (m == NULL) { 885 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 886 m_freem(m_new); 887 } 888 return (ENOMEM); 889 } 890 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_busaddr); 891 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_busaddr); 892 r->bge_flags = BGE_RXBDFLAG_END; 893 r->bge_len = m_new->m_len; 894 r->bge_idx = i; 895 896 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 897 sc->bge_cdata.bge_rx_std_dmamap[i], 898 BUS_DMASYNC_PREREAD); 899 900 return (0); 901 } 902 903 /* 904 * Initialize a jumbo receive ring descriptor. This allocates 905 * a jumbo buffer from the pool managed internally by the driver. 906 */ 907 static int 908 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 909 { 910 bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 911 struct bge_extrx_bd *r; 912 struct mbuf *m_new = NULL; 913 int nsegs; 914 int error; 915 916 if (m == NULL) { 917 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 918 if (m_new == NULL) 919 return (ENOBUFS); 920 921 m_cljget(m_new, M_DONTWAIT, MJUM9BYTES); 922 if (!(m_new->m_flags & M_EXT)) { 923 m_freem(m_new); 924 return (ENOBUFS); 925 } 926 m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES; 927 } else { 928 m_new = m; 929 m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES; 930 m_new->m_data = m_new->m_ext.ext_buf; 931 } 932 933 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 934 m_adj(m_new, ETHER_ALIGN); 935 936 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 937 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 938 m_new, segs, &nsegs, BUS_DMA_NOWAIT); 939 if (error) { 940 if (m == NULL) 941 m_freem(m_new); 942 return (error); 943 } 944 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 945 946 /* 947 * Fill in the extended RX buffer descriptor. 948 */ 949 r = &sc->bge_ldata.bge_rx_jumbo_ring[i]; 950 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 951 r->bge_idx = i; 952 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 953 switch (nsegs) { 954 case 4: 955 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 956 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 957 r->bge_len3 = segs[3].ds_len; 958 case 3: 959 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 960 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 961 r->bge_len2 = segs[2].ds_len; 962 case 2: 963 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 964 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 965 r->bge_len1 = segs[1].ds_len; 966 case 1: 967 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 968 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 969 r->bge_len0 = segs[0].ds_len; 970 break; 971 default: 972 panic("%s: %d segments\n", __func__, nsegs); 973 } 974 975 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 976 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 977 BUS_DMASYNC_PREREAD); 978 979 return (0); 980 } 981 982 /* 983 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 984 * that's 1MB or memory, which is a lot. For now, we fill only the first 985 * 256 ring entries and hope that our CPU is fast enough to keep up with 986 * the NIC. 987 */ 988 static int 989 bge_init_rx_ring_std(struct bge_softc *sc) 990 { 991 int i; 992 993 for (i = 0; i < BGE_SSLOTS; i++) { 994 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 995 return (ENOBUFS); 996 }; 997 998 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 999 sc->bge_cdata.bge_rx_std_ring_map, 1000 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1001 1002 sc->bge_std = i - 1; 1003 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1004 1005 return (0); 1006 } 1007 1008 static void 1009 bge_free_rx_ring_std(struct bge_softc *sc) 1010 { 1011 int i; 1012 1013 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1014 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1015 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 1016 sc->bge_cdata.bge_rx_std_dmamap[i], 1017 BUS_DMASYNC_POSTREAD); 1018 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 1019 sc->bge_cdata.bge_rx_std_dmamap[i]); 1020 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1021 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1022 } 1023 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1024 sizeof(struct bge_rx_bd)); 1025 } 1026 } 1027 1028 static int 1029 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1030 { 1031 struct bge_rcb *rcb; 1032 int i; 1033 1034 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1035 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1036 return (ENOBUFS); 1037 }; 1038 1039 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1040 sc->bge_cdata.bge_rx_jumbo_ring_map, 1041 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1042 1043 sc->bge_jumbo = i - 1; 1044 1045 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1046 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1047 BGE_RCB_FLAG_USE_EXT_RX_BD); 1048 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1049 1050 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1051 1052 return (0); 1053 } 1054 1055 static void 1056 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1057 { 1058 int i; 1059 1060 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1061 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1062 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1063 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 1064 BUS_DMASYNC_POSTREAD); 1065 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1066 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1067 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1068 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1069 } 1070 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1071 sizeof(struct bge_extrx_bd)); 1072 } 1073 } 1074 1075 static void 1076 bge_free_tx_ring(struct bge_softc *sc) 1077 { 1078 int i; 1079 1080 if (sc->bge_ldata.bge_tx_ring == NULL) 1081 return; 1082 1083 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1084 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1085 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 1086 sc->bge_cdata.bge_tx_dmamap[i], 1087 BUS_DMASYNC_POSTWRITE); 1088 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 1089 sc->bge_cdata.bge_tx_dmamap[i]); 1090 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1091 sc->bge_cdata.bge_tx_chain[i] = NULL; 1092 } 1093 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1094 sizeof(struct bge_tx_bd)); 1095 } 1096 } 1097 1098 static int 1099 bge_init_tx_ring(struct bge_softc *sc) 1100 { 1101 sc->bge_txcnt = 0; 1102 sc->bge_tx_saved_considx = 0; 1103 1104 /* Initialize transmit producer index for host-memory send ring. */ 1105 sc->bge_tx_prodidx = 0; 1106 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1107 1108 /* 5700 b2 errata */ 1109 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1110 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1111 1112 /* NIC-memory send ring not used; initialize to zero. */ 1113 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1114 /* 5700 b2 errata */ 1115 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1116 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1117 1118 return (0); 1119 } 1120 1121 static void 1122 bge_setpromisc(struct bge_softc *sc) 1123 { 1124 struct ifnet *ifp; 1125 1126 BGE_LOCK_ASSERT(sc); 1127 1128 ifp = sc->bge_ifp; 1129 1130 /* Enable or disable promiscuous mode as needed. */ 1131 if (ifp->if_flags & IFF_PROMISC) 1132 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1133 else 1134 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1135 } 1136 1137 static void 1138 bge_setmulti(struct bge_softc *sc) 1139 { 1140 struct ifnet *ifp; 1141 struct ifmultiaddr *ifma; 1142 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1143 int h, i; 1144 1145 BGE_LOCK_ASSERT(sc); 1146 1147 ifp = sc->bge_ifp; 1148 1149 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1150 for (i = 0; i < 4; i++) 1151 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1152 return; 1153 } 1154 1155 /* First, zot all the existing filters. */ 1156 for (i = 0; i < 4; i++) 1157 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1158 1159 /* Now program new ones. */ 1160 IF_ADDR_LOCK(ifp); 1161 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1162 if (ifma->ifma_addr->sa_family != AF_LINK) 1163 continue; 1164 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1165 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F; 1166 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1167 } 1168 IF_ADDR_UNLOCK(ifp); 1169 1170 for (i = 0; i < 4; i++) 1171 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1172 } 1173 1174 static void 1175 bge_setvlan(struct bge_softc *sc) 1176 { 1177 struct ifnet *ifp; 1178 1179 BGE_LOCK_ASSERT(sc); 1180 1181 ifp = sc->bge_ifp; 1182 1183 /* Enable or disable VLAN tag stripping as needed. */ 1184 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1185 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1186 else 1187 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1188 } 1189 1190 static void 1191 bge_sig_pre_reset(sc, type) 1192 struct bge_softc *sc; 1193 int type; 1194 { 1195 /* 1196 * Some chips don't like this so only do this if ASF is enabled 1197 */ 1198 if (sc->bge_asf_mode) 1199 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1200 1201 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1202 switch (type) { 1203 case BGE_RESET_START: 1204 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1205 break; 1206 case BGE_RESET_STOP: 1207 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1208 break; 1209 } 1210 } 1211 } 1212 1213 static void 1214 bge_sig_post_reset(sc, type) 1215 struct bge_softc *sc; 1216 int type; 1217 { 1218 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1219 switch (type) { 1220 case BGE_RESET_START: 1221 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001); 1222 /* START DONE */ 1223 break; 1224 case BGE_RESET_STOP: 1225 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002); 1226 break; 1227 } 1228 } 1229 } 1230 1231 static void 1232 bge_sig_legacy(sc, type) 1233 struct bge_softc *sc; 1234 int type; 1235 { 1236 if (sc->bge_asf_mode) { 1237 switch (type) { 1238 case BGE_RESET_START: 1239 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1240 break; 1241 case BGE_RESET_STOP: 1242 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1243 break; 1244 } 1245 } 1246 } 1247 1248 void bge_stop_fw(struct bge_softc *); 1249 void 1250 bge_stop_fw(sc) 1251 struct bge_softc *sc; 1252 { 1253 int i; 1254 1255 if (sc->bge_asf_mode) { 1256 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE); 1257 CSR_WRITE_4(sc, BGE_CPU_EVENT, 1258 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 1259 1260 for (i = 0; i < 100; i++ ) { 1261 if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14))) 1262 break; 1263 DELAY(10); 1264 } 1265 } 1266 } 1267 1268 /* 1269 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1270 * self-test results. 1271 */ 1272 static int 1273 bge_chipinit(struct bge_softc *sc) 1274 { 1275 uint32_t dma_rw_ctl; 1276 int i; 1277 1278 /* Set endianness before we access any non-PCI registers. */ 1279 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4); 1280 1281 /* 1282 * Check the 'ROM failed' bit on the RX CPU to see if 1283 * self-tests passed. Skip this check when there's no 1284 * chip containing the Ethernet address fitted, since 1285 * in that case it will always fail. 1286 */ 1287 if ((sc->bge_flags & BGE_FLAG_EADDR) && 1288 CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1289 device_printf(sc->bge_dev, "RX CPU self-diagnostics failed!\n"); 1290 return (ENODEV); 1291 } 1292 1293 /* Clear the MAC control register */ 1294 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1295 1296 /* 1297 * Clear the MAC statistics block in the NIC's 1298 * internal memory. 1299 */ 1300 for (i = BGE_STATS_BLOCK; 1301 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1302 BGE_MEMWIN_WRITE(sc, i, 0); 1303 1304 for (i = BGE_STATUS_BLOCK; 1305 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1306 BGE_MEMWIN_WRITE(sc, i, 0); 1307 1308 /* 1309 * Set up the PCI DMA control register. 1310 */ 1311 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1312 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); 1313 if (sc->bge_flags & BGE_FLAG_PCIE) { 1314 /* Read watermark not used, 128 bytes for write. */ 1315 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1316 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1317 if (BGE_IS_5714_FAMILY(sc)) { 1318 /* 256 bytes for read and write. */ 1319 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1320 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1321 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? 1322 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : 1323 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1324 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1325 /* 1536 bytes for read, 384 bytes for write. */ 1326 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1327 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1328 } else { 1329 /* 384 bytes for read and write. */ 1330 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1331 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1332 0x0F; 1333 } 1334 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1335 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1336 uint32_t tmp; 1337 1338 /* Set ONE_DMA_AT_ONCE for hardware workaround. */ 1339 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1340 if (tmp == 6 || tmp == 7) 1341 dma_rw_ctl |= 1342 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1343 1344 /* Set PCI-X DMA write workaround. */ 1345 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1346 } 1347 } else { 1348 /* Conventional PCI bus: 256 bytes for read and write. */ 1349 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1350 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1351 1352 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1353 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1354 dma_rw_ctl |= 0x0F; 1355 } 1356 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1357 sc->bge_asicrev == BGE_ASICREV_BCM5701) 1358 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1359 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1360 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1361 sc->bge_asicrev == BGE_ASICREV_BCM5704) 1362 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1363 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1364 1365 /* 1366 * Set up general mode register. 1367 */ 1368 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1369 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1370 BGE_MODECTL_TX_NO_PHDR_CSUM); 1371 1372 /* 1373 * BCM5701 B5 have a bug causing data corruption when using 1374 * 64-bit DMA reads, which can be terminated early and then 1375 * completed later as 32-bit accesses, in combination with 1376 * certain bridges. 1377 */ 1378 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 1379 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1380 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32); 1381 1382 /* 1383 * Tell the firmware the driver is running 1384 */ 1385 if (sc->bge_asf_mode & ASF_STACKUP) 1386 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 1387 1388 /* 1389 * Disable memory write invalidate. Apparently it is not supported 1390 * properly by these devices. 1391 */ 1392 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1393 1394 /* Set the timer prescaler (always 66Mhz) */ 1395 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1396 1397 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ 1398 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1399 DELAY(40); /* XXX */ 1400 1401 /* Put PHY into ready state */ 1402 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1403 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1404 DELAY(40); 1405 } 1406 1407 return (0); 1408 } 1409 1410 static int 1411 bge_blockinit(struct bge_softc *sc) 1412 { 1413 struct bge_rcb *rcb; 1414 bus_size_t vrcb; 1415 bge_hostaddr taddr; 1416 uint32_t val; 1417 int i; 1418 1419 /* 1420 * Initialize the memory window pointer register so that 1421 * we can access the first 32K of internal NIC RAM. This will 1422 * allow us to set up the TX send ring RCBs and the RX return 1423 * ring RCBs, plus other things which live in NIC memory. 1424 */ 1425 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1426 1427 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1428 1429 if (!(BGE_IS_5705_PLUS(sc))) { 1430 /* Configure mbuf memory pool */ 1431 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1432 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1433 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1434 else 1435 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1436 1437 /* Configure DMA resource pool */ 1438 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1439 BGE_DMA_DESCRIPTORS); 1440 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1441 } 1442 1443 /* Configure mbuf pool watermarks */ 1444 if (!BGE_IS_5705_PLUS(sc)) { 1445 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1446 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1447 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1448 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1449 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1450 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1451 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1452 } else { 1453 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1454 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1455 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1456 } 1457 1458 /* Configure DMA resource watermarks */ 1459 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1460 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1461 1462 /* Enable buffer manager */ 1463 if (!(BGE_IS_5705_PLUS(sc))) { 1464 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1465 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 1466 1467 /* Poll for buffer manager start indication */ 1468 for (i = 0; i < BGE_TIMEOUT; i++) { 1469 DELAY(10); 1470 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1471 break; 1472 } 1473 1474 if (i == BGE_TIMEOUT) { 1475 device_printf(sc->bge_dev, 1476 "buffer manager failed to start\n"); 1477 return (ENXIO); 1478 } 1479 } 1480 1481 /* Enable flow-through queues */ 1482 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1483 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1484 1485 /* Wait until queue initialization is complete */ 1486 for (i = 0; i < BGE_TIMEOUT; i++) { 1487 DELAY(10); 1488 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1489 break; 1490 } 1491 1492 if (i == BGE_TIMEOUT) { 1493 device_printf(sc->bge_dev, "flow-through queue init failed\n"); 1494 return (ENXIO); 1495 } 1496 1497 /* Initialize the standard RX ring control block */ 1498 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 1499 rcb->bge_hostaddr.bge_addr_lo = 1500 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 1501 rcb->bge_hostaddr.bge_addr_hi = 1502 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 1503 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1504 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 1505 if (BGE_IS_5705_PLUS(sc)) 1506 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1507 else 1508 rcb->bge_maxlen_flags = 1509 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1510 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1511 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1512 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1513 1514 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1515 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1516 1517 /* 1518 * Initialize the jumbo RX ring control block 1519 * We set the 'ring disabled' bit in the flags 1520 * field until we're actually ready to start 1521 * using this ring (i.e. once we set the MTU 1522 * high enough to require it). 1523 */ 1524 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1525 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1526 1527 rcb->bge_hostaddr.bge_addr_lo = 1528 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1529 rcb->bge_hostaddr.bge_addr_hi = 1530 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1531 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1532 sc->bge_cdata.bge_rx_jumbo_ring_map, 1533 BUS_DMASYNC_PREREAD); 1534 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1535 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 1536 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1537 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1538 rcb->bge_hostaddr.bge_addr_hi); 1539 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1540 rcb->bge_hostaddr.bge_addr_lo); 1541 1542 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1543 rcb->bge_maxlen_flags); 1544 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1545 1546 /* Set up dummy disabled mini ring RCB */ 1547 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 1548 rcb->bge_maxlen_flags = 1549 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1550 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1551 rcb->bge_maxlen_flags); 1552 } 1553 1554 /* 1555 * Set the BD ring replentish thresholds. The recommended 1556 * values are 1/8th the number of descriptors allocated to 1557 * each ring. 1558 * XXX The 5754 requires a lower threshold, so it might be a 1559 * requirement of all 575x family chips. The Linux driver sets 1560 * the lower threshold for all 5705 family chips as well, but there 1561 * are reports that it might not need to be so strict. 1562 * 1563 * XXX Linux does some extra fiddling here for the 5906 parts as 1564 * well. 1565 */ 1566 if (BGE_IS_5705_PLUS(sc)) 1567 val = 8; 1568 else 1569 val = BGE_STD_RX_RING_CNT / 8; 1570 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 1571 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1572 1573 /* 1574 * Disable all unused send rings by setting the 'ring disabled' 1575 * bit in the flags field of all the TX send ring control blocks. 1576 * These are located in NIC memory. 1577 */ 1578 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1579 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1580 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1581 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1582 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1583 vrcb += sizeof(struct bge_rcb); 1584 } 1585 1586 /* Configure TX RCB 0 (we use only the first ring) */ 1587 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1588 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 1589 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1590 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1591 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 1592 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1593 if (!(BGE_IS_5705_PLUS(sc))) 1594 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1595 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1596 1597 /* Disable all unused RX return rings */ 1598 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1599 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1600 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 1601 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 1602 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1603 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1604 BGE_RCB_FLAG_RING_DISABLED)); 1605 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1606 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1607 (i * (sizeof(uint64_t))), 0); 1608 vrcb += sizeof(struct bge_rcb); 1609 } 1610 1611 /* Initialize RX ring indexes */ 1612 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1613 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1614 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1615 1616 /* 1617 * Set up RX return ring 0 1618 * Note that the NIC address for RX return rings is 0x00000000. 1619 * The return rings live entirely within the host, so the 1620 * nicaddr field in the RCB isn't used. 1621 */ 1622 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1623 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 1624 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1625 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1626 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000); 1627 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1628 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1629 1630 /* Set random backoff seed for TX */ 1631 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1632 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 1633 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 1634 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] + 1635 BGE_TX_BACKOFF_SEED_MASK); 1636 1637 /* Set inter-packet gap */ 1638 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1639 1640 /* 1641 * Specify which ring to use for packets that don't match 1642 * any RX rules. 1643 */ 1644 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1645 1646 /* 1647 * Configure number of RX lists. One interrupt distribution 1648 * list, sixteen active lists, one bad frames class. 1649 */ 1650 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1651 1652 /* Inialize RX list placement stats mask. */ 1653 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1654 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1655 1656 /* Disable host coalescing until we get it set up */ 1657 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1658 1659 /* Poll to make sure it's shut down. */ 1660 for (i = 0; i < BGE_TIMEOUT; i++) { 1661 DELAY(10); 1662 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1663 break; 1664 } 1665 1666 if (i == BGE_TIMEOUT) { 1667 device_printf(sc->bge_dev, 1668 "host coalescing engine failed to idle\n"); 1669 return (ENXIO); 1670 } 1671 1672 /* Set up host coalescing defaults */ 1673 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1674 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1675 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1676 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1677 if (!(BGE_IS_5705_PLUS(sc))) { 1678 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1679 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1680 } 1681 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 1682 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 1683 1684 /* Set up address of statistics block */ 1685 if (!(BGE_IS_5705_PLUS(sc))) { 1686 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 1687 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 1688 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1689 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 1690 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1691 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1692 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1693 } 1694 1695 /* Set up address of status block */ 1696 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1697 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 1698 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1699 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 1700 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0; 1701 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0; 1702 1703 /* Turn on host coalescing state machine */ 1704 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1705 1706 /* Turn on RX BD completion state machine and enable attentions */ 1707 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1708 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 1709 1710 /* Turn on RX list placement state machine */ 1711 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1712 1713 /* Turn on RX list selector state machine. */ 1714 if (!(BGE_IS_5705_PLUS(sc))) 1715 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1716 1717 /* Turn on DMA, clear stats */ 1718 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB | 1719 BGE_MACMODE_RXDMA_ENB | BGE_MACMODE_RX_STATS_CLEAR | 1720 BGE_MACMODE_TX_STATS_CLEAR | BGE_MACMODE_RX_STATS_ENB | 1721 BGE_MACMODE_TX_STATS_ENB | BGE_MACMODE_FRMHDR_DMA_ENB | 1722 ((sc->bge_flags & BGE_FLAG_TBI) ? 1723 BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1724 1725 /* Set misc. local control, enable interrupts on attentions */ 1726 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1727 1728 #ifdef notdef 1729 /* Assert GPIO pins for PHY reset */ 1730 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 1731 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 1732 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 1733 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 1734 #endif 1735 1736 /* Turn on DMA completion state machine */ 1737 if (!(BGE_IS_5705_PLUS(sc))) 1738 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1739 1740 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 1741 1742 /* Enable host coalescing bug fix. */ 1743 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 1744 sc->bge_asicrev == BGE_ASICREV_BCM5787) 1745 val |= 1 << 29; 1746 1747 /* Turn on write DMA state machine */ 1748 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 1749 1750 /* Turn on read DMA state machine */ 1751 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1752 BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS); 1753 1754 /* Turn on RX data completion state machine */ 1755 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1756 1757 /* Turn on RX BD initiator state machine */ 1758 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1759 1760 /* Turn on RX data and RX BD initiator state machine */ 1761 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1762 1763 /* Turn on Mbuf cluster free state machine */ 1764 if (!(BGE_IS_5705_PLUS(sc))) 1765 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1766 1767 /* Turn on send BD completion state machine */ 1768 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1769 1770 /* Turn on send data completion state machine */ 1771 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1772 1773 /* Turn on send data initiator state machine */ 1774 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1775 1776 /* Turn on send BD initiator state machine */ 1777 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1778 1779 /* Turn on send BD selector state machine */ 1780 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1781 1782 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1783 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1784 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 1785 1786 /* ack/clear link change events */ 1787 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 1788 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 1789 BGE_MACSTAT_LINK_CHANGED); 1790 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1791 1792 /* Enable PHY auto polling (for MII/GMII only) */ 1793 if (sc->bge_flags & BGE_FLAG_TBI) { 1794 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1795 } else { 1796 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 1797 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 1798 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 1799 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1800 BGE_EVTENB_MI_INTERRUPT); 1801 } 1802 1803 /* 1804 * Clear any pending link state attention. 1805 * Otherwise some link state change events may be lost until attention 1806 * is cleared by bge_intr() -> bge_link_upd() sequence. 1807 * It's not necessary on newer BCM chips - perhaps enabling link 1808 * state change attentions implies clearing pending attention. 1809 */ 1810 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 1811 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 1812 BGE_MACSTAT_LINK_CHANGED); 1813 1814 /* Enable link state change attentions. */ 1815 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1816 1817 return (0); 1818 } 1819 1820 const struct bge_revision * 1821 bge_lookup_rev(uint32_t chipid) 1822 { 1823 const struct bge_revision *br; 1824 1825 for (br = bge_revisions; br->br_name != NULL; br++) { 1826 if (br->br_chipid == chipid) 1827 return (br); 1828 } 1829 1830 for (br = bge_majorrevs; br->br_name != NULL; br++) { 1831 if (br->br_chipid == BGE_ASICREV(chipid)) 1832 return (br); 1833 } 1834 1835 return (NULL); 1836 } 1837 1838 const struct bge_vendor * 1839 bge_lookup_vendor(uint16_t vid) 1840 { 1841 const struct bge_vendor *v; 1842 1843 for (v = bge_vendors; v->v_name != NULL; v++) 1844 if (v->v_id == vid) 1845 return (v); 1846 1847 panic("%s: unknown vendor %d", __func__, vid); 1848 return (NULL); 1849 } 1850 1851 /* 1852 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1853 * against our list and return its name if we find a match. 1854 * 1855 * Note that since the Broadcom controller contains VPD support, we 1856 * try to get the device name string from the controller itself instead 1857 * of the compiled-in string. It guarantees we'll always announce the 1858 * right product name. We fall back to the compiled-in string when 1859 * VPD is unavailable or corrupt. 1860 */ 1861 static int 1862 bge_probe(device_t dev) 1863 { 1864 const struct bge_type *t = bge_devs; 1865 struct bge_softc *sc = device_get_softc(dev); 1866 uint16_t vid, did; 1867 1868 sc->bge_dev = dev; 1869 vid = pci_get_vendor(dev); 1870 did = pci_get_device(dev); 1871 while(t->bge_vid != 0) { 1872 if ((vid == t->bge_vid) && (did == t->bge_did)) { 1873 char model[64], buf[96]; 1874 const struct bge_revision *br; 1875 const struct bge_vendor *v; 1876 uint32_t id; 1877 1878 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 1879 BGE_PCIMISCCTL_ASICREV; 1880 br = bge_lookup_rev(id); 1881 v = bge_lookup_vendor(vid); 1882 { 1883 #if __FreeBSD_version > 700024 1884 const char *pname; 1885 1886 if (bge_has_eaddr(sc) && 1887 pci_get_vpd_ident(dev, &pname) == 0) 1888 snprintf(model, 64, "%s", pname); 1889 else 1890 #endif 1891 snprintf(model, 64, "%s %s", 1892 v->v_name, 1893 br != NULL ? br->br_name : 1894 "NetXtreme Ethernet Controller"); 1895 } 1896 snprintf(buf, 96, "%s, %sASIC rev. %#04x", model, 1897 br != NULL ? "" : "unknown ", id >> 16); 1898 device_set_desc_copy(dev, buf); 1899 if (pci_get_subvendor(dev) == DELL_VENDORID) 1900 sc->bge_flags |= BGE_FLAG_NO_3LED; 1901 if (did == BCOM_DEVICEID_BCM5755M) 1902 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM; 1903 return (0); 1904 } 1905 t++; 1906 } 1907 1908 return (ENXIO); 1909 } 1910 1911 static void 1912 bge_dma_free(struct bge_softc *sc) 1913 { 1914 int i; 1915 1916 /* Destroy DMA maps for RX buffers. */ 1917 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1918 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 1919 bus_dmamap_destroy(sc->bge_cdata.bge_mtag, 1920 sc->bge_cdata.bge_rx_std_dmamap[i]); 1921 } 1922 1923 /* Destroy DMA maps for jumbo RX buffers. */ 1924 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1925 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 1926 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 1927 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1928 } 1929 1930 /* Destroy DMA maps for TX buffers. */ 1931 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1932 if (sc->bge_cdata.bge_tx_dmamap[i]) 1933 bus_dmamap_destroy(sc->bge_cdata.bge_mtag, 1934 sc->bge_cdata.bge_tx_dmamap[i]); 1935 } 1936 1937 if (sc->bge_cdata.bge_mtag) 1938 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag); 1939 1940 1941 /* Destroy standard RX ring. */ 1942 if (sc->bge_cdata.bge_rx_std_ring_map) 1943 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 1944 sc->bge_cdata.bge_rx_std_ring_map); 1945 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring) 1946 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 1947 sc->bge_ldata.bge_rx_std_ring, 1948 sc->bge_cdata.bge_rx_std_ring_map); 1949 1950 if (sc->bge_cdata.bge_rx_std_ring_tag) 1951 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 1952 1953 /* Destroy jumbo RX ring. */ 1954 if (sc->bge_cdata.bge_rx_jumbo_ring_map) 1955 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1956 sc->bge_cdata.bge_rx_jumbo_ring_map); 1957 1958 if (sc->bge_cdata.bge_rx_jumbo_ring_map && 1959 sc->bge_ldata.bge_rx_jumbo_ring) 1960 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1961 sc->bge_ldata.bge_rx_jumbo_ring, 1962 sc->bge_cdata.bge_rx_jumbo_ring_map); 1963 1964 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 1965 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 1966 1967 /* Destroy RX return ring. */ 1968 if (sc->bge_cdata.bge_rx_return_ring_map) 1969 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 1970 sc->bge_cdata.bge_rx_return_ring_map); 1971 1972 if (sc->bge_cdata.bge_rx_return_ring_map && 1973 sc->bge_ldata.bge_rx_return_ring) 1974 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 1975 sc->bge_ldata.bge_rx_return_ring, 1976 sc->bge_cdata.bge_rx_return_ring_map); 1977 1978 if (sc->bge_cdata.bge_rx_return_ring_tag) 1979 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 1980 1981 /* Destroy TX ring. */ 1982 if (sc->bge_cdata.bge_tx_ring_map) 1983 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 1984 sc->bge_cdata.bge_tx_ring_map); 1985 1986 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring) 1987 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 1988 sc->bge_ldata.bge_tx_ring, 1989 sc->bge_cdata.bge_tx_ring_map); 1990 1991 if (sc->bge_cdata.bge_tx_ring_tag) 1992 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 1993 1994 /* Destroy status block. */ 1995 if (sc->bge_cdata.bge_status_map) 1996 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 1997 sc->bge_cdata.bge_status_map); 1998 1999 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block) 2000 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 2001 sc->bge_ldata.bge_status_block, 2002 sc->bge_cdata.bge_status_map); 2003 2004 if (sc->bge_cdata.bge_status_tag) 2005 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 2006 2007 /* Destroy statistics block. */ 2008 if (sc->bge_cdata.bge_stats_map) 2009 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 2010 sc->bge_cdata.bge_stats_map); 2011 2012 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats) 2013 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 2014 sc->bge_ldata.bge_stats, 2015 sc->bge_cdata.bge_stats_map); 2016 2017 if (sc->bge_cdata.bge_stats_tag) 2018 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 2019 2020 /* Destroy the parent tag. */ 2021 if (sc->bge_cdata.bge_parent_tag) 2022 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 2023 } 2024 2025 static int 2026 bge_dma_alloc(device_t dev) 2027 { 2028 struct bge_dmamap_arg ctx; 2029 struct bge_softc *sc; 2030 int i, error; 2031 2032 sc = device_get_softc(dev); 2033 2034 /* 2035 * Allocate the parent bus DMA tag appropriate for PCI. 2036 */ 2037 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2038 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2039 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2040 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); 2041 2042 if (error != 0) { 2043 device_printf(sc->bge_dev, 2044 "could not allocate parent dma tag\n"); 2045 return (ENOMEM); 2046 } 2047 2048 /* 2049 * Create tag for mbufs. 2050 */ 2051 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 2052 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2053 NULL, MCLBYTES * BGE_NSEG_NEW, BGE_NSEG_NEW, MCLBYTES, 2054 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->bge_cdata.bge_mtag); 2055 2056 if (error) { 2057 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2058 return (ENOMEM); 2059 } 2060 2061 /* Create DMA maps for RX buffers. */ 2062 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2063 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, 2064 &sc->bge_cdata.bge_rx_std_dmamap[i]); 2065 if (error) { 2066 device_printf(sc->bge_dev, 2067 "can't create DMA map for RX\n"); 2068 return (ENOMEM); 2069 } 2070 } 2071 2072 /* Create DMA maps for TX buffers. */ 2073 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2074 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, 2075 &sc->bge_cdata.bge_tx_dmamap[i]); 2076 if (error) { 2077 device_printf(sc->bge_dev, 2078 "can't create DMA map for RX\n"); 2079 return (ENOMEM); 2080 } 2081 } 2082 2083 /* Create tag for standard RX ring. */ 2084 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2085 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2086 NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0, 2087 NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag); 2088 2089 if (error) { 2090 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2091 return (ENOMEM); 2092 } 2093 2094 /* Allocate DMA'able memory for standard RX ring. */ 2095 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag, 2096 (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT, 2097 &sc->bge_cdata.bge_rx_std_ring_map); 2098 if (error) 2099 return (ENOMEM); 2100 2101 bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 2102 2103 /* Load the address of the standard RX ring. */ 2104 ctx.bge_maxsegs = 1; 2105 ctx.sc = sc; 2106 2107 error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag, 2108 sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring, 2109 BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2110 2111 if (error) 2112 return (ENOMEM); 2113 2114 sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr; 2115 2116 /* Create tags for jumbo mbufs. */ 2117 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2118 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2119 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2120 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 2121 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 2122 if (error) { 2123 device_printf(sc->bge_dev, 2124 "could not allocate jumbo dma tag\n"); 2125 return (ENOMEM); 2126 } 2127 2128 /* Create tag for jumbo RX ring. */ 2129 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2130 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2131 NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0, 2132 NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag); 2133 2134 if (error) { 2135 device_printf(sc->bge_dev, 2136 "could not allocate jumbo ring dma tag\n"); 2137 return (ENOMEM); 2138 } 2139 2140 /* Allocate DMA'able memory for jumbo RX ring. */ 2141 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2142 (void **)&sc->bge_ldata.bge_rx_jumbo_ring, 2143 BUS_DMA_NOWAIT | BUS_DMA_ZERO, 2144 &sc->bge_cdata.bge_rx_jumbo_ring_map); 2145 if (error) 2146 return (ENOMEM); 2147 2148 /* Load the address of the jumbo RX ring. */ 2149 ctx.bge_maxsegs = 1; 2150 ctx.sc = sc; 2151 2152 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2153 sc->bge_cdata.bge_rx_jumbo_ring_map, 2154 sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ, 2155 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2156 2157 if (error) 2158 return (ENOMEM); 2159 2160 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr; 2161 2162 /* Create DMA maps for jumbo RX buffers. */ 2163 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2164 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2165 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2166 if (error) { 2167 device_printf(sc->bge_dev, 2168 "can't create DMA map for jumbo RX\n"); 2169 return (ENOMEM); 2170 } 2171 } 2172 2173 } 2174 2175 /* Create tag for RX return ring. */ 2176 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2177 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2178 NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0, 2179 NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag); 2180 2181 if (error) { 2182 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2183 return (ENOMEM); 2184 } 2185 2186 /* Allocate DMA'able memory for RX return ring. */ 2187 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag, 2188 (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT, 2189 &sc->bge_cdata.bge_rx_return_ring_map); 2190 if (error) 2191 return (ENOMEM); 2192 2193 bzero((char *)sc->bge_ldata.bge_rx_return_ring, 2194 BGE_RX_RTN_RING_SZ(sc)); 2195 2196 /* Load the address of the RX return ring. */ 2197 ctx.bge_maxsegs = 1; 2198 ctx.sc = sc; 2199 2200 error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag, 2201 sc->bge_cdata.bge_rx_return_ring_map, 2202 sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc), 2203 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2204 2205 if (error) 2206 return (ENOMEM); 2207 2208 sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr; 2209 2210 /* Create tag for TX ring. */ 2211 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2212 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2213 NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL, 2214 &sc->bge_cdata.bge_tx_ring_tag); 2215 2216 if (error) { 2217 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2218 return (ENOMEM); 2219 } 2220 2221 /* Allocate DMA'able memory for TX ring. */ 2222 error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag, 2223 (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT, 2224 &sc->bge_cdata.bge_tx_ring_map); 2225 if (error) 2226 return (ENOMEM); 2227 2228 bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 2229 2230 /* Load the address of the TX ring. */ 2231 ctx.bge_maxsegs = 1; 2232 ctx.sc = sc; 2233 2234 error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag, 2235 sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring, 2236 BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2237 2238 if (error) 2239 return (ENOMEM); 2240 2241 sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr; 2242 2243 /* Create tag for status block. */ 2244 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2245 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2246 NULL, BGE_STATUS_BLK_SZ, 1, BGE_STATUS_BLK_SZ, 0, 2247 NULL, NULL, &sc->bge_cdata.bge_status_tag); 2248 2249 if (error) { 2250 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2251 return (ENOMEM); 2252 } 2253 2254 /* Allocate DMA'able memory for status block. */ 2255 error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag, 2256 (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT, 2257 &sc->bge_cdata.bge_status_map); 2258 if (error) 2259 return (ENOMEM); 2260 2261 bzero((char *)sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 2262 2263 /* Load the address of the status block. */ 2264 ctx.sc = sc; 2265 ctx.bge_maxsegs = 1; 2266 2267 error = bus_dmamap_load(sc->bge_cdata.bge_status_tag, 2268 sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block, 2269 BGE_STATUS_BLK_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2270 2271 if (error) 2272 return (ENOMEM); 2273 2274 sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr; 2275 2276 /* Create tag for statistics block. */ 2277 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2278 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2279 NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL, 2280 &sc->bge_cdata.bge_stats_tag); 2281 2282 if (error) { 2283 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2284 return (ENOMEM); 2285 } 2286 2287 /* Allocate DMA'able memory for statistics block. */ 2288 error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag, 2289 (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT, 2290 &sc->bge_cdata.bge_stats_map); 2291 if (error) 2292 return (ENOMEM); 2293 2294 bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ); 2295 2296 /* Load the address of the statstics block. */ 2297 ctx.sc = sc; 2298 ctx.bge_maxsegs = 1; 2299 2300 error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag, 2301 sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats, 2302 BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2303 2304 if (error) 2305 return (ENOMEM); 2306 2307 sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr; 2308 2309 return (0); 2310 } 2311 2312 #if __FreeBSD_version > 602105 2313 /* 2314 * Return true if this device has more than one port. 2315 */ 2316 static int 2317 bge_has_multiple_ports(struct bge_softc *sc) 2318 { 2319 device_t dev = sc->bge_dev; 2320 u_int b, d, f, fscan, s; 2321 2322 d = pci_get_domain(dev); 2323 b = pci_get_bus(dev); 2324 s = pci_get_slot(dev); 2325 f = pci_get_function(dev); 2326 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 2327 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL) 2328 return (1); 2329 return (0); 2330 } 2331 2332 /* 2333 * Return true if MSI can be used with this device. 2334 */ 2335 static int 2336 bge_can_use_msi(struct bge_softc *sc) 2337 { 2338 int can_use_msi = 0; 2339 2340 switch (sc->bge_asicrev) { 2341 case BGE_ASICREV_BCM5714_A0: 2342 case BGE_ASICREV_BCM5714: 2343 /* 2344 * Apparently, MSI doesn't work when these chips are 2345 * configured in single-port mode. 2346 */ 2347 if (bge_has_multiple_ports(sc)) 2348 can_use_msi = 1; 2349 break; 2350 case BGE_ASICREV_BCM5750: 2351 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 2352 sc->bge_chiprev != BGE_CHIPREV_5750_BX) 2353 can_use_msi = 1; 2354 break; 2355 default: 2356 if (BGE_IS_575X_PLUS(sc)) 2357 can_use_msi = 1; 2358 } 2359 return (can_use_msi); 2360 } 2361 #endif 2362 2363 static int 2364 bge_attach(device_t dev) 2365 { 2366 struct ifnet *ifp; 2367 struct bge_softc *sc; 2368 uint32_t hwcfg = 0, misccfg; 2369 u_char eaddr[ETHER_ADDR_LEN]; 2370 int error, reg, rid, trys; 2371 2372 sc = device_get_softc(dev); 2373 sc->bge_dev = dev; 2374 2375 /* 2376 * Map control/status registers. 2377 */ 2378 pci_enable_busmaster(dev); 2379 2380 rid = BGE_PCI_BAR0; 2381 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2382 RF_ACTIVE); 2383 2384 if (sc->bge_res == NULL) { 2385 device_printf (sc->bge_dev, "couldn't map memory\n"); 2386 error = ENXIO; 2387 goto fail; 2388 } 2389 2390 /* Save ASIC rev. */ 2391 sc->bge_chipid = 2392 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 2393 BGE_PCIMISCCTL_ASICREV; 2394 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2395 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2396 2397 /* 2398 * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the 2399 * 5705 A0 and A1 chips. 2400 */ 2401 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 && 2402 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 2403 sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2404 sc->bge_chipid != BGE_CHIPID_BCM5705_A1) 2405 sc->bge_flags |= BGE_FLAG_WIRESPEED; 2406 2407 if (bge_has_eaddr(sc)) 2408 sc->bge_flags |= BGE_FLAG_EADDR; 2409 2410 /* Save chipset family. */ 2411 switch (sc->bge_asicrev) { 2412 case BGE_ASICREV_BCM5700: 2413 case BGE_ASICREV_BCM5701: 2414 case BGE_ASICREV_BCM5703: 2415 case BGE_ASICREV_BCM5704: 2416 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 2417 break; 2418 case BGE_ASICREV_BCM5714_A0: 2419 case BGE_ASICREV_BCM5780: 2420 case BGE_ASICREV_BCM5714: 2421 sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */; 2422 /* FALLTHRU */ 2423 case BGE_ASICREV_BCM5750: 2424 case BGE_ASICREV_BCM5752: 2425 case BGE_ASICREV_BCM5755: 2426 case BGE_ASICREV_BCM5787: 2427 case BGE_ASICREV_BCM5906: 2428 sc->bge_flags |= BGE_FLAG_575X_PLUS; 2429 /* FALLTHRU */ 2430 case BGE_ASICREV_BCM5705: 2431 sc->bge_flags |= BGE_FLAG_5705_PLUS; 2432 break; 2433 } 2434 2435 /* Set various bug flags. */ 2436 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2437 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2438 sc->bge_flags |= BGE_FLAG_CRC_BUG; 2439 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 2440 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 2441 sc->bge_flags |= BGE_FLAG_ADC_BUG; 2442 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2443 sc->bge_flags |= BGE_FLAG_5704_A0_BUG; 2444 if (BGE_IS_5705_PLUS(sc) && 2445 !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) { 2446 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2447 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 2448 if (sc->bge_chipid != BGE_CHIPID_BCM5722_A0) 2449 sc->bge_flags |= BGE_FLAG_JITTER_BUG; 2450 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 2451 sc->bge_flags |= BGE_FLAG_BER_BUG; 2452 } 2453 2454 2455 /* 2456 * We could possibly check for BCOM_DEVICEID_BCM5788 in bge_probe() 2457 * but I do not know the DEVICEID for the 5788M. 2458 */ 2459 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID; 2460 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2461 misccfg == BGE_MISCCFG_BOARD_ID_5788M) 2462 sc->bge_flags |= BGE_FLAG_5788; 2463 2464 /* 2465 * Check if this is a PCI-X or PCI Express device. 2466 */ 2467 #if __FreeBSD_version > 602101 2468 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 2469 /* 2470 * Found a PCI Express capabilities register, this 2471 * must be a PCI Express device. 2472 */ 2473 if (reg != 0) 2474 sc->bge_flags |= BGE_FLAG_PCIE; 2475 #else 2476 if (BGE_IS_5705_PLUS(sc)) { 2477 reg = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4); 2478 if ((reg & 0xFF) == BGE_PCIE_CAPID) 2479 sc->bge_flags |= BGE_FLAG_PCIE; 2480 #endif 2481 } else { 2482 /* 2483 * Check if the device is in PCI-X Mode. 2484 * (This bit is not valid on PCI Express controllers.) 2485 */ 2486 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 2487 BGE_PCISTATE_PCI_BUSMODE) == 0) 2488 sc->bge_flags |= BGE_FLAG_PCIX; 2489 } 2490 2491 #if __FreeBSD_version > 602105 2492 { 2493 int msicount; 2494 2495 /* 2496 * Allocate the interrupt, using MSI if possible. These devices 2497 * support 8 MSI messages, but only the first one is used in 2498 * normal operation. 2499 */ 2500 if (bge_can_use_msi(sc)) { 2501 msicount = pci_msi_count(dev); 2502 if (msicount > 1) 2503 msicount = 1; 2504 } else 2505 msicount = 0; 2506 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) { 2507 rid = 1; 2508 sc->bge_flags |= BGE_FLAG_MSI; 2509 } else 2510 rid = 0; 2511 } 2512 #else 2513 rid = 0; 2514 #endif 2515 2516 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2517 RF_SHAREABLE | RF_ACTIVE); 2518 2519 if (sc->bge_irq == NULL) { 2520 device_printf(sc->bge_dev, "couldn't map interrupt\n"); 2521 error = ENXIO; 2522 goto fail; 2523 } 2524 2525 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 2526 2527 /* Try to reset the chip. */ 2528 if (bge_reset(sc)) { 2529 device_printf(sc->bge_dev, "chip reset failed\n"); 2530 error = ENXIO; 2531 goto fail; 2532 } 2533 2534 sc->bge_asf_mode = 0; 2535 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) 2536 == BGE_MAGIC_NUMBER)) { 2537 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG) 2538 & BGE_HWCFG_ASF) { 2539 sc->bge_asf_mode |= ASF_ENABLE; 2540 sc->bge_asf_mode |= ASF_STACKUP; 2541 if (sc->bge_asicrev == BGE_ASICREV_BCM5750) { 2542 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 2543 } 2544 } 2545 } 2546 2547 /* Try to reset the chip again the nice way. */ 2548 bge_stop_fw(sc); 2549 bge_sig_pre_reset(sc, BGE_RESET_STOP); 2550 if (bge_reset(sc)) { 2551 device_printf(sc->bge_dev, "chip reset failed\n"); 2552 error = ENXIO; 2553 goto fail; 2554 } 2555 2556 bge_sig_legacy(sc, BGE_RESET_STOP); 2557 bge_sig_post_reset(sc, BGE_RESET_STOP); 2558 2559 if (bge_chipinit(sc)) { 2560 device_printf(sc->bge_dev, "chip initialization failed\n"); 2561 error = ENXIO; 2562 goto fail; 2563 } 2564 2565 error = bge_get_eaddr(sc, eaddr); 2566 if (error) { 2567 device_printf(sc->bge_dev, 2568 "failed to read station address\n"); 2569 error = ENXIO; 2570 goto fail; 2571 } 2572 2573 /* 5705 limits RX return ring to 512 entries. */ 2574 if (BGE_IS_5705_PLUS(sc)) 2575 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2576 else 2577 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2578 2579 if (bge_dma_alloc(dev)) { 2580 device_printf(sc->bge_dev, 2581 "failed to allocate DMA resources\n"); 2582 error = ENXIO; 2583 goto fail; 2584 } 2585 2586 /* Set default tuneable values. */ 2587 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2588 sc->bge_rx_coal_ticks = 150; 2589 sc->bge_tx_coal_ticks = 150; 2590 sc->bge_rx_max_coal_bds = 10; 2591 sc->bge_tx_max_coal_bds = 10; 2592 2593 /* Set up ifnet structure */ 2594 ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 2595 if (ifp == NULL) { 2596 device_printf(sc->bge_dev, "failed to if_alloc()\n"); 2597 error = ENXIO; 2598 goto fail; 2599 } 2600 ifp->if_softc = sc; 2601 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2602 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2603 ifp->if_ioctl = bge_ioctl; 2604 ifp->if_start = bge_start; 2605 ifp->if_init = bge_init; 2606 ifp->if_mtu = ETHERMTU; 2607 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1; 2608 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 2609 IFQ_SET_READY(&ifp->if_snd); 2610 ifp->if_hwassist = BGE_CSUM_FEATURES; 2611 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 2612 IFCAP_VLAN_MTU; 2613 #ifdef IFCAP_VLAN_HWCSUM 2614 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 2615 #endif 2616 ifp->if_capenable = ifp->if_capabilities; 2617 #ifdef DEVICE_POLLING 2618 ifp->if_capabilities |= IFCAP_POLLING; 2619 #endif 2620 2621 /* 2622 * 5700 B0 chips do not support checksumming correctly due 2623 * to hardware bugs. 2624 */ 2625 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 2626 ifp->if_capabilities &= ~IFCAP_HWCSUM; 2627 ifp->if_capenable &= IFCAP_HWCSUM; 2628 ifp->if_hwassist = 0; 2629 } 2630 2631 /* 2632 * Figure out what sort of media we have by checking the 2633 * hardware config word in the first 32k of NIC internal memory, 2634 * or fall back to examining the EEPROM if necessary. 2635 * Note: on some BCM5700 cards, this value appears to be unset. 2636 * If that's the case, we have to rely on identifying the NIC 2637 * by its PCI subsystem ID, as we do below for the SysKonnect 2638 * SK-9D41. 2639 */ 2640 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 2641 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2642 else if ((sc->bge_flags & BGE_FLAG_EADDR) && 2643 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 2644 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 2645 sizeof(hwcfg))) { 2646 device_printf(sc->bge_dev, "failed to read EEPROM\n"); 2647 error = ENXIO; 2648 goto fail; 2649 } 2650 hwcfg = ntohl(hwcfg); 2651 } 2652 2653 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2654 sc->bge_flags |= BGE_FLAG_TBI; 2655 2656 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2657 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 2658 sc->bge_flags |= BGE_FLAG_TBI; 2659 2660 if (sc->bge_flags & BGE_FLAG_TBI) { 2661 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2662 bge_ifmedia_sts); 2663 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 2664 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 2665 0, NULL); 2666 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 2667 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 2668 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2669 } else { 2670 /* 2671 * Do transceiver setup and tell the firmware the 2672 * driver is down so we can try to get access the 2673 * probe if ASF is running. Retry a couple of times 2674 * if we get a conflict with the ASF firmware accessing 2675 * the PHY. 2676 */ 2677 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2678 again: 2679 bge_asf_driver_up(sc); 2680 2681 trys = 0; 2682 if (mii_phy_probe(dev, &sc->bge_miibus, 2683 bge_ifmedia_upd, bge_ifmedia_sts)) { 2684 if (trys++ < 4) { 2685 device_printf(sc->bge_dev, "Try again\n"); 2686 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR, 2687 BMCR_RESET); 2688 goto again; 2689 } 2690 2691 device_printf(sc->bge_dev, "MII without any PHY!\n"); 2692 error = ENXIO; 2693 goto fail; 2694 } 2695 2696 /* 2697 * Now tell the firmware we are going up after probing the PHY 2698 */ 2699 if (sc->bge_asf_mode & ASF_STACKUP) 2700 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2701 } 2702 2703 /* 2704 * When using the BCM5701 in PCI-X mode, data corruption has 2705 * been observed in the first few bytes of some received packets. 2706 * Aligning the packet buffer in memory eliminates the corruption. 2707 * Unfortunately, this misaligns the packet payloads. On platforms 2708 * which do not support unaligned accesses, we will realign the 2709 * payloads by copying the received packets. 2710 */ 2711 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 2712 sc->bge_flags & BGE_FLAG_PCIX) 2713 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 2714 2715 /* 2716 * Call MI attach routine. 2717 */ 2718 ether_ifattach(ifp, eaddr); 2719 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 2720 2721 /* 2722 * Hookup IRQ last. 2723 */ 2724 #if __FreeBSD_version > 700030 2725 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, 2726 NULL, bge_intr, sc, &sc->bge_intrhand); 2727 #else 2728 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, 2729 bge_intr, sc, &sc->bge_intrhand); 2730 #endif 2731 2732 if (error) { 2733 bge_detach(dev); 2734 device_printf(sc->bge_dev, "couldn't set up irq\n"); 2735 } 2736 2737 bge_add_sysctls(sc); 2738 2739 return (0); 2740 2741 fail: 2742 bge_release_resources(sc); 2743 2744 return (error); 2745 } 2746 2747 static int 2748 bge_detach(device_t dev) 2749 { 2750 struct bge_softc *sc; 2751 struct ifnet *ifp; 2752 2753 sc = device_get_softc(dev); 2754 ifp = sc->bge_ifp; 2755 2756 #ifdef DEVICE_POLLING 2757 if (ifp->if_capenable & IFCAP_POLLING) 2758 ether_poll_deregister(ifp); 2759 #endif 2760 2761 BGE_LOCK(sc); 2762 bge_stop(sc); 2763 bge_reset(sc); 2764 BGE_UNLOCK(sc); 2765 2766 callout_drain(&sc->bge_stat_ch); 2767 2768 ether_ifdetach(ifp); 2769 2770 if (sc->bge_flags & BGE_FLAG_TBI) { 2771 ifmedia_removeall(&sc->bge_ifmedia); 2772 } else { 2773 bus_generic_detach(dev); 2774 device_delete_child(dev, sc->bge_miibus); 2775 } 2776 2777 bge_release_resources(sc); 2778 2779 return (0); 2780 } 2781 2782 static void 2783 bge_release_resources(struct bge_softc *sc) 2784 { 2785 device_t dev; 2786 2787 dev = sc->bge_dev; 2788 2789 if (sc->bge_intrhand != NULL) 2790 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 2791 2792 if (sc->bge_irq != NULL) 2793 bus_release_resource(dev, SYS_RES_IRQ, 2794 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq); 2795 2796 #if __FreeBSD_version > 602105 2797 if (sc->bge_flags & BGE_FLAG_MSI) 2798 pci_release_msi(dev); 2799 #endif 2800 2801 if (sc->bge_res != NULL) 2802 bus_release_resource(dev, SYS_RES_MEMORY, 2803 BGE_PCI_BAR0, sc->bge_res); 2804 2805 if (sc->bge_ifp != NULL) 2806 if_free(sc->bge_ifp); 2807 2808 bge_dma_free(sc); 2809 2810 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 2811 BGE_LOCK_DESTROY(sc); 2812 } 2813 2814 static int 2815 bge_reset(struct bge_softc *sc) 2816 { 2817 device_t dev; 2818 uint32_t cachesize, command, pcistate, reset, val; 2819 void (*write_op)(struct bge_softc *, int, int); 2820 int i; 2821 2822 dev = sc->bge_dev; 2823 2824 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 2825 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 2826 if (sc->bge_flags & BGE_FLAG_PCIE) 2827 write_op = bge_writemem_direct; 2828 else 2829 write_op = bge_writemem_ind; 2830 } else 2831 write_op = bge_writereg_ind; 2832 2833 /* Save some important PCI state. */ 2834 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 2835 command = pci_read_config(dev, BGE_PCI_CMD, 4); 2836 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 2837 2838 pci_write_config(dev, BGE_PCI_MISC_CTL, 2839 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 2840 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 2841 2842 /* Disable fastboot on controllers that support it. */ 2843 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 2844 sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2845 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 2846 if (bootverbose) 2847 device_printf(sc->bge_dev, "Disabling fastboot\n"); 2848 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 2849 } 2850 2851 /* 2852 * Write the magic number to SRAM at offset 0xB50. 2853 * When firmware finishes its initialization it will 2854 * write ~BGE_MAGIC_NUMBER to the same location. 2855 */ 2856 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2857 2858 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 2859 2860 /* XXX: Broadcom Linux driver. */ 2861 if (sc->bge_flags & BGE_FLAG_PCIE) { 2862 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 2863 CSR_WRITE_4(sc, 0x7E2C, 0x20); 2864 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2865 /* Prevent PCIE link training during global reset */ 2866 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 2867 reset |= 1 << 29; 2868 } 2869 } 2870 2871 /* 2872 * Set GPHY Power Down Override to leave GPHY 2873 * powered up in D0 uninitialized. 2874 */ 2875 if (BGE_IS_5705_PLUS(sc)) 2876 reset |= 0x04000000; 2877 2878 /* Issue global reset */ 2879 write_op(sc, BGE_MISC_CFG, reset); 2880 2881 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2882 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2883 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 2884 val | BGE_VCPU_STATUS_DRV_RESET); 2885 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 2886 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 2887 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 2888 } 2889 2890 DELAY(1000); 2891 2892 /* XXX: Broadcom Linux driver. */ 2893 if (sc->bge_flags & BGE_FLAG_PCIE) { 2894 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2895 DELAY(500000); /* wait for link training to complete */ 2896 val = pci_read_config(dev, 0xC4, 4); 2897 pci_write_config(dev, 0xC4, val | (1 << 15), 4); 2898 } 2899 /* 2900 * Set PCIE max payload size to 128 bytes and clear error 2901 * status. 2902 */ 2903 pci_write_config(dev, 0xD8, 0xF5000, 4); 2904 } 2905 2906 /* Reset some of the PCI state that got zapped by reset. */ 2907 pci_write_config(dev, BGE_PCI_MISC_CTL, 2908 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 2909 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 2910 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 2911 pci_write_config(dev, BGE_PCI_CMD, command, 4); 2912 write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2913 2914 /* Re-enable MSI, if neccesary, and enable the memory arbiter. */ 2915 if (BGE_IS_5714_FAMILY(sc)) { 2916 /* This chip disables MSI on reset. */ 2917 if (sc->bge_flags & BGE_FLAG_MSI) { 2918 val = pci_read_config(dev, BGE_PCI_MSI_CTL, 2); 2919 pci_write_config(dev, BGE_PCI_MSI_CTL, 2920 val | PCIM_MSICTRL_MSI_ENABLE, 2); 2921 val = CSR_READ_4(sc, BGE_MSI_MODE); 2922 CSR_WRITE_4(sc, BGE_MSI_MODE, 2923 val | BGE_MSIMODE_ENABLE); 2924 } 2925 val = CSR_READ_4(sc, BGE_MARB_MODE); 2926 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 2927 } else 2928 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2929 2930 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2931 for (i = 0; i < BGE_TIMEOUT; i++) { 2932 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2933 if (val & BGE_VCPU_STATUS_INIT_DONE) 2934 break; 2935 DELAY(100); 2936 } 2937 if (i == BGE_TIMEOUT) { 2938 device_printf(sc->bge_dev, "reset timed out\n"); 2939 return (1); 2940 } 2941 } else { 2942 /* 2943 * Poll until we see the 1's complement of the magic number. 2944 * This indicates that the firmware initialization is complete. 2945 * We expect this to fail if no chip containing the Ethernet 2946 * address is fitted though. 2947 */ 2948 for (i = 0; i < BGE_TIMEOUT; i++) { 2949 DELAY(10); 2950 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2951 if (val == ~BGE_MAGIC_NUMBER) 2952 break; 2953 } 2954 2955 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT) 2956 device_printf(sc->bge_dev, "firmware handshake timed out, " 2957 "found 0x%08x\n", val); 2958 } 2959 2960 /* 2961 * XXX Wait for the value of the PCISTATE register to 2962 * return to its original pre-reset state. This is a 2963 * fairly good indicator of reset completion. If we don't 2964 * wait for the reset to fully complete, trying to read 2965 * from the device's non-PCI registers may yield garbage 2966 * results. 2967 */ 2968 for (i = 0; i < BGE_TIMEOUT; i++) { 2969 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 2970 break; 2971 DELAY(10); 2972 } 2973 2974 if (sc->bge_flags & BGE_FLAG_PCIE) { 2975 reset = bge_readmem_ind(sc, 0x7C00); 2976 bge_writemem_ind(sc, 0x7C00, reset | (1 << 25)); 2977 } 2978 2979 /* Fix up byte swapping. */ 2980 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 2981 BGE_MODECTL_BYTESWAP_DATA); 2982 2983 /* Tell the ASF firmware we are up */ 2984 if (sc->bge_asf_mode & ASF_STACKUP) 2985 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2986 2987 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2988 2989 /* 2990 * The 5704 in TBI mode apparently needs some special 2991 * adjustment to insure the SERDES drive level is set 2992 * to 1.2V. 2993 */ 2994 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 2995 sc->bge_flags & BGE_FLAG_TBI) { 2996 val = CSR_READ_4(sc, BGE_SERDES_CFG); 2997 val = (val & ~0xFFF) | 0x880; 2998 CSR_WRITE_4(sc, BGE_SERDES_CFG, val); 2999 } 3000 3001 /* XXX: Broadcom Linux driver. */ 3002 if (sc->bge_flags & BGE_FLAG_PCIE && 3003 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3004 val = CSR_READ_4(sc, 0x7C00); 3005 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); 3006 } 3007 DELAY(10000); 3008 3009 return(0); 3010 } 3011 3012 /* 3013 * Frame reception handling. This is called if there's a frame 3014 * on the receive return list. 3015 * 3016 * Note: we have to be able to handle two possibilities here: 3017 * 1) the frame is from the jumbo receive ring 3018 * 2) the frame is from the standard receive ring 3019 */ 3020 3021 static void 3022 bge_rxeof(struct bge_softc *sc) 3023 { 3024 struct ifnet *ifp; 3025 int stdcnt = 0, jumbocnt = 0; 3026 3027 BGE_LOCK_ASSERT(sc); 3028 3029 /* Nothing to do. */ 3030 if (sc->bge_rx_saved_considx == 3031 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) 3032 return; 3033 3034 ifp = sc->bge_ifp; 3035 3036 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 3037 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 3038 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3039 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTREAD); 3040 if (BGE_IS_JUMBO_CAPABLE(sc)) 3041 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3042 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTREAD); 3043 3044 while(sc->bge_rx_saved_considx != 3045 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) { 3046 struct bge_rx_bd *cur_rx; 3047 uint32_t rxidx; 3048 struct mbuf *m = NULL; 3049 uint16_t vlan_tag = 0; 3050 int have_tag = 0; 3051 3052 #ifdef DEVICE_POLLING 3053 if (ifp->if_capenable & IFCAP_POLLING) { 3054 if (sc->rxcycles <= 0) 3055 break; 3056 sc->rxcycles--; 3057 } 3058 #endif 3059 3060 cur_rx = 3061 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx]; 3062 3063 rxidx = cur_rx->bge_idx; 3064 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 3065 3066 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING && 3067 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3068 have_tag = 1; 3069 vlan_tag = cur_rx->bge_vlan_tag; 3070 } 3071 3072 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3073 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3074 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 3075 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx], 3076 BUS_DMASYNC_POSTREAD); 3077 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 3078 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx]); 3079 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 3080 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 3081 jumbocnt++; 3082 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3083 ifp->if_ierrors++; 3084 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3085 continue; 3086 } 3087 if (bge_newbuf_jumbo(sc, 3088 sc->bge_jumbo, NULL) == ENOBUFS) { 3089 ifp->if_ierrors++; 3090 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3091 continue; 3092 } 3093 } else { 3094 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3095 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 3096 sc->bge_cdata.bge_rx_std_dmamap[rxidx], 3097 BUS_DMASYNC_POSTREAD); 3098 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 3099 sc->bge_cdata.bge_rx_std_dmamap[rxidx]); 3100 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 3101 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 3102 stdcnt++; 3103 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3104 ifp->if_ierrors++; 3105 bge_newbuf_std(sc, sc->bge_std, m); 3106 continue; 3107 } 3108 if (bge_newbuf_std(sc, sc->bge_std, 3109 NULL) == ENOBUFS) { 3110 ifp->if_ierrors++; 3111 bge_newbuf_std(sc, sc->bge_std, m); 3112 continue; 3113 } 3114 } 3115 3116 ifp->if_ipackets++; 3117 #ifndef __NO_STRICT_ALIGNMENT 3118 /* 3119 * For architectures with strict alignment we must make sure 3120 * the payload is aligned. 3121 */ 3122 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 3123 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 3124 cur_rx->bge_len); 3125 m->m_data += ETHER_ALIGN; 3126 } 3127 #endif 3128 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3129 m->m_pkthdr.rcvif = ifp; 3130 3131 if (ifp->if_capenable & IFCAP_RXCSUM) { 3132 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 3133 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3134 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 3135 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3136 } 3137 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3138 m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 3139 m->m_pkthdr.csum_data = 3140 cur_rx->bge_tcp_udp_csum; 3141 m->m_pkthdr.csum_flags |= 3142 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 3143 } 3144 } 3145 3146 /* 3147 * If we received a packet with a vlan tag, 3148 * attach that information to the packet. 3149 */ 3150 if (have_tag) { 3151 #if __FreeBSD_version > 700022 3152 m->m_pkthdr.ether_vtag = vlan_tag; 3153 m->m_flags |= M_VLANTAG; 3154 #else 3155 VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag); 3156 if (m == NULL) 3157 continue; 3158 #endif 3159 } 3160 3161 BGE_UNLOCK(sc); 3162 (*ifp->if_input)(ifp, m); 3163 BGE_LOCK(sc); 3164 } 3165 3166 if (stdcnt > 0) 3167 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3168 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 3169 3170 if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0) 3171 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3172 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 3173 3174 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3175 if (stdcnt) 3176 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3177 if (jumbocnt) 3178 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3179 #ifdef notyet 3180 /* 3181 * This register wraps very quickly under heavy packet drops. 3182 * If you need correct statistics, you can enable this check. 3183 */ 3184 if (BGE_IS_5705_PLUS(sc)) 3185 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3186 #endif 3187 } 3188 3189 static void 3190 bge_txeof(struct bge_softc *sc) 3191 { 3192 struct bge_tx_bd *cur_tx = NULL; 3193 struct ifnet *ifp; 3194 3195 BGE_LOCK_ASSERT(sc); 3196 3197 /* Nothing to do. */ 3198 if (sc->bge_tx_saved_considx == 3199 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) 3200 return; 3201 3202 ifp = sc->bge_ifp; 3203 3204 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 3205 sc->bge_cdata.bge_tx_ring_map, 3206 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3207 /* 3208 * Go through our tx ring and free mbufs for those 3209 * frames that have been sent. 3210 */ 3211 while (sc->bge_tx_saved_considx != 3212 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) { 3213 uint32_t idx = 0; 3214 3215 idx = sc->bge_tx_saved_considx; 3216 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 3217 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3218 ifp->if_opackets++; 3219 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 3220 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 3221 sc->bge_cdata.bge_tx_dmamap[idx], 3222 BUS_DMASYNC_POSTWRITE); 3223 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 3224 sc->bge_cdata.bge_tx_dmamap[idx]); 3225 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 3226 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3227 } 3228 sc->bge_txcnt--; 3229 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3230 } 3231 3232 if (cur_tx != NULL) 3233 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3234 if (sc->bge_txcnt == 0) 3235 sc->bge_timer = 0; 3236 } 3237 3238 #ifdef DEVICE_POLLING 3239 static void 3240 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3241 { 3242 struct bge_softc *sc = ifp->if_softc; 3243 uint32_t statusword; 3244 3245 BGE_LOCK(sc); 3246 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3247 BGE_UNLOCK(sc); 3248 return; 3249 } 3250 3251 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3252 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD); 3253 3254 statusword = atomic_readandclear_32( 3255 &sc->bge_ldata.bge_status_block->bge_status); 3256 3257 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3258 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD); 3259 3260 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 3261 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 3262 sc->bge_link_evt++; 3263 3264 if (cmd == POLL_AND_CHECK_STATUS) 3265 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3266 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3267 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 3268 bge_link_upd(sc); 3269 3270 sc->rxcycles = count; 3271 bge_rxeof(sc); 3272 bge_txeof(sc); 3273 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3274 bge_start_locked(ifp); 3275 3276 BGE_UNLOCK(sc); 3277 } 3278 #endif /* DEVICE_POLLING */ 3279 3280 static void 3281 bge_intr(void *xsc) 3282 { 3283 struct bge_softc *sc; 3284 struct ifnet *ifp; 3285 uint32_t statusword; 3286 3287 sc = xsc; 3288 3289 BGE_LOCK(sc); 3290 3291 ifp = sc->bge_ifp; 3292 3293 #ifdef DEVICE_POLLING 3294 if (ifp->if_capenable & IFCAP_POLLING) { 3295 BGE_UNLOCK(sc); 3296 return; 3297 } 3298 #endif 3299 3300 /* 3301 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 3302 * disable interrupts by writing nonzero like we used to, since with 3303 * our current organization this just gives complications and 3304 * pessimizations for re-enabling interrupts. We used to have races 3305 * instead of the necessary complications. Disabling interrupts 3306 * would just reduce the chance of a status update while we are 3307 * running (by switching to the interrupt-mode coalescence 3308 * parameters), but this chance is already very low so it is more 3309 * efficient to get another interrupt than prevent it. 3310 * 3311 * We do the ack first to ensure another interrupt if there is a 3312 * status update after the ack. We don't check for the status 3313 * changing later because it is more efficient to get another 3314 * interrupt than prevent it, not quite as above (not checking is 3315 * a smaller optimization than not toggling the interrupt enable, 3316 * since checking doesn't involve PCI accesses and toggling require 3317 * the status check). So toggling would probably be a pessimization 3318 * even with MSI. It would only be needed for using a task queue. 3319 */ 3320 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3321 3322 /* 3323 * Do the mandatory PCI flush as well as get the link status. 3324 */ 3325 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 3326 3327 /* Make sure the descriptor ring indexes are coherent. */ 3328 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3329 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD); 3330 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3331 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD); 3332 3333 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3334 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3335 statusword || sc->bge_link_evt) 3336 bge_link_upd(sc); 3337 3338 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3339 /* Check RX return ring producer/consumer. */ 3340 bge_rxeof(sc); 3341 3342 /* Check TX ring producer/consumer. */ 3343 bge_txeof(sc); 3344 } 3345 3346 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3347 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3348 bge_start_locked(ifp); 3349 3350 BGE_UNLOCK(sc); 3351 } 3352 3353 static void 3354 bge_asf_driver_up(struct bge_softc *sc) 3355 { 3356 if (sc->bge_asf_mode & ASF_STACKUP) { 3357 /* Send ASF heartbeat aprox. every 2s */ 3358 if (sc->bge_asf_count) 3359 sc->bge_asf_count --; 3360 else { 3361 sc->bge_asf_count = 5; 3362 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, 3363 BGE_FW_DRV_ALIVE); 3364 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4); 3365 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3); 3366 CSR_WRITE_4(sc, BGE_CPU_EVENT, 3367 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 3368 } 3369 } 3370 } 3371 3372 static void 3373 bge_tick(void *xsc) 3374 { 3375 struct bge_softc *sc = xsc; 3376 struct mii_data *mii = NULL; 3377 3378 BGE_LOCK_ASSERT(sc); 3379 3380 /* Synchronize with possible callout reset/stop. */ 3381 if (callout_pending(&sc->bge_stat_ch) || 3382 !callout_active(&sc->bge_stat_ch)) 3383 return; 3384 3385 if (BGE_IS_5705_PLUS(sc)) 3386 bge_stats_update_regs(sc); 3387 else 3388 bge_stats_update(sc); 3389 3390 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 3391 mii = device_get_softc(sc->bge_miibus); 3392 /* 3393 * Do not touch PHY if we have link up. This could break 3394 * IPMI/ASF mode or produce extra input errors 3395 * (extra errors was reported for bcm5701 & bcm5704). 3396 */ 3397 if (!sc->bge_link) 3398 mii_tick(mii); 3399 } else { 3400 /* 3401 * Since in TBI mode auto-polling can't be used we should poll 3402 * link status manually. Here we register pending link event 3403 * and trigger interrupt. 3404 */ 3405 #ifdef DEVICE_POLLING 3406 /* In polling mode we poll link state in bge_poll(). */ 3407 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING)) 3408 #endif 3409 { 3410 sc->bge_link_evt++; 3411 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 3412 sc->bge_flags & BGE_FLAG_5788) 3413 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3414 else 3415 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 3416 } 3417 } 3418 3419 bge_asf_driver_up(sc); 3420 bge_watchdog(sc); 3421 3422 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 3423 } 3424 3425 static void 3426 bge_stats_update_regs(struct bge_softc *sc) 3427 { 3428 struct ifnet *ifp; 3429 3430 ifp = sc->bge_ifp; 3431 3432 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 3433 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 3434 3435 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3436 } 3437 3438 static void 3439 bge_stats_update(struct bge_softc *sc) 3440 { 3441 struct ifnet *ifp; 3442 bus_size_t stats; 3443 uint32_t cnt; /* current register value */ 3444 3445 ifp = sc->bge_ifp; 3446 3447 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3448 3449 #define READ_STAT(sc, stats, stat) \ 3450 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3451 3452 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 3453 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions); 3454 sc->bge_tx_collisions = cnt; 3455 3456 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 3457 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards); 3458 sc->bge_rx_discards = cnt; 3459 3460 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 3461 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards); 3462 sc->bge_tx_discards = cnt; 3463 3464 #undef READ_STAT 3465 } 3466 3467 /* 3468 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3469 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3470 * but when such padded frames employ the bge IP/TCP checksum offload, 3471 * the hardware checksum assist gives incorrect results (possibly 3472 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3473 * If we pad such runts with zeros, the onboard checksum comes out correct. 3474 */ 3475 static __inline int 3476 bge_cksum_pad(struct mbuf *m) 3477 { 3478 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 3479 struct mbuf *last; 3480 3481 /* If there's only the packet-header and we can pad there, use it. */ 3482 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 3483 M_TRAILINGSPACE(m) >= padlen) { 3484 last = m; 3485 } else { 3486 /* 3487 * Walk packet chain to find last mbuf. We will either 3488 * pad there, or append a new mbuf and pad it. 3489 */ 3490 for (last = m; last->m_next != NULL; last = last->m_next); 3491 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 3492 /* Allocate new empty mbuf, pad it. Compact later. */ 3493 struct mbuf *n; 3494 3495 MGET(n, M_DONTWAIT, MT_DATA); 3496 if (n == NULL) 3497 return (ENOBUFS); 3498 n->m_len = 0; 3499 last->m_next = n; 3500 last = n; 3501 } 3502 } 3503 3504 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 3505 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 3506 last->m_len += padlen; 3507 m->m_pkthdr.len += padlen; 3508 3509 return (0); 3510 } 3511 3512 /* 3513 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3514 * pointers to descriptors. 3515 */ 3516 static int 3517 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 3518 { 3519 bus_dma_segment_t segs[BGE_NSEG_NEW]; 3520 bus_dmamap_t map; 3521 struct bge_tx_bd *d; 3522 struct mbuf *m = *m_head; 3523 uint32_t idx = *txidx; 3524 uint16_t csum_flags; 3525 int nsegs, i, error; 3526 3527 csum_flags = 0; 3528 if (m->m_pkthdr.csum_flags) { 3529 if (m->m_pkthdr.csum_flags & CSUM_IP) 3530 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3531 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 3532 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3533 if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 3534 (error = bge_cksum_pad(m)) != 0) { 3535 m_freem(m); 3536 *m_head = NULL; 3537 return (error); 3538 } 3539 } 3540 if (m->m_flags & M_LASTFRAG) 3541 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 3542 else if (m->m_flags & M_FRAG) 3543 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 3544 } 3545 3546 map = sc->bge_cdata.bge_tx_dmamap[idx]; 3547 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m, segs, 3548 &nsegs, BUS_DMA_NOWAIT); 3549 if (error == EFBIG) { 3550 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW); 3551 if (m == NULL) { 3552 m_freem(*m_head); 3553 *m_head = NULL; 3554 return (ENOBUFS); 3555 } 3556 *m_head = m; 3557 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m, 3558 segs, &nsegs, BUS_DMA_NOWAIT); 3559 if (error) { 3560 m_freem(m); 3561 *m_head = NULL; 3562 return (error); 3563 } 3564 } else if (error != 0) 3565 return (error); 3566 3567 /* 3568 * Sanity check: avoid coming within 16 descriptors 3569 * of the end of the ring. 3570 */ 3571 if (nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 3572 bus_dmamap_unload(sc->bge_cdata.bge_mtag, map); 3573 return (ENOBUFS); 3574 } 3575 3576 bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE); 3577 3578 for (i = 0; ; i++) { 3579 d = &sc->bge_ldata.bge_tx_ring[idx]; 3580 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 3581 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 3582 d->bge_len = segs[i].ds_len; 3583 d->bge_flags = csum_flags; 3584 if (i == nsegs - 1) 3585 break; 3586 BGE_INC(idx, BGE_TX_RING_CNT); 3587 } 3588 3589 /* Mark the last segment as end of packet... */ 3590 d->bge_flags |= BGE_TXBDFLAG_END; 3591 3592 /* ... and put VLAN tag into first segment. */ 3593 d = &sc->bge_ldata.bge_tx_ring[*txidx]; 3594 #if __FreeBSD_version > 700022 3595 if (m->m_flags & M_VLANTAG) { 3596 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3597 d->bge_vlan_tag = m->m_pkthdr.ether_vtag; 3598 } else 3599 d->bge_vlan_tag = 0; 3600 #else 3601 { 3602 struct m_tag *mtag; 3603 3604 if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) { 3605 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3606 d->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 3607 } else 3608 d->bge_vlan_tag = 0; 3609 } 3610 #endif 3611 3612 /* 3613 * Insure that the map for this transmission 3614 * is placed at the array index of the last descriptor 3615 * in this chain. 3616 */ 3617 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 3618 sc->bge_cdata.bge_tx_dmamap[idx] = map; 3619 sc->bge_cdata.bge_tx_chain[idx] = m; 3620 sc->bge_txcnt += nsegs; 3621 3622 BGE_INC(idx, BGE_TX_RING_CNT); 3623 *txidx = idx; 3624 3625 return (0); 3626 } 3627 3628 /* 3629 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3630 * to the mbuf data regions directly in the transmit descriptors. 3631 */ 3632 static void 3633 bge_start_locked(struct ifnet *ifp) 3634 { 3635 struct bge_softc *sc; 3636 struct mbuf *m_head = NULL; 3637 uint32_t prodidx; 3638 int count = 0; 3639 3640 sc = ifp->if_softc; 3641 3642 if (!sc->bge_link || IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3643 return; 3644 3645 prodidx = sc->bge_tx_prodidx; 3646 3647 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3648 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3649 if (m_head == NULL) 3650 break; 3651 3652 /* 3653 * XXX 3654 * The code inside the if() block is never reached since we 3655 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting 3656 * requests to checksum TCP/UDP in a fragmented packet. 3657 * 3658 * XXX 3659 * safety overkill. If this is a fragmented packet chain 3660 * with delayed TCP/UDP checksums, then only encapsulate 3661 * it if we have enough descriptors to handle the entire 3662 * chain at once. 3663 * (paranoia -- may not actually be needed) 3664 */ 3665 if (m_head->m_flags & M_FIRSTFRAG && 3666 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3667 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3668 m_head->m_pkthdr.csum_data + 16) { 3669 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3670 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3671 break; 3672 } 3673 } 3674 3675 /* 3676 * Pack the data into the transmit ring. If we 3677 * don't have room, set the OACTIVE flag and wait 3678 * for the NIC to drain the ring. 3679 */ 3680 if (bge_encap(sc, &m_head, &prodidx)) { 3681 if (m_head == NULL) 3682 break; 3683 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3684 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3685 break; 3686 } 3687 ++count; 3688 3689 /* 3690 * If there's a BPF listener, bounce a copy of this frame 3691 * to him. 3692 */ 3693 #ifdef ETHER_BPF_MTAP 3694 ETHER_BPF_MTAP(ifp, m_head); 3695 #else 3696 BPF_MTAP(ifp, m_head); 3697 #endif 3698 } 3699 3700 if (count == 0) 3701 /* No packets were dequeued. */ 3702 return; 3703 3704 /* Transmit. */ 3705 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3706 /* 5700 b2 errata */ 3707 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 3708 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3709 3710 sc->bge_tx_prodidx = prodidx; 3711 3712 /* 3713 * Set a timeout in case the chip goes out to lunch. 3714 */ 3715 sc->bge_timer = 5; 3716 } 3717 3718 /* 3719 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3720 * to the mbuf data regions directly in the transmit descriptors. 3721 */ 3722 static void 3723 bge_start(struct ifnet *ifp) 3724 { 3725 struct bge_softc *sc; 3726 3727 sc = ifp->if_softc; 3728 BGE_LOCK(sc); 3729 bge_start_locked(ifp); 3730 BGE_UNLOCK(sc); 3731 } 3732 3733 static void 3734 bge_init_locked(struct bge_softc *sc) 3735 { 3736 struct ifnet *ifp; 3737 uint16_t *m; 3738 3739 BGE_LOCK_ASSERT(sc); 3740 3741 ifp = sc->bge_ifp; 3742 3743 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3744 return; 3745 3746 /* Cancel pending I/O and flush buffers. */ 3747 bge_stop(sc); 3748 3749 bge_stop_fw(sc); 3750 bge_sig_pre_reset(sc, BGE_RESET_START); 3751 bge_reset(sc); 3752 bge_sig_legacy(sc, BGE_RESET_START); 3753 bge_sig_post_reset(sc, BGE_RESET_START); 3754 3755 bge_chipinit(sc); 3756 3757 /* 3758 * Init the various state machines, ring 3759 * control blocks and firmware. 3760 */ 3761 if (bge_blockinit(sc)) { 3762 device_printf(sc->bge_dev, "initialization failure\n"); 3763 return; 3764 } 3765 3766 ifp = sc->bge_ifp; 3767 3768 /* Specify MTU. */ 3769 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3770 ETHER_HDR_LEN + ETHER_CRC_LEN + 3771 (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0)); 3772 3773 /* Load our MAC address. */ 3774 m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 3775 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3776 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3777 3778 /* Program promiscuous mode. */ 3779 bge_setpromisc(sc); 3780 3781 /* Program multicast filter. */ 3782 bge_setmulti(sc); 3783 3784 /* Program VLAN tag stripping. */ 3785 bge_setvlan(sc); 3786 3787 /* Init RX ring. */ 3788 bge_init_rx_ring_std(sc); 3789 3790 /* 3791 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 3792 * memory to insure that the chip has in fact read the first 3793 * entry of the ring. 3794 */ 3795 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 3796 uint32_t v, i; 3797 for (i = 0; i < 10; i++) { 3798 DELAY(20); 3799 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 3800 if (v == (MCLBYTES - ETHER_ALIGN)) 3801 break; 3802 } 3803 if (i == 10) 3804 device_printf (sc->bge_dev, 3805 "5705 A0 chip failed to load RX ring\n"); 3806 } 3807 3808 /* Init jumbo RX ring. */ 3809 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3810 bge_init_rx_ring_jumbo(sc); 3811 3812 /* Init our RX return ring index. */ 3813 sc->bge_rx_saved_considx = 0; 3814 3815 /* Init our RX/TX stat counters. */ 3816 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 3817 3818 /* Init TX ring. */ 3819 bge_init_tx_ring(sc); 3820 3821 /* Turn on transmitter. */ 3822 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3823 3824 /* Turn on receiver. */ 3825 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3826 3827 /* Tell firmware we're alive. */ 3828 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3829 3830 #ifdef DEVICE_POLLING 3831 /* Disable interrupts if we are polling. */ 3832 if (ifp->if_capenable & IFCAP_POLLING) { 3833 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 3834 BGE_PCIMISCCTL_MASK_PCI_INTR); 3835 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3836 } else 3837 #endif 3838 3839 /* Enable host interrupts. */ 3840 { 3841 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3842 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3843 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3844 } 3845 3846 bge_ifmedia_upd_locked(ifp); 3847 3848 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3849 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3850 3851 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 3852 } 3853 3854 static void 3855 bge_init(void *xsc) 3856 { 3857 struct bge_softc *sc = xsc; 3858 3859 BGE_LOCK(sc); 3860 bge_init_locked(sc); 3861 BGE_UNLOCK(sc); 3862 } 3863 3864 /* 3865 * Set media options. 3866 */ 3867 static int 3868 bge_ifmedia_upd(struct ifnet *ifp) 3869 { 3870 struct bge_softc *sc = ifp->if_softc; 3871 int res; 3872 3873 BGE_LOCK(sc); 3874 res = bge_ifmedia_upd_locked(ifp); 3875 BGE_UNLOCK(sc); 3876 3877 return (res); 3878 } 3879 3880 static int 3881 bge_ifmedia_upd_locked(struct ifnet *ifp) 3882 { 3883 struct bge_softc *sc = ifp->if_softc; 3884 struct mii_data *mii; 3885 struct ifmedia *ifm; 3886 3887 BGE_LOCK_ASSERT(sc); 3888 3889 ifm = &sc->bge_ifmedia; 3890 3891 /* If this is a 1000baseX NIC, enable the TBI port. */ 3892 if (sc->bge_flags & BGE_FLAG_TBI) { 3893 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3894 return (EINVAL); 3895 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3896 case IFM_AUTO: 3897 /* 3898 * The BCM5704 ASIC appears to have a special 3899 * mechanism for programming the autoneg 3900 * advertisement registers in TBI mode. 3901 */ 3902 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 3903 uint32_t sgdig; 3904 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 3905 if (sgdig & BGE_SGDIGSTS_DONE) { 3906 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 3907 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 3908 sgdig |= BGE_SGDIGCFG_AUTO | 3909 BGE_SGDIGCFG_PAUSE_CAP | 3910 BGE_SGDIGCFG_ASYM_PAUSE; 3911 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 3912 sgdig | BGE_SGDIGCFG_SEND); 3913 DELAY(5); 3914 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 3915 } 3916 } 3917 break; 3918 case IFM_1000_SX: 3919 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3920 BGE_CLRBIT(sc, BGE_MAC_MODE, 3921 BGE_MACMODE_HALF_DUPLEX); 3922 } else { 3923 BGE_SETBIT(sc, BGE_MAC_MODE, 3924 BGE_MACMODE_HALF_DUPLEX); 3925 } 3926 break; 3927 default: 3928 return (EINVAL); 3929 } 3930 return (0); 3931 } 3932 3933 sc->bge_link_evt++; 3934 mii = device_get_softc(sc->bge_miibus); 3935 if (mii->mii_instance) { 3936 struct mii_softc *miisc; 3937 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 3938 miisc = LIST_NEXT(miisc, mii_list)) 3939 mii_phy_reset(miisc); 3940 } 3941 mii_mediachg(mii); 3942 3943 /* 3944 * Force an interrupt so that we will call bge_link_upd 3945 * if needed and clear any pending link state attention. 3946 * Without this we are not getting any further interrupts 3947 * for link state changes and thus will not UP the link and 3948 * not be able to send in bge_start_locked. The only 3949 * way to get things working was to receive a packet and 3950 * get an RX intr. 3951 * bge_tick should help for fiber cards and we might not 3952 * need to do this here if BGE_FLAG_TBI is set but as 3953 * we poll for fiber anyway it should not harm. 3954 */ 3955 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 3956 sc->bge_flags & BGE_FLAG_5788) 3957 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3958 else 3959 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 3960 3961 return (0); 3962 } 3963 3964 /* 3965 * Report current media status. 3966 */ 3967 static void 3968 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3969 { 3970 struct bge_softc *sc = ifp->if_softc; 3971 struct mii_data *mii; 3972 3973 BGE_LOCK(sc); 3974 3975 if (sc->bge_flags & BGE_FLAG_TBI) { 3976 ifmr->ifm_status = IFM_AVALID; 3977 ifmr->ifm_active = IFM_ETHER; 3978 if (CSR_READ_4(sc, BGE_MAC_STS) & 3979 BGE_MACSTAT_TBI_PCS_SYNCHED) 3980 ifmr->ifm_status |= IFM_ACTIVE; 3981 else { 3982 ifmr->ifm_active |= IFM_NONE; 3983 BGE_UNLOCK(sc); 3984 return; 3985 } 3986 ifmr->ifm_active |= IFM_1000_SX; 3987 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3988 ifmr->ifm_active |= IFM_HDX; 3989 else 3990 ifmr->ifm_active |= IFM_FDX; 3991 BGE_UNLOCK(sc); 3992 return; 3993 } 3994 3995 mii = device_get_softc(sc->bge_miibus); 3996 mii_pollstat(mii); 3997 ifmr->ifm_active = mii->mii_media_active; 3998 ifmr->ifm_status = mii->mii_media_status; 3999 4000 BGE_UNLOCK(sc); 4001 } 4002 4003 static int 4004 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 4005 { 4006 struct bge_softc *sc = ifp->if_softc; 4007 struct ifreq *ifr = (struct ifreq *) data; 4008 struct mii_data *mii; 4009 int flags, mask, error = 0; 4010 4011 switch (command) { 4012 case SIOCSIFMTU: 4013 if (ifr->ifr_mtu < ETHERMIN || 4014 ((BGE_IS_JUMBO_CAPABLE(sc)) && 4015 ifr->ifr_mtu > BGE_JUMBO_MTU) || 4016 ((!BGE_IS_JUMBO_CAPABLE(sc)) && 4017 ifr->ifr_mtu > ETHERMTU)) 4018 error = EINVAL; 4019 else if (ifp->if_mtu != ifr->ifr_mtu) { 4020 ifp->if_mtu = ifr->ifr_mtu; 4021 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4022 bge_init(sc); 4023 } 4024 break; 4025 case SIOCSIFFLAGS: 4026 BGE_LOCK(sc); 4027 if (ifp->if_flags & IFF_UP) { 4028 /* 4029 * If only the state of the PROMISC flag changed, 4030 * then just use the 'set promisc mode' command 4031 * instead of reinitializing the entire NIC. Doing 4032 * a full re-init means reloading the firmware and 4033 * waiting for it to start up, which may take a 4034 * second or two. Similarly for ALLMULTI. 4035 */ 4036 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4037 flags = ifp->if_flags ^ sc->bge_if_flags; 4038 if (flags & IFF_PROMISC) 4039 bge_setpromisc(sc); 4040 if (flags & IFF_ALLMULTI) 4041 bge_setmulti(sc); 4042 } else 4043 bge_init_locked(sc); 4044 } else { 4045 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4046 bge_stop(sc); 4047 } 4048 } 4049 sc->bge_if_flags = ifp->if_flags; 4050 BGE_UNLOCK(sc); 4051 error = 0; 4052 break; 4053 case SIOCADDMULTI: 4054 case SIOCDELMULTI: 4055 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4056 BGE_LOCK(sc); 4057 bge_setmulti(sc); 4058 BGE_UNLOCK(sc); 4059 error = 0; 4060 } 4061 break; 4062 case SIOCSIFMEDIA: 4063 case SIOCGIFMEDIA: 4064 if (sc->bge_flags & BGE_FLAG_TBI) { 4065 error = ifmedia_ioctl(ifp, ifr, 4066 &sc->bge_ifmedia, command); 4067 } else { 4068 mii = device_get_softc(sc->bge_miibus); 4069 error = ifmedia_ioctl(ifp, ifr, 4070 &mii->mii_media, command); 4071 } 4072 break; 4073 case SIOCSIFCAP: 4074 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 4075 #ifdef DEVICE_POLLING 4076 if (mask & IFCAP_POLLING) { 4077 if (ifr->ifr_reqcap & IFCAP_POLLING) { 4078 error = ether_poll_register(bge_poll, ifp); 4079 if (error) 4080 return (error); 4081 BGE_LOCK(sc); 4082 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 4083 BGE_PCIMISCCTL_MASK_PCI_INTR); 4084 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4085 ifp->if_capenable |= IFCAP_POLLING; 4086 BGE_UNLOCK(sc); 4087 } else { 4088 error = ether_poll_deregister(ifp); 4089 /* Enable interrupt even in error case */ 4090 BGE_LOCK(sc); 4091 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 4092 BGE_PCIMISCCTL_MASK_PCI_INTR); 4093 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4094 ifp->if_capenable &= ~IFCAP_POLLING; 4095 BGE_UNLOCK(sc); 4096 } 4097 } 4098 #endif 4099 if (mask & IFCAP_HWCSUM) { 4100 ifp->if_capenable ^= IFCAP_HWCSUM; 4101 if (IFCAP_HWCSUM & ifp->if_capenable && 4102 IFCAP_HWCSUM & ifp->if_capabilities) 4103 ifp->if_hwassist = BGE_CSUM_FEATURES; 4104 else 4105 ifp->if_hwassist = 0; 4106 #ifdef VLAN_CAPABILITIES 4107 VLAN_CAPABILITIES(ifp); 4108 #endif 4109 } 4110 4111 if (mask & IFCAP_VLAN_MTU) { 4112 ifp->if_capenable ^= IFCAP_VLAN_MTU; 4113 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4114 bge_init(sc); 4115 } 4116 4117 if (mask & IFCAP_VLAN_HWTAGGING) { 4118 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 4119 BGE_LOCK(sc); 4120 bge_setvlan(sc); 4121 BGE_UNLOCK(sc); 4122 #ifdef VLAN_CAPABILITIES 4123 VLAN_CAPABILITIES(ifp); 4124 #endif 4125 } 4126 4127 break; 4128 default: 4129 error = ether_ioctl(ifp, command, data); 4130 break; 4131 } 4132 4133 return (error); 4134 } 4135 4136 static void 4137 bge_watchdog(struct bge_softc *sc) 4138 { 4139 struct ifnet *ifp; 4140 4141 BGE_LOCK_ASSERT(sc); 4142 4143 if (sc->bge_timer == 0 || --sc->bge_timer) 4144 return; 4145 4146 ifp = sc->bge_ifp; 4147 4148 if_printf(ifp, "watchdog timeout -- resetting\n"); 4149 4150 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4151 bge_init_locked(sc); 4152 4153 ifp->if_oerrors++; 4154 } 4155 4156 /* 4157 * Stop the adapter and free any mbufs allocated to the 4158 * RX and TX lists. 4159 */ 4160 static void 4161 bge_stop(struct bge_softc *sc) 4162 { 4163 struct ifnet *ifp; 4164 struct ifmedia_entry *ifm; 4165 struct mii_data *mii = NULL; 4166 int mtmp, itmp; 4167 4168 BGE_LOCK_ASSERT(sc); 4169 4170 ifp = sc->bge_ifp; 4171 4172 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) 4173 mii = device_get_softc(sc->bge_miibus); 4174 4175 callout_stop(&sc->bge_stat_ch); 4176 4177 /* 4178 * Disable all of the receiver blocks. 4179 */ 4180 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4181 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4182 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4183 if (!(BGE_IS_5705_PLUS(sc))) 4184 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4185 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4186 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4187 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4188 4189 /* 4190 * Disable all of the transmit blocks. 4191 */ 4192 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4193 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4194 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4195 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4196 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4197 if (!(BGE_IS_5705_PLUS(sc))) 4198 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4199 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4200 4201 /* 4202 * Shut down all of the memory managers and related 4203 * state machines. 4204 */ 4205 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4206 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4207 if (!(BGE_IS_5705_PLUS(sc))) 4208 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4209 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4210 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4211 if (!(BGE_IS_5705_PLUS(sc))) { 4212 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4213 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4214 } 4215 4216 /* Disable host interrupts. */ 4217 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4218 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4219 4220 /* 4221 * Tell firmware we're shutting down. 4222 */ 4223 4224 bge_stop_fw(sc); 4225 bge_sig_pre_reset(sc, BGE_RESET_STOP); 4226 bge_reset(sc); 4227 bge_sig_legacy(sc, BGE_RESET_STOP); 4228 bge_sig_post_reset(sc, BGE_RESET_STOP); 4229 4230 /* 4231 * Keep the ASF firmware running if up. 4232 */ 4233 if (sc->bge_asf_mode & ASF_STACKUP) 4234 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4235 else 4236 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4237 4238 /* Free the RX lists. */ 4239 bge_free_rx_ring_std(sc); 4240 4241 /* Free jumbo RX list. */ 4242 if (BGE_IS_JUMBO_CAPABLE(sc)) 4243 bge_free_rx_ring_jumbo(sc); 4244 4245 /* Free TX buffers. */ 4246 bge_free_tx_ring(sc); 4247 4248 /* 4249 * Isolate/power down the PHY, but leave the media selection 4250 * unchanged so that things will be put back to normal when 4251 * we bring the interface back up. 4252 */ 4253 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 4254 itmp = ifp->if_flags; 4255 ifp->if_flags |= IFF_UP; 4256 /* 4257 * If we are called from bge_detach(), mii is already NULL. 4258 */ 4259 if (mii != NULL) { 4260 ifm = mii->mii_media.ifm_cur; 4261 mtmp = ifm->ifm_media; 4262 ifm->ifm_media = IFM_ETHER | IFM_NONE; 4263 mii_mediachg(mii); 4264 ifm->ifm_media = mtmp; 4265 } 4266 ifp->if_flags = itmp; 4267 } 4268 4269 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4270 4271 /* Clear MAC's link state (PHY may still have link UP). */ 4272 if (bootverbose && sc->bge_link) 4273 if_printf(sc->bge_ifp, "link DOWN\n"); 4274 sc->bge_link = 0; 4275 4276 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4277 } 4278 4279 /* 4280 * Stop all chip I/O so that the kernel's probe routines don't 4281 * get confused by errant DMAs when rebooting. 4282 */ 4283 static void 4284 bge_shutdown(device_t dev) 4285 { 4286 struct bge_softc *sc; 4287 4288 sc = device_get_softc(dev); 4289 4290 BGE_LOCK(sc); 4291 bge_stop(sc); 4292 bge_reset(sc); 4293 BGE_UNLOCK(sc); 4294 } 4295 4296 static int 4297 bge_suspend(device_t dev) 4298 { 4299 struct bge_softc *sc; 4300 4301 sc = device_get_softc(dev); 4302 BGE_LOCK(sc); 4303 bge_stop(sc); 4304 BGE_UNLOCK(sc); 4305 4306 return (0); 4307 } 4308 4309 static int 4310 bge_resume(device_t dev) 4311 { 4312 struct bge_softc *sc; 4313 struct ifnet *ifp; 4314 4315 sc = device_get_softc(dev); 4316 BGE_LOCK(sc); 4317 ifp = sc->bge_ifp; 4318 if (ifp->if_flags & IFF_UP) { 4319 bge_init_locked(sc); 4320 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4321 bge_start_locked(ifp); 4322 } 4323 BGE_UNLOCK(sc); 4324 4325 return (0); 4326 } 4327 4328 static void 4329 bge_link_upd(struct bge_softc *sc) 4330 { 4331 struct mii_data *mii; 4332 uint32_t link, status; 4333 4334 BGE_LOCK_ASSERT(sc); 4335 4336 /* Clear 'pending link event' flag. */ 4337 sc->bge_link_evt = 0; 4338 4339 /* 4340 * Process link state changes. 4341 * Grrr. The link status word in the status block does 4342 * not work correctly on the BCM5700 rev AX and BX chips, 4343 * according to all available information. Hence, we have 4344 * to enable MII interrupts in order to properly obtain 4345 * async link changes. Unfortunately, this also means that 4346 * we have to read the MAC status register to detect link 4347 * changes, thereby adding an additional register access to 4348 * the interrupt handler. 4349 * 4350 * XXX: perhaps link state detection procedure used for 4351 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 4352 */ 4353 4354 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4355 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 4356 status = CSR_READ_4(sc, BGE_MAC_STS); 4357 if (status & BGE_MACSTAT_MI_INTERRUPT) { 4358 mii = device_get_softc(sc->bge_miibus); 4359 mii_pollstat(mii); 4360 if (!sc->bge_link && 4361 mii->mii_media_status & IFM_ACTIVE && 4362 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4363 sc->bge_link++; 4364 if (bootverbose) 4365 if_printf(sc->bge_ifp, "link UP\n"); 4366 } else if (sc->bge_link && 4367 (!(mii->mii_media_status & IFM_ACTIVE) || 4368 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4369 sc->bge_link = 0; 4370 if (bootverbose) 4371 if_printf(sc->bge_ifp, "link DOWN\n"); 4372 } 4373 4374 /* Clear the interrupt. */ 4375 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 4376 BGE_EVTENB_MI_INTERRUPT); 4377 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4378 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 4379 BRGPHY_INTRS); 4380 } 4381 return; 4382 } 4383 4384 if (sc->bge_flags & BGE_FLAG_TBI) { 4385 status = CSR_READ_4(sc, BGE_MAC_STS); 4386 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4387 if (!sc->bge_link) { 4388 sc->bge_link++; 4389 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 4390 BGE_CLRBIT(sc, BGE_MAC_MODE, 4391 BGE_MACMODE_TBI_SEND_CFGS); 4392 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4393 if (bootverbose) 4394 if_printf(sc->bge_ifp, "link UP\n"); 4395 if_link_state_change(sc->bge_ifp, 4396 LINK_STATE_UP); 4397 } 4398 } else if (sc->bge_link) { 4399 sc->bge_link = 0; 4400 if (bootverbose) 4401 if_printf(sc->bge_ifp, "link DOWN\n"); 4402 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 4403 } 4404 } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) { 4405 /* 4406 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 4407 * in status word always set. Workaround this bug by reading 4408 * PHY link status directly. 4409 */ 4410 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 4411 4412 if (link != sc->bge_link || 4413 sc->bge_asicrev == BGE_ASICREV_BCM5700) { 4414 mii = device_get_softc(sc->bge_miibus); 4415 mii_pollstat(mii); 4416 if (!sc->bge_link && 4417 mii->mii_media_status & IFM_ACTIVE && 4418 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4419 sc->bge_link++; 4420 if (bootverbose) 4421 if_printf(sc->bge_ifp, "link UP\n"); 4422 } else if (sc->bge_link && 4423 (!(mii->mii_media_status & IFM_ACTIVE) || 4424 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4425 sc->bge_link = 0; 4426 if (bootverbose) 4427 if_printf(sc->bge_ifp, "link DOWN\n"); 4428 } 4429 } 4430 } else { 4431 /* 4432 * Discard link events for MII/GMII controllers 4433 * if MI auto-polling is disabled. 4434 */ 4435 } 4436 4437 /* Clear the attention. */ 4438 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4439 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4440 BGE_MACSTAT_LINK_CHANGED); 4441 } 4442 4443 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ 4444 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \ 4445 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \ 4446 desc) 4447 4448 static void 4449 bge_add_sysctls(struct bge_softc *sc) 4450 { 4451 struct sysctl_ctx_list *ctx; 4452 struct sysctl_oid_list *children, *schildren; 4453 struct sysctl_oid *tree; 4454 4455 ctx = device_get_sysctl_ctx(sc->bge_dev); 4456 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 4457 4458 #ifdef BGE_REGISTER_DEBUG 4459 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 4460 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", 4461 "Debug Information"); 4462 4463 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 4464 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", 4465 "Register Read"); 4466 4467 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 4468 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", 4469 "Memory Read"); 4470 4471 #endif 4472 4473 if (BGE_IS_5705_PLUS(sc)) 4474 return; 4475 4476 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 4477 NULL, "BGE Statistics"); 4478 schildren = children = SYSCTL_CHILDREN(tree); 4479 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", 4480 children, COSFramesDroppedDueToFilters, 4481 "FramesDroppedDueToFilters"); 4482 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", 4483 children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); 4484 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", 4485 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); 4486 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", 4487 children, nicNoMoreRxBDs, "NoMoreRxBDs"); 4488 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", 4489 children, ifInDiscards, "InputDiscards"); 4490 BGE_SYSCTL_STAT(sc, ctx, "Input Errors", 4491 children, ifInErrors, "InputErrors"); 4492 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", 4493 children, nicRecvThresholdHit, "RecvThresholdHit"); 4494 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", 4495 children, nicDmaReadQueueFull, "DmaReadQueueFull"); 4496 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", 4497 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); 4498 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", 4499 children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); 4500 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", 4501 children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); 4502 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", 4503 children, nicRingStatusUpdate, "RingStatusUpdate"); 4504 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", 4505 children, nicInterrupts, "Interrupts"); 4506 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", 4507 children, nicAvoidedInterrupts, "AvoidedInterrupts"); 4508 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", 4509 children, nicSendThresholdHit, "SendThresholdHit"); 4510 4511 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD, 4512 NULL, "BGE RX Statistics"); 4513 children = SYSCTL_CHILDREN(tree); 4514 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", 4515 children, rxstats.ifHCInOctets, "Octets"); 4516 BGE_SYSCTL_STAT(sc, ctx, "Fragments", 4517 children, rxstats.etherStatsFragments, "Fragments"); 4518 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", 4519 children, rxstats.ifHCInUcastPkts, "UcastPkts"); 4520 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", 4521 children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); 4522 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", 4523 children, rxstats.dot3StatsFCSErrors, "FCSErrors"); 4524 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", 4525 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); 4526 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", 4527 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); 4528 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", 4529 children, rxstats.xoffPauseFramesReceived, 4530 "xoffPauseFramesReceived"); 4531 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", 4532 children, rxstats.macControlFramesReceived, 4533 "ControlFramesReceived"); 4534 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", 4535 children, rxstats.xoffStateEntered, "xoffStateEntered"); 4536 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", 4537 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); 4538 BGE_SYSCTL_STAT(sc, ctx, "Jabbers", 4539 children, rxstats.etherStatsJabbers, "Jabbers"); 4540 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", 4541 children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); 4542 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", 4543 children, rxstats.inRangeLengthError, "inRangeLengthError"); 4544 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", 4545 children, rxstats.outRangeLengthError, "outRangeLengthError"); 4546 4547 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD, 4548 NULL, "BGE TX Statistics"); 4549 children = SYSCTL_CHILDREN(tree); 4550 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", 4551 children, txstats.ifHCOutOctets, "Octets"); 4552 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", 4553 children, txstats.etherStatsCollisions, "Collisions"); 4554 BGE_SYSCTL_STAT(sc, ctx, "XON Sent", 4555 children, txstats.outXonSent, "XonSent"); 4556 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", 4557 children, txstats.outXoffSent, "XoffSent"); 4558 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", 4559 children, txstats.flowControlDone, "flowControlDone"); 4560 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", 4561 children, txstats.dot3StatsInternalMacTransmitErrors, 4562 "InternalMacTransmitErrors"); 4563 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", 4564 children, txstats.dot3StatsSingleCollisionFrames, 4565 "SingleCollisionFrames"); 4566 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", 4567 children, txstats.dot3StatsMultipleCollisionFrames, 4568 "MultipleCollisionFrames"); 4569 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", 4570 children, txstats.dot3StatsDeferredTransmissions, 4571 "DeferredTransmissions"); 4572 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", 4573 children, txstats.dot3StatsExcessiveCollisions, 4574 "ExcessiveCollisions"); 4575 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", 4576 children, txstats.dot3StatsLateCollisions, 4577 "LateCollisions"); 4578 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", 4579 children, txstats.ifHCOutUcastPkts, "UcastPkts"); 4580 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", 4581 children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); 4582 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", 4583 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); 4584 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", 4585 children, txstats.dot3StatsCarrierSenseErrors, 4586 "CarrierSenseErrors"); 4587 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", 4588 children, txstats.ifOutDiscards, "Discards"); 4589 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", 4590 children, txstats.ifOutErrors, "Errors"); 4591 } 4592 4593 static int 4594 bge_sysctl_stats(SYSCTL_HANDLER_ARGS) 4595 { 4596 struct bge_softc *sc; 4597 uint32_t result; 4598 int offset; 4599 4600 sc = (struct bge_softc *)arg1; 4601 offset = arg2; 4602 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + 4603 offsetof(bge_hostaddr, bge_addr_lo)); 4604 return (sysctl_handle_int(oidp, &result, 0, req)); 4605 } 4606 4607 #ifdef BGE_REGISTER_DEBUG 4608 static int 4609 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4610 { 4611 struct bge_softc *sc; 4612 uint16_t *sbdata; 4613 int error; 4614 int result; 4615 int i, j; 4616 4617 result = -1; 4618 error = sysctl_handle_int(oidp, &result, 0, req); 4619 if (error || (req->newptr == NULL)) 4620 return (error); 4621 4622 if (result == 1) { 4623 sc = (struct bge_softc *)arg1; 4624 4625 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 4626 printf("Status Block:\n"); 4627 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) { 4628 printf("%06x:", i); 4629 for (j = 0; j < 8; j++) { 4630 printf(" %04x", sbdata[i]); 4631 i += 4; 4632 } 4633 printf("\n"); 4634 } 4635 4636 printf("Registers:\n"); 4637 for (i = 0x800; i < 0xA00; ) { 4638 printf("%06x:", i); 4639 for (j = 0; j < 8; j++) { 4640 printf(" %08x", CSR_READ_4(sc, i)); 4641 i += 4; 4642 } 4643 printf("\n"); 4644 } 4645 4646 printf("Hardware Flags:\n"); 4647 if (BGE_IS_575X_PLUS(sc)) 4648 printf(" - 575X Plus\n"); 4649 if (BGE_IS_5705_PLUS(sc)) 4650 printf(" - 5705 Plus\n"); 4651 if (BGE_IS_5714_FAMILY(sc)) 4652 printf(" - 5714 Family\n"); 4653 if (BGE_IS_5700_FAMILY(sc)) 4654 printf(" - 5700 Family\n"); 4655 if (sc->bge_flags & BGE_FLAG_JUMBO) 4656 printf(" - Supports Jumbo Frames\n"); 4657 if (sc->bge_flags & BGE_FLAG_PCIX) 4658 printf(" - PCI-X Bus\n"); 4659 if (sc->bge_flags & BGE_FLAG_PCIE) 4660 printf(" - PCI Express Bus\n"); 4661 if (sc->bge_flags & BGE_FLAG_NO_3LED) 4662 printf(" - No 3 LEDs\n"); 4663 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 4664 printf(" - RX Alignment Bug\n"); 4665 } 4666 4667 return (error); 4668 } 4669 4670 static int 4671 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 4672 { 4673 struct bge_softc *sc; 4674 int error; 4675 uint16_t result; 4676 uint32_t val; 4677 4678 result = -1; 4679 error = sysctl_handle_int(oidp, &result, 0, req); 4680 if (error || (req->newptr == NULL)) 4681 return (error); 4682 4683 if (result < 0x8000) { 4684 sc = (struct bge_softc *)arg1; 4685 val = CSR_READ_4(sc, result); 4686 printf("reg 0x%06X = 0x%08X\n", result, val); 4687 } 4688 4689 return (error); 4690 } 4691 4692 static int 4693 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 4694 { 4695 struct bge_softc *sc; 4696 int error; 4697 uint16_t result; 4698 uint32_t val; 4699 4700 result = -1; 4701 error = sysctl_handle_int(oidp, &result, 0, req); 4702 if (error || (req->newptr == NULL)) 4703 return (error); 4704 4705 if (result < 0x8000) { 4706 sc = (struct bge_softc *)arg1; 4707 val = bge_readmem_ind(sc, result); 4708 printf("mem 0x%06X = 0x%08X\n", result, val); 4709 } 4710 4711 return (error); 4712 } 4713 #endif 4714 4715 static int 4716 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 4717 { 4718 4719 if (sc->bge_flags & BGE_FLAG_EADDR) 4720 return (1); 4721 4722 #ifdef __sparc64__ 4723 OF_getetheraddr(sc->bge_dev, ether_addr); 4724 return (0); 4725 #endif 4726 return (1); 4727 } 4728 4729 static int 4730 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 4731 { 4732 uint32_t mac_addr; 4733 4734 mac_addr = bge_readmem_ind(sc, 0x0c14); 4735 if ((mac_addr >> 16) == 0x484b) { 4736 ether_addr[0] = (uint8_t)(mac_addr >> 8); 4737 ether_addr[1] = (uint8_t)mac_addr; 4738 mac_addr = bge_readmem_ind(sc, 0x0c18); 4739 ether_addr[2] = (uint8_t)(mac_addr >> 24); 4740 ether_addr[3] = (uint8_t)(mac_addr >> 16); 4741 ether_addr[4] = (uint8_t)(mac_addr >> 8); 4742 ether_addr[5] = (uint8_t)mac_addr; 4743 return (0); 4744 } 4745 return (1); 4746 } 4747 4748 static int 4749 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 4750 { 4751 int mac_offset = BGE_EE_MAC_OFFSET; 4752 4753 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 4754 mac_offset = BGE_EE_MAC_OFFSET_5906; 4755 4756 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 4757 ETHER_ADDR_LEN)); 4758 } 4759 4760 static int 4761 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 4762 { 4763 4764 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 4765 return (1); 4766 4767 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 4768 ETHER_ADDR_LEN)); 4769 } 4770 4771 static int 4772 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 4773 { 4774 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 4775 /* NOTE: Order is critical */ 4776 bge_get_eaddr_fw, 4777 bge_get_eaddr_mem, 4778 bge_get_eaddr_nvram, 4779 bge_get_eaddr_eeprom, 4780 NULL 4781 }; 4782 const bge_eaddr_fcn_t *func; 4783 4784 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 4785 if ((*func)(sc, eaddr) == 0) 4786 break; 4787 } 4788 return (*func == NULL ? ENXIO : 0); 4789 } 4790