xref: /freebsd/sys/dev/bge/if_bge.c (revision dad64f0e)
1 /*-
2  * SPDX-License-Identifier: BSD-4-Clause
3  *
4  * Copyright (c) 2001 Wind River Systems
5  * Copyright (c) 1997, 1998, 1999, 2001
6  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *	This product includes software developed by Bill Paul.
19  * 4. Neither the name of the author nor the names of any co-contributors
20  *    may be used to endorse or promote products derived from this software
21  *    without specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33  * THE POSSIBILITY OF SUCH DAMAGE.
34  */
35 
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
38 
39 /*
40  * Broadcom BCM57xx(x)/BCM590x NetXtreme and NetLink family Ethernet driver
41  *
42  * The Broadcom BCM5700 is based on technology originally developed by
43  * Alteon Networks as part of the Tigon I and Tigon II Gigabit Ethernet
44  * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has
45  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
46  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
47  * frames, highly configurable RX filtering, and 16 RX and TX queues
48  * (which, along with RX filter rules, can be used for QOS applications).
49  * Other features, such as TCP segmentation, may be available as part
50  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
51  * firmware images can be stored in hardware and need not be compiled
52  * into the driver.
53  *
54  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
55  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
56  *
57  * The BCM5701 is a single-chip solution incorporating both the BCM5700
58  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
59  * does not support external SSRAM.
60  *
61  * Broadcom also produces a variation of the BCM5700 under the "Altima"
62  * brand name, which is functionally similar but lacks PCI-X support.
63  *
64  * Without external SSRAM, you can only have at most 4 TX rings,
65  * and the use of the mini RX ring is disabled. This seems to imply
66  * that these features are simply not available on the BCM5701. As a
67  * result, this driver does not implement any support for the mini RX
68  * ring.
69  */
70 
71 #ifdef HAVE_KERNEL_OPTION_HEADERS
72 #include "opt_device_polling.h"
73 #endif
74 
75 #include <sys/param.h>
76 #include <sys/endian.h>
77 #include <sys/systm.h>
78 #include <sys/sockio.h>
79 #include <sys/mbuf.h>
80 #include <sys/malloc.h>
81 #include <sys/kernel.h>
82 #include <sys/module.h>
83 #include <sys/socket.h>
84 #include <sys/sysctl.h>
85 #include <sys/taskqueue.h>
86 
87 #include <net/debugnet.h>
88 #include <net/if.h>
89 #include <net/if_var.h>
90 #include <net/if_arp.h>
91 #include <net/ethernet.h>
92 #include <net/if_dl.h>
93 #include <net/if_media.h>
94 
95 #include <net/bpf.h>
96 
97 #include <net/if_types.h>
98 #include <net/if_vlan_var.h>
99 
100 #include <netinet/in_systm.h>
101 #include <netinet/in.h>
102 #include <netinet/ip.h>
103 #include <netinet/tcp.h>
104 
105 #include <machine/bus.h>
106 #include <machine/resource.h>
107 #include <sys/bus.h>
108 #include <sys/rman.h>
109 
110 #include <dev/mii/mii.h>
111 #include <dev/mii/miivar.h>
112 #include "miidevs.h"
113 #include <dev/mii/brgphyreg.h>
114 
115 #include <dev/pci/pcireg.h>
116 #include <dev/pci/pcivar.h>
117 
118 #include <dev/bge/if_bgereg.h>
119 
120 #define	BGE_CSUM_FEATURES	(CSUM_IP | CSUM_TCP)
121 #define	ETHER_MIN_NOPAD		(ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
122 
123 MODULE_DEPEND(bge, pci, 1, 1, 1);
124 MODULE_DEPEND(bge, ether, 1, 1, 1);
125 MODULE_DEPEND(bge, miibus, 1, 1, 1);
126 
127 /* "device miibus" required.  See GENERIC if you get errors here. */
128 #include "miibus_if.h"
129 
130 /*
131  * Various supported device vendors/types and their names. Note: the
132  * spec seems to indicate that the hardware still has Alteon's vendor
133  * ID burned into it, though it will always be overridden by the vendor
134  * ID in the EEPROM. Just to be safe, we cover all possibilities.
135  */
136 static const struct bge_type {
137 	uint16_t	bge_vid;
138 	uint16_t	bge_did;
139 } bge_devs[] = {
140 	{ ALTEON_VENDORID,	ALTEON_DEVICEID_BCM5700 },
141 	{ ALTEON_VENDORID,	ALTEON_DEVICEID_BCM5701 },
142 
143 	{ ALTIMA_VENDORID,	ALTIMA_DEVICE_AC1000 },
144 	{ ALTIMA_VENDORID,	ALTIMA_DEVICE_AC1002 },
145 	{ ALTIMA_VENDORID,	ALTIMA_DEVICE_AC9100 },
146 
147 	{ APPLE_VENDORID,	APPLE_DEVICE_BCM5701 },
148 
149 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5700 },
150 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5701 },
151 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5702 },
152 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5702_ALT },
153 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5702X },
154 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5703 },
155 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5703_ALT },
156 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5703X },
157 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5704C },
158 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5704S },
159 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5704S_ALT },
160 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5705 },
161 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5705F },
162 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5705K },
163 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5705M },
164 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5705M_ALT },
165 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5714C },
166 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5714S },
167 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5715 },
168 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5715S },
169 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5717 },
170 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5717C },
171 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5718 },
172 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5719 },
173 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5720 },
174 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5721 },
175 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5722 },
176 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5723 },
177 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5725 },
178 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5727 },
179 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5750 },
180 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5750M },
181 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5751 },
182 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5751F },
183 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5751M },
184 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5752 },
185 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5752M },
186 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5753 },
187 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5753F },
188 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5753M },
189 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5754 },
190 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5754M },
191 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5755 },
192 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5755M },
193 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5756 },
194 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5761 },
195 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5761E },
196 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5761S },
197 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5761SE },
198 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5762 },
199 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5764 },
200 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5780 },
201 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5780S },
202 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5781 },
203 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5782 },
204 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5784 },
205 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5785F },
206 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5785G },
207 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5786 },
208 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5787 },
209 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5787F },
210 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5787M },
211 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5788 },
212 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5789 },
213 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5901 },
214 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5901A2 },
215 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5903M },
216 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5906 },
217 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5906M },
218 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57760 },
219 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57761 },
220 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57762 },
221 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57764 },
222 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57765 },
223 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57766 },
224 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57767 },
225 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57780 },
226 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57781 },
227 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57782 },
228 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57785 },
229 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57786 },
230 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57787 },
231 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57788 },
232 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57790 },
233 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57791 },
234 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57795 },
235 
236 	{ SK_VENDORID,		SK_DEVICEID_ALTIMA },
237 
238 	{ TC_VENDORID,		TC_DEVICEID_3C996 },
239 
240 	{ FJTSU_VENDORID,	FJTSU_DEVICEID_PW008GE4 },
241 	{ FJTSU_VENDORID,	FJTSU_DEVICEID_PW008GE5 },
242 	{ 0, 0 }
243 };
244 
245 static const struct bge_vendor {
246 	uint16_t	v_id;
247 	const char	*v_name;
248 } bge_vendors[] = {
249 	{ ALTEON_VENDORID,	"Alteon" },
250 	{ ALTIMA_VENDORID,	"Altima" },
251 	{ APPLE_VENDORID,	"Apple" },
252 	{ BCOM_VENDORID,	"Broadcom" },
253 	{ SK_VENDORID,		"SysKonnect" },
254 	{ TC_VENDORID,		"3Com" },
255 	{ FJTSU_VENDORID,	"Fujitsu" },
256 	{ 0, NULL }
257 };
258 
259 static const struct bge_revision {
260 	uint32_t	br_chipid;
261 	const char	*br_name;
262 } bge_revisions[] = {
263 	{ BGE_CHIPID_BCM5700_A0,	"BCM5700 A0" },
264 	{ BGE_CHIPID_BCM5700_A1,	"BCM5700 A1" },
265 	{ BGE_CHIPID_BCM5700_B0,	"BCM5700 B0" },
266 	{ BGE_CHIPID_BCM5700_B1,	"BCM5700 B1" },
267 	{ BGE_CHIPID_BCM5700_B2,	"BCM5700 B2" },
268 	{ BGE_CHIPID_BCM5700_B3,	"BCM5700 B3" },
269 	{ BGE_CHIPID_BCM5700_ALTIMA,	"BCM5700 Altima" },
270 	{ BGE_CHIPID_BCM5700_C0,	"BCM5700 C0" },
271 	{ BGE_CHIPID_BCM5701_A0,	"BCM5701 A0" },
272 	{ BGE_CHIPID_BCM5701_B0,	"BCM5701 B0" },
273 	{ BGE_CHIPID_BCM5701_B2,	"BCM5701 B2" },
274 	{ BGE_CHIPID_BCM5701_B5,	"BCM5701 B5" },
275 	{ BGE_CHIPID_BCM5703_A0,	"BCM5703 A0" },
276 	{ BGE_CHIPID_BCM5703_A1,	"BCM5703 A1" },
277 	{ BGE_CHIPID_BCM5703_A2,	"BCM5703 A2" },
278 	{ BGE_CHIPID_BCM5703_A3,	"BCM5703 A3" },
279 	{ BGE_CHIPID_BCM5703_B0,	"BCM5703 B0" },
280 	{ BGE_CHIPID_BCM5704_A0,	"BCM5704 A0" },
281 	{ BGE_CHIPID_BCM5704_A1,	"BCM5704 A1" },
282 	{ BGE_CHIPID_BCM5704_A2,	"BCM5704 A2" },
283 	{ BGE_CHIPID_BCM5704_A3,	"BCM5704 A3" },
284 	{ BGE_CHIPID_BCM5704_B0,	"BCM5704 B0" },
285 	{ BGE_CHIPID_BCM5705_A0,	"BCM5705 A0" },
286 	{ BGE_CHIPID_BCM5705_A1,	"BCM5705 A1" },
287 	{ BGE_CHIPID_BCM5705_A2,	"BCM5705 A2" },
288 	{ BGE_CHIPID_BCM5705_A3,	"BCM5705 A3" },
289 	{ BGE_CHIPID_BCM5750_A0,	"BCM5750 A0" },
290 	{ BGE_CHIPID_BCM5750_A1,	"BCM5750 A1" },
291 	{ BGE_CHIPID_BCM5750_A3,	"BCM5750 A3" },
292 	{ BGE_CHIPID_BCM5750_B0,	"BCM5750 B0" },
293 	{ BGE_CHIPID_BCM5750_B1,	"BCM5750 B1" },
294 	{ BGE_CHIPID_BCM5750_C0,	"BCM5750 C0" },
295 	{ BGE_CHIPID_BCM5750_C1,	"BCM5750 C1" },
296 	{ BGE_CHIPID_BCM5750_C2,	"BCM5750 C2" },
297 	{ BGE_CHIPID_BCM5714_A0,	"BCM5714 A0" },
298 	{ BGE_CHIPID_BCM5752_A0,	"BCM5752 A0" },
299 	{ BGE_CHIPID_BCM5752_A1,	"BCM5752 A1" },
300 	{ BGE_CHIPID_BCM5752_A2,	"BCM5752 A2" },
301 	{ BGE_CHIPID_BCM5714_B0,	"BCM5714 B0" },
302 	{ BGE_CHIPID_BCM5714_B3,	"BCM5714 B3" },
303 	{ BGE_CHIPID_BCM5715_A0,	"BCM5715 A0" },
304 	{ BGE_CHIPID_BCM5715_A1,	"BCM5715 A1" },
305 	{ BGE_CHIPID_BCM5715_A3,	"BCM5715 A3" },
306 	{ BGE_CHIPID_BCM5717_A0,	"BCM5717 A0" },
307 	{ BGE_CHIPID_BCM5717_B0,	"BCM5717 B0" },
308 	{ BGE_CHIPID_BCM5717_C0,	"BCM5717 C0" },
309 	{ BGE_CHIPID_BCM5719_A0,	"BCM5719 A0" },
310 	{ BGE_CHIPID_BCM5720_A0,	"BCM5720 A0" },
311 	{ BGE_CHIPID_BCM5755_A0,	"BCM5755 A0" },
312 	{ BGE_CHIPID_BCM5755_A1,	"BCM5755 A1" },
313 	{ BGE_CHIPID_BCM5755_A2,	"BCM5755 A2" },
314 	{ BGE_CHIPID_BCM5722_A0,	"BCM5722 A0" },
315 	{ BGE_CHIPID_BCM5761_A0,	"BCM5761 A0" },
316 	{ BGE_CHIPID_BCM5761_A1,	"BCM5761 A1" },
317 	{ BGE_CHIPID_BCM5762_A0,	"BCM5762 A0" },
318 	{ BGE_CHIPID_BCM5784_A0,	"BCM5784 A0" },
319 	{ BGE_CHIPID_BCM5784_A1,	"BCM5784 A1" },
320 	/* 5754 and 5787 share the same ASIC ID */
321 	{ BGE_CHIPID_BCM5787_A0,	"BCM5754/5787 A0" },
322 	{ BGE_CHIPID_BCM5787_A1,	"BCM5754/5787 A1" },
323 	{ BGE_CHIPID_BCM5787_A2,	"BCM5754/5787 A2" },
324 	{ BGE_CHIPID_BCM5906_A1,	"BCM5906 A1" },
325 	{ BGE_CHIPID_BCM5906_A2,	"BCM5906 A2" },
326 	{ BGE_CHIPID_BCM57765_A0,	"BCM57765 A0" },
327 	{ BGE_CHIPID_BCM57765_B0,	"BCM57765 B0" },
328 	{ BGE_CHIPID_BCM57780_A0,	"BCM57780 A0" },
329 	{ BGE_CHIPID_BCM57780_A1,	"BCM57780 A1" },
330 	{ 0, NULL }
331 };
332 
333 /*
334  * Some defaults for major revisions, so that newer steppings
335  * that we don't know about have a shot at working.
336  */
337 static const struct bge_revision bge_majorrevs[] = {
338 	{ BGE_ASICREV_BCM5700,		"unknown BCM5700" },
339 	{ BGE_ASICREV_BCM5701,		"unknown BCM5701" },
340 	{ BGE_ASICREV_BCM5703,		"unknown BCM5703" },
341 	{ BGE_ASICREV_BCM5704,		"unknown BCM5704" },
342 	{ BGE_ASICREV_BCM5705,		"unknown BCM5705" },
343 	{ BGE_ASICREV_BCM5750,		"unknown BCM5750" },
344 	{ BGE_ASICREV_BCM5714_A0,	"unknown BCM5714" },
345 	{ BGE_ASICREV_BCM5752,		"unknown BCM5752" },
346 	{ BGE_ASICREV_BCM5780,		"unknown BCM5780" },
347 	{ BGE_ASICREV_BCM5714,		"unknown BCM5714" },
348 	{ BGE_ASICREV_BCM5755,		"unknown BCM5755" },
349 	{ BGE_ASICREV_BCM5761,		"unknown BCM5761" },
350 	{ BGE_ASICREV_BCM5784,		"unknown BCM5784" },
351 	{ BGE_ASICREV_BCM5785,		"unknown BCM5785" },
352 	/* 5754 and 5787 share the same ASIC ID */
353 	{ BGE_ASICREV_BCM5787,		"unknown BCM5754/5787" },
354 	{ BGE_ASICREV_BCM5906,		"unknown BCM5906" },
355 	{ BGE_ASICREV_BCM57765,		"unknown BCM57765" },
356 	{ BGE_ASICREV_BCM57766,		"unknown BCM57766" },
357 	{ BGE_ASICREV_BCM57780,		"unknown BCM57780" },
358 	{ BGE_ASICREV_BCM5717,		"unknown BCM5717" },
359 	{ BGE_ASICREV_BCM5719,		"unknown BCM5719" },
360 	{ BGE_ASICREV_BCM5720,		"unknown BCM5720" },
361 	{ BGE_ASICREV_BCM5762,		"unknown BCM5762" },
362 	{ 0, NULL }
363 };
364 
365 #define	BGE_IS_JUMBO_CAPABLE(sc)	((sc)->bge_flags & BGE_FLAG_JUMBO)
366 #define	BGE_IS_5700_FAMILY(sc)		((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
367 #define	BGE_IS_5705_PLUS(sc)		((sc)->bge_flags & BGE_FLAG_5705_PLUS)
368 #define	BGE_IS_5714_FAMILY(sc)		((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
369 #define	BGE_IS_575X_PLUS(sc)		((sc)->bge_flags & BGE_FLAG_575X_PLUS)
370 #define	BGE_IS_5755_PLUS(sc)		((sc)->bge_flags & BGE_FLAG_5755_PLUS)
371 #define	BGE_IS_5717_PLUS(sc)		((sc)->bge_flags & BGE_FLAG_5717_PLUS)
372 #define	BGE_IS_57765_PLUS(sc)		((sc)->bge_flags & BGE_FLAG_57765_PLUS)
373 
374 static uint32_t bge_chipid(device_t);
375 static const struct bge_vendor * bge_lookup_vendor(uint16_t);
376 static const struct bge_revision * bge_lookup_rev(uint32_t);
377 
378 typedef int	(*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
379 
380 static int bge_probe(device_t);
381 static int bge_attach(device_t);
382 static int bge_detach(device_t);
383 static int bge_suspend(device_t);
384 static int bge_resume(device_t);
385 static void bge_release_resources(struct bge_softc *);
386 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
387 static int bge_dma_alloc(struct bge_softc *);
388 static void bge_dma_free(struct bge_softc *);
389 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t,
390     bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
391 
392 static void bge_devinfo(struct bge_softc *);
393 static int bge_mbox_reorder(struct bge_softc *);
394 
395 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
396 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
397 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
398 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
399 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
400 
401 static void bge_txeof(struct bge_softc *, uint16_t);
402 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *);
403 static int bge_rxeof(struct bge_softc *, uint16_t, int);
404 
405 static void bge_asf_driver_up (struct bge_softc *);
406 static void bge_tick(void *);
407 static void bge_stats_clear_regs(struct bge_softc *);
408 static void bge_stats_update(struct bge_softc *);
409 static void bge_stats_update_regs(struct bge_softc *);
410 static struct mbuf *bge_check_short_dma(struct mbuf *);
411 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
412     uint16_t *, uint16_t *);
413 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
414 
415 static void bge_intr(void *);
416 static int bge_msi_intr(void *);
417 static void bge_intr_task(void *, int);
418 static void bge_start(if_t);
419 static void bge_start_locked(if_t);
420 static void bge_start_tx(struct bge_softc *, uint32_t);
421 static int bge_ioctl(if_t, u_long, caddr_t);
422 static void bge_init_locked(struct bge_softc *);
423 static void bge_init(void *);
424 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
425 static void bge_stop(struct bge_softc *);
426 static void bge_watchdog(struct bge_softc *);
427 static int bge_shutdown(device_t);
428 static int bge_ifmedia_upd_locked(if_t);
429 static int bge_ifmedia_upd(if_t);
430 static void bge_ifmedia_sts(if_t, struct ifmediareq *);
431 static uint64_t bge_get_counter(if_t, ift_counter);
432 
433 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
434 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
435 
436 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
437 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
438 
439 static void bge_setpromisc(struct bge_softc *);
440 static void bge_setmulti(struct bge_softc *);
441 static void bge_setvlan(struct bge_softc *);
442 
443 static __inline void bge_rxreuse_std(struct bge_softc *, int);
444 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int);
445 static int bge_newbuf_std(struct bge_softc *, int);
446 static int bge_newbuf_jumbo(struct bge_softc *, int);
447 static int bge_init_rx_ring_std(struct bge_softc *);
448 static void bge_free_rx_ring_std(struct bge_softc *);
449 static int bge_init_rx_ring_jumbo(struct bge_softc *);
450 static void bge_free_rx_ring_jumbo(struct bge_softc *);
451 static void bge_free_tx_ring(struct bge_softc *);
452 static int bge_init_tx_ring(struct bge_softc *);
453 
454 static int bge_chipinit(struct bge_softc *);
455 static int bge_blockinit(struct bge_softc *);
456 static uint32_t bge_dma_swap_options(struct bge_softc *);
457 
458 static int bge_has_eaddr(struct bge_softc *);
459 static uint32_t bge_readmem_ind(struct bge_softc *, int);
460 static void bge_writemem_ind(struct bge_softc *, int, int);
461 static void bge_writembx(struct bge_softc *, int, int);
462 #ifdef notdef
463 static uint32_t bge_readreg_ind(struct bge_softc *, int);
464 #endif
465 static void bge_writemem_direct(struct bge_softc *, int, int);
466 static void bge_writereg_ind(struct bge_softc *, int, int);
467 
468 static int bge_miibus_readreg(device_t, int, int);
469 static int bge_miibus_writereg(device_t, int, int, int);
470 static void bge_miibus_statchg(device_t);
471 #ifdef DEVICE_POLLING
472 static int bge_poll(if_t ifp, enum poll_cmd cmd, int count);
473 #endif
474 
475 #define	BGE_RESET_SHUTDOWN	0
476 #define	BGE_RESET_START		1
477 #define	BGE_RESET_SUSPEND	2
478 static void bge_sig_post_reset(struct bge_softc *, int);
479 static void bge_sig_legacy(struct bge_softc *, int);
480 static void bge_sig_pre_reset(struct bge_softc *, int);
481 static void bge_stop_fw(struct bge_softc *);
482 static int bge_reset(struct bge_softc *);
483 static void bge_link_upd(struct bge_softc *);
484 
485 static void bge_ape_lock_init(struct bge_softc *);
486 static void bge_ape_read_fw_ver(struct bge_softc *);
487 static int bge_ape_lock(struct bge_softc *, int);
488 static void bge_ape_unlock(struct bge_softc *, int);
489 static void bge_ape_send_event(struct bge_softc *, uint32_t);
490 static void bge_ape_driver_state_change(struct bge_softc *, int);
491 
492 /*
493  * The BGE_REGISTER_DEBUG option is only for low-level debugging.  It may
494  * leak information to untrusted users.  It is also known to cause alignment
495  * traps on certain architectures.
496  */
497 #ifdef BGE_REGISTER_DEBUG
498 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
499 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
500 static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS);
501 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
502 #endif
503 static void bge_add_sysctls(struct bge_softc *);
504 static void bge_add_sysctl_stats_regs(struct bge_softc *,
505     struct sysctl_ctx_list *, struct sysctl_oid_list *);
506 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *,
507     struct sysctl_oid_list *);
508 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
509 
510 DEBUGNET_DEFINE(bge);
511 
512 static device_method_t bge_methods[] = {
513 	/* Device interface */
514 	DEVMETHOD(device_probe,		bge_probe),
515 	DEVMETHOD(device_attach,	bge_attach),
516 	DEVMETHOD(device_detach,	bge_detach),
517 	DEVMETHOD(device_shutdown,	bge_shutdown),
518 	DEVMETHOD(device_suspend,	bge_suspend),
519 	DEVMETHOD(device_resume,	bge_resume),
520 
521 	/* MII interface */
522 	DEVMETHOD(miibus_readreg,	bge_miibus_readreg),
523 	DEVMETHOD(miibus_writereg,	bge_miibus_writereg),
524 	DEVMETHOD(miibus_statchg,	bge_miibus_statchg),
525 
526 	DEVMETHOD_END
527 };
528 
529 static driver_t bge_driver = {
530 	"bge",
531 	bge_methods,
532 	sizeof(struct bge_softc)
533 };
534 
535 DRIVER_MODULE(bge, pci, bge_driver, 0, 0);
536 MODULE_PNP_INFO("U16:vendor;U16:device", pci, bge, bge_devs,
537     nitems(bge_devs) - 1);
538 DRIVER_MODULE(miibus, bge, miibus_driver, 0, 0);
539 
540 static int bge_allow_asf = 1;
541 
542 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
543     "BGE driver parameters");
544 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RDTUN, &bge_allow_asf, 0,
545 	"Allow ASF mode if available");
546 
547 static int
548 bge_has_eaddr(struct bge_softc *sc)
549 {
550 	return (1);
551 }
552 
553 static uint32_t
554 bge_readmem_ind(struct bge_softc *sc, int off)
555 {
556 	device_t dev;
557 	uint32_t val;
558 
559 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
560 	    off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
561 		return (0);
562 
563 	dev = sc->bge_dev;
564 
565 	pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
566 	val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
567 	pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
568 	return (val);
569 }
570 
571 static void
572 bge_writemem_ind(struct bge_softc *sc, int off, int val)
573 {
574 	device_t dev;
575 
576 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
577 	    off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
578 		return;
579 
580 	dev = sc->bge_dev;
581 
582 	pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
583 	pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
584 	pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
585 }
586 
587 #ifdef notdef
588 static uint32_t
589 bge_readreg_ind(struct bge_softc *sc, int off)
590 {
591 	device_t dev;
592 
593 	dev = sc->bge_dev;
594 
595 	pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
596 	return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
597 }
598 #endif
599 
600 static void
601 bge_writereg_ind(struct bge_softc *sc, int off, int val)
602 {
603 	device_t dev;
604 
605 	dev = sc->bge_dev;
606 
607 	pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
608 	pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
609 }
610 
611 static void
612 bge_writemem_direct(struct bge_softc *sc, int off, int val)
613 {
614 	CSR_WRITE_4(sc, off, val);
615 }
616 
617 static void
618 bge_writembx(struct bge_softc *sc, int off, int val)
619 {
620 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
621 		off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
622 
623 	CSR_WRITE_4(sc, off, val);
624 	if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0)
625 		CSR_READ_4(sc, off);
626 }
627 
628 /*
629  * Clear all stale locks and select the lock for this driver instance.
630  */
631 static void
632 bge_ape_lock_init(struct bge_softc *sc)
633 {
634 	uint32_t bit, regbase;
635 	int i;
636 
637 	if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
638 		regbase = BGE_APE_LOCK_GRANT;
639 	else
640 		regbase = BGE_APE_PER_LOCK_GRANT;
641 
642 	/* Clear any stale locks. */
643 	for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) {
644 		switch (i) {
645 		case BGE_APE_LOCK_PHY0:
646 		case BGE_APE_LOCK_PHY1:
647 		case BGE_APE_LOCK_PHY2:
648 		case BGE_APE_LOCK_PHY3:
649 			bit = BGE_APE_LOCK_GRANT_DRIVER0;
650 			break;
651 		default:
652 			if (sc->bge_func_addr == 0)
653 				bit = BGE_APE_LOCK_GRANT_DRIVER0;
654 			else
655 				bit = (1 << sc->bge_func_addr);
656 		}
657 		APE_WRITE_4(sc, regbase + 4 * i, bit);
658 	}
659 
660 	/* Select the PHY lock based on the device's function number. */
661 	switch (sc->bge_func_addr) {
662 	case 0:
663 		sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0;
664 		break;
665 	case 1:
666 		sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1;
667 		break;
668 	case 2:
669 		sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2;
670 		break;
671 	case 3:
672 		sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3;
673 		break;
674 	default:
675 		device_printf(sc->bge_dev,
676 		    "PHY lock not supported on this function\n");
677 	}
678 }
679 
680 /*
681  * Check for APE firmware, set flags, and print version info.
682  */
683 static void
684 bge_ape_read_fw_ver(struct bge_softc *sc)
685 {
686 	const char *fwtype;
687 	uint32_t apedata, features;
688 
689 	/* Check for a valid APE signature in shared memory. */
690 	apedata = APE_READ_4(sc, BGE_APE_SEG_SIG);
691 	if (apedata != BGE_APE_SEG_SIG_MAGIC) {
692 		sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE;
693 		return;
694 	}
695 
696 	/* Check if APE firmware is running. */
697 	apedata = APE_READ_4(sc, BGE_APE_FW_STATUS);
698 	if ((apedata & BGE_APE_FW_STATUS_READY) == 0) {
699 		device_printf(sc->bge_dev, "APE signature found "
700 		    "but FW status not ready! 0x%08x\n", apedata);
701 		return;
702 	}
703 
704 	sc->bge_mfw_flags |= BGE_MFW_ON_APE;
705 
706 	/* Fetch the APE firwmare type and version. */
707 	apedata = APE_READ_4(sc, BGE_APE_FW_VERSION);
708 	features = APE_READ_4(sc, BGE_APE_FW_FEATURES);
709 	if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) {
710 		sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI;
711 		fwtype = "NCSI";
712 	} else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) {
713 		sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH;
714 		fwtype = "DASH";
715 	} else
716 		fwtype = "UNKN";
717 
718 	/* Print the APE firmware version. */
719 	device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n",
720 	    fwtype,
721 	    (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT,
722 	    (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT,
723 	    (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT,
724 	    (apedata & BGE_APE_FW_VERSION_BLDMSK));
725 }
726 
727 static int
728 bge_ape_lock(struct bge_softc *sc, int locknum)
729 {
730 	uint32_t bit, gnt, req, status;
731 	int i, off;
732 
733 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
734 		return (0);
735 
736 	/* Lock request/grant registers have different bases. */
737 	if (sc->bge_asicrev == BGE_ASICREV_BCM5761) {
738 		req = BGE_APE_LOCK_REQ;
739 		gnt = BGE_APE_LOCK_GRANT;
740 	} else {
741 		req = BGE_APE_PER_LOCK_REQ;
742 		gnt = BGE_APE_PER_LOCK_GRANT;
743 	}
744 
745 	off = 4 * locknum;
746 
747 	switch (locknum) {
748 	case BGE_APE_LOCK_GPIO:
749 		/* Lock required when using GPIO. */
750 		if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
751 			return (0);
752 		if (sc->bge_func_addr == 0)
753 			bit = BGE_APE_LOCK_REQ_DRIVER0;
754 		else
755 			bit = (1 << sc->bge_func_addr);
756 		break;
757 	case BGE_APE_LOCK_GRC:
758 		/* Lock required to reset the device. */
759 		if (sc->bge_func_addr == 0)
760 			bit = BGE_APE_LOCK_REQ_DRIVER0;
761 		else
762 			bit = (1 << sc->bge_func_addr);
763 		break;
764 	case BGE_APE_LOCK_MEM:
765 		/* Lock required when accessing certain APE memory. */
766 		if (sc->bge_func_addr == 0)
767 			bit = BGE_APE_LOCK_REQ_DRIVER0;
768 		else
769 			bit = (1 << sc->bge_func_addr);
770 		break;
771 	case BGE_APE_LOCK_PHY0:
772 	case BGE_APE_LOCK_PHY1:
773 	case BGE_APE_LOCK_PHY2:
774 	case BGE_APE_LOCK_PHY3:
775 		/* Lock required when accessing PHYs. */
776 		bit = BGE_APE_LOCK_REQ_DRIVER0;
777 		break;
778 	default:
779 		return (EINVAL);
780 	}
781 
782 	/* Request a lock. */
783 	APE_WRITE_4(sc, req + off, bit);
784 
785 	/* Wait up to 1 second to acquire lock. */
786 	for (i = 0; i < 20000; i++) {
787 		status = APE_READ_4(sc, gnt + off);
788 		if (status == bit)
789 			break;
790 		DELAY(50);
791 	}
792 
793 	/* Handle any errors. */
794 	if (status != bit) {
795 		device_printf(sc->bge_dev, "APE lock %d request failed! "
796 		    "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n",
797 		    locknum, req + off, bit & 0xFFFF, gnt + off,
798 		    status & 0xFFFF);
799 		/* Revoke the lock request. */
800 		APE_WRITE_4(sc, gnt + off, bit);
801 		return (EBUSY);
802 	}
803 
804 	return (0);
805 }
806 
807 static void
808 bge_ape_unlock(struct bge_softc *sc, int locknum)
809 {
810 	uint32_t bit, gnt;
811 	int off;
812 
813 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
814 		return;
815 
816 	if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
817 		gnt = BGE_APE_LOCK_GRANT;
818 	else
819 		gnt = BGE_APE_PER_LOCK_GRANT;
820 
821 	off = 4 * locknum;
822 
823 	switch (locknum) {
824 	case BGE_APE_LOCK_GPIO:
825 		if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
826 			return;
827 		if (sc->bge_func_addr == 0)
828 			bit = BGE_APE_LOCK_GRANT_DRIVER0;
829 		else
830 			bit = (1 << sc->bge_func_addr);
831 		break;
832 	case BGE_APE_LOCK_GRC:
833 		if (sc->bge_func_addr == 0)
834 			bit = BGE_APE_LOCK_GRANT_DRIVER0;
835 		else
836 			bit = (1 << sc->bge_func_addr);
837 		break;
838 	case BGE_APE_LOCK_MEM:
839 		if (sc->bge_func_addr == 0)
840 			bit = BGE_APE_LOCK_GRANT_DRIVER0;
841 		else
842 			bit = (1 << sc->bge_func_addr);
843 		break;
844 	case BGE_APE_LOCK_PHY0:
845 	case BGE_APE_LOCK_PHY1:
846 	case BGE_APE_LOCK_PHY2:
847 	case BGE_APE_LOCK_PHY3:
848 		bit = BGE_APE_LOCK_GRANT_DRIVER0;
849 		break;
850 	default:
851 		return;
852 	}
853 
854 	APE_WRITE_4(sc, gnt + off, bit);
855 }
856 
857 /*
858  * Send an event to the APE firmware.
859  */
860 static void
861 bge_ape_send_event(struct bge_softc *sc, uint32_t event)
862 {
863 	uint32_t apedata;
864 	int i;
865 
866 	/* NCSI does not support APE events. */
867 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
868 		return;
869 
870 	/* Wait up to 1ms for APE to service previous event. */
871 	for (i = 10; i > 0; i--) {
872 		if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0)
873 			break;
874 		apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS);
875 		if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) {
876 			APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event |
877 			    BGE_APE_EVENT_STATUS_EVENT_PENDING);
878 			bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
879 			APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1);
880 			break;
881 		}
882 		bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
883 		DELAY(100);
884 	}
885 	if (i == 0)
886 		device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n",
887 		    event);
888 }
889 
890 static void
891 bge_ape_driver_state_change(struct bge_softc *sc, int kind)
892 {
893 	uint32_t apedata, event;
894 
895 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
896 		return;
897 
898 	switch (kind) {
899 	case BGE_RESET_START:
900 		/* If this is the first load, clear the load counter. */
901 		apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG);
902 		if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC)
903 			APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0);
904 		else {
905 			apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT);
906 			APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata);
907 		}
908 		APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG,
909 		    BGE_APE_HOST_SEG_SIG_MAGIC);
910 		APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN,
911 		    BGE_APE_HOST_SEG_LEN_MAGIC);
912 
913 		/* Add some version info if bge(4) supports it. */
914 		APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID,
915 		    BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0));
916 		APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR,
917 		    BGE_APE_HOST_BEHAV_NO_PHYLOCK);
918 		APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS,
919 		    BGE_APE_HOST_HEARTBEAT_INT_DISABLE);
920 		APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
921 		    BGE_APE_HOST_DRVR_STATE_START);
922 		event = BGE_APE_EVENT_STATUS_STATE_START;
923 		break;
924 	case BGE_RESET_SHUTDOWN:
925 		APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
926 		    BGE_APE_HOST_DRVR_STATE_UNLOAD);
927 		event = BGE_APE_EVENT_STATUS_STATE_UNLOAD;
928 		break;
929 	case BGE_RESET_SUSPEND:
930 		event = BGE_APE_EVENT_STATUS_STATE_SUSPEND;
931 		break;
932 	default:
933 		return;
934 	}
935 
936 	bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT |
937 	    BGE_APE_EVENT_STATUS_STATE_CHNGE);
938 }
939 
940 /*
941  * Map a single buffer address.
942  */
943 
944 static void
945 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
946 {
947 	struct bge_dmamap_arg *ctx;
948 
949 	if (error)
950 		return;
951 
952 	KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg));
953 
954 	ctx = arg;
955 	ctx->bge_busaddr = segs->ds_addr;
956 }
957 
958 static uint8_t
959 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
960 {
961 	uint32_t access, byte = 0;
962 	int i;
963 
964 	/* Lock. */
965 	CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
966 	for (i = 0; i < 8000; i++) {
967 		if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
968 			break;
969 		DELAY(20);
970 	}
971 	if (i == 8000)
972 		return (1);
973 
974 	/* Enable access. */
975 	access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
976 	CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
977 
978 	CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
979 	CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
980 	for (i = 0; i < BGE_TIMEOUT * 10; i++) {
981 		DELAY(10);
982 		if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
983 			DELAY(10);
984 			break;
985 		}
986 	}
987 
988 	if (i == BGE_TIMEOUT * 10) {
989 		if_printf(sc->bge_ifp, "nvram read timed out\n");
990 		return (1);
991 	}
992 
993 	/* Get result. */
994 	byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
995 
996 	*dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
997 
998 	/* Disable access. */
999 	CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
1000 
1001 	/* Unlock. */
1002 	CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
1003 	CSR_READ_4(sc, BGE_NVRAM_SWARB);
1004 
1005 	return (0);
1006 }
1007 
1008 /*
1009  * Read a sequence of bytes from NVRAM.
1010  */
1011 static int
1012 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1013 {
1014 	int err = 0, i;
1015 	uint8_t byte = 0;
1016 
1017 	if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1018 		return (1);
1019 
1020 	for (i = 0; i < cnt; i++) {
1021 		err = bge_nvram_getbyte(sc, off + i, &byte);
1022 		if (err)
1023 			break;
1024 		*(dest + i) = byte;
1025 	}
1026 
1027 	return (err ? 1 : 0);
1028 }
1029 
1030 /*
1031  * Read a byte of data stored in the EEPROM at address 'addr.' The
1032  * BCM570x supports both the traditional bitbang interface and an
1033  * auto access interface for reading the EEPROM. We use the auto
1034  * access method.
1035  */
1036 static uint8_t
1037 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1038 {
1039 	int i;
1040 	uint32_t byte = 0;
1041 
1042 	/*
1043 	 * Enable use of auto EEPROM access so we can avoid
1044 	 * having to use the bitbang method.
1045 	 */
1046 	BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
1047 
1048 	/* Reset the EEPROM, load the clock period. */
1049 	CSR_WRITE_4(sc, BGE_EE_ADDR,
1050 	    BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
1051 	DELAY(20);
1052 
1053 	/* Issue the read EEPROM command. */
1054 	CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
1055 
1056 	/* Wait for completion */
1057 	for(i = 0; i < BGE_TIMEOUT * 10; i++) {
1058 		DELAY(10);
1059 		if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
1060 			break;
1061 	}
1062 
1063 	if (i == BGE_TIMEOUT * 10) {
1064 		device_printf(sc->bge_dev, "EEPROM read timed out\n");
1065 		return (1);
1066 	}
1067 
1068 	/* Get result. */
1069 	byte = CSR_READ_4(sc, BGE_EE_DATA);
1070 
1071 	*dest = (byte >> ((addr % 4) * 8)) & 0xFF;
1072 
1073 	return (0);
1074 }
1075 
1076 /*
1077  * Read a sequence of bytes from the EEPROM.
1078  */
1079 static int
1080 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1081 {
1082 	int i, error = 0;
1083 	uint8_t byte = 0;
1084 
1085 	for (i = 0; i < cnt; i++) {
1086 		error = bge_eeprom_getbyte(sc, off + i, &byte);
1087 		if (error)
1088 			break;
1089 		*(dest + i) = byte;
1090 	}
1091 
1092 	return (error ? 1 : 0);
1093 }
1094 
1095 static int
1096 bge_miibus_readreg(device_t dev, int phy, int reg)
1097 {
1098 	struct bge_softc *sc;
1099 	uint32_t val;
1100 	int i;
1101 
1102 	sc = device_get_softc(dev);
1103 
1104 	if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1105 		return (0);
1106 
1107 	/* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1108 	if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1109 		CSR_WRITE_4(sc, BGE_MI_MODE,
1110 		    sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1111 		DELAY(80);
1112 	}
1113 
1114 	CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
1115 	    BGE_MIPHY(phy) | BGE_MIREG(reg));
1116 
1117 	/* Poll for the PHY register access to complete. */
1118 	for (i = 0; i < BGE_TIMEOUT; i++) {
1119 		DELAY(10);
1120 		val = CSR_READ_4(sc, BGE_MI_COMM);
1121 		if ((val & BGE_MICOMM_BUSY) == 0) {
1122 			DELAY(5);
1123 			val = CSR_READ_4(sc, BGE_MI_COMM);
1124 			break;
1125 		}
1126 	}
1127 
1128 	if (i == BGE_TIMEOUT) {
1129 		device_printf(sc->bge_dev,
1130 		    "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
1131 		    phy, reg, val);
1132 		val = 0;
1133 	}
1134 
1135 	/* Restore the autopoll bit if necessary. */
1136 	if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1137 		CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1138 		DELAY(80);
1139 	}
1140 
1141 	bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1142 
1143 	if (val & BGE_MICOMM_READFAIL)
1144 		return (0);
1145 
1146 	return (val & 0xFFFF);
1147 }
1148 
1149 static int
1150 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
1151 {
1152 	struct bge_softc *sc;
1153 	int i;
1154 
1155 	sc = device_get_softc(dev);
1156 
1157 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1158 	    (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
1159 		return (0);
1160 
1161 	if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1162 		return (0);
1163 
1164 	/* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1165 	if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1166 		CSR_WRITE_4(sc, BGE_MI_MODE,
1167 		    sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1168 		DELAY(80);
1169 	}
1170 
1171 	CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
1172 	    BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
1173 
1174 	for (i = 0; i < BGE_TIMEOUT; i++) {
1175 		DELAY(10);
1176 		if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
1177 			DELAY(5);
1178 			CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
1179 			break;
1180 		}
1181 	}
1182 
1183 	/* Restore the autopoll bit if necessary. */
1184 	if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1185 		CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1186 		DELAY(80);
1187 	}
1188 
1189 	bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1190 
1191 	if (i == BGE_TIMEOUT)
1192 		device_printf(sc->bge_dev,
1193 		    "PHY write timed out (phy %d, reg %d, val 0x%04x)\n",
1194 		    phy, reg, val);
1195 
1196 	return (0);
1197 }
1198 
1199 static void
1200 bge_miibus_statchg(device_t dev)
1201 {
1202 	struct bge_softc *sc;
1203 	struct mii_data *mii;
1204 	uint32_t mac_mode, rx_mode, tx_mode;
1205 
1206 	sc = device_get_softc(dev);
1207 	if ((if_getdrvflags(sc->bge_ifp) & IFF_DRV_RUNNING) == 0)
1208 		return;
1209 	mii = device_get_softc(sc->bge_miibus);
1210 
1211 	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1212 	    (IFM_ACTIVE | IFM_AVALID)) {
1213 		switch (IFM_SUBTYPE(mii->mii_media_active)) {
1214 		case IFM_10_T:
1215 		case IFM_100_TX:
1216 			sc->bge_link = 1;
1217 			break;
1218 		case IFM_1000_T:
1219 		case IFM_1000_SX:
1220 		case IFM_2500_SX:
1221 			if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1222 				sc->bge_link = 1;
1223 			else
1224 				sc->bge_link = 0;
1225 			break;
1226 		default:
1227 			sc->bge_link = 0;
1228 			break;
1229 		}
1230 	} else
1231 		sc->bge_link = 0;
1232 	if (sc->bge_link == 0)
1233 		return;
1234 
1235 	/*
1236 	 * APE firmware touches these registers to keep the MAC
1237 	 * connected to the outside world.  Try to keep the
1238 	 * accesses atomic.
1239 	 */
1240 
1241 	/* Set the port mode (MII/GMII) to match the link speed. */
1242 	mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &
1243 	    ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX);
1244 	tx_mode = CSR_READ_4(sc, BGE_TX_MODE);
1245 	rx_mode = CSR_READ_4(sc, BGE_RX_MODE);
1246 
1247 	if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1248 	    IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
1249 		mac_mode |= BGE_PORTMODE_GMII;
1250 	else
1251 		mac_mode |= BGE_PORTMODE_MII;
1252 
1253 	/* Set MAC flow control behavior to match link flow control settings. */
1254 	tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE;
1255 	rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE;
1256 	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1257 		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1258 			tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE;
1259 		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1260 			rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE;
1261 	} else
1262 		mac_mode |= BGE_MACMODE_HALF_DUPLEX;
1263 
1264 	CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode);
1265 	DELAY(40);
1266 	CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode);
1267 	CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode);
1268 }
1269 
1270 /*
1271  * Intialize a standard receive ring descriptor.
1272  */
1273 static int
1274 bge_newbuf_std(struct bge_softc *sc, int i)
1275 {
1276 	struct mbuf *m;
1277 	struct bge_rx_bd *r;
1278 	bus_dma_segment_t segs[1];
1279 	bus_dmamap_t map;
1280 	int error, nsegs;
1281 
1282 	if (sc->bge_flags & BGE_FLAG_JUMBO_STD &&
1283 	    (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
1284 	    ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) {
1285 		m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1286 		if (m == NULL)
1287 			return (ENOBUFS);
1288 		m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1289 	} else {
1290 		m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1291 		if (m == NULL)
1292 			return (ENOBUFS);
1293 		m->m_len = m->m_pkthdr.len = MCLBYTES;
1294 	}
1295 	if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1296 		m_adj(m, ETHER_ALIGN);
1297 
1298 	error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
1299 	    sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
1300 	if (error != 0) {
1301 		m_freem(m);
1302 		return (error);
1303 	}
1304 	if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1305 		bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1306 		    sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
1307 		bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1308 		    sc->bge_cdata.bge_rx_std_dmamap[i]);
1309 	}
1310 	map = sc->bge_cdata.bge_rx_std_dmamap[i];
1311 	sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
1312 	sc->bge_cdata.bge_rx_std_sparemap = map;
1313 	sc->bge_cdata.bge_rx_std_chain[i] = m;
1314 	sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len;
1315 	r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
1316 	r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1317 	r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1318 	r->bge_flags = BGE_RXBDFLAG_END;
1319 	r->bge_len = segs[0].ds_len;
1320 	r->bge_idx = i;
1321 
1322 	bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1323 	    sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
1324 
1325 	return (0);
1326 }
1327 
1328 /*
1329  * Initialize a jumbo receive ring descriptor. This allocates
1330  * a jumbo buffer from the pool managed internally by the driver.
1331  */
1332 static int
1333 bge_newbuf_jumbo(struct bge_softc *sc, int i)
1334 {
1335 	bus_dma_segment_t segs[BGE_NSEG_JUMBO];
1336 	bus_dmamap_t map;
1337 	struct bge_extrx_bd *r;
1338 	struct mbuf *m;
1339 	int error, nsegs;
1340 
1341 	MGETHDR(m, M_NOWAIT, MT_DATA);
1342 	if (m == NULL)
1343 		return (ENOBUFS);
1344 
1345 	if (m_cljget(m, M_NOWAIT, MJUM9BYTES) == NULL) {
1346 		m_freem(m);
1347 		return (ENOBUFS);
1348 	}
1349 	m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1350 	if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1351 		m_adj(m, ETHER_ALIGN);
1352 
1353 	error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
1354 	    sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1355 	if (error != 0) {
1356 		m_freem(m);
1357 		return (error);
1358 	}
1359 
1360 	if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1361 		bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1362 		    sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
1363 		bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1364 		    sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1365 	}
1366 	map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1367 	sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1368 	    sc->bge_cdata.bge_rx_jumbo_sparemap;
1369 	sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1370 	sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1371 	sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0;
1372 	sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0;
1373 	sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0;
1374 	sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0;
1375 
1376 	/*
1377 	 * Fill in the extended RX buffer descriptor.
1378 	 */
1379 	r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1380 	r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
1381 	r->bge_idx = i;
1382 	r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
1383 	switch (nsegs) {
1384 	case 4:
1385 		r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1386 		r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1387 		r->bge_len3 = segs[3].ds_len;
1388 		sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len;
1389 	case 3:
1390 		r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1391 		r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1392 		r->bge_len2 = segs[2].ds_len;
1393 		sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len;
1394 	case 2:
1395 		r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1396 		r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1397 		r->bge_len1 = segs[1].ds_len;
1398 		sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len;
1399 	case 1:
1400 		r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1401 		r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1402 		r->bge_len0 = segs[0].ds_len;
1403 		sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len;
1404 		break;
1405 	default:
1406 		panic("%s: %d segments\n", __func__, nsegs);
1407 	}
1408 
1409 	bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1410 	    sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1411 
1412 	return (0);
1413 }
1414 
1415 static int
1416 bge_init_rx_ring_std(struct bge_softc *sc)
1417 {
1418 	int error, i;
1419 
1420 	bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1421 	sc->bge_std = 0;
1422 	for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1423 		if ((error = bge_newbuf_std(sc, i)) != 0)
1424 			return (error);
1425 		BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1426 	}
1427 
1428 	bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1429 	    sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1430 
1431 	sc->bge_std = 0;
1432 	bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1);
1433 
1434 	return (0);
1435 }
1436 
1437 static void
1438 bge_free_rx_ring_std(struct bge_softc *sc)
1439 {
1440 	int i;
1441 
1442 	for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1443 		if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1444 			bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1445 			    sc->bge_cdata.bge_rx_std_dmamap[i],
1446 			    BUS_DMASYNC_POSTREAD);
1447 			bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1448 			    sc->bge_cdata.bge_rx_std_dmamap[i]);
1449 			m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1450 			sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1451 		}
1452 		bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1453 		    sizeof(struct bge_rx_bd));
1454 	}
1455 }
1456 
1457 static int
1458 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1459 {
1460 	struct bge_rcb *rcb;
1461 	int error, i;
1462 
1463 	bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1464 	sc->bge_jumbo = 0;
1465 	for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1466 		if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1467 			return (error);
1468 		BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1469 	}
1470 
1471 	bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1472 	    sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1473 
1474 	sc->bge_jumbo = 0;
1475 
1476 	/* Enable the jumbo receive producer ring. */
1477 	rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1478 	rcb->bge_maxlen_flags =
1479 	    BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD);
1480 	CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1481 
1482 	bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1);
1483 
1484 	return (0);
1485 }
1486 
1487 static void
1488 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1489 {
1490 	int i;
1491 
1492 	for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1493 		if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1494 			bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1495 			    sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1496 			    BUS_DMASYNC_POSTREAD);
1497 			bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1498 			    sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1499 			m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1500 			sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1501 		}
1502 		bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1503 		    sizeof(struct bge_extrx_bd));
1504 	}
1505 }
1506 
1507 static void
1508 bge_free_tx_ring(struct bge_softc *sc)
1509 {
1510 	int i;
1511 
1512 	if (sc->bge_ldata.bge_tx_ring == NULL)
1513 		return;
1514 
1515 	for (i = 0; i < BGE_TX_RING_CNT; i++) {
1516 		if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1517 			bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1518 			    sc->bge_cdata.bge_tx_dmamap[i],
1519 			    BUS_DMASYNC_POSTWRITE);
1520 			bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1521 			    sc->bge_cdata.bge_tx_dmamap[i]);
1522 			m_freem(sc->bge_cdata.bge_tx_chain[i]);
1523 			sc->bge_cdata.bge_tx_chain[i] = NULL;
1524 		}
1525 		bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1526 		    sizeof(struct bge_tx_bd));
1527 	}
1528 }
1529 
1530 static int
1531 bge_init_tx_ring(struct bge_softc *sc)
1532 {
1533 	sc->bge_txcnt = 0;
1534 	sc->bge_tx_saved_considx = 0;
1535 
1536 	bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1537 	bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1538 	    sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1539 
1540 	/* Initialize transmit producer index for host-memory send ring. */
1541 	sc->bge_tx_prodidx = 0;
1542 	bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1543 
1544 	/* 5700 b2 errata */
1545 	if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1546 		bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1547 
1548 	/* NIC-memory send ring not used; initialize to zero. */
1549 	bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1550 	/* 5700 b2 errata */
1551 	if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1552 		bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1553 
1554 	return (0);
1555 }
1556 
1557 static void
1558 bge_setpromisc(struct bge_softc *sc)
1559 {
1560 	if_t ifp;
1561 
1562 	BGE_LOCK_ASSERT(sc);
1563 
1564 	ifp = sc->bge_ifp;
1565 
1566 	/* Enable or disable promiscuous mode as needed. */
1567 	if (if_getflags(ifp) & IFF_PROMISC)
1568 		BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1569 	else
1570 		BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1571 }
1572 
1573 static u_int
1574 bge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1575 {
1576 	uint32_t *hashes = arg;
1577 	int h;
1578 
1579 	h = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN) & 0x7F;
1580 	hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1581 
1582 	return (1);
1583 }
1584 
1585 static void
1586 bge_setmulti(struct bge_softc *sc)
1587 {
1588 	if_t ifp;
1589 	uint32_t hashes[4] = { 0, 0, 0, 0 };
1590 	int i;
1591 
1592 	BGE_LOCK_ASSERT(sc);
1593 
1594 	ifp = sc->bge_ifp;
1595 
1596 	if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) {
1597 		for (i = 0; i < 4; i++)
1598 			CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1599 		return;
1600 	}
1601 
1602 	/* First, zot all the existing filters. */
1603 	for (i = 0; i < 4; i++)
1604 		CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1605 
1606 	if_foreach_llmaddr(ifp, bge_hash_maddr, hashes);
1607 
1608 	for (i = 0; i < 4; i++)
1609 		CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1610 }
1611 
1612 static void
1613 bge_setvlan(struct bge_softc *sc)
1614 {
1615 	if_t ifp;
1616 
1617 	BGE_LOCK_ASSERT(sc);
1618 
1619 	ifp = sc->bge_ifp;
1620 
1621 	/* Enable or disable VLAN tag stripping as needed. */
1622 	if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING)
1623 		BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1624 	else
1625 		BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1626 }
1627 
1628 static void
1629 bge_sig_pre_reset(struct bge_softc *sc, int type)
1630 {
1631 
1632 	/*
1633 	 * Some chips don't like this so only do this if ASF is enabled
1634 	 */
1635 	if (sc->bge_asf_mode)
1636 		bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
1637 
1638 	if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1639 		switch (type) {
1640 		case BGE_RESET_START:
1641 			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1642 			    BGE_FW_DRV_STATE_START);
1643 			break;
1644 		case BGE_RESET_SHUTDOWN:
1645 			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1646 			    BGE_FW_DRV_STATE_UNLOAD);
1647 			break;
1648 		case BGE_RESET_SUSPEND:
1649 			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1650 			    BGE_FW_DRV_STATE_SUSPEND);
1651 			break;
1652 		}
1653 	}
1654 
1655 	if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND)
1656 		bge_ape_driver_state_change(sc, type);
1657 }
1658 
1659 static void
1660 bge_sig_post_reset(struct bge_softc *sc, int type)
1661 {
1662 
1663 	if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1664 		switch (type) {
1665 		case BGE_RESET_START:
1666 			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1667 			    BGE_FW_DRV_STATE_START_DONE);
1668 			/* START DONE */
1669 			break;
1670 		case BGE_RESET_SHUTDOWN:
1671 			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1672 			    BGE_FW_DRV_STATE_UNLOAD_DONE);
1673 			break;
1674 		}
1675 	}
1676 	if (type == BGE_RESET_SHUTDOWN)
1677 		bge_ape_driver_state_change(sc, type);
1678 }
1679 
1680 static void
1681 bge_sig_legacy(struct bge_softc *sc, int type)
1682 {
1683 
1684 	if (sc->bge_asf_mode) {
1685 		switch (type) {
1686 		case BGE_RESET_START:
1687 			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1688 			    BGE_FW_DRV_STATE_START);
1689 			break;
1690 		case BGE_RESET_SHUTDOWN:
1691 			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1692 			    BGE_FW_DRV_STATE_UNLOAD);
1693 			break;
1694 		}
1695 	}
1696 }
1697 
1698 static void
1699 bge_stop_fw(struct bge_softc *sc)
1700 {
1701 	int i;
1702 
1703 	if (sc->bge_asf_mode) {
1704 		bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
1705 		CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
1706 		    CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
1707 
1708 		for (i = 0; i < 100; i++ ) {
1709 			if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
1710 			    BGE_RX_CPU_DRV_EVENT))
1711 				break;
1712 			DELAY(10);
1713 		}
1714 	}
1715 }
1716 
1717 static uint32_t
1718 bge_dma_swap_options(struct bge_softc *sc)
1719 {
1720 	uint32_t dma_options;
1721 
1722 	dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
1723 	    BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
1724 #if BYTE_ORDER == BIG_ENDIAN
1725 	dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
1726 #endif
1727 	return (dma_options);
1728 }
1729 
1730 /*
1731  * Do endian, PCI and DMA initialization.
1732  */
1733 static int
1734 bge_chipinit(struct bge_softc *sc)
1735 {
1736 	uint32_t dma_rw_ctl, misc_ctl, mode_ctl;
1737 	uint16_t val;
1738 	int i;
1739 
1740 	/* Set endianness before we access any non-PCI registers. */
1741 	misc_ctl = BGE_INIT;
1742 	if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS)
1743 		misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS;
1744 	pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4);
1745 
1746 	/*
1747 	 * Clear the MAC statistics block in the NIC's
1748 	 * internal memory.
1749 	 */
1750 	for (i = BGE_STATS_BLOCK;
1751 	    i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1752 		BGE_MEMWIN_WRITE(sc, i, 0);
1753 
1754 	for (i = BGE_STATUS_BLOCK;
1755 	    i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1756 		BGE_MEMWIN_WRITE(sc, i, 0);
1757 
1758 	if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1759 		/*
1760 		 *  Fix data corruption caused by non-qword write with WB.
1761 		 *  Fix master abort in PCI mode.
1762 		 *  Fix PCI latency timer.
1763 		 */
1764 		val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1765 		val |= (1 << 10) | (1 << 12) | (1 << 13);
1766 		pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1767 	}
1768 
1769 	if (sc->bge_asicrev == BGE_ASICREV_BCM57765 ||
1770 	    sc->bge_asicrev == BGE_ASICREV_BCM57766) {
1771 		/*
1772 		 * For the 57766 and non Ax versions of 57765, bootcode
1773 		 * needs to setup the PCIE Fast Training Sequence (FTS)
1774 		 * value to prevent transmit hangs.
1775 		 */
1776 		if (sc->bge_chiprev != BGE_CHIPREV_57765_AX) {
1777 			CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL,
1778 			    CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) |
1779 			    BGE_CPMU_PADRNG_CTL_RDIV2);
1780 		}
1781 	}
1782 
1783 	/*
1784 	 * Set up the PCI DMA control register.
1785 	 */
1786 	dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1787 	    BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1788 	if (sc->bge_flags & BGE_FLAG_PCIE) {
1789 		if (sc->bge_mps >= 256)
1790 			dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1791 		else
1792 			dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1793 	} else if (sc->bge_flags & BGE_FLAG_PCIX) {
1794 		if (BGE_IS_5714_FAMILY(sc)) {
1795 			/* 256 bytes for read and write. */
1796 			dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1797 			    BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1798 			dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1799 			    BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1800 			    BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1801 		} else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1802 			/*
1803 			 * In the BCM5703, the DMA read watermark should
1804 			 * be set to less than or equal to the maximum
1805 			 * memory read byte count of the PCI-X command
1806 			 * register.
1807 			 */
1808 			dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) |
1809 			    BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1810 		} else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1811 			/* 1536 bytes for read, 384 bytes for write. */
1812 			dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1813 			    BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1814 		} else {
1815 			/* 384 bytes for read and write. */
1816 			dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1817 			    BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1818 			    0x0F;
1819 		}
1820 		if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1821 		    sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1822 			uint32_t tmp;
1823 
1824 			/* Set ONE_DMA_AT_ONCE for hardware workaround. */
1825 			tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1826 			if (tmp == 6 || tmp == 7)
1827 				dma_rw_ctl |=
1828 				    BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1829 
1830 			/* Set PCI-X DMA write workaround. */
1831 			dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1832 		}
1833 	} else {
1834 		/* Conventional PCI bus: 256 bytes for read and write. */
1835 		dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1836 		    BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1837 
1838 		if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1839 		    sc->bge_asicrev != BGE_ASICREV_BCM5750)
1840 			dma_rw_ctl |= 0x0F;
1841 	}
1842 	if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1843 	    sc->bge_asicrev == BGE_ASICREV_BCM5701)
1844 		dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1845 		    BGE_PCIDMARWCTL_ASRT_ALL_BE;
1846 	if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1847 	    sc->bge_asicrev == BGE_ASICREV_BCM5704)
1848 		dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1849 	if (BGE_IS_5717_PLUS(sc)) {
1850 		dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1851 		if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
1852 			dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1853 		/*
1854 		 * Enable HW workaround for controllers that misinterpret
1855 		 * a status tag update and leave interrupts permanently
1856 		 * disabled.
1857 		 */
1858 		if (!BGE_IS_57765_PLUS(sc) &&
1859 		    sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
1860 		    sc->bge_asicrev != BGE_ASICREV_BCM5762)
1861 			dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1862 	}
1863 	pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1864 
1865 	/*
1866 	 * Set up general mode register.
1867 	 */
1868 	mode_ctl = bge_dma_swap_options(sc);
1869 	if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
1870 	    sc->bge_asicrev == BGE_ASICREV_BCM5762) {
1871 		/* Retain Host-2-BMC settings written by APE firmware. */
1872 		mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) &
1873 		    (BGE_MODECTL_BYTESWAP_B2HRX_DATA |
1874 		    BGE_MODECTL_WORDSWAP_B2HRX_DATA |
1875 		    BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE);
1876 	}
1877 	mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1878 	    BGE_MODECTL_TX_NO_PHDR_CSUM;
1879 
1880 	/*
1881 	 * BCM5701 B5 have a bug causing data corruption when using
1882 	 * 64-bit DMA reads, which can be terminated early and then
1883 	 * completed later as 32-bit accesses, in combination with
1884 	 * certain bridges.
1885 	 */
1886 	if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1887 	    sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1888 		mode_ctl |= BGE_MODECTL_FORCE_PCI32;
1889 
1890 	/*
1891 	 * Tell the firmware the driver is running
1892 	 */
1893 	if (sc->bge_asf_mode & ASF_STACKUP)
1894 		mode_ctl |= BGE_MODECTL_STACKUP;
1895 
1896 	CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1897 
1898 	/*
1899 	 * Disable memory write invalidate.  Apparently it is not supported
1900 	 * properly by these devices.
1901 	 */
1902 	PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1903 
1904 	/* Set the timer prescaler (always 66 MHz). */
1905 	CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1906 
1907 	/* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1908 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1909 		DELAY(40);	/* XXX */
1910 
1911 		/* Put PHY into ready state */
1912 		BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1913 		CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1914 		DELAY(40);
1915 	}
1916 
1917 	return (0);
1918 }
1919 
1920 static int
1921 bge_blockinit(struct bge_softc *sc)
1922 {
1923 	struct bge_rcb *rcb;
1924 	bus_size_t vrcb;
1925 	caddr_t	lladdr;
1926 	bge_hostaddr taddr;
1927 	uint32_t dmactl, rdmareg, val;
1928 	int i, limit;
1929 
1930 	/*
1931 	 * Initialize the memory window pointer register so that
1932 	 * we can access the first 32K of internal NIC RAM. This will
1933 	 * allow us to set up the TX send ring RCBs and the RX return
1934 	 * ring RCBs, plus other things which live in NIC memory.
1935 	 */
1936 	CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1937 
1938 	/* Note: the BCM5704 has a smaller mbuf space than other chips. */
1939 
1940 	if (!(BGE_IS_5705_PLUS(sc))) {
1941 		/* Configure mbuf memory pool */
1942 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1943 		if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1944 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1945 		else
1946 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1947 
1948 		/* Configure DMA resource pool */
1949 		CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1950 		    BGE_DMA_DESCRIPTORS);
1951 		CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1952 	}
1953 
1954 	/* Configure mbuf pool watermarks */
1955 	if (BGE_IS_5717_PLUS(sc)) {
1956 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1957 		if (if_getmtu(sc->bge_ifp) > ETHERMTU) {
1958 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1959 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1960 		} else {
1961 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1962 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1963 		}
1964 	} else if (!BGE_IS_5705_PLUS(sc)) {
1965 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1966 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1967 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1968 	} else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1969 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1970 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1971 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1972 	} else {
1973 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1974 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1975 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1976 	}
1977 
1978 	/* Configure DMA resource watermarks */
1979 	CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1980 	CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1981 
1982 	/* Enable buffer manager */
1983 	val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1984 	/*
1985 	 * Change the arbitration algorithm of TXMBUF read request to
1986 	 * round-robin instead of priority based for BCM5719.  When
1987 	 * TXFIFO is almost empty, RDMA will hold its request until
1988 	 * TXFIFO is not almost empty.
1989 	 */
1990 	if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
1991 		val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1992 	CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1993 
1994 	/* Poll for buffer manager start indication */
1995 	for (i = 0; i < BGE_TIMEOUT; i++) {
1996 		DELAY(10);
1997 		if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1998 			break;
1999 	}
2000 
2001 	if (i == BGE_TIMEOUT) {
2002 		device_printf(sc->bge_dev, "buffer manager failed to start\n");
2003 		return (ENXIO);
2004 	}
2005 
2006 	/* Enable flow-through queues */
2007 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2008 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2009 
2010 	/* Wait until queue initialization is complete */
2011 	for (i = 0; i < BGE_TIMEOUT; i++) {
2012 		DELAY(10);
2013 		if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
2014 			break;
2015 	}
2016 
2017 	if (i == BGE_TIMEOUT) {
2018 		device_printf(sc->bge_dev, "flow-through queue init failed\n");
2019 		return (ENXIO);
2020 	}
2021 
2022 	/*
2023 	 * Summary of rings supported by the controller:
2024 	 *
2025 	 * Standard Receive Producer Ring
2026 	 * - This ring is used to feed receive buffers for "standard"
2027 	 *   sized frames (typically 1536 bytes) to the controller.
2028 	 *
2029 	 * Jumbo Receive Producer Ring
2030 	 * - This ring is used to feed receive buffers for jumbo sized
2031 	 *   frames (i.e. anything bigger than the "standard" frames)
2032 	 *   to the controller.
2033 	 *
2034 	 * Mini Receive Producer Ring
2035 	 * - This ring is used to feed receive buffers for "mini"
2036 	 *   sized frames to the controller.
2037 	 * - This feature required external memory for the controller
2038 	 *   but was never used in a production system.  Should always
2039 	 *   be disabled.
2040 	 *
2041 	 * Receive Return Ring
2042 	 * - After the controller has placed an incoming frame into a
2043 	 *   receive buffer that buffer is moved into a receive return
2044 	 *   ring.  The driver is then responsible to passing the
2045 	 *   buffer up to the stack.  Many versions of the controller
2046 	 *   support multiple RR rings.
2047 	 *
2048 	 * Send Ring
2049 	 * - This ring is used for outgoing frames.  Many versions of
2050 	 *   the controller support multiple send rings.
2051 	 */
2052 
2053 	/* Initialize the standard receive producer ring control block. */
2054 	rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
2055 	rcb->bge_hostaddr.bge_addr_lo =
2056 	    BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
2057 	rcb->bge_hostaddr.bge_addr_hi =
2058 	    BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
2059 	bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2060 	    sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
2061 	if (BGE_IS_5717_PLUS(sc)) {
2062 		/*
2063 		 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
2064 		 * Bits 15-2 : Maximum RX frame size
2065 		 * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
2066 		 * Bit 0     : Reserved
2067 		 */
2068 		rcb->bge_maxlen_flags =
2069 		    BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2);
2070 	} else if (BGE_IS_5705_PLUS(sc)) {
2071 		/*
2072 		 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
2073 		 * Bits 15-2 : Reserved (should be 0)
2074 		 * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
2075 		 * Bit 0     : Reserved
2076 		 */
2077 		rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
2078 	} else {
2079 		/*
2080 		 * Ring size is always XXX entries
2081 		 * Bits 31-16: Maximum RX frame size
2082 		 * Bits 15-2 : Reserved (should be 0)
2083 		 * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
2084 		 * Bit 0     : Reserved
2085 		 */
2086 		rcb->bge_maxlen_flags =
2087 		    BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
2088 	}
2089 	if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2090 	    sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2091 	    sc->bge_asicrev == BGE_ASICREV_BCM5720)
2092 		rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
2093 	else
2094 		rcb->bge_nicaddr = BGE_STD_RX_RINGS;
2095 	/* Write the standard receive producer ring control block. */
2096 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
2097 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
2098 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
2099 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
2100 
2101 	/* Reset the standard receive producer ring producer index. */
2102 	bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
2103 
2104 	/*
2105 	 * Initialize the jumbo RX producer ring control
2106 	 * block.  We set the 'ring disabled' bit in the
2107 	 * flags field until we're actually ready to start
2108 	 * using this ring (i.e. once we set the MTU
2109 	 * high enough to require it).
2110 	 */
2111 	if (BGE_IS_JUMBO_CAPABLE(sc)) {
2112 		rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
2113 		/* Get the jumbo receive producer ring RCB parameters. */
2114 		rcb->bge_hostaddr.bge_addr_lo =
2115 		    BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2116 		rcb->bge_hostaddr.bge_addr_hi =
2117 		    BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2118 		bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2119 		    sc->bge_cdata.bge_rx_jumbo_ring_map,
2120 		    BUS_DMASYNC_PREREAD);
2121 		rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
2122 		    BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
2123 		if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2124 		    sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2125 		    sc->bge_asicrev == BGE_ASICREV_BCM5720)
2126 			rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
2127 		else
2128 			rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
2129 		CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
2130 		    rcb->bge_hostaddr.bge_addr_hi);
2131 		CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
2132 		    rcb->bge_hostaddr.bge_addr_lo);
2133 		/* Program the jumbo receive producer ring RCB parameters. */
2134 		CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
2135 		    rcb->bge_maxlen_flags);
2136 		CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
2137 		/* Reset the jumbo receive producer ring producer index. */
2138 		bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
2139 	}
2140 
2141 	/* Disable the mini receive producer ring RCB. */
2142 	if (BGE_IS_5700_FAMILY(sc)) {
2143 		rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
2144 		rcb->bge_maxlen_flags =
2145 		    BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
2146 		CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
2147 		    rcb->bge_maxlen_flags);
2148 		/* Reset the mini receive producer ring producer index. */
2149 		bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
2150 	}
2151 
2152 	/* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
2153 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2154 		if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
2155 		    sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
2156 		    sc->bge_chipid == BGE_CHIPID_BCM5906_A2)
2157 			CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
2158 			    (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
2159 	}
2160 	/*
2161 	 * The BD ring replenish thresholds control how often the
2162 	 * hardware fetches new BD's from the producer rings in host
2163 	 * memory.  Setting the value too low on a busy system can
2164 	 * starve the hardware and recue the throughpout.
2165 	 *
2166 	 * Set the BD ring replentish thresholds. The recommended
2167 	 * values are 1/8th the number of descriptors allocated to
2168 	 * each ring.
2169 	 * XXX The 5754 requires a lower threshold, so it might be a
2170 	 * requirement of all 575x family chips.  The Linux driver sets
2171 	 * the lower threshold for all 5705 family chips as well, but there
2172 	 * are reports that it might not need to be so strict.
2173 	 *
2174 	 * XXX Linux does some extra fiddling here for the 5906 parts as
2175 	 * well.
2176 	 */
2177 	if (BGE_IS_5705_PLUS(sc))
2178 		val = 8;
2179 	else
2180 		val = BGE_STD_RX_RING_CNT / 8;
2181 	CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
2182 	if (BGE_IS_JUMBO_CAPABLE(sc))
2183 		CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
2184 		    BGE_JUMBO_RX_RING_CNT/8);
2185 	if (BGE_IS_5717_PLUS(sc)) {
2186 		CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
2187 		CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
2188 	}
2189 
2190 	/*
2191 	 * Disable all send rings by setting the 'ring disabled' bit
2192 	 * in the flags field of all the TX send ring control blocks,
2193 	 * located in NIC memory.
2194 	 */
2195 	if (!BGE_IS_5705_PLUS(sc))
2196 		/* 5700 to 5704 had 16 send rings. */
2197 		limit = BGE_TX_RINGS_EXTSSRAM_MAX;
2198 	else if (BGE_IS_57765_PLUS(sc) ||
2199 	    sc->bge_asicrev == BGE_ASICREV_BCM5762)
2200 		limit = 2;
2201 	else if (BGE_IS_5717_PLUS(sc))
2202 		limit = 4;
2203 	else
2204 		limit = 1;
2205 	vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2206 	for (i = 0; i < limit; i++) {
2207 		RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2208 		    BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
2209 		RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2210 		vrcb += sizeof(struct bge_rcb);
2211 	}
2212 
2213 	/* Configure send ring RCB 0 (we use only the first ring) */
2214 	vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2215 	BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
2216 	RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2217 	RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2218 	if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2219 	    sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2220 	    sc->bge_asicrev == BGE_ASICREV_BCM5720)
2221 		RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
2222 	else
2223 		RCB_WRITE_4(sc, vrcb, bge_nicaddr,
2224 		    BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
2225 	RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2226 	    BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
2227 
2228 	/*
2229 	 * Disable all receive return rings by setting the
2230 	 * 'ring diabled' bit in the flags field of all the receive
2231 	 * return ring control blocks, located in NIC memory.
2232 	 */
2233 	if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2234 	    sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2235 	    sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2236 		/* Should be 17, use 16 until we get an SRAM map. */
2237 		limit = 16;
2238 	} else if (!BGE_IS_5705_PLUS(sc))
2239 		limit = BGE_RX_RINGS_MAX;
2240 	else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2241 	    sc->bge_asicrev == BGE_ASICREV_BCM5762 ||
2242 	    BGE_IS_57765_PLUS(sc))
2243 		limit = 4;
2244 	else
2245 		limit = 1;
2246 	/* Disable all receive return rings. */
2247 	vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2248 	for (i = 0; i < limit; i++) {
2249 		RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
2250 		RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
2251 		RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2252 		    BGE_RCB_FLAG_RING_DISABLED);
2253 		RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2254 		bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
2255 		    (i * (sizeof(uint64_t))), 0);
2256 		vrcb += sizeof(struct bge_rcb);
2257 	}
2258 
2259 	/*
2260 	 * Set up receive return ring 0.  Note that the NIC address
2261 	 * for RX return rings is 0x0.  The return rings live entirely
2262 	 * within the host, so the nicaddr field in the RCB isn't used.
2263 	 */
2264 	vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2265 	BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
2266 	RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2267 	RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2268 	RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2269 	RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2270 	    BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
2271 
2272 	lladdr = if_getlladdr(sc->bge_ifp);
2273 	/* Set random backoff seed for TX */
2274 	CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
2275 	    (lladdr[0] + lladdr[1] +
2276 	    lladdr[2] + lladdr[3] +
2277 	    lladdr[4] + lladdr[5]) &
2278 	    BGE_TX_BACKOFF_SEED_MASK);
2279 
2280 	/* Set inter-packet gap */
2281 	val = 0x2620;
2282 	if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2283 	    sc->bge_asicrev == BGE_ASICREV_BCM5762)
2284 		val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
2285 		    (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
2286 	CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
2287 
2288 	/*
2289 	 * Specify which ring to use for packets that don't match
2290 	 * any RX rules.
2291 	 */
2292 	CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
2293 
2294 	/*
2295 	 * Configure number of RX lists. One interrupt distribution
2296 	 * list, sixteen active lists, one bad frames class.
2297 	 */
2298 	CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
2299 
2300 	/* Inialize RX list placement stats mask. */
2301 	CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
2302 	CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
2303 
2304 	/* Disable host coalescing until we get it set up */
2305 	CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
2306 
2307 	/* Poll to make sure it's shut down. */
2308 	for (i = 0; i < BGE_TIMEOUT; i++) {
2309 		DELAY(10);
2310 		if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
2311 			break;
2312 	}
2313 
2314 	if (i == BGE_TIMEOUT) {
2315 		device_printf(sc->bge_dev,
2316 		    "host coalescing engine failed to idle\n");
2317 		return (ENXIO);
2318 	}
2319 
2320 	/* Set up host coalescing defaults */
2321 	CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
2322 	CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
2323 	CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
2324 	CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
2325 	if (!(BGE_IS_5705_PLUS(sc))) {
2326 		CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
2327 		CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
2328 	}
2329 	CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
2330 	CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
2331 
2332 	/* Set up address of statistics block */
2333 	if (!(BGE_IS_5705_PLUS(sc))) {
2334 		CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
2335 		    BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
2336 		CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
2337 		    BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
2338 		CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
2339 		CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
2340 		CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
2341 	}
2342 
2343 	/* Set up address of status block */
2344 	CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
2345 	    BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
2346 	CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
2347 	    BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
2348 
2349 	/* Set up status block size. */
2350 	if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2351 	    sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
2352 		val = BGE_STATBLKSZ_FULL;
2353 		bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
2354 	} else {
2355 		val = BGE_STATBLKSZ_32BYTE;
2356 		bzero(sc->bge_ldata.bge_status_block, 32);
2357 	}
2358 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2359 	    sc->bge_cdata.bge_status_map,
2360 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2361 
2362 	/* Turn on host coalescing state machine */
2363 	CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
2364 
2365 	/* Turn on RX BD completion state machine and enable attentions */
2366 	CSR_WRITE_4(sc, BGE_RBDC_MODE,
2367 	    BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
2368 
2369 	/* Turn on RX list placement state machine */
2370 	CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2371 
2372 	/* Turn on RX list selector state machine. */
2373 	if (!(BGE_IS_5705_PLUS(sc)))
2374 		CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2375 
2376 	/* Turn on DMA, clear stats. */
2377 	val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
2378 	    BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
2379 	    BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
2380 	    BGE_MACMODE_FRMHDR_DMA_ENB;
2381 
2382 	if (sc->bge_flags & BGE_FLAG_TBI)
2383 		val |= BGE_PORTMODE_TBI;
2384 	else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
2385 		val |= BGE_PORTMODE_GMII;
2386 	else
2387 		val |= BGE_PORTMODE_MII;
2388 
2389 	/* Allow APE to send/receive frames. */
2390 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
2391 		val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
2392 
2393 	CSR_WRITE_4(sc, BGE_MAC_MODE, val);
2394 	DELAY(40);
2395 
2396 	/* Set misc. local control, enable interrupts on attentions */
2397 	BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
2398 
2399 #ifdef notdef
2400 	/* Assert GPIO pins for PHY reset */
2401 	BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
2402 	    BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
2403 	BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
2404 	    BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
2405 #endif
2406 
2407 	/* Turn on DMA completion state machine */
2408 	if (!(BGE_IS_5705_PLUS(sc)))
2409 		CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2410 
2411 	val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
2412 
2413 	/* Enable host coalescing bug fix. */
2414 	if (BGE_IS_5755_PLUS(sc))
2415 		val |= BGE_WDMAMODE_STATUS_TAG_FIX;
2416 
2417 	/* Request larger DMA burst size to get better performance. */
2418 	if (sc->bge_asicrev == BGE_ASICREV_BCM5785)
2419 		val |= BGE_WDMAMODE_BURST_ALL_DATA;
2420 
2421 	/* Turn on write DMA state machine */
2422 	CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
2423 	DELAY(40);
2424 
2425 	/* Turn on read DMA state machine */
2426 	val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
2427 
2428 	if (sc->bge_asicrev == BGE_ASICREV_BCM5717)
2429 		val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
2430 
2431 	if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2432 	    sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2433 	    sc->bge_asicrev == BGE_ASICREV_BCM57780)
2434 		val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
2435 		    BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
2436 		    BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
2437 	if (sc->bge_flags & BGE_FLAG_PCIE)
2438 		val |= BGE_RDMAMODE_FIFO_LONG_BURST;
2439 	if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2440 		val |= BGE_RDMAMODE_TSO4_ENABLE;
2441 		if (sc->bge_flags & BGE_FLAG_TSO3 ||
2442 		    sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2443 		    sc->bge_asicrev == BGE_ASICREV_BCM57780)
2444 			val |= BGE_RDMAMODE_TSO6_ENABLE;
2445 	}
2446 
2447 	if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2448 	    sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2449 		val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
2450 			BGE_RDMAMODE_H2BNC_VLAN_DET;
2451 		/*
2452 		 * Allow multiple outstanding read requests from
2453 		 * non-LSO read DMA engine.
2454 		 */
2455 		val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
2456 	}
2457 
2458 	if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2459 	    sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2460 	    sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2461 	    sc->bge_asicrev == BGE_ASICREV_BCM57780 ||
2462 	    BGE_IS_5717_PLUS(sc) || BGE_IS_57765_PLUS(sc)) {
2463 		if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
2464 			rdmareg = BGE_RDMA_RSRVCTRL_REG2;
2465 		else
2466 			rdmareg = BGE_RDMA_RSRVCTRL;
2467 		dmactl = CSR_READ_4(sc, rdmareg);
2468 		/*
2469 		 * Adjust tx margin to prevent TX data corruption and
2470 		 * fix internal FIFO overflow.
2471 		 */
2472 		if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 ||
2473 		    sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2474 			dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
2475 			    BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
2476 			    BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
2477 			dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
2478 			    BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
2479 			    BGE_RDMA_RSRVCTRL_TXMRGN_320B;
2480 		}
2481 		/*
2482 		 * Enable fix for read DMA FIFO overruns.
2483 		 * The fix is to limit the number of RX BDs
2484 		 * the hardware would fetch at a fime.
2485 		 */
2486 		CSR_WRITE_4(sc, rdmareg, dmactl |
2487 		    BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
2488 	}
2489 
2490 	if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2491 		CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2492 		    CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2493 		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2494 		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2495 	} else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2496 		/*
2497 		 * Allow 4KB burst length reads for non-LSO frames.
2498 		 * Enable 512B burst length reads for buffer descriptors.
2499 		 */
2500 		CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2501 		    CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2502 		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
2503 		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2504 	} else if (sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2505 		CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2,
2506 		    CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) |
2507 		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2508 		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2509 	}
2510 
2511 	CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
2512 	DELAY(40);
2513 
2514 	if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
2515 		for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) {
2516 			val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4);
2517 			if ((val & 0xFFFF) > BGE_FRAMELEN)
2518 				break;
2519 			if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN)
2520 				break;
2521 		}
2522 		if (i != BGE_NUM_RDMA_CHANNELS / 2) {
2523 			val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
2524 			if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2525 				val |= BGE_RDMA_TX_LENGTH_WA_5719;
2526 			else
2527 				val |= BGE_RDMA_TX_LENGTH_WA_5720;
2528 			CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
2529 		}
2530 	}
2531 
2532 	/* Turn on RX data completion state machine */
2533 	CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2534 
2535 	/* Turn on RX BD initiator state machine */
2536 	CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2537 
2538 	/* Turn on RX data and RX BD initiator state machine */
2539 	CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
2540 
2541 	/* Turn on Mbuf cluster free state machine */
2542 	if (!(BGE_IS_5705_PLUS(sc)))
2543 		CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2544 
2545 	/* Turn on send BD completion state machine */
2546 	CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2547 
2548 	/* Turn on send data completion state machine */
2549 	val = BGE_SDCMODE_ENABLE;
2550 	if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
2551 		val |= BGE_SDCMODE_CDELAY;
2552 	CSR_WRITE_4(sc, BGE_SDC_MODE, val);
2553 
2554 	/* Turn on send data initiator state machine */
2555 	if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3))
2556 		CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
2557 		    BGE_SDIMODE_HW_LSO_PRE_DMA);
2558 	else
2559 		CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2560 
2561 	/* Turn on send BD initiator state machine */
2562 	CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2563 
2564 	/* Turn on send BD selector state machine */
2565 	CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2566 
2567 	CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
2568 	CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
2569 	    BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
2570 
2571 	/* ack/clear link change events */
2572 	CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2573 	    BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2574 	    BGE_MACSTAT_LINK_CHANGED);
2575 	CSR_WRITE_4(sc, BGE_MI_STS, 0);
2576 
2577 	/*
2578 	 * Enable attention when the link has changed state for
2579 	 * devices that use auto polling.
2580 	 */
2581 	if (sc->bge_flags & BGE_FLAG_TBI) {
2582 		CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
2583 	} else {
2584 		if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2585 			CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
2586 			DELAY(80);
2587 		}
2588 		if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2589 		    sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
2590 			CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2591 			    BGE_EVTENB_MI_INTERRUPT);
2592 	}
2593 
2594 	/*
2595 	 * Clear any pending link state attention.
2596 	 * Otherwise some link state change events may be lost until attention
2597 	 * is cleared by bge_intr() -> bge_link_upd() sequence.
2598 	 * It's not necessary on newer BCM chips - perhaps enabling link
2599 	 * state change attentions implies clearing pending attention.
2600 	 */
2601 	CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2602 	    BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2603 	    BGE_MACSTAT_LINK_CHANGED);
2604 
2605 	/* Enable link state change attentions. */
2606 	BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
2607 
2608 	return (0);
2609 }
2610 
2611 static const struct bge_revision *
2612 bge_lookup_rev(uint32_t chipid)
2613 {
2614 	const struct bge_revision *br;
2615 
2616 	for (br = bge_revisions; br->br_name != NULL; br++) {
2617 		if (br->br_chipid == chipid)
2618 			return (br);
2619 	}
2620 
2621 	for (br = bge_majorrevs; br->br_name != NULL; br++) {
2622 		if (br->br_chipid == BGE_ASICREV(chipid))
2623 			return (br);
2624 	}
2625 
2626 	return (NULL);
2627 }
2628 
2629 static const struct bge_vendor *
2630 bge_lookup_vendor(uint16_t vid)
2631 {
2632 	const struct bge_vendor *v;
2633 
2634 	for (v = bge_vendors; v->v_name != NULL; v++)
2635 		if (v->v_id == vid)
2636 			return (v);
2637 
2638 	return (NULL);
2639 }
2640 
2641 static uint32_t
2642 bge_chipid(device_t dev)
2643 {
2644 	uint32_t id;
2645 
2646 	id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2647 	    BGE_PCIMISCCTL_ASICREV_SHIFT;
2648 	if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) {
2649 		/*
2650 		 * Find the ASCI revision.  Different chips use different
2651 		 * registers.
2652 		 */
2653 		switch (pci_get_device(dev)) {
2654 		case BCOM_DEVICEID_BCM5717C:
2655 			/* 5717 C0 seems to belong to 5720 line. */
2656 			id = BGE_CHIPID_BCM5720_A0;
2657 			break;
2658 		case BCOM_DEVICEID_BCM5717:
2659 		case BCOM_DEVICEID_BCM5718:
2660 		case BCOM_DEVICEID_BCM5719:
2661 		case BCOM_DEVICEID_BCM5720:
2662 		case BCOM_DEVICEID_BCM5725:
2663 		case BCOM_DEVICEID_BCM5727:
2664 		case BCOM_DEVICEID_BCM5762:
2665 		case BCOM_DEVICEID_BCM57764:
2666 		case BCOM_DEVICEID_BCM57767:
2667 		case BCOM_DEVICEID_BCM57787:
2668 			id = pci_read_config(dev,
2669 			    BGE_PCI_GEN2_PRODID_ASICREV, 4);
2670 			break;
2671 		case BCOM_DEVICEID_BCM57761:
2672 		case BCOM_DEVICEID_BCM57762:
2673 		case BCOM_DEVICEID_BCM57765:
2674 		case BCOM_DEVICEID_BCM57766:
2675 		case BCOM_DEVICEID_BCM57781:
2676 		case BCOM_DEVICEID_BCM57782:
2677 		case BCOM_DEVICEID_BCM57785:
2678 		case BCOM_DEVICEID_BCM57786:
2679 		case BCOM_DEVICEID_BCM57791:
2680 		case BCOM_DEVICEID_BCM57795:
2681 			id = pci_read_config(dev,
2682 			    BGE_PCI_GEN15_PRODID_ASICREV, 4);
2683 			break;
2684 		default:
2685 			id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
2686 		}
2687 	}
2688 	return (id);
2689 }
2690 
2691 /*
2692  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
2693  * against our list and return its name if we find a match.
2694  *
2695  * Note that since the Broadcom controller contains VPD support, we
2696  * try to get the device name string from the controller itself instead
2697  * of the compiled-in string. It guarantees we'll always announce the
2698  * right product name. We fall back to the compiled-in string when
2699  * VPD is unavailable or corrupt.
2700  */
2701 static int
2702 bge_probe(device_t dev)
2703 {
2704 	char buf[96];
2705 	char model[64];
2706 	const struct bge_revision *br;
2707 	const char *pname;
2708 	struct bge_softc *sc;
2709 	const struct bge_type *t = bge_devs;
2710 	const struct bge_vendor *v;
2711 	uint32_t id;
2712 	uint16_t did, vid;
2713 
2714 	sc = device_get_softc(dev);
2715 	sc->bge_dev = dev;
2716 	vid = pci_get_vendor(dev);
2717 	did = pci_get_device(dev);
2718 	while(t->bge_vid != 0) {
2719 		if ((vid == t->bge_vid) && (did == t->bge_did)) {
2720 			id = bge_chipid(dev);
2721 			br = bge_lookup_rev(id);
2722 			if (bge_has_eaddr(sc) &&
2723 			    pci_get_vpd_ident(dev, &pname) == 0)
2724 				snprintf(model, sizeof(model), "%s", pname);
2725 			else {
2726 				v = bge_lookup_vendor(vid);
2727 				snprintf(model, sizeof(model), "%s %s",
2728 				    v != NULL ? v->v_name : "Unknown",
2729 				    br != NULL ? br->br_name :
2730 				    "NetXtreme/NetLink Ethernet Controller");
2731 			}
2732 			snprintf(buf, sizeof(buf), "%s, %sASIC rev. %#08x",
2733 			    model, br != NULL ? "" : "unknown ", id);
2734 			device_set_desc_copy(dev, buf);
2735 			return (BUS_PROBE_DEFAULT);
2736 		}
2737 		t++;
2738 	}
2739 
2740 	return (ENXIO);
2741 }
2742 
2743 static void
2744 bge_dma_free(struct bge_softc *sc)
2745 {
2746 	int i;
2747 
2748 	/* Destroy DMA maps for RX buffers. */
2749 	for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2750 		if (sc->bge_cdata.bge_rx_std_dmamap[i])
2751 			bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2752 			    sc->bge_cdata.bge_rx_std_dmamap[i]);
2753 	}
2754 	if (sc->bge_cdata.bge_rx_std_sparemap)
2755 		bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2756 		    sc->bge_cdata.bge_rx_std_sparemap);
2757 
2758 	/* Destroy DMA maps for jumbo RX buffers. */
2759 	for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2760 		if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2761 			bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2762 			    sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2763 	}
2764 	if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2765 		bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2766 		    sc->bge_cdata.bge_rx_jumbo_sparemap);
2767 
2768 	/* Destroy DMA maps for TX buffers. */
2769 	for (i = 0; i < BGE_TX_RING_CNT; i++) {
2770 		if (sc->bge_cdata.bge_tx_dmamap[i])
2771 			bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2772 			    sc->bge_cdata.bge_tx_dmamap[i]);
2773 	}
2774 
2775 	if (sc->bge_cdata.bge_rx_mtag)
2776 		bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2777 	if (sc->bge_cdata.bge_mtag_jumbo)
2778 		bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo);
2779 	if (sc->bge_cdata.bge_tx_mtag)
2780 		bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2781 
2782 	/* Destroy standard RX ring. */
2783 	if (sc->bge_ldata.bge_rx_std_ring_paddr)
2784 		bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2785 		    sc->bge_cdata.bge_rx_std_ring_map);
2786 	if (sc->bge_ldata.bge_rx_std_ring)
2787 		bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2788 		    sc->bge_ldata.bge_rx_std_ring,
2789 		    sc->bge_cdata.bge_rx_std_ring_map);
2790 
2791 	if (sc->bge_cdata.bge_rx_std_ring_tag)
2792 		bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2793 
2794 	/* Destroy jumbo RX ring. */
2795 	if (sc->bge_ldata.bge_rx_jumbo_ring_paddr)
2796 		bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2797 		    sc->bge_cdata.bge_rx_jumbo_ring_map);
2798 
2799 	if (sc->bge_ldata.bge_rx_jumbo_ring)
2800 		bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2801 		    sc->bge_ldata.bge_rx_jumbo_ring,
2802 		    sc->bge_cdata.bge_rx_jumbo_ring_map);
2803 
2804 	if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2805 		bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2806 
2807 	/* Destroy RX return ring. */
2808 	if (sc->bge_ldata.bge_rx_return_ring_paddr)
2809 		bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2810 		    sc->bge_cdata.bge_rx_return_ring_map);
2811 
2812 	if (sc->bge_ldata.bge_rx_return_ring)
2813 		bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2814 		    sc->bge_ldata.bge_rx_return_ring,
2815 		    sc->bge_cdata.bge_rx_return_ring_map);
2816 
2817 	if (sc->bge_cdata.bge_rx_return_ring_tag)
2818 		bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2819 
2820 	/* Destroy TX ring. */
2821 	if (sc->bge_ldata.bge_tx_ring_paddr)
2822 		bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2823 		    sc->bge_cdata.bge_tx_ring_map);
2824 
2825 	if (sc->bge_ldata.bge_tx_ring)
2826 		bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2827 		    sc->bge_ldata.bge_tx_ring,
2828 		    sc->bge_cdata.bge_tx_ring_map);
2829 
2830 	if (sc->bge_cdata.bge_tx_ring_tag)
2831 		bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2832 
2833 	/* Destroy status block. */
2834 	if (sc->bge_ldata.bge_status_block_paddr)
2835 		bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2836 		    sc->bge_cdata.bge_status_map);
2837 
2838 	if (sc->bge_ldata.bge_status_block)
2839 		bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2840 		    sc->bge_ldata.bge_status_block,
2841 		    sc->bge_cdata.bge_status_map);
2842 
2843 	if (sc->bge_cdata.bge_status_tag)
2844 		bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2845 
2846 	/* Destroy statistics block. */
2847 	if (sc->bge_ldata.bge_stats_paddr)
2848 		bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2849 		    sc->bge_cdata.bge_stats_map);
2850 
2851 	if (sc->bge_ldata.bge_stats)
2852 		bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2853 		    sc->bge_ldata.bge_stats,
2854 		    sc->bge_cdata.bge_stats_map);
2855 
2856 	if (sc->bge_cdata.bge_stats_tag)
2857 		bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2858 
2859 	if (sc->bge_cdata.bge_buffer_tag)
2860 		bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag);
2861 
2862 	/* Destroy the parent tag. */
2863 	if (sc->bge_cdata.bge_parent_tag)
2864 		bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2865 }
2866 
2867 static int
2868 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment,
2869     bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
2870     bus_addr_t *paddr, const char *msg)
2871 {
2872 	struct bge_dmamap_arg ctx;
2873 	bus_addr_t lowaddr;
2874 	bus_size_t ring_end;
2875 	int error;
2876 
2877 	lowaddr = BUS_SPACE_MAXADDR;
2878 again:
2879 	error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2880 	    alignment, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2881 	    NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag);
2882 	if (error != 0) {
2883 		device_printf(sc->bge_dev,
2884 		    "could not create %s dma tag\n", msg);
2885 		return (ENOMEM);
2886 	}
2887 	/* Allocate DMA'able memory for ring. */
2888 	error = bus_dmamem_alloc(*tag, (void **)ring,
2889 	    BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
2890 	if (error != 0) {
2891 		device_printf(sc->bge_dev,
2892 		    "could not allocate DMA'able memory for %s\n", msg);
2893 		return (ENOMEM);
2894 	}
2895 	/* Load the address of the ring. */
2896 	ctx.bge_busaddr = 0;
2897 	error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr,
2898 	    &ctx, BUS_DMA_NOWAIT);
2899 	if (error != 0) {
2900 		device_printf(sc->bge_dev,
2901 		    "could not load DMA'able memory for %s\n", msg);
2902 		return (ENOMEM);
2903 	}
2904 	*paddr = ctx.bge_busaddr;
2905 	ring_end = *paddr + maxsize;
2906 	if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0 &&
2907 	    BGE_ADDR_HI(*paddr) != BGE_ADDR_HI(ring_end)) {
2908 		/*
2909 		 * 4GB boundary crossed.  Limit maximum allowable DMA
2910 		 * address space to 32bit and try again.
2911 		 */
2912 		bus_dmamap_unload(*tag, *map);
2913 		bus_dmamem_free(*tag, *ring, *map);
2914 		bus_dma_tag_destroy(*tag);
2915 		if (bootverbose)
2916 			device_printf(sc->bge_dev, "4GB boundary crossed, "
2917 			    "limit DMA address space to 32bit for %s\n", msg);
2918 		*ring = NULL;
2919 		*tag = NULL;
2920 		*map = NULL;
2921 		lowaddr = BUS_SPACE_MAXADDR_32BIT;
2922 		goto again;
2923 	}
2924 	return (0);
2925 }
2926 
2927 static int
2928 bge_dma_alloc(struct bge_softc *sc)
2929 {
2930 	bus_addr_t lowaddr;
2931 	bus_size_t boundary, sbsz, rxmaxsegsz, txsegsz, txmaxsegsz;
2932 	int i, error;
2933 
2934 	lowaddr = BUS_SPACE_MAXADDR;
2935 	if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2936 		lowaddr = BGE_DMA_MAXADDR;
2937 	/*
2938 	 * Allocate the parent bus DMA tag appropriate for PCI.
2939 	 */
2940 	error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2941 	    1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2942 	    NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2943 	    0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2944 	if (error != 0) {
2945 		device_printf(sc->bge_dev,
2946 		    "could not allocate parent dma tag\n");
2947 		return (ENOMEM);
2948 	}
2949 
2950 	/* Create tag for standard RX ring. */
2951 	error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ,
2952 	    &sc->bge_cdata.bge_rx_std_ring_tag,
2953 	    (uint8_t **)&sc->bge_ldata.bge_rx_std_ring,
2954 	    &sc->bge_cdata.bge_rx_std_ring_map,
2955 	    &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring");
2956 	if (error)
2957 		return (error);
2958 
2959 	/* Create tag for RX return ring. */
2960 	error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc),
2961 	    &sc->bge_cdata.bge_rx_return_ring_tag,
2962 	    (uint8_t **)&sc->bge_ldata.bge_rx_return_ring,
2963 	    &sc->bge_cdata.bge_rx_return_ring_map,
2964 	    &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring");
2965 	if (error)
2966 		return (error);
2967 
2968 	/* Create tag for TX ring. */
2969 	error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ,
2970 	    &sc->bge_cdata.bge_tx_ring_tag,
2971 	    (uint8_t **)&sc->bge_ldata.bge_tx_ring,
2972 	    &sc->bge_cdata.bge_tx_ring_map,
2973 	    &sc->bge_ldata.bge_tx_ring_paddr, "TX ring");
2974 	if (error)
2975 		return (error);
2976 
2977 	/*
2978 	 * Create tag for status block.
2979 	 * Because we only use single Tx/Rx/Rx return ring, use
2980 	 * minimum status block size except BCM5700 AX/BX which
2981 	 * seems to want to see full status block size regardless
2982 	 * of configured number of ring.
2983 	 */
2984 	if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2985 	    sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
2986 		sbsz = BGE_STATUS_BLK_SZ;
2987 	else
2988 		sbsz = 32;
2989 	error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz,
2990 	    &sc->bge_cdata.bge_status_tag,
2991 	    (uint8_t **)&sc->bge_ldata.bge_status_block,
2992 	    &sc->bge_cdata.bge_status_map,
2993 	    &sc->bge_ldata.bge_status_block_paddr, "status block");
2994 	if (error)
2995 		return (error);
2996 
2997 	/* Create tag for statistics block. */
2998 	error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ,
2999 	    &sc->bge_cdata.bge_stats_tag,
3000 	    (uint8_t **)&sc->bge_ldata.bge_stats,
3001 	    &sc->bge_cdata.bge_stats_map,
3002 	    &sc->bge_ldata.bge_stats_paddr, "statistics block");
3003 	if (error)
3004 		return (error);
3005 
3006 	/* Create tag for jumbo RX ring. */
3007 	if (BGE_IS_JUMBO_CAPABLE(sc)) {
3008 		error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ,
3009 		    &sc->bge_cdata.bge_rx_jumbo_ring_tag,
3010 		    (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring,
3011 		    &sc->bge_cdata.bge_rx_jumbo_ring_map,
3012 		    &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring");
3013 		if (error)
3014 			return (error);
3015 	}
3016 
3017 	/* Create parent tag for buffers. */
3018 	boundary = 0;
3019 	if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) {
3020 		boundary = BGE_DMA_BNDRY;
3021 		/*
3022 		 * XXX
3023 		 * watchdog timeout issue was observed on BCM5704 which
3024 		 * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge).
3025 		 * Both limiting DMA address space to 32bits and flushing
3026 		 * mailbox write seem to address the issue.
3027 		 */
3028 		if (sc->bge_pcixcap != 0)
3029 			lowaddr = BUS_SPACE_MAXADDR_32BIT;
3030 	}
3031 	error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
3032 	    1, boundary, lowaddr, BUS_SPACE_MAXADDR, NULL,
3033 	    NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3034 	    0, NULL, NULL, &sc->bge_cdata.bge_buffer_tag);
3035 	if (error != 0) {
3036 		device_printf(sc->bge_dev,
3037 		    "could not allocate buffer dma tag\n");
3038 		return (ENOMEM);
3039 	}
3040 	/* Create tag for Tx mbufs. */
3041 	if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
3042 		txsegsz = BGE_TSOSEG_SZ;
3043 		txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
3044 	} else {
3045 		txsegsz = MCLBYTES;
3046 		txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
3047 	}
3048 	error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1,
3049 	    0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
3050 	    txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
3051 	    &sc->bge_cdata.bge_tx_mtag);
3052 
3053 	if (error) {
3054 		device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
3055 		return (ENOMEM);
3056 	}
3057 
3058 	/* Create tag for Rx mbufs. */
3059 	if (sc->bge_flags & BGE_FLAG_JUMBO_STD)
3060 		rxmaxsegsz = MJUM9BYTES;
3061 	else
3062 		rxmaxsegsz = MCLBYTES;
3063 	error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0,
3064 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1,
3065 	    rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
3066 
3067 	if (error) {
3068 		device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
3069 		return (ENOMEM);
3070 	}
3071 
3072 	/* Create DMA maps for RX buffers. */
3073 	error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3074 	    &sc->bge_cdata.bge_rx_std_sparemap);
3075 	if (error) {
3076 		device_printf(sc->bge_dev,
3077 		    "can't create spare DMA map for RX\n");
3078 		return (ENOMEM);
3079 	}
3080 	for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3081 		error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3082 			    &sc->bge_cdata.bge_rx_std_dmamap[i]);
3083 		if (error) {
3084 			device_printf(sc->bge_dev,
3085 			    "can't create DMA map for RX\n");
3086 			return (ENOMEM);
3087 		}
3088 	}
3089 
3090 	/* Create DMA maps for TX buffers. */
3091 	for (i = 0; i < BGE_TX_RING_CNT; i++) {
3092 		error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
3093 			    &sc->bge_cdata.bge_tx_dmamap[i]);
3094 		if (error) {
3095 			device_printf(sc->bge_dev,
3096 			    "can't create DMA map for TX\n");
3097 			return (ENOMEM);
3098 		}
3099 	}
3100 
3101 	/* Create tags for jumbo RX buffers. */
3102 	if (BGE_IS_JUMBO_CAPABLE(sc)) {
3103 		error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag,
3104 		    1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
3105 		    NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
3106 		    0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
3107 		if (error) {
3108 			device_printf(sc->bge_dev,
3109 			    "could not allocate jumbo dma tag\n");
3110 			return (ENOMEM);
3111 		}
3112 		/* Create DMA maps for jumbo RX buffers. */
3113 		error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3114 		    0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
3115 		if (error) {
3116 			device_printf(sc->bge_dev,
3117 			    "can't create spare DMA map for jumbo RX\n");
3118 			return (ENOMEM);
3119 		}
3120 		for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
3121 			error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3122 				    0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
3123 			if (error) {
3124 				device_printf(sc->bge_dev,
3125 				    "can't create DMA map for jumbo RX\n");
3126 				return (ENOMEM);
3127 			}
3128 		}
3129 	}
3130 
3131 	return (0);
3132 }
3133 
3134 /*
3135  * Return true if this device has more than one port.
3136  */
3137 static int
3138 bge_has_multiple_ports(struct bge_softc *sc)
3139 {
3140 	device_t dev = sc->bge_dev;
3141 	u_int b, d, f, fscan, s;
3142 
3143 	d = pci_get_domain(dev);
3144 	b = pci_get_bus(dev);
3145 	s = pci_get_slot(dev);
3146 	f = pci_get_function(dev);
3147 	for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
3148 		if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
3149 			return (1);
3150 	return (0);
3151 }
3152 
3153 /*
3154  * Return true if MSI can be used with this device.
3155  */
3156 static int
3157 bge_can_use_msi(struct bge_softc *sc)
3158 {
3159 	int can_use_msi = 0;
3160 
3161 	if (sc->bge_msi == 0)
3162 		return (0);
3163 
3164 	/* Disable MSI for polling(4). */
3165 #ifdef DEVICE_POLLING
3166 	return (0);
3167 #endif
3168 	switch (sc->bge_asicrev) {
3169 	case BGE_ASICREV_BCM5714_A0:
3170 	case BGE_ASICREV_BCM5714:
3171 		/*
3172 		 * Apparently, MSI doesn't work when these chips are
3173 		 * configured in single-port mode.
3174 		 */
3175 		if (bge_has_multiple_ports(sc))
3176 			can_use_msi = 1;
3177 		break;
3178 	case BGE_ASICREV_BCM5750:
3179 		if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
3180 		    sc->bge_chiprev != BGE_CHIPREV_5750_BX)
3181 			can_use_msi = 1;
3182 		break;
3183 	case BGE_ASICREV_BCM5784:
3184 		/*
3185 		 * Prevent infinite "watchdog timeout" errors
3186 		 * in some MacBook Pro and make it work out-of-the-box.
3187 		 */
3188 		if (sc->bge_chiprev == BGE_CHIPREV_5784_AX)
3189 			break;
3190 		/* FALLTHROUGH */
3191 	default:
3192 		if (BGE_IS_575X_PLUS(sc))
3193 			can_use_msi = 1;
3194 	}
3195 	return (can_use_msi);
3196 }
3197 
3198 static int
3199 bge_mbox_reorder(struct bge_softc *sc)
3200 {
3201 	/* Lists of PCI bridges that are known to reorder mailbox writes. */
3202 	static const struct mbox_reorder {
3203 		const uint16_t vendor;
3204 		const uint16_t device;
3205 		const char *desc;
3206 	} mbox_reorder_lists[] = {
3207 		{ 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" },
3208 	};
3209 	devclass_t pci, pcib;
3210 	device_t bus, dev;
3211 	int i;
3212 
3213 	pci = devclass_find("pci");
3214 	pcib = devclass_find("pcib");
3215 	dev = sc->bge_dev;
3216 	bus = device_get_parent(dev);
3217 	for (;;) {
3218 		dev = device_get_parent(bus);
3219 		bus = device_get_parent(dev);
3220 		if (device_get_devclass(dev) != pcib)
3221 			break;
3222 		if (device_get_devclass(bus) != pci)
3223 			break;
3224 		for (i = 0; i < nitems(mbox_reorder_lists); i++) {
3225 			if (pci_get_vendor(dev) ==
3226 			    mbox_reorder_lists[i].vendor &&
3227 			    pci_get_device(dev) ==
3228 			    mbox_reorder_lists[i].device) {
3229 				device_printf(sc->bge_dev,
3230 				    "enabling MBOX workaround for %s\n",
3231 				    mbox_reorder_lists[i].desc);
3232 				return (1);
3233 			}
3234 		}
3235 	}
3236 	return (0);
3237 }
3238 
3239 static void
3240 bge_devinfo(struct bge_softc *sc)
3241 {
3242 	uint32_t cfg, clk;
3243 
3244 	device_printf(sc->bge_dev,
3245 	    "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ",
3246 	    sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev);
3247 	if (sc->bge_flags & BGE_FLAG_PCIE)
3248 		printf("PCI-E\n");
3249 	else if (sc->bge_flags & BGE_FLAG_PCIX) {
3250 		printf("PCI-X ");
3251 		cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3252 		if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE)
3253 			clk = 133;
3254 		else {
3255 			clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
3256 			switch (clk) {
3257 			case 0:
3258 				clk = 33;
3259 				break;
3260 			case 2:
3261 				clk = 50;
3262 				break;
3263 			case 4:
3264 				clk = 66;
3265 				break;
3266 			case 6:
3267 				clk = 100;
3268 				break;
3269 			case 7:
3270 				clk = 133;
3271 				break;
3272 			}
3273 		}
3274 		printf("%u MHz\n", clk);
3275 	} else {
3276 		if (sc->bge_pcixcap != 0)
3277 			printf("PCI on PCI-X ");
3278 		else
3279 			printf("PCI ");
3280 		cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
3281 		if (cfg & BGE_PCISTATE_PCI_BUSSPEED)
3282 			clk = 66;
3283 		else
3284 			clk = 33;
3285 		if (cfg & BGE_PCISTATE_32BIT_BUS)
3286 			printf("%u MHz; 32bit\n", clk);
3287 		else
3288 			printf("%u MHz; 64bit\n", clk);
3289 	}
3290 }
3291 
3292 static int
3293 bge_attach(device_t dev)
3294 {
3295 	if_t ifp;
3296 	struct bge_softc *sc;
3297 	uint32_t hwcfg = 0, misccfg, pcistate;
3298 	u_char eaddr[ETHER_ADDR_LEN];
3299 	int capmask, error, reg, rid, trys;
3300 
3301 	sc = device_get_softc(dev);
3302 	sc->bge_dev = dev;
3303 
3304 	BGE_LOCK_INIT(sc, device_get_nameunit(dev));
3305 	NET_TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
3306 	callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
3307 
3308 	pci_enable_busmaster(dev);
3309 
3310 	/*
3311 	 * Allocate control/status registers.
3312 	 */
3313 	rid = PCIR_BAR(0);
3314 	sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3315 	    RF_ACTIVE);
3316 
3317 	if (sc->bge_res == NULL) {
3318 		device_printf (sc->bge_dev, "couldn't map BAR0 memory\n");
3319 		error = ENXIO;
3320 		goto fail;
3321 	}
3322 
3323 	/* Save various chip information. */
3324 	sc->bge_func_addr = pci_get_function(dev);
3325 	sc->bge_chipid = bge_chipid(dev);
3326 	sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
3327 	sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
3328 
3329 	/* Set default PHY address. */
3330 	sc->bge_phy_addr = 1;
3331 	 /*
3332 	  * PHY address mapping for various devices.
3333 	  *
3334 	  *          | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
3335 	  * ---------+-------+-------+-------+-------+
3336 	  * BCM57XX  |   1   |   X   |   X   |   X   |
3337 	  * BCM5704  |   1   |   X   |   1   |   X   |
3338 	  * BCM5717  |   1   |   8   |   2   |   9   |
3339 	  * BCM5719  |   1   |   8   |   2   |   9   |
3340 	  * BCM5720  |   1   |   8   |   2   |   9   |
3341 	  *
3342 	  *          | F2 Cu | F2 Sr | F3 Cu | F3 Sr |
3343 	  * ---------+-------+-------+-------+-------+
3344 	  * BCM57XX  |   X   |   X   |   X   |   X   |
3345 	  * BCM5704  |   X   |   X   |   X   |   X   |
3346 	  * BCM5717  |   X   |   X   |   X   |   X   |
3347 	  * BCM5719  |   3   |   10  |   4   |   11  |
3348 	  * BCM5720  |   X   |   X   |   X   |   X   |
3349 	  *
3350 	  * Other addresses may respond but they are not
3351 	  * IEEE compliant PHYs and should be ignored.
3352 	  */
3353 	if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
3354 	    sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3355 	    sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3356 		if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) {
3357 			if (CSR_READ_4(sc, BGE_SGDIG_STS) &
3358 			    BGE_SGDIGSTS_IS_SERDES)
3359 				sc->bge_phy_addr = sc->bge_func_addr + 8;
3360 			else
3361 				sc->bge_phy_addr = sc->bge_func_addr + 1;
3362 		} else {
3363 			if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
3364 			    BGE_CPMU_PHY_STRAP_IS_SERDES)
3365 				sc->bge_phy_addr = sc->bge_func_addr + 8;
3366 			else
3367 				sc->bge_phy_addr = sc->bge_func_addr + 1;
3368 		}
3369 	}
3370 
3371 	if (bge_has_eaddr(sc))
3372 		sc->bge_flags |= BGE_FLAG_EADDR;
3373 
3374 	/* Save chipset family. */
3375 	switch (sc->bge_asicrev) {
3376 	case BGE_ASICREV_BCM5762:
3377 	case BGE_ASICREV_BCM57765:
3378 	case BGE_ASICREV_BCM57766:
3379 		sc->bge_flags |= BGE_FLAG_57765_PLUS;
3380 		/* FALLTHROUGH */
3381 	case BGE_ASICREV_BCM5717:
3382 	case BGE_ASICREV_BCM5719:
3383 	case BGE_ASICREV_BCM5720:
3384 		sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS |
3385 		    BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO |
3386 		    BGE_FLAG_JUMBO_FRAME;
3387 		if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3388 		    sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3389 			/*
3390 			 * Enable work around for DMA engine miscalculation
3391 			 * of TXMBUF available space.
3392 			 */
3393 			sc->bge_flags |= BGE_FLAG_RDMA_BUG;
3394 			if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3395 			    sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3396 				/* Jumbo frame on BCM5719 A0 does not work. */
3397 				sc->bge_flags &= ~BGE_FLAG_JUMBO;
3398 			}
3399 		}
3400 		break;
3401 	case BGE_ASICREV_BCM5755:
3402 	case BGE_ASICREV_BCM5761:
3403 	case BGE_ASICREV_BCM5784:
3404 	case BGE_ASICREV_BCM5785:
3405 	case BGE_ASICREV_BCM5787:
3406 	case BGE_ASICREV_BCM57780:
3407 		sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
3408 		    BGE_FLAG_5705_PLUS;
3409 		break;
3410 	case BGE_ASICREV_BCM5700:
3411 	case BGE_ASICREV_BCM5701:
3412 	case BGE_ASICREV_BCM5703:
3413 	case BGE_ASICREV_BCM5704:
3414 		sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
3415 		break;
3416 	case BGE_ASICREV_BCM5714_A0:
3417 	case BGE_ASICREV_BCM5780:
3418 	case BGE_ASICREV_BCM5714:
3419 		sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD;
3420 		/* FALLTHROUGH */
3421 	case BGE_ASICREV_BCM5750:
3422 	case BGE_ASICREV_BCM5752:
3423 	case BGE_ASICREV_BCM5906:
3424 		sc->bge_flags |= BGE_FLAG_575X_PLUS;
3425 		/* FALLTHROUGH */
3426 	case BGE_ASICREV_BCM5705:
3427 		sc->bge_flags |= BGE_FLAG_5705_PLUS;
3428 		break;
3429 	}
3430 
3431 	/* Identify chips with APE processor. */
3432 	switch (sc->bge_asicrev) {
3433 	case BGE_ASICREV_BCM5717:
3434 	case BGE_ASICREV_BCM5719:
3435 	case BGE_ASICREV_BCM5720:
3436 	case BGE_ASICREV_BCM5761:
3437 	case BGE_ASICREV_BCM5762:
3438 		sc->bge_flags |= BGE_FLAG_APE;
3439 		break;
3440 	}
3441 
3442 	/* Chips with APE need BAR2 access for APE registers/memory. */
3443 	if ((sc->bge_flags & BGE_FLAG_APE) != 0) {
3444 		rid = PCIR_BAR(2);
3445 		sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3446 		    RF_ACTIVE);
3447 		if (sc->bge_res2 == NULL) {
3448 			device_printf (sc->bge_dev,
3449 			    "couldn't map BAR2 memory\n");
3450 			error = ENXIO;
3451 			goto fail;
3452 		}
3453 
3454 		/* Enable APE register/memory access by host driver. */
3455 		pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3456 		pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
3457 		    BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
3458 		    BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
3459 		pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4);
3460 
3461 		bge_ape_lock_init(sc);
3462 		bge_ape_read_fw_ver(sc);
3463 	}
3464 
3465 	/* Add SYSCTLs, requires the chipset family to be set. */
3466 	bge_add_sysctls(sc);
3467 
3468 	/* Identify the chips that use an CPMU. */
3469 	if (BGE_IS_5717_PLUS(sc) ||
3470 	    sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3471 	    sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3472 	    sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
3473 	    sc->bge_asicrev == BGE_ASICREV_BCM57780)
3474 		sc->bge_flags |= BGE_FLAG_CPMU_PRESENT;
3475 	if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0)
3476 		sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
3477 	else
3478 		sc->bge_mi_mode = BGE_MIMODE_BASE;
3479 	/* Enable auto polling for BCM570[0-5]. */
3480 	if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705)
3481 		sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
3482 
3483 	/*
3484 	 * All Broadcom controllers have 4GB boundary DMA bug.
3485 	 * Whenever an address crosses a multiple of the 4GB boundary
3486 	 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3487 	 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3488 	 * state machine will lockup and cause the device to hang.
3489 	 */
3490 	sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
3491 
3492 	/* BCM5755 or higher and BCM5906 have short DMA bug. */
3493 	if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3494 		sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG;
3495 
3496 	/*
3497 	 * BCM5719 cannot handle DMA requests for DMA segments that
3498 	 * have larger than 4KB in size.  However the maximum DMA
3499 	 * segment size created in DMA tag is 4KB for TSO, so we
3500 	 * wouldn't encounter the issue here.
3501 	 */
3502 	if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
3503 		sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG;
3504 
3505 	misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3506 	if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
3507 		if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
3508 		    misccfg == BGE_MISCCFG_BOARD_ID_5788M)
3509 			sc->bge_flags |= BGE_FLAG_5788;
3510 	}
3511 
3512 	capmask = BMSR_DEFCAPMASK;
3513 	if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
3514 	    (misccfg == 0x4000 || misccfg == 0x8000)) ||
3515 	    (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3516 	    pci_get_vendor(dev) == BCOM_VENDORID &&
3517 	    (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 ||
3518 	    pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 ||
3519 	    pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) ||
3520 	    (pci_get_vendor(dev) == BCOM_VENDORID &&
3521 	    (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F ||
3522 	    pci_get_device(dev) == BCOM_DEVICEID_BCM5753F ||
3523 	    pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) ||
3524 	    pci_get_device(dev) == BCOM_DEVICEID_BCM57790 ||
3525 	    pci_get_device(dev) == BCOM_DEVICEID_BCM57791 ||
3526 	    pci_get_device(dev) == BCOM_DEVICEID_BCM57795 ||
3527 	    sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3528 		/* These chips are 10/100 only. */
3529 		capmask &= ~BMSR_EXTSTAT;
3530 		sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3531 	}
3532 
3533 	/*
3534 	 * Some controllers seem to require a special firmware to use
3535 	 * TSO. But the firmware is not available to FreeBSD and Linux
3536 	 * claims that the TSO performed by the firmware is slower than
3537 	 * hardware based TSO. Moreover the firmware based TSO has one
3538 	 * known bug which can't handle TSO if Ethernet header + IP/TCP
3539 	 * header is greater than 80 bytes. A workaround for the TSO
3540 	 * bug exist but it seems it's too expensive than not using
3541 	 * TSO at all. Some hardwares also have the TSO bug so limit
3542 	 * the TSO to the controllers that are not affected TSO issues
3543 	 * (e.g. 5755 or higher).
3544 	 */
3545 	if (BGE_IS_5717_PLUS(sc)) {
3546 		/* BCM5717 requires different TSO configuration. */
3547 		sc->bge_flags |= BGE_FLAG_TSO3;
3548 		if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3549 		    sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3550 			/* TSO on BCM5719 A0 does not work. */
3551 			sc->bge_flags &= ~BGE_FLAG_TSO3;
3552 		}
3553 	} else if (BGE_IS_5755_PLUS(sc)) {
3554 		/*
3555 		 * BCM5754 and BCM5787 shares the same ASIC id so
3556 		 * explicit device id check is required.
3557 		 * Due to unknown reason TSO does not work on BCM5755M.
3558 		 */
3559 		if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
3560 		    pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
3561 		    pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)
3562 			sc->bge_flags |= BGE_FLAG_TSO;
3563 	}
3564 
3565 	/*
3566 	 * Check if this is a PCI-X or PCI Express device.
3567 	 */
3568 	if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {
3569 		/*
3570 		 * Found a PCI Express capabilities register, this
3571 		 * must be a PCI Express device.
3572 		 */
3573 		sc->bge_flags |= BGE_FLAG_PCIE;
3574 		sc->bge_expcap = reg;
3575 		/* Extract supported maximum payload size. */
3576 		sc->bge_mps = pci_read_config(dev, sc->bge_expcap +
3577 		    PCIER_DEVICE_CAP, 2);
3578 		sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD);
3579 		if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3580 		    sc->bge_asicrev == BGE_ASICREV_BCM5720)
3581 			sc->bge_expmrq = 2048;
3582 		else
3583 			sc->bge_expmrq = 4096;
3584 		pci_set_max_read_req(dev, sc->bge_expmrq);
3585 	} else {
3586 		/*
3587 		 * Check if the device is in PCI-X Mode.
3588 		 * (This bit is not valid on PCI Express controllers.)
3589 		 */
3590 		if (pci_find_cap(dev, PCIY_PCIX, &reg) == 0)
3591 			sc->bge_pcixcap = reg;
3592 		if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
3593 		    BGE_PCISTATE_PCI_BUSMODE) == 0)
3594 			sc->bge_flags |= BGE_FLAG_PCIX;
3595 	}
3596 
3597 	/*
3598 	 * The 40bit DMA bug applies to the 5714/5715 controllers and is
3599 	 * not actually a MAC controller bug but an issue with the embedded
3600 	 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
3601 	 */
3602 	if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
3603 		sc->bge_flags |= BGE_FLAG_40BIT_BUG;
3604 	/*
3605 	 * Some PCI-X bridges are known to trigger write reordering to
3606 	 * the mailbox registers. Typical phenomena is watchdog timeouts
3607 	 * caused by out-of-order TX completions.  Enable workaround for
3608 	 * PCI-X devices that live behind these bridges.
3609 	 * Note, PCI-X controllers can run in PCI mode so we can't use
3610 	 * BGE_FLAG_PCIX flag to detect PCI-X controllers.
3611 	 */
3612 	if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0)
3613 		sc->bge_flags |= BGE_FLAG_MBOX_REORDER;
3614 	/*
3615 	 * Allocate the interrupt, using MSI if possible.  These devices
3616 	 * support 8 MSI messages, but only the first one is used in
3617 	 * normal operation.
3618 	 */
3619 	rid = 0;
3620 	if (pci_find_cap(sc->bge_dev, PCIY_MSI, &reg) == 0) {
3621 		sc->bge_msicap = reg;
3622 		reg = 1;
3623 		if (bge_can_use_msi(sc) && pci_alloc_msi(dev, &reg) == 0) {
3624 			rid = 1;
3625 			sc->bge_flags |= BGE_FLAG_MSI;
3626 		}
3627 	}
3628 
3629 	/*
3630 	 * All controllers except BCM5700 supports tagged status but
3631 	 * we use tagged status only for MSI case on BCM5717. Otherwise
3632 	 * MSI on BCM5717 does not work.
3633 	 */
3634 #ifndef DEVICE_POLLING
3635 	if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc))
3636 		sc->bge_flags |= BGE_FLAG_TAGGED_STATUS;
3637 #endif
3638 
3639 	sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
3640 	    RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
3641 
3642 	if (sc->bge_irq == NULL) {
3643 		device_printf(sc->bge_dev, "couldn't map interrupt\n");
3644 		error = ENXIO;
3645 		goto fail;
3646 	}
3647 
3648 	bge_devinfo(sc);
3649 
3650 	sc->bge_asf_mode = 0;
3651 	/* No ASF if APE present. */
3652 	if ((sc->bge_flags & BGE_FLAG_APE) == 0) {
3653 		if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
3654 		    BGE_SRAM_DATA_SIG_MAGIC)) {
3655 			if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) &
3656 			    BGE_HWCFG_ASF) {
3657 				sc->bge_asf_mode |= ASF_ENABLE;
3658 				sc->bge_asf_mode |= ASF_STACKUP;
3659 				if (BGE_IS_575X_PLUS(sc))
3660 					sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
3661 			}
3662 		}
3663 	}
3664 
3665 	bge_stop_fw(sc);
3666 	bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
3667 	if (bge_reset(sc)) {
3668 		device_printf(sc->bge_dev, "chip reset failed\n");
3669 		error = ENXIO;
3670 		goto fail;
3671 	}
3672 
3673 	bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
3674 	bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
3675 
3676 	if (bge_chipinit(sc)) {
3677 		device_printf(sc->bge_dev, "chip initialization failed\n");
3678 		error = ENXIO;
3679 		goto fail;
3680 	}
3681 
3682 	error = bge_get_eaddr(sc, eaddr);
3683 	if (error) {
3684 		device_printf(sc->bge_dev,
3685 		    "failed to read station address\n");
3686 		error = ENXIO;
3687 		goto fail;
3688 	}
3689 
3690 	/* 5705 limits RX return ring to 512 entries. */
3691 	if (BGE_IS_5717_PLUS(sc))
3692 		sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3693 	else if (BGE_IS_5705_PLUS(sc))
3694 		sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
3695 	else
3696 		sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3697 
3698 	if (bge_dma_alloc(sc)) {
3699 		device_printf(sc->bge_dev,
3700 		    "failed to allocate DMA resources\n");
3701 		error = ENXIO;
3702 		goto fail;
3703 	}
3704 
3705 	/* Set default tuneable values. */
3706 	sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
3707 	sc->bge_rx_coal_ticks = 150;
3708 	sc->bge_tx_coal_ticks = 150;
3709 	sc->bge_rx_max_coal_bds = 10;
3710 	sc->bge_tx_max_coal_bds = 10;
3711 
3712 	/* Initialize checksum features to use. */
3713 	sc->bge_csum_features = BGE_CSUM_FEATURES;
3714 	if (sc->bge_forced_udpcsum != 0)
3715 		sc->bge_csum_features |= CSUM_UDP;
3716 
3717 	/* Set up ifnet structure */
3718 	ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
3719 	if (ifp == NULL) {
3720 		device_printf(sc->bge_dev, "failed to if_alloc()\n");
3721 		error = ENXIO;
3722 		goto fail;
3723 	}
3724 	if_setsoftc(ifp, sc);
3725 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
3726 	if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
3727 	if_setioctlfn(ifp, bge_ioctl);
3728 	if_setstartfn(ifp, bge_start);
3729 	if_setinitfn(ifp, bge_init);
3730 	if_setgetcounterfn(ifp, bge_get_counter);
3731 	if_setsendqlen(ifp, BGE_TX_RING_CNT - 1);
3732 	if_setsendqready(ifp);
3733 	if_sethwassist(ifp, sc->bge_csum_features);
3734 	if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
3735 	    IFCAP_VLAN_MTU);
3736 	if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) {
3737 		if_sethwassistbits(ifp, CSUM_TSO, 0);
3738 		if_setcapabilitiesbit(ifp, IFCAP_TSO4 | IFCAP_VLAN_HWTSO, 0);
3739 	}
3740 #ifdef IFCAP_VLAN_HWCSUM
3741 	if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0);
3742 #endif
3743 	if_setcapenable(ifp, if_getcapabilities(ifp));
3744 #ifdef DEVICE_POLLING
3745 	if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
3746 #endif
3747 
3748 	/*
3749 	 * 5700 B0 chips do not support checksumming correctly due
3750 	 * to hardware bugs.
3751 	 */
3752 	if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
3753 		if_setcapabilitiesbit(ifp, 0, IFCAP_HWCSUM);
3754 		if_setcapenablebit(ifp, 0, IFCAP_HWCSUM);
3755 		if_sethwassist(ifp, 0);
3756 	}
3757 
3758 	/*
3759 	 * Figure out what sort of media we have by checking the
3760 	 * hardware config word in the first 32k of NIC internal memory,
3761 	 * or fall back to examining the EEPROM if necessary.
3762 	 * Note: on some BCM5700 cards, this value appears to be unset.
3763 	 * If that's the case, we have to rely on identifying the NIC
3764 	 * by its PCI subsystem ID, as we do below for the SysKonnect
3765 	 * SK-9D41.
3766 	 */
3767 	if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC)
3768 		hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
3769 	else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
3770 	    (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3771 		if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
3772 		    sizeof(hwcfg))) {
3773 			device_printf(sc->bge_dev, "failed to read EEPROM\n");
3774 			error = ENXIO;
3775 			goto fail;
3776 		}
3777 		hwcfg = ntohl(hwcfg);
3778 	}
3779 
3780 	/* The SysKonnect SK-9D41 is a 1000baseSX card. */
3781 	if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
3782 	    SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
3783 		if (BGE_IS_5705_PLUS(sc)) {
3784 			sc->bge_flags |= BGE_FLAG_MII_SERDES;
3785 			sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3786 		} else
3787 			sc->bge_flags |= BGE_FLAG_TBI;
3788 	}
3789 
3790 	/* Set various PHY bug flags. */
3791 	if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
3792 	    sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
3793 		sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
3794 	if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
3795 	    sc->bge_chiprev == BGE_CHIPREV_5704_AX)
3796 		sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
3797 	if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
3798 		sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
3799 	if (pci_get_subvendor(dev) == DELL_VENDORID)
3800 		sc->bge_phy_flags |= BGE_PHY_NO_3LED;
3801 	if ((BGE_IS_5705_PLUS(sc)) &&
3802 	    sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
3803 	    sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
3804 	    sc->bge_asicrev != BGE_ASICREV_BCM57780 &&
3805 	    !BGE_IS_5717_PLUS(sc)) {
3806 		if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
3807 		    sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3808 		    sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3809 		    sc->bge_asicrev == BGE_ASICREV_BCM5787) {
3810 			if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
3811 			    pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
3812 				sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
3813 			if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
3814 				sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
3815 		} else
3816 			sc->bge_phy_flags |= BGE_PHY_BER_BUG;
3817 	}
3818 
3819 	/*
3820 	 * Don't enable Ethernet@WireSpeed for the 5700 or the
3821 	 * 5705 A0 and A1 chips.
3822 	 */
3823 	if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3824 	    (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3825 	    (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
3826 	    sc->bge_chipid != BGE_CHIPID_BCM5705_A1)))
3827 		sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3828 
3829 	if (sc->bge_flags & BGE_FLAG_TBI) {
3830 		ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
3831 		    bge_ifmedia_sts);
3832 		ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
3833 		ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
3834 		    0, NULL);
3835 		ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
3836 		ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
3837 		sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
3838 	} else {
3839 		/*
3840 		 * Do transceiver setup and tell the firmware the
3841 		 * driver is down so we can try to get access the
3842 		 * probe if ASF is running.  Retry a couple of times
3843 		 * if we get a conflict with the ASF firmware accessing
3844 		 * the PHY.
3845 		 */
3846 		trys = 0;
3847 		BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3848 again:
3849 		bge_asf_driver_up(sc);
3850 
3851 		error = mii_attach(dev, &sc->bge_miibus, ifp,
3852 		    (ifm_change_cb_t)bge_ifmedia_upd,
3853 		    (ifm_stat_cb_t)bge_ifmedia_sts, capmask, sc->bge_phy_addr,
3854 		    MII_OFFSET_ANY, MIIF_DOPAUSE);
3855 		if (error != 0) {
3856 			if (trys++ < 4) {
3857 				device_printf(sc->bge_dev, "Try again\n");
3858 				bge_miibus_writereg(sc->bge_dev,
3859 				    sc->bge_phy_addr, MII_BMCR, BMCR_RESET);
3860 				goto again;
3861 			}
3862 			device_printf(sc->bge_dev, "attaching PHYs failed\n");
3863 			goto fail;
3864 		}
3865 
3866 		/*
3867 		 * Now tell the firmware we are going up after probing the PHY
3868 		 */
3869 		if (sc->bge_asf_mode & ASF_STACKUP)
3870 			BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3871 	}
3872 
3873 	/*
3874 	 * When using the BCM5701 in PCI-X mode, data corruption has
3875 	 * been observed in the first few bytes of some received packets.
3876 	 * Aligning the packet buffer in memory eliminates the corruption.
3877 	 * Unfortunately, this misaligns the packet payloads.  On platforms
3878 	 * which do not support unaligned accesses, we will realign the
3879 	 * payloads by copying the received packets.
3880 	 */
3881 	if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
3882 	    sc->bge_flags & BGE_FLAG_PCIX)
3883                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
3884 
3885 	/*
3886 	 * Call MI attach routine.
3887 	 */
3888 	ether_ifattach(ifp, eaddr);
3889 
3890 	/* Tell upper layer we support long frames. */
3891 	if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
3892 
3893 	/*
3894 	 * Hookup IRQ last.
3895 	 */
3896 	if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
3897 		/* Take advantage of single-shot MSI. */
3898 		CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
3899 		    ~BGE_MSIMODE_ONE_SHOT_DISABLE);
3900 		sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
3901 		    taskqueue_thread_enqueue, &sc->bge_tq);
3902 		if (sc->bge_tq == NULL) {
3903 			device_printf(dev, "could not create taskqueue.\n");
3904 			ether_ifdetach(ifp);
3905 			error = ENOMEM;
3906 			goto fail;
3907 		}
3908 		error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET,
3909 		    "%s taskq", device_get_nameunit(sc->bge_dev));
3910 		if (error != 0) {
3911 			device_printf(dev, "could not start threads.\n");
3912 			ether_ifdetach(ifp);
3913 			goto fail;
3914 		}
3915 		error = bus_setup_intr(dev, sc->bge_irq,
3916 		    INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
3917 		    &sc->bge_intrhand);
3918 	} else
3919 		error = bus_setup_intr(dev, sc->bge_irq,
3920 		    INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
3921 		    &sc->bge_intrhand);
3922 
3923 	if (error) {
3924 		ether_ifdetach(ifp);
3925 		device_printf(sc->bge_dev, "couldn't set up irq\n");
3926 		goto fail;
3927 	}
3928 
3929 	/* Attach driver debugnet methods. */
3930 	DEBUGNET_SET(ifp, bge);
3931 
3932 fail:
3933 	if (error)
3934 		bge_detach(dev);
3935 	return (error);
3936 }
3937 
3938 static int
3939 bge_detach(device_t dev)
3940 {
3941 	struct bge_softc *sc;
3942 	if_t ifp;
3943 
3944 	sc = device_get_softc(dev);
3945 	ifp = sc->bge_ifp;
3946 
3947 #ifdef DEVICE_POLLING
3948 	if (if_getcapenable(ifp) & IFCAP_POLLING)
3949 		ether_poll_deregister(ifp);
3950 #endif
3951 
3952 	if (device_is_attached(dev)) {
3953 		ether_ifdetach(ifp);
3954 		BGE_LOCK(sc);
3955 		bge_stop(sc);
3956 		BGE_UNLOCK(sc);
3957 		callout_drain(&sc->bge_stat_ch);
3958 	}
3959 
3960 	if (sc->bge_tq)
3961 		taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
3962 
3963 	if (sc->bge_flags & BGE_FLAG_TBI)
3964 		ifmedia_removeall(&sc->bge_ifmedia);
3965 	else if (sc->bge_miibus != NULL) {
3966 		bus_generic_detach(dev);
3967 		device_delete_child(dev, sc->bge_miibus);
3968 	}
3969 
3970 	bge_release_resources(sc);
3971 
3972 	return (0);
3973 }
3974 
3975 static void
3976 bge_release_resources(struct bge_softc *sc)
3977 {
3978 	device_t dev;
3979 
3980 	dev = sc->bge_dev;
3981 
3982 	if (sc->bge_tq != NULL)
3983 		taskqueue_free(sc->bge_tq);
3984 
3985 	if (sc->bge_intrhand != NULL)
3986 		bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
3987 
3988 	if (sc->bge_irq != NULL) {
3989 		bus_release_resource(dev, SYS_RES_IRQ,
3990 		    rman_get_rid(sc->bge_irq), sc->bge_irq);
3991 		pci_release_msi(dev);
3992 	}
3993 
3994 	if (sc->bge_res != NULL)
3995 		bus_release_resource(dev, SYS_RES_MEMORY,
3996 		    rman_get_rid(sc->bge_res), sc->bge_res);
3997 
3998 	if (sc->bge_res2 != NULL)
3999 		bus_release_resource(dev, SYS_RES_MEMORY,
4000 		    rman_get_rid(sc->bge_res2), sc->bge_res2);
4001 
4002 	if (sc->bge_ifp != NULL)
4003 		if_free(sc->bge_ifp);
4004 
4005 	bge_dma_free(sc);
4006 
4007 	if (mtx_initialized(&sc->bge_mtx))	/* XXX */
4008 		BGE_LOCK_DESTROY(sc);
4009 }
4010 
4011 static int
4012 bge_reset(struct bge_softc *sc)
4013 {
4014 	device_t dev;
4015 	uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val;
4016 	void (*write_op)(struct bge_softc *, int, int);
4017 	uint16_t devctl;
4018 	int i;
4019 
4020 	dev = sc->bge_dev;
4021 
4022 	mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE;
4023 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4024 		mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
4025 	mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;
4026 
4027 	if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
4028 	    (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
4029 		if (sc->bge_flags & BGE_FLAG_PCIE)
4030 			write_op = bge_writemem_direct;
4031 		else
4032 			write_op = bge_writemem_ind;
4033 	} else
4034 		write_op = bge_writereg_ind;
4035 
4036 	if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
4037 	    sc->bge_asicrev != BGE_ASICREV_BCM5701) {
4038 		CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
4039 		for (i = 0; i < 8000; i++) {
4040 			if (CSR_READ_4(sc, BGE_NVRAM_SWARB) &
4041 			    BGE_NVRAMSWARB_GNT1)
4042 				break;
4043 			DELAY(20);
4044 		}
4045 		if (i == 8000) {
4046 			if (bootverbose)
4047 				device_printf(dev, "NVRAM lock timedout!\n");
4048 		}
4049 	}
4050 	/* Take APE lock when performing reset. */
4051 	bge_ape_lock(sc, BGE_APE_LOCK_GRC);
4052 
4053 	/* Save some important PCI state. */
4054 	cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
4055 	command = pci_read_config(dev, BGE_PCI_CMD, 4);
4056 
4057 	pci_write_config(dev, BGE_PCI_MISC_CTL,
4058 	    BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4059 	    BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4060 
4061 	/* Disable fastboot on controllers that support it. */
4062 	if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
4063 	    BGE_IS_5755_PLUS(sc)) {
4064 		if (bootverbose)
4065 			device_printf(dev, "Disabling fastboot\n");
4066 		CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
4067 	}
4068 
4069 	/*
4070 	 * Write the magic number to SRAM at offset 0xB50.
4071 	 * When firmware finishes its initialization it will
4072 	 * write ~BGE_SRAM_FW_MB_MAGIC to the same location.
4073 	 */
4074 	bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
4075 
4076 	reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
4077 
4078 	/* XXX: Broadcom Linux driver. */
4079 	if (sc->bge_flags & BGE_FLAG_PCIE) {
4080 		if (sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
4081 		    (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) {
4082 			if (CSR_READ_4(sc, 0x7E2C) == 0x60)	/* PCIE 1.0 */
4083 				CSR_WRITE_4(sc, 0x7E2C, 0x20);
4084 		}
4085 		if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
4086 			/* Prevent PCIE link training during global reset */
4087 			CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
4088 			reset |= 1 << 29;
4089 		}
4090 	}
4091 
4092 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4093 		val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4094 		CSR_WRITE_4(sc, BGE_VCPU_STATUS,
4095 		    val | BGE_VCPU_STATUS_DRV_RESET);
4096 		val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
4097 		CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
4098 		    val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
4099 	}
4100 
4101 	/*
4102 	 * Set GPHY Power Down Override to leave GPHY
4103 	 * powered up in D0 uninitialized.
4104 	 */
4105 	if (BGE_IS_5705_PLUS(sc) &&
4106 	    (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0)
4107 		reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
4108 
4109 	/* Issue global reset */
4110 	write_op(sc, BGE_MISC_CFG, reset);
4111 
4112 	if (sc->bge_flags & BGE_FLAG_PCIE)
4113 		DELAY(100 * 1000);
4114 	else
4115 		DELAY(1000);
4116 
4117 	/* XXX: Broadcom Linux driver. */
4118 	if (sc->bge_flags & BGE_FLAG_PCIE) {
4119 		if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
4120 			DELAY(500000); /* wait for link training to complete */
4121 			val = pci_read_config(dev, 0xC4, 4);
4122 			pci_write_config(dev, 0xC4, val | (1 << 15), 4);
4123 		}
4124 		devctl = pci_read_config(dev,
4125 		    sc->bge_expcap + PCIER_DEVICE_CTL, 2);
4126 		/* Clear enable no snoop and disable relaxed ordering. */
4127 		devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE |
4128 		    PCIEM_CTL_NOSNOOP_ENABLE);
4129 		pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL,
4130 		    devctl, 2);
4131 		pci_set_max_read_req(dev, sc->bge_expmrq);
4132 		/* Clear error status. */
4133 		pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA,
4134 		    PCIEM_STA_CORRECTABLE_ERROR |
4135 		    PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR |
4136 		    PCIEM_STA_UNSUPPORTED_REQ, 2);
4137 	}
4138 
4139 	/* Reset some of the PCI state that got zapped by reset. */
4140 	pci_write_config(dev, BGE_PCI_MISC_CTL,
4141 	    BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4142 	    BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4143 	val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE;
4144 	if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 &&
4145 	    (sc->bge_flags & BGE_FLAG_PCIX) != 0)
4146 		val |= BGE_PCISTATE_RETRY_SAME_DMA;
4147 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4148 		val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
4149 		    BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
4150 		    BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
4151 	pci_write_config(dev, BGE_PCI_PCISTATE, val, 4);
4152 	pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
4153 	pci_write_config(dev, BGE_PCI_CMD, command, 4);
4154 	/*
4155 	 * Disable PCI-X relaxed ordering to ensure status block update
4156 	 * comes first then packet buffer DMA. Otherwise driver may
4157 	 * read stale status block.
4158 	 */
4159 	if (sc->bge_flags & BGE_FLAG_PCIX) {
4160 		devctl = pci_read_config(dev,
4161 		    sc->bge_pcixcap + PCIXR_COMMAND, 2);
4162 		devctl &= ~PCIXM_COMMAND_ERO;
4163 		if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
4164 			devctl &= ~PCIXM_COMMAND_MAX_READ;
4165 			devctl |= PCIXM_COMMAND_MAX_READ_2048;
4166 		} else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4167 			devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
4168 			    PCIXM_COMMAND_MAX_READ);
4169 			devctl |= PCIXM_COMMAND_MAX_READ_2048;
4170 		}
4171 		pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
4172 		    devctl, 2);
4173 	}
4174 	/* Re-enable MSI, if necessary, and enable the memory arbiter. */
4175 	if (BGE_IS_5714_FAMILY(sc)) {
4176 		/* This chip disables MSI on reset. */
4177 		if (sc->bge_flags & BGE_FLAG_MSI) {
4178 			val = pci_read_config(dev,
4179 			    sc->bge_msicap + PCIR_MSI_CTRL, 2);
4180 			pci_write_config(dev,
4181 			    sc->bge_msicap + PCIR_MSI_CTRL,
4182 			    val | PCIM_MSICTRL_MSI_ENABLE, 2);
4183 			val = CSR_READ_4(sc, BGE_MSI_MODE);
4184 			CSR_WRITE_4(sc, BGE_MSI_MODE,
4185 			    val | BGE_MSIMODE_ENABLE);
4186 		}
4187 		val = CSR_READ_4(sc, BGE_MARB_MODE);
4188 		CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
4189 	} else
4190 		CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4191 
4192 	/* Fix up byte swapping. */
4193 	CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc));
4194 
4195 	val = CSR_READ_4(sc, BGE_MAC_MODE);
4196 	val = (val & ~mac_mode_mask) | mac_mode;
4197 	CSR_WRITE_4(sc, BGE_MAC_MODE, val);
4198 	DELAY(40);
4199 
4200 	bge_ape_unlock(sc, BGE_APE_LOCK_GRC);
4201 
4202 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4203 		for (i = 0; i < BGE_TIMEOUT; i++) {
4204 			val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4205 			if (val & BGE_VCPU_STATUS_INIT_DONE)
4206 				break;
4207 			DELAY(100);
4208 		}
4209 		if (i == BGE_TIMEOUT) {
4210 			device_printf(dev, "reset timed out\n");
4211 			return (1);
4212 		}
4213 	} else {
4214 		/*
4215 		 * Poll until we see the 1's complement of the magic number.
4216 		 * This indicates that the firmware initialization is complete.
4217 		 * We expect this to fail if no chip containing the Ethernet
4218 		 * address is fitted though.
4219 		 */
4220 		for (i = 0; i < BGE_TIMEOUT; i++) {
4221 			DELAY(10);
4222 			val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
4223 			if (val == ~BGE_SRAM_FW_MB_MAGIC)
4224 				break;
4225 		}
4226 
4227 		if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
4228 			device_printf(dev,
4229 			    "firmware handshake timed out, found 0x%08x\n",
4230 			    val);
4231 		/* BCM57765 A0 needs additional time before accessing. */
4232 		if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
4233 			DELAY(10 * 1000);	/* XXX */
4234 	}
4235 
4236 	/*
4237 	 * The 5704 in TBI mode apparently needs some special
4238 	 * adjustment to insure the SERDES drive level is set
4239 	 * to 1.2V.
4240 	 */
4241 	if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
4242 	    sc->bge_flags & BGE_FLAG_TBI) {
4243 		val = CSR_READ_4(sc, BGE_SERDES_CFG);
4244 		val = (val & ~0xFFF) | 0x880;
4245 		CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
4246 	}
4247 
4248 	/* XXX: Broadcom Linux driver. */
4249 	if (sc->bge_flags & BGE_FLAG_PCIE &&
4250 	    !BGE_IS_5717_PLUS(sc) &&
4251 	    sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
4252 	    sc->bge_asicrev != BGE_ASICREV_BCM5785) {
4253 		/* Enable Data FIFO protection. */
4254 		val = CSR_READ_4(sc, 0x7C00);
4255 		CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
4256 	}
4257 
4258 	if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
4259 		BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
4260 		    CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
4261 
4262 	return (0);
4263 }
4264 
4265 static __inline void
4266 bge_rxreuse_std(struct bge_softc *sc, int i)
4267 {
4268 	struct bge_rx_bd *r;
4269 
4270 	r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
4271 	r->bge_flags = BGE_RXBDFLAG_END;
4272 	r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i];
4273 	r->bge_idx = i;
4274 	BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4275 }
4276 
4277 static __inline void
4278 bge_rxreuse_jumbo(struct bge_softc *sc, int i)
4279 {
4280 	struct bge_extrx_bd *r;
4281 
4282 	r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
4283 	r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
4284 	r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0];
4285 	r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1];
4286 	r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2];
4287 	r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3];
4288 	r->bge_idx = i;
4289 	BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4290 }
4291 
4292 /*
4293  * Frame reception handling. This is called if there's a frame
4294  * on the receive return list.
4295  *
4296  * Note: we have to be able to handle two possibilities here:
4297  * 1) the frame is from the jumbo receive ring
4298  * 2) the frame is from the standard receive ring
4299  */
4300 
4301 static int
4302 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
4303 {
4304 	if_t ifp;
4305 	int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
4306 	uint16_t rx_cons;
4307 
4308 	rx_cons = sc->bge_rx_saved_considx;
4309 
4310 	/* Nothing to do. */
4311 	if (rx_cons == rx_prod)
4312 		return (rx_npkts);
4313 
4314 	ifp = sc->bge_ifp;
4315 
4316 	bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4317 	    sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
4318 	bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4319 	    sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
4320 	if (BGE_IS_JUMBO_CAPABLE(sc) &&
4321 	    if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
4322 	    ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))
4323 		bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4324 		    sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
4325 
4326 	while (rx_cons != rx_prod) {
4327 		struct bge_rx_bd	*cur_rx;
4328 		uint32_t		rxidx;
4329 		struct mbuf		*m = NULL;
4330 		uint16_t		vlan_tag = 0;
4331 		int			have_tag = 0;
4332 
4333 #ifdef DEVICE_POLLING
4334 		if (if_getcapenable(ifp) & IFCAP_POLLING) {
4335 			if (sc->rxcycles <= 0)
4336 				break;
4337 			sc->rxcycles--;
4338 		}
4339 #endif
4340 
4341 		cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
4342 
4343 		rxidx = cur_rx->bge_idx;
4344 		BGE_INC(rx_cons, sc->bge_return_ring_cnt);
4345 
4346 		if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING &&
4347 		    cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
4348 			have_tag = 1;
4349 			vlan_tag = cur_rx->bge_vlan_tag;
4350 		}
4351 
4352 		if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
4353 			jumbocnt++;
4354 			m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
4355 			if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4356 				bge_rxreuse_jumbo(sc, rxidx);
4357 				continue;
4358 			}
4359 			if (bge_newbuf_jumbo(sc, rxidx) != 0) {
4360 				bge_rxreuse_jumbo(sc, rxidx);
4361 				if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
4362 				continue;
4363 			}
4364 			BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4365 		} else {
4366 			stdcnt++;
4367 			m = sc->bge_cdata.bge_rx_std_chain[rxidx];
4368 			if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4369 				bge_rxreuse_std(sc, rxidx);
4370 				continue;
4371 			}
4372 			if (bge_newbuf_std(sc, rxidx) != 0) {
4373 				bge_rxreuse_std(sc, rxidx);
4374 				if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
4375 				continue;
4376 			}
4377 			BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4378 		}
4379 
4380 		if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
4381 #ifndef __NO_STRICT_ALIGNMENT
4382 		/*
4383 		 * For architectures with strict alignment we must make sure
4384 		 * the payload is aligned.
4385 		 */
4386 		if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
4387 			bcopy(m->m_data, m->m_data + ETHER_ALIGN,
4388 			    cur_rx->bge_len);
4389 			m->m_data += ETHER_ALIGN;
4390 		}
4391 #endif
4392 		m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
4393 		m->m_pkthdr.rcvif = ifp;
4394 
4395 		if (if_getcapenable(ifp) & IFCAP_RXCSUM)
4396 			bge_rxcsum(sc, cur_rx, m);
4397 
4398 		/*
4399 		 * If we received a packet with a vlan tag,
4400 		 * attach that information to the packet.
4401 		 */
4402 		if (have_tag) {
4403 			m->m_pkthdr.ether_vtag = vlan_tag;
4404 			m->m_flags |= M_VLANTAG;
4405 		}
4406 
4407 		if (holdlck != 0) {
4408 			BGE_UNLOCK(sc);
4409 			if_input(ifp, m);
4410 			BGE_LOCK(sc);
4411 		} else
4412 			if_input(ifp, m);
4413 		rx_npkts++;
4414 
4415 		if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4416 			return (rx_npkts);
4417 	}
4418 
4419 	bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4420 	    sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
4421 	if (stdcnt > 0)
4422 		bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4423 		    sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
4424 
4425 	if (jumbocnt > 0)
4426 		bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4427 		    sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
4428 
4429 	sc->bge_rx_saved_considx = rx_cons;
4430 	bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
4431 	if (stdcnt)
4432 		bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std +
4433 		    BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT);
4434 	if (jumbocnt)
4435 		bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo +
4436 		    BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT);
4437 #ifdef notyet
4438 	/*
4439 	 * This register wraps very quickly under heavy packet drops.
4440 	 * If you need correct statistics, you can enable this check.
4441 	 */
4442 	if (BGE_IS_5705_PLUS(sc))
4443 		if_incierrors(ifp, CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS));
4444 #endif
4445 	return (rx_npkts);
4446 }
4447 
4448 static void
4449 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m)
4450 {
4451 
4452 	if (BGE_IS_5717_PLUS(sc)) {
4453 		if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
4454 			if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4455 				m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4456 				if ((cur_rx->bge_error_flag &
4457 				    BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
4458 					m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4459 			}
4460 			if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
4461 				m->m_pkthdr.csum_data =
4462 				    cur_rx->bge_tcp_udp_csum;
4463 				m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4464 				    CSUM_PSEUDO_HDR;
4465 			}
4466 		}
4467 	} else {
4468 		if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4469 			m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4470 			if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
4471 				m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4472 		}
4473 		if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
4474 		    m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
4475 			m->m_pkthdr.csum_data =
4476 			    cur_rx->bge_tcp_udp_csum;
4477 			m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4478 			    CSUM_PSEUDO_HDR;
4479 		}
4480 	}
4481 }
4482 
4483 static void
4484 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
4485 {
4486 	struct bge_tx_bd *cur_tx;
4487 	if_t ifp;
4488 
4489 	BGE_LOCK_ASSERT(sc);
4490 
4491 	/* Nothing to do. */
4492 	if (sc->bge_tx_saved_considx == tx_cons)
4493 		return;
4494 
4495 	ifp = sc->bge_ifp;
4496 
4497 	bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4498 	    sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
4499 	/*
4500 	 * Go through our tx ring and free mbufs for those
4501 	 * frames that have been sent.
4502 	 */
4503 	while (sc->bge_tx_saved_considx != tx_cons) {
4504 		uint32_t		idx;
4505 
4506 		idx = sc->bge_tx_saved_considx;
4507 		cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
4508 		if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
4509 			if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
4510 		if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
4511 			bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
4512 			    sc->bge_cdata.bge_tx_dmamap[idx],
4513 			    BUS_DMASYNC_POSTWRITE);
4514 			bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
4515 			    sc->bge_cdata.bge_tx_dmamap[idx]);
4516 			m_freem(sc->bge_cdata.bge_tx_chain[idx]);
4517 			sc->bge_cdata.bge_tx_chain[idx] = NULL;
4518 		}
4519 		sc->bge_txcnt--;
4520 		BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
4521 	}
4522 
4523 	if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
4524 	if (sc->bge_txcnt == 0)
4525 		sc->bge_timer = 0;
4526 }
4527 
4528 #ifdef DEVICE_POLLING
4529 static int
4530 bge_poll(if_t ifp, enum poll_cmd cmd, int count)
4531 {
4532 	struct bge_softc *sc = if_getsoftc(ifp);
4533 	uint16_t rx_prod, tx_cons;
4534 	uint32_t statusword;
4535 	int rx_npkts = 0;
4536 
4537 	BGE_LOCK(sc);
4538 	if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
4539 		BGE_UNLOCK(sc);
4540 		return (rx_npkts);
4541 	}
4542 
4543 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4544 	    sc->bge_cdata.bge_status_map,
4545 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4546 	/* Fetch updates from the status block. */
4547 	rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4548 	tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4549 
4550 	statusword = sc->bge_ldata.bge_status_block->bge_status;
4551 	/* Clear the status so the next pass only sees the changes. */
4552 	sc->bge_ldata.bge_status_block->bge_status = 0;
4553 
4554 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4555 	    sc->bge_cdata.bge_status_map,
4556 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4557 
4558 	/* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
4559 	if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
4560 		sc->bge_link_evt++;
4561 
4562 	if (cmd == POLL_AND_CHECK_STATUS)
4563 		if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4564 		    sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4565 		    sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
4566 			bge_link_upd(sc);
4567 
4568 	sc->rxcycles = count;
4569 	rx_npkts = bge_rxeof(sc, rx_prod, 1);
4570 	if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
4571 		BGE_UNLOCK(sc);
4572 		return (rx_npkts);
4573 	}
4574 	bge_txeof(sc, tx_cons);
4575 	if (!if_sendq_empty(ifp))
4576 		bge_start_locked(ifp);
4577 
4578 	BGE_UNLOCK(sc);
4579 	return (rx_npkts);
4580 }
4581 #endif /* DEVICE_POLLING */
4582 
4583 static int
4584 bge_msi_intr(void *arg)
4585 {
4586 	struct bge_softc *sc;
4587 
4588 	sc = (struct bge_softc *)arg;
4589 	/*
4590 	 * This interrupt is not shared and controller already
4591 	 * disabled further interrupt.
4592 	 */
4593 	taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
4594 	return (FILTER_HANDLED);
4595 }
4596 
4597 static void
4598 bge_intr_task(void *arg, int pending)
4599 {
4600 	struct bge_softc *sc;
4601 	if_t ifp;
4602 	uint32_t status, status_tag;
4603 	uint16_t rx_prod, tx_cons;
4604 
4605 	sc = (struct bge_softc *)arg;
4606 	ifp = sc->bge_ifp;
4607 
4608 	BGE_LOCK(sc);
4609 	if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
4610 		BGE_UNLOCK(sc);
4611 		return;
4612 	}
4613 
4614 	/* Get updated status block. */
4615 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4616 	    sc->bge_cdata.bge_status_map,
4617 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4618 
4619 	/* Save producer/consumer indices. */
4620 	rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4621 	tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4622 	status = sc->bge_ldata.bge_status_block->bge_status;
4623 	status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24;
4624 	/* Dirty the status flag. */
4625 	sc->bge_ldata.bge_status_block->bge_status = 0;
4626 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4627 	    sc->bge_cdata.bge_status_map,
4628 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4629 	if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0)
4630 		status_tag = 0;
4631 
4632 	if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0)
4633 		bge_link_upd(sc);
4634 
4635 	/* Let controller work. */
4636 	bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag);
4637 
4638 	if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
4639 	    sc->bge_rx_saved_considx != rx_prod) {
4640 		/* Check RX return ring producer/consumer. */
4641 		BGE_UNLOCK(sc);
4642 		bge_rxeof(sc, rx_prod, 0);
4643 		BGE_LOCK(sc);
4644 	}
4645 	if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4646 		/* Check TX ring producer/consumer. */
4647 		bge_txeof(sc, tx_cons);
4648 		if (!if_sendq_empty(ifp))
4649 			bge_start_locked(ifp);
4650 	}
4651 	BGE_UNLOCK(sc);
4652 }
4653 
4654 static void
4655 bge_intr(void *xsc)
4656 {
4657 	struct bge_softc *sc;
4658 	if_t ifp;
4659 	uint32_t statusword;
4660 	uint16_t rx_prod, tx_cons;
4661 
4662 	sc = xsc;
4663 
4664 	BGE_LOCK(sc);
4665 
4666 	ifp = sc->bge_ifp;
4667 
4668 #ifdef DEVICE_POLLING
4669 	if (if_getcapenable(ifp) & IFCAP_POLLING) {
4670 		BGE_UNLOCK(sc);
4671 		return;
4672 	}
4673 #endif
4674 
4675 	/*
4676 	 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
4677 	 * disable interrupts by writing nonzero like we used to, since with
4678 	 * our current organization this just gives complications and
4679 	 * pessimizations for re-enabling interrupts.  We used to have races
4680 	 * instead of the necessary complications.  Disabling interrupts
4681 	 * would just reduce the chance of a status update while we are
4682 	 * running (by switching to the interrupt-mode coalescence
4683 	 * parameters), but this chance is already very low so it is more
4684 	 * efficient to get another interrupt than prevent it.
4685 	 *
4686 	 * We do the ack first to ensure another interrupt if there is a
4687 	 * status update after the ack.  We don't check for the status
4688 	 * changing later because it is more efficient to get another
4689 	 * interrupt than prevent it, not quite as above (not checking is
4690 	 * a smaller optimization than not toggling the interrupt enable,
4691 	 * since checking doesn't involve PCI accesses and toggling require
4692 	 * the status check).  So toggling would probably be a pessimization
4693 	 * even with MSI.  It would only be needed for using a task queue.
4694 	 */
4695 	bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4696 
4697 	/*
4698 	 * Do the mandatory PCI flush as well as get the link status.
4699 	 */
4700 	statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
4701 
4702 	/* Make sure the descriptor ring indexes are coherent. */
4703 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4704 	    sc->bge_cdata.bge_status_map,
4705 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4706 	rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4707 	tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4708 	sc->bge_ldata.bge_status_block->bge_status = 0;
4709 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4710 	    sc->bge_cdata.bge_status_map,
4711 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4712 
4713 	if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4714 	    sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4715 	    statusword || sc->bge_link_evt)
4716 		bge_link_upd(sc);
4717 
4718 	if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4719 		/* Check RX return ring producer/consumer. */
4720 		bge_rxeof(sc, rx_prod, 1);
4721 	}
4722 
4723 	if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4724 		/* Check TX ring producer/consumer. */
4725 		bge_txeof(sc, tx_cons);
4726 	}
4727 
4728 	if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
4729 	    !if_sendq_empty(ifp))
4730 		bge_start_locked(ifp);
4731 
4732 	BGE_UNLOCK(sc);
4733 }
4734 
4735 static void
4736 bge_asf_driver_up(struct bge_softc *sc)
4737 {
4738 	if (sc->bge_asf_mode & ASF_STACKUP) {
4739 		/* Send ASF heartbeat aprox. every 2s */
4740 		if (sc->bge_asf_count)
4741 			sc->bge_asf_count --;
4742 		else {
4743 			sc->bge_asf_count = 2;
4744 			bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
4745 			    BGE_FW_CMD_DRV_ALIVE);
4746 			bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
4747 			bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB,
4748 			    BGE_FW_HB_TIMEOUT_SEC);
4749 			CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
4750 			    CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
4751 			    BGE_RX_CPU_DRV_EVENT);
4752 		}
4753 	}
4754 }
4755 
4756 static void
4757 bge_tick(void *xsc)
4758 {
4759 	struct bge_softc *sc = xsc;
4760 	struct mii_data *mii = NULL;
4761 
4762 	BGE_LOCK_ASSERT(sc);
4763 
4764 	/* Synchronize with possible callout reset/stop. */
4765 	if (callout_pending(&sc->bge_stat_ch) ||
4766 	    !callout_active(&sc->bge_stat_ch))
4767 		return;
4768 
4769 	if (BGE_IS_5705_PLUS(sc))
4770 		bge_stats_update_regs(sc);
4771 	else
4772 		bge_stats_update(sc);
4773 
4774 	/* XXX Add APE heartbeat check here? */
4775 
4776 	if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4777 		mii = device_get_softc(sc->bge_miibus);
4778 		/*
4779 		 * Do not touch PHY if we have link up. This could break
4780 		 * IPMI/ASF mode or produce extra input errors
4781 		 * (extra errors was reported for bcm5701 & bcm5704).
4782 		 */
4783 		if (!sc->bge_link)
4784 			mii_tick(mii);
4785 	} else {
4786 		/*
4787 		 * Since in TBI mode auto-polling can't be used we should poll
4788 		 * link status manually. Here we register pending link event
4789 		 * and trigger interrupt.
4790 		 */
4791 #ifdef DEVICE_POLLING
4792 		/* In polling mode we poll link state in bge_poll(). */
4793 		if (!(if_getcapenable(sc->bge_ifp) & IFCAP_POLLING))
4794 #endif
4795 		{
4796 		sc->bge_link_evt++;
4797 		if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4798 		    sc->bge_flags & BGE_FLAG_5788)
4799 			BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4800 		else
4801 			BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4802 		}
4803 	}
4804 
4805 	bge_asf_driver_up(sc);
4806 	bge_watchdog(sc);
4807 
4808 	callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4809 }
4810 
4811 static void
4812 bge_stats_update_regs(struct bge_softc *sc)
4813 {
4814 	struct bge_mac_stats *stats;
4815 	uint32_t val;
4816 
4817 	stats = &sc->bge_mac_stats;
4818 
4819 	stats->ifHCOutOctets +=
4820 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4821 	stats->etherStatsCollisions +=
4822 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4823 	stats->outXonSent +=
4824 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4825 	stats->outXoffSent +=
4826 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4827 	stats->dot3StatsInternalMacTransmitErrors +=
4828 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4829 	stats->dot3StatsSingleCollisionFrames +=
4830 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4831 	stats->dot3StatsMultipleCollisionFrames +=
4832 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4833 	stats->dot3StatsDeferredTransmissions +=
4834 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4835 	stats->dot3StatsExcessiveCollisions +=
4836 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4837 	stats->dot3StatsLateCollisions +=
4838 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4839 	stats->ifHCOutUcastPkts +=
4840 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4841 	stats->ifHCOutMulticastPkts +=
4842 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4843 	stats->ifHCOutBroadcastPkts +=
4844 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4845 
4846 	stats->ifHCInOctets +=
4847 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4848 	stats->etherStatsFragments +=
4849 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4850 	stats->ifHCInUcastPkts +=
4851 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4852 	stats->ifHCInMulticastPkts +=
4853 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4854 	stats->ifHCInBroadcastPkts +=
4855 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4856 	stats->dot3StatsFCSErrors +=
4857 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4858 	stats->dot3StatsAlignmentErrors +=
4859 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4860 	stats->xonPauseFramesReceived +=
4861 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4862 	stats->xoffPauseFramesReceived +=
4863 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4864 	stats->macControlFramesReceived +=
4865 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4866 	stats->xoffStateEntered +=
4867 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4868 	stats->dot3StatsFramesTooLong +=
4869 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4870 	stats->etherStatsJabbers +=
4871 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4872 	stats->etherStatsUndersizePkts +=
4873 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4874 
4875 	stats->FramesDroppedDueToFilters +=
4876 	    CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4877 	stats->DmaWriteQueueFull +=
4878 	    CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4879 	stats->DmaWriteHighPriQueueFull +=
4880 	    CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4881 	stats->NoMoreRxBDs +=
4882 	    CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4883 	/*
4884 	 * XXX
4885 	 * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS
4886 	 * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0
4887 	 * includes number of unwanted multicast frames.  This comes
4888 	 * from silicon bug and known workaround to get rough(not
4889 	 * exact) counter is to enable interrupt on MBUF low water
4890 	 * attention.  This can be accomplished by setting
4891 	 * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE,
4892 	 * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and
4893 	 * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL.
4894 	 * However that change would generate more interrupts and
4895 	 * there are still possibilities of losing multiple frames
4896 	 * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling.
4897 	 * Given that the workaround still would not get correct
4898 	 * counter I don't think it's worth to implement it.  So
4899 	 * ignore reading the counter on controllers that have the
4900 	 * silicon bug.
4901 	 */
4902 	if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
4903 	    sc->bge_chipid != BGE_CHIPID_BCM5719_A0 &&
4904 	    sc->bge_chipid != BGE_CHIPID_BCM5720_A0)
4905 		stats->InputDiscards +=
4906 		    CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4907 	stats->InputErrors +=
4908 	    CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4909 	stats->RecvThresholdHit +=
4910 	    CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4911 
4912 	if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
4913 		/*
4914 		 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS
4915 		 * frames, it's safe to disable workaround for DMA engine's
4916 		 * miscalculation of TXMBUF space.
4917 		 */
4918 		if (stats->ifHCOutUcastPkts + stats->ifHCOutMulticastPkts +
4919 		    stats->ifHCOutBroadcastPkts > BGE_NUM_RDMA_CHANNELS) {
4920 			val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
4921 			if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
4922 				val &= ~BGE_RDMA_TX_LENGTH_WA_5719;
4923 			else
4924 				val &= ~BGE_RDMA_TX_LENGTH_WA_5720;
4925 			CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
4926 			sc->bge_flags &= ~BGE_FLAG_RDMA_BUG;
4927 		}
4928 	}
4929 }
4930 
4931 static void
4932 bge_stats_clear_regs(struct bge_softc *sc)
4933 {
4934 
4935 	CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4936 	CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4937 	CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4938 	CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4939 	CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4940 	CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4941 	CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4942 	CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4943 	CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4944 	CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4945 	CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4946 	CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4947 	CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4948 
4949 	CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4950 	CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4951 	CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4952 	CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4953 	CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4954 	CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4955 	CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4956 	CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4957 	CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4958 	CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4959 	CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4960 	CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4961 	CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4962 	CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4963 
4964 	CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4965 	CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4966 	CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4967 	CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4968 	CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4969 	CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4970 	CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4971 }
4972 
4973 static void
4974 bge_stats_update(struct bge_softc *sc)
4975 {
4976 	if_t ifp;
4977 	bus_size_t stats;
4978 	uint32_t cnt;	/* current register value */
4979 
4980 	ifp = sc->bge_ifp;
4981 
4982 	stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
4983 
4984 #define	READ_STAT(sc, stats, stat) \
4985 	CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
4986 
4987 	cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
4988 	if_inc_counter(ifp, IFCOUNTER_COLLISIONS, cnt - sc->bge_tx_collisions);
4989 	sc->bge_tx_collisions = cnt;
4990 
4991 	cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo);
4992 	if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_nobds);
4993 	sc->bge_rx_nobds = cnt;
4994 	cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo);
4995 	if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_inerrs);
4996 	sc->bge_rx_inerrs = cnt;
4997 	cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
4998 	if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_discards);
4999 	sc->bge_rx_discards = cnt;
5000 
5001 	cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
5002 	if_inc_counter(ifp, IFCOUNTER_OERRORS, cnt - sc->bge_tx_discards);
5003 	sc->bge_tx_discards = cnt;
5004 
5005 #undef	READ_STAT
5006 }
5007 
5008 /*
5009  * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
5010  * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
5011  * but when such padded frames employ the bge IP/TCP checksum offload,
5012  * the hardware checksum assist gives incorrect results (possibly
5013  * from incorporating its own padding into the UDP/TCP checksum; who knows).
5014  * If we pad such runts with zeros, the onboard checksum comes out correct.
5015  */
5016 static __inline int
5017 bge_cksum_pad(struct mbuf *m)
5018 {
5019 	int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
5020 	struct mbuf *last;
5021 
5022 	/* If there's only the packet-header and we can pad there, use it. */
5023 	if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
5024 	    M_TRAILINGSPACE(m) >= padlen) {
5025 		last = m;
5026 	} else {
5027 		/*
5028 		 * Walk packet chain to find last mbuf. We will either
5029 		 * pad there, or append a new mbuf and pad it.
5030 		 */
5031 		for (last = m; last->m_next != NULL; last = last->m_next);
5032 		if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
5033 			/* Allocate new empty mbuf, pad it. Compact later. */
5034 			struct mbuf *n;
5035 
5036 			MGET(n, M_NOWAIT, MT_DATA);
5037 			if (n == NULL)
5038 				return (ENOBUFS);
5039 			n->m_len = 0;
5040 			last->m_next = n;
5041 			last = n;
5042 		}
5043 	}
5044 
5045 	/* Now zero the pad area, to avoid the bge cksum-assist bug. */
5046 	memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
5047 	last->m_len += padlen;
5048 	m->m_pkthdr.len += padlen;
5049 
5050 	return (0);
5051 }
5052 
5053 static struct mbuf *
5054 bge_check_short_dma(struct mbuf *m)
5055 {
5056 	struct mbuf *n;
5057 	int found;
5058 
5059 	/*
5060 	 * If device receive two back-to-back send BDs with less than
5061 	 * or equal to 8 total bytes then the device may hang.  The two
5062 	 * back-to-back send BDs must in the same frame for this failure
5063 	 * to occur.  Scan mbuf chains and see whether two back-to-back
5064 	 * send BDs are there. If this is the case, allocate new mbuf
5065 	 * and copy the frame to workaround the silicon bug.
5066 	 */
5067 	for (n = m, found = 0; n != NULL; n = n->m_next) {
5068 		if (n->m_len < 8) {
5069 			found++;
5070 			if (found > 1)
5071 				break;
5072 			continue;
5073 		}
5074 		found = 0;
5075 	}
5076 
5077 	if (found > 1) {
5078 		n = m_defrag(m, M_NOWAIT);
5079 		if (n == NULL)
5080 			m_freem(m);
5081 	} else
5082 		n = m;
5083 	return (n);
5084 }
5085 
5086 static struct mbuf *
5087 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss,
5088     uint16_t *flags)
5089 {
5090 	struct ip *ip;
5091 	struct tcphdr *tcp;
5092 	struct mbuf *n;
5093 	uint16_t hlen;
5094 	uint32_t poff;
5095 
5096 	if (M_WRITABLE(m) == 0) {
5097 		/* Get a writable copy. */
5098 		n = m_dup(m, M_NOWAIT);
5099 		m_freem(m);
5100 		if (n == NULL)
5101 			return (NULL);
5102 		m = n;
5103 	}
5104 	m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip));
5105 	if (m == NULL)
5106 		return (NULL);
5107 	ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5108 	poff = sizeof(struct ether_header) + (ip->ip_hl << 2);
5109 	m = m_pullup(m, poff + sizeof(struct tcphdr));
5110 	if (m == NULL)
5111 		return (NULL);
5112 	tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5113 	m = m_pullup(m, poff + (tcp->th_off << 2));
5114 	if (m == NULL)
5115 		return (NULL);
5116 	/*
5117 	 * It seems controller doesn't modify IP length and TCP pseudo
5118 	 * checksum. These checksum computed by upper stack should be 0.
5119 	 */
5120 	*mss = m->m_pkthdr.tso_segsz;
5121 	ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5122 	ip->ip_sum = 0;
5123 	ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
5124 	/* Clear pseudo checksum computed by TCP stack. */
5125 	tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5126 	tcp->th_sum = 0;
5127 	/*
5128 	 * Broadcom controllers uses different descriptor format for
5129 	 * TSO depending on ASIC revision. Due to TSO-capable firmware
5130 	 * license issue and lower performance of firmware based TSO
5131 	 * we only support hardware based TSO.
5132 	 */
5133 	/* Calculate header length, incl. TCP/IP options, in 32 bit units. */
5134 	hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
5135 	if (sc->bge_flags & BGE_FLAG_TSO3) {
5136 		/*
5137 		 * For BCM5717 and newer controllers, hardware based TSO
5138 		 * uses the 14 lower bits of the bge_mss field to store the
5139 		 * MSS and the upper 2 bits to store the lowest 2 bits of
5140 		 * the IP/TCP header length.  The upper 6 bits of the header
5141 		 * length are stored in the bge_flags[14:10,4] field.  Jumbo
5142 		 * frames are supported.
5143 		 */
5144 		*mss |= ((hlen & 0x3) << 14);
5145 		*flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2);
5146 	} else {
5147 		/*
5148 		 * For BCM5755 and newer controllers, hardware based TSO uses
5149 		 * the lower 11	bits to store the MSS and the upper 5 bits to
5150 		 * store the IP/TCP header length. Jumbo frames are not
5151 		 * supported.
5152 		 */
5153 		*mss |= (hlen << 11);
5154 	}
5155 	return (m);
5156 }
5157 
5158 /*
5159  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
5160  * pointers to descriptors.
5161  */
5162 static int
5163 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
5164 {
5165 	bus_dma_segment_t	segs[BGE_NSEG_NEW];
5166 	bus_dmamap_t		map;
5167 	struct bge_tx_bd	*d;
5168 	struct mbuf		*m = *m_head;
5169 	uint32_t		idx = *txidx;
5170 	uint16_t		csum_flags, mss, vlan_tag;
5171 	int			nsegs, i, error;
5172 
5173 	csum_flags = 0;
5174 	mss = 0;
5175 	vlan_tag = 0;
5176 	if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 &&
5177 	    m->m_next != NULL) {
5178 		*m_head = bge_check_short_dma(m);
5179 		if (*m_head == NULL)
5180 			return (ENOBUFS);
5181 		m = *m_head;
5182 	}
5183 	if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5184 		*m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags);
5185 		if (*m_head == NULL)
5186 			return (ENOBUFS);
5187 		csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
5188 		    BGE_TXBDFLAG_CPU_POST_DMA;
5189 	} else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) {
5190 		if (m->m_pkthdr.csum_flags & CSUM_IP)
5191 			csum_flags |= BGE_TXBDFLAG_IP_CSUM;
5192 		if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
5193 			csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
5194 			if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
5195 			    (error = bge_cksum_pad(m)) != 0) {
5196 				m_freem(m);
5197 				*m_head = NULL;
5198 				return (error);
5199 			}
5200 		}
5201 	}
5202 
5203 	if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) {
5204 		if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME &&
5205 		    m->m_pkthdr.len > ETHER_MAX_LEN)
5206 			csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME;
5207 		if (sc->bge_forced_collapse > 0 &&
5208 		    (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
5209 			/*
5210 			 * Forcedly collapse mbuf chains to overcome hardware
5211 			 * limitation which only support a single outstanding
5212 			 * DMA read operation.
5213 			 */
5214 			if (sc->bge_forced_collapse == 1)
5215 				m = m_defrag(m, M_NOWAIT);
5216 			else
5217 				m = m_collapse(m, M_NOWAIT,
5218 				    sc->bge_forced_collapse);
5219 			if (m == NULL)
5220 				m = *m_head;
5221 			*m_head = m;
5222 		}
5223 	}
5224 
5225 	map = sc->bge_cdata.bge_tx_dmamap[idx];
5226 	error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
5227 	    &nsegs, BUS_DMA_NOWAIT);
5228 	if (error == EFBIG) {
5229 		m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW);
5230 		if (m == NULL) {
5231 			m_freem(*m_head);
5232 			*m_head = NULL;
5233 			return (ENOBUFS);
5234 		}
5235 		*m_head = m;
5236 		error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
5237 		    m, segs, &nsegs, BUS_DMA_NOWAIT);
5238 		if (error) {
5239 			m_freem(m);
5240 			*m_head = NULL;
5241 			return (error);
5242 		}
5243 	} else if (error != 0)
5244 		return (error);
5245 
5246 	/* Check if we have enough free send BDs. */
5247 	if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
5248 		bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5249 		return (ENOBUFS);
5250 	}
5251 
5252 	bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
5253 
5254 	if (m->m_flags & M_VLANTAG) {
5255 		csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
5256 		vlan_tag = m->m_pkthdr.ether_vtag;
5257 	}
5258 
5259 	if (sc->bge_asicrev == BGE_ASICREV_BCM5762 &&
5260 	    (m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5261 		/*
5262 		 * 5725 family of devices corrupts TSO packets when TSO DMA
5263 		 * buffers cross into regions which are within MSS bytes of
5264 		 * a 4GB boundary.  If we encounter the condition, drop the
5265 		 * packet.
5266 		 */
5267 		for (i = 0; ; i++) {
5268 			d = &sc->bge_ldata.bge_tx_ring[idx];
5269 			d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5270 			d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5271 			d->bge_len = segs[i].ds_len;
5272 			if (d->bge_addr.bge_addr_lo + segs[i].ds_len + mss <
5273 			    d->bge_addr.bge_addr_lo)
5274 				break;
5275 			d->bge_flags = csum_flags;
5276 			d->bge_vlan_tag = vlan_tag;
5277 			d->bge_mss = mss;
5278 			if (i == nsegs - 1)
5279 				break;
5280 			BGE_INC(idx, BGE_TX_RING_CNT);
5281 		}
5282 		if (i != nsegs - 1) {
5283 			bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map,
5284 			    BUS_DMASYNC_POSTWRITE);
5285 			bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5286 			m_freem(*m_head);
5287 			*m_head = NULL;
5288 			return (EIO);
5289 		}
5290 	} else {
5291 		for (i = 0; ; i++) {
5292 			d = &sc->bge_ldata.bge_tx_ring[idx];
5293 			d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5294 			d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5295 			d->bge_len = segs[i].ds_len;
5296 			d->bge_flags = csum_flags;
5297 			d->bge_vlan_tag = vlan_tag;
5298 			d->bge_mss = mss;
5299 			if (i == nsegs - 1)
5300 				break;
5301 			BGE_INC(idx, BGE_TX_RING_CNT);
5302 		}
5303 	}
5304 
5305 	/* Mark the last segment as end of packet... */
5306 	d->bge_flags |= BGE_TXBDFLAG_END;
5307 
5308 	/*
5309 	 * Insure that the map for this transmission
5310 	 * is placed at the array index of the last descriptor
5311 	 * in this chain.
5312 	 */
5313 	sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
5314 	sc->bge_cdata.bge_tx_dmamap[idx] = map;
5315 	sc->bge_cdata.bge_tx_chain[idx] = m;
5316 	sc->bge_txcnt += nsegs;
5317 
5318 	BGE_INC(idx, BGE_TX_RING_CNT);
5319 	*txidx = idx;
5320 
5321 	return (0);
5322 }
5323 
5324 /*
5325  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5326  * to the mbuf data regions directly in the transmit descriptors.
5327  */
5328 static void
5329 bge_start_locked(if_t ifp)
5330 {
5331 	struct bge_softc *sc;
5332 	struct mbuf *m_head;
5333 	uint32_t prodidx;
5334 	int count;
5335 
5336 	sc = if_getsoftc(ifp);
5337 	BGE_LOCK_ASSERT(sc);
5338 
5339 	if (!sc->bge_link ||
5340 	    (if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
5341 	    IFF_DRV_RUNNING)
5342 		return;
5343 
5344 	prodidx = sc->bge_tx_prodidx;
5345 
5346 	for (count = 0; !if_sendq_empty(ifp);) {
5347 		if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
5348 			if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
5349 			break;
5350 		}
5351 		m_head = if_dequeue(ifp);
5352 		if (m_head == NULL)
5353 			break;
5354 
5355 		/*
5356 		 * Pack the data into the transmit ring. If we
5357 		 * don't have room, set the OACTIVE flag and wait
5358 		 * for the NIC to drain the ring.
5359 		 */
5360 		if (bge_encap(sc, &m_head, &prodidx)) {
5361 			if (m_head == NULL)
5362 				break;
5363 			if_sendq_prepend(ifp, m_head);
5364 			if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
5365 			break;
5366 		}
5367 		++count;
5368 
5369 		/*
5370 		 * If there's a BPF listener, bounce a copy of this frame
5371 		 * to him.
5372 		 */
5373 		if_bpfmtap(ifp, m_head);
5374 	}
5375 
5376 	if (count > 0)
5377 		bge_start_tx(sc, prodidx);
5378 }
5379 
5380 static void
5381 bge_start_tx(struct bge_softc *sc, uint32_t prodidx)
5382 {
5383 
5384 	bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
5385 	    sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
5386 	/* Transmit. */
5387 	bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5388 	/* 5700 b2 errata */
5389 	if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
5390 		bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5391 
5392 	sc->bge_tx_prodidx = prodidx;
5393 
5394 	/* Set a timeout in case the chip goes out to lunch. */
5395 	sc->bge_timer = BGE_TX_TIMEOUT;
5396 }
5397 
5398 /*
5399  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5400  * to the mbuf data regions directly in the transmit descriptors.
5401  */
5402 static void
5403 bge_start(if_t ifp)
5404 {
5405 	struct bge_softc *sc;
5406 
5407 	sc = if_getsoftc(ifp);
5408 	BGE_LOCK(sc);
5409 	bge_start_locked(ifp);
5410 	BGE_UNLOCK(sc);
5411 }
5412 
5413 static void
5414 bge_init_locked(struct bge_softc *sc)
5415 {
5416 	if_t ifp;
5417 	uint16_t *m;
5418 	uint32_t mode;
5419 
5420 	BGE_LOCK_ASSERT(sc);
5421 
5422 	ifp = sc->bge_ifp;
5423 
5424 	if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
5425 		return;
5426 
5427 	/* Cancel pending I/O and flush buffers. */
5428 	bge_stop(sc);
5429 
5430 	bge_stop_fw(sc);
5431 	bge_sig_pre_reset(sc, BGE_RESET_START);
5432 	bge_reset(sc);
5433 	bge_sig_legacy(sc, BGE_RESET_START);
5434 	bge_sig_post_reset(sc, BGE_RESET_START);
5435 
5436 	bge_chipinit(sc);
5437 
5438 	/*
5439 	 * Init the various state machines, ring
5440 	 * control blocks and firmware.
5441 	 */
5442 	if (bge_blockinit(sc)) {
5443 		device_printf(sc->bge_dev, "initialization failure\n");
5444 		return;
5445 	}
5446 
5447 	ifp = sc->bge_ifp;
5448 
5449 	/* Specify MTU. */
5450 	CSR_WRITE_4(sc, BGE_RX_MTU, if_getmtu(ifp) +
5451 	    ETHER_HDR_LEN + ETHER_CRC_LEN +
5452 	    (if_getcapenable(ifp) & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
5453 
5454 	/* Load our MAC address. */
5455 	m = (uint16_t *)if_getlladdr(sc->bge_ifp);
5456 	CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
5457 	CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
5458 
5459 	/* Program promiscuous mode. */
5460 	bge_setpromisc(sc);
5461 
5462 	/* Program multicast filter. */
5463 	bge_setmulti(sc);
5464 
5465 	/* Program VLAN tag stripping. */
5466 	bge_setvlan(sc);
5467 
5468 	/* Override UDP checksum offloading. */
5469 	if (sc->bge_forced_udpcsum == 0)
5470 		sc->bge_csum_features &= ~CSUM_UDP;
5471 	else
5472 		sc->bge_csum_features |= CSUM_UDP;
5473 	if (if_getcapabilities(ifp) & IFCAP_TXCSUM &&
5474 	    if_getcapenable(ifp) & IFCAP_TXCSUM) {
5475 		if_sethwassistbits(ifp, 0, (BGE_CSUM_FEATURES | CSUM_UDP));
5476 		if_sethwassistbits(ifp, sc->bge_csum_features, 0);
5477 	}
5478 
5479 	/* Init RX ring. */
5480 	if (bge_init_rx_ring_std(sc) != 0) {
5481 		device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
5482 		bge_stop(sc);
5483 		return;
5484 	}
5485 
5486 	/*
5487 	 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
5488 	 * memory to insure that the chip has in fact read the first
5489 	 * entry of the ring.
5490 	 */
5491 	if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
5492 		uint32_t		v, i;
5493 		for (i = 0; i < 10; i++) {
5494 			DELAY(20);
5495 			v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
5496 			if (v == (MCLBYTES - ETHER_ALIGN))
5497 				break;
5498 		}
5499 		if (i == 10)
5500 			device_printf (sc->bge_dev,
5501 			    "5705 A0 chip failed to load RX ring\n");
5502 	}
5503 
5504 	/* Init jumbo RX ring. */
5505 	if (BGE_IS_JUMBO_CAPABLE(sc) &&
5506 	    if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
5507      	    ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)) {
5508 		if (bge_init_rx_ring_jumbo(sc) != 0) {
5509 			device_printf(sc->bge_dev,
5510 			    "no memory for jumbo Rx buffers.\n");
5511 			bge_stop(sc);
5512 			return;
5513 		}
5514 	}
5515 
5516 	/* Init our RX return ring index. */
5517 	sc->bge_rx_saved_considx = 0;
5518 
5519 	/* Init our RX/TX stat counters. */
5520 	sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
5521 
5522 	/* Init TX ring. */
5523 	bge_init_tx_ring(sc);
5524 
5525 	/* Enable TX MAC state machine lockup fix. */
5526 	mode = CSR_READ_4(sc, BGE_TX_MODE);
5527 	if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
5528 		mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
5529 	if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
5530 	    sc->bge_asicrev == BGE_ASICREV_BCM5762) {
5531 		mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5532 		mode |= CSR_READ_4(sc, BGE_TX_MODE) &
5533 		    (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5534 	}
5535 	/* Turn on transmitter. */
5536 	CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
5537 	DELAY(100);
5538 
5539 	/* Turn on receiver. */
5540 	mode = CSR_READ_4(sc, BGE_RX_MODE);
5541 	if (BGE_IS_5755_PLUS(sc))
5542 		mode |= BGE_RXMODE_IPV6_ENABLE;
5543 	if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
5544 		mode |= BGE_RXMODE_IPV4_FRAG_FIX;
5545 	CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE);
5546 	DELAY(10);
5547 
5548 	/*
5549 	 * Set the number of good frames to receive after RX MBUF
5550 	 * Low Watermark has been reached. After the RX MAC receives
5551 	 * this number of frames, it will drop subsequent incoming
5552 	 * frames until the MBUF High Watermark is reached.
5553 	 */
5554 	if (BGE_IS_57765_PLUS(sc))
5555 		CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
5556 	else
5557 		CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
5558 
5559 	/* Clear MAC statistics. */
5560 	if (BGE_IS_5705_PLUS(sc))
5561 		bge_stats_clear_regs(sc);
5562 
5563 	/* Tell firmware we're alive. */
5564 	BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5565 
5566 #ifdef DEVICE_POLLING
5567 	/* Disable interrupts if we are polling. */
5568 	if (if_getcapenable(ifp) & IFCAP_POLLING) {
5569 		BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5570 		    BGE_PCIMISCCTL_MASK_PCI_INTR);
5571 		bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5572 	} else
5573 #endif
5574 
5575 	/* Enable host interrupts. */
5576 	{
5577 	BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
5578 	BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5579 	bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5580 	}
5581 
5582 	if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
5583 	if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
5584 
5585 	bge_ifmedia_upd_locked(ifp);
5586 
5587 	callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
5588 }
5589 
5590 static void
5591 bge_init(void *xsc)
5592 {
5593 	struct bge_softc *sc = xsc;
5594 
5595 	BGE_LOCK(sc);
5596 	bge_init_locked(sc);
5597 	BGE_UNLOCK(sc);
5598 }
5599 
5600 /*
5601  * Set media options.
5602  */
5603 static int
5604 bge_ifmedia_upd(if_t ifp)
5605 {
5606 	struct bge_softc *sc = if_getsoftc(ifp);
5607 	int res;
5608 
5609 	BGE_LOCK(sc);
5610 	res = bge_ifmedia_upd_locked(ifp);
5611 	BGE_UNLOCK(sc);
5612 
5613 	return (res);
5614 }
5615 
5616 static int
5617 bge_ifmedia_upd_locked(if_t ifp)
5618 {
5619 	struct bge_softc *sc = if_getsoftc(ifp);
5620 	struct mii_data *mii;
5621 	struct mii_softc *miisc;
5622 	struct ifmedia *ifm;
5623 
5624 	BGE_LOCK_ASSERT(sc);
5625 
5626 	ifm = &sc->bge_ifmedia;
5627 
5628 	/* If this is a 1000baseX NIC, enable the TBI port. */
5629 	if (sc->bge_flags & BGE_FLAG_TBI) {
5630 		if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
5631 			return (EINVAL);
5632 		switch(IFM_SUBTYPE(ifm->ifm_media)) {
5633 		case IFM_AUTO:
5634 			/*
5635 			 * The BCM5704 ASIC appears to have a special
5636 			 * mechanism for programming the autoneg
5637 			 * advertisement registers in TBI mode.
5638 			 */
5639 			if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
5640 				uint32_t sgdig;
5641 				sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
5642 				if (sgdig & BGE_SGDIGSTS_DONE) {
5643 					CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
5644 					sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
5645 					sgdig |= BGE_SGDIGCFG_AUTO |
5646 					    BGE_SGDIGCFG_PAUSE_CAP |
5647 					    BGE_SGDIGCFG_ASYM_PAUSE;
5648 					CSR_WRITE_4(sc, BGE_SGDIG_CFG,
5649 					    sgdig | BGE_SGDIGCFG_SEND);
5650 					DELAY(5);
5651 					CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
5652 				}
5653 			}
5654 			break;
5655 		case IFM_1000_SX:
5656 			if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
5657 				BGE_CLRBIT(sc, BGE_MAC_MODE,
5658 				    BGE_MACMODE_HALF_DUPLEX);
5659 			} else {
5660 				BGE_SETBIT(sc, BGE_MAC_MODE,
5661 				    BGE_MACMODE_HALF_DUPLEX);
5662 			}
5663 			DELAY(40);
5664 			break;
5665 		default:
5666 			return (EINVAL);
5667 		}
5668 		return (0);
5669 	}
5670 
5671 	sc->bge_link_evt++;
5672 	mii = device_get_softc(sc->bge_miibus);
5673 	LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
5674 		PHY_RESET(miisc);
5675 	mii_mediachg(mii);
5676 
5677 	/*
5678 	 * Force an interrupt so that we will call bge_link_upd
5679 	 * if needed and clear any pending link state attention.
5680 	 * Without this we are not getting any further interrupts
5681 	 * for link state changes and thus will not UP the link and
5682 	 * not be able to send in bge_start_locked. The only
5683 	 * way to get things working was to receive a packet and
5684 	 * get an RX intr.
5685 	 * bge_tick should help for fiber cards and we might not
5686 	 * need to do this here if BGE_FLAG_TBI is set but as
5687 	 * we poll for fiber anyway it should not harm.
5688 	 */
5689 	if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
5690 	    sc->bge_flags & BGE_FLAG_5788)
5691 		BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
5692 	else
5693 		BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
5694 
5695 	return (0);
5696 }
5697 
5698 /*
5699  * Report current media status.
5700  */
5701 static void
5702 bge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
5703 {
5704 	struct bge_softc *sc = if_getsoftc(ifp);
5705 	struct mii_data *mii;
5706 
5707 	BGE_LOCK(sc);
5708 
5709 	if ((if_getflags(ifp) & IFF_UP) == 0) {
5710 		BGE_UNLOCK(sc);
5711 		return;
5712 	}
5713 	if (sc->bge_flags & BGE_FLAG_TBI) {
5714 		ifmr->ifm_status = IFM_AVALID;
5715 		ifmr->ifm_active = IFM_ETHER;
5716 		if (CSR_READ_4(sc, BGE_MAC_STS) &
5717 		    BGE_MACSTAT_TBI_PCS_SYNCHED)
5718 			ifmr->ifm_status |= IFM_ACTIVE;
5719 		else {
5720 			ifmr->ifm_active |= IFM_NONE;
5721 			BGE_UNLOCK(sc);
5722 			return;
5723 		}
5724 		ifmr->ifm_active |= IFM_1000_SX;
5725 		if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
5726 			ifmr->ifm_active |= IFM_HDX;
5727 		else
5728 			ifmr->ifm_active |= IFM_FDX;
5729 		BGE_UNLOCK(sc);
5730 		return;
5731 	}
5732 
5733 	mii = device_get_softc(sc->bge_miibus);
5734 	mii_pollstat(mii);
5735 	ifmr->ifm_active = mii->mii_media_active;
5736 	ifmr->ifm_status = mii->mii_media_status;
5737 
5738 	BGE_UNLOCK(sc);
5739 }
5740 
5741 static int
5742 bge_ioctl(if_t ifp, u_long command, caddr_t data)
5743 {
5744 	struct bge_softc *sc = if_getsoftc(ifp);
5745 	struct ifreq *ifr = (struct ifreq *) data;
5746 	struct mii_data *mii;
5747 	int flags, mask, error = 0;
5748 
5749 	switch (command) {
5750 	case SIOCSIFMTU:
5751 		if (BGE_IS_JUMBO_CAPABLE(sc) ||
5752 		    (sc->bge_flags & BGE_FLAG_JUMBO_STD)) {
5753 			if (ifr->ifr_mtu < ETHERMIN ||
5754 			    ifr->ifr_mtu > BGE_JUMBO_MTU) {
5755 				error = EINVAL;
5756 				break;
5757 			}
5758 		} else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) {
5759 			error = EINVAL;
5760 			break;
5761 		}
5762 		BGE_LOCK(sc);
5763 		if (if_getmtu(ifp) != ifr->ifr_mtu) {
5764 			if_setmtu(ifp, ifr->ifr_mtu);
5765 			if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5766 				if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5767 				bge_init_locked(sc);
5768 			}
5769 		}
5770 		BGE_UNLOCK(sc);
5771 		break;
5772 	case SIOCSIFFLAGS:
5773 		BGE_LOCK(sc);
5774 		if (if_getflags(ifp) & IFF_UP) {
5775 			/*
5776 			 * If only the state of the PROMISC flag changed,
5777 			 * then just use the 'set promisc mode' command
5778 			 * instead of reinitializing the entire NIC. Doing
5779 			 * a full re-init means reloading the firmware and
5780 			 * waiting for it to start up, which may take a
5781 			 * second or two.  Similarly for ALLMULTI.
5782 			 */
5783 			if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5784 				flags = if_getflags(ifp) ^ sc->bge_if_flags;
5785 				if (flags & IFF_PROMISC)
5786 					bge_setpromisc(sc);
5787 				if (flags & IFF_ALLMULTI)
5788 					bge_setmulti(sc);
5789 			} else
5790 				bge_init_locked(sc);
5791 		} else {
5792 			if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5793 				bge_stop(sc);
5794 			}
5795 		}
5796 		sc->bge_if_flags = if_getflags(ifp);
5797 		BGE_UNLOCK(sc);
5798 		error = 0;
5799 		break;
5800 	case SIOCADDMULTI:
5801 	case SIOCDELMULTI:
5802 		if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5803 			BGE_LOCK(sc);
5804 			bge_setmulti(sc);
5805 			BGE_UNLOCK(sc);
5806 			error = 0;
5807 		}
5808 		break;
5809 	case SIOCSIFMEDIA:
5810 	case SIOCGIFMEDIA:
5811 		if (sc->bge_flags & BGE_FLAG_TBI) {
5812 			error = ifmedia_ioctl(ifp, ifr,
5813 			    &sc->bge_ifmedia, command);
5814 		} else {
5815 			mii = device_get_softc(sc->bge_miibus);
5816 			error = ifmedia_ioctl(ifp, ifr,
5817 			    &mii->mii_media, command);
5818 		}
5819 		break;
5820 	case SIOCSIFCAP:
5821 		mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
5822 #ifdef DEVICE_POLLING
5823 		if (mask & IFCAP_POLLING) {
5824 			if (ifr->ifr_reqcap & IFCAP_POLLING) {
5825 				error = ether_poll_register(bge_poll, ifp);
5826 				if (error)
5827 					return (error);
5828 				BGE_LOCK(sc);
5829 				BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5830 				    BGE_PCIMISCCTL_MASK_PCI_INTR);
5831 				bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5832 				if_setcapenablebit(ifp, IFCAP_POLLING, 0);
5833 				BGE_UNLOCK(sc);
5834 			} else {
5835 				error = ether_poll_deregister(ifp);
5836 				/* Enable interrupt even in error case */
5837 				BGE_LOCK(sc);
5838 				BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
5839 				    BGE_PCIMISCCTL_MASK_PCI_INTR);
5840 				bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5841 				if_setcapenablebit(ifp, 0, IFCAP_POLLING);
5842 				BGE_UNLOCK(sc);
5843 			}
5844 		}
5845 #endif
5846 		if ((mask & IFCAP_TXCSUM) != 0 &&
5847 		    (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
5848 			if_togglecapenable(ifp, IFCAP_TXCSUM);
5849 			if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
5850 				if_sethwassistbits(ifp,
5851 				    sc->bge_csum_features, 0);
5852 			else
5853 				if_sethwassistbits(ifp, 0,
5854 				    sc->bge_csum_features);
5855 		}
5856 
5857 		if ((mask & IFCAP_RXCSUM) != 0 &&
5858 		    (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0)
5859 			if_togglecapenable(ifp, IFCAP_RXCSUM);
5860 
5861 		if ((mask & IFCAP_TSO4) != 0 &&
5862 		    (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) {
5863 			if_togglecapenable(ifp, IFCAP_TSO4);
5864 			if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0)
5865 				if_sethwassistbits(ifp, CSUM_TSO, 0);
5866 			else
5867 				if_sethwassistbits(ifp, 0, CSUM_TSO);
5868 		}
5869 
5870 		if (mask & IFCAP_VLAN_MTU) {
5871 			if_togglecapenable(ifp, IFCAP_VLAN_MTU);
5872 			if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5873 			bge_init(sc);
5874 		}
5875 
5876 		if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
5877 		    (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
5878 			if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
5879 		if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
5880 		    (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
5881 			if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
5882 			if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
5883 				if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO);
5884 			BGE_LOCK(sc);
5885 			bge_setvlan(sc);
5886 			BGE_UNLOCK(sc);
5887 		}
5888 #ifdef VLAN_CAPABILITIES
5889 		if_vlancap(ifp);
5890 #endif
5891 		break;
5892 	default:
5893 		error = ether_ioctl(ifp, command, data);
5894 		break;
5895 	}
5896 
5897 	return (error);
5898 }
5899 
5900 static void
5901 bge_watchdog(struct bge_softc *sc)
5902 {
5903 	if_t ifp;
5904 	uint32_t status;
5905 
5906 	BGE_LOCK_ASSERT(sc);
5907 
5908 	if (sc->bge_timer == 0 || --sc->bge_timer)
5909 		return;
5910 
5911 	/* If pause frames are active then don't reset the hardware. */
5912 	if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) {
5913 		status = CSR_READ_4(sc, BGE_RX_STS);
5914 		if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) {
5915 			/*
5916 			 * If link partner has us in XOFF state then wait for
5917 			 * the condition to clear.
5918 			 */
5919 			CSR_WRITE_4(sc, BGE_RX_STS, status);
5920 			sc->bge_timer = BGE_TX_TIMEOUT;
5921 			return;
5922 		} else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 &&
5923 		    (status & BGE_RXSTAT_RCVD_XON) != 0) {
5924 			/*
5925 			 * If link partner has us in XOFF state then wait for
5926 			 * the condition to clear.
5927 			 */
5928 			CSR_WRITE_4(sc, BGE_RX_STS, status);
5929 			sc->bge_timer = BGE_TX_TIMEOUT;
5930 			return;
5931 		}
5932 		/*
5933 		 * Any other condition is unexpected and the controller
5934 		 * should be reset.
5935 		 */
5936 	}
5937 
5938 	ifp = sc->bge_ifp;
5939 
5940 	if_printf(ifp, "watchdog timeout -- resetting\n");
5941 
5942 	if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5943 	bge_init_locked(sc);
5944 
5945 	if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
5946 }
5947 
5948 static void
5949 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
5950 {
5951 	int i;
5952 
5953 	BGE_CLRBIT(sc, reg, bit);
5954 
5955 	for (i = 0; i < BGE_TIMEOUT; i++) {
5956 		if ((CSR_READ_4(sc, reg) & bit) == 0)
5957 			return;
5958 		DELAY(100);
5959         }
5960 }
5961 
5962 /*
5963  * Stop the adapter and free any mbufs allocated to the
5964  * RX and TX lists.
5965  */
5966 static void
5967 bge_stop(struct bge_softc *sc)
5968 {
5969 	if_t ifp;
5970 
5971 	BGE_LOCK_ASSERT(sc);
5972 
5973 	ifp = sc->bge_ifp;
5974 
5975 	callout_stop(&sc->bge_stat_ch);
5976 
5977 	/* Disable host interrupts. */
5978 	BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5979 	bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5980 
5981 	/*
5982 	 * Tell firmware we're shutting down.
5983 	 */
5984 	bge_stop_fw(sc);
5985 	bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
5986 
5987 	/*
5988 	 * Disable all of the receiver blocks.
5989 	 */
5990 	bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
5991 	bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
5992 	bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
5993 	if (BGE_IS_5700_FAMILY(sc))
5994 		bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
5995 	bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
5996 	bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
5997 	bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
5998 
5999 	/*
6000 	 * Disable all of the transmit blocks.
6001 	 */
6002 	bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
6003 	bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
6004 	bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
6005 	bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
6006 	bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
6007 	if (BGE_IS_5700_FAMILY(sc))
6008 		bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
6009 	bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
6010 
6011 	/*
6012 	 * Shut down all of the memory managers and related
6013 	 * state machines.
6014 	 */
6015 	bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
6016 	bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
6017 	if (BGE_IS_5700_FAMILY(sc))
6018 		bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
6019 
6020 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
6021 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
6022 	if (!(BGE_IS_5705_PLUS(sc))) {
6023 		BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
6024 		BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
6025 	}
6026 	/* Update MAC statistics. */
6027 	if (BGE_IS_5705_PLUS(sc))
6028 		bge_stats_update_regs(sc);
6029 
6030 	bge_reset(sc);
6031 	bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
6032 	bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
6033 
6034 	/*
6035 	 * Keep the ASF firmware running if up.
6036 	 */
6037 	if (sc->bge_asf_mode & ASF_STACKUP)
6038 		BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6039 	else
6040 		BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6041 
6042 	/* Free the RX lists. */
6043 	bge_free_rx_ring_std(sc);
6044 
6045 	/* Free jumbo RX list. */
6046 	if (BGE_IS_JUMBO_CAPABLE(sc))
6047 		bge_free_rx_ring_jumbo(sc);
6048 
6049 	/* Free TX buffers. */
6050 	bge_free_tx_ring(sc);
6051 
6052 	sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
6053 
6054 	/* Clear MAC's link state (PHY may still have link UP). */
6055 	if (bootverbose && sc->bge_link)
6056 		if_printf(sc->bge_ifp, "link DOWN\n");
6057 	sc->bge_link = 0;
6058 
6059 	if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
6060 }
6061 
6062 /*
6063  * Stop all chip I/O so that the kernel's probe routines don't
6064  * get confused by errant DMAs when rebooting.
6065  */
6066 static int
6067 bge_shutdown(device_t dev)
6068 {
6069 	struct bge_softc *sc;
6070 
6071 	sc = device_get_softc(dev);
6072 	BGE_LOCK(sc);
6073 	bge_stop(sc);
6074 	BGE_UNLOCK(sc);
6075 
6076 	return (0);
6077 }
6078 
6079 static int
6080 bge_suspend(device_t dev)
6081 {
6082 	struct bge_softc *sc;
6083 
6084 	sc = device_get_softc(dev);
6085 	BGE_LOCK(sc);
6086 	bge_stop(sc);
6087 	BGE_UNLOCK(sc);
6088 
6089 	return (0);
6090 }
6091 
6092 static int
6093 bge_resume(device_t dev)
6094 {
6095 	struct bge_softc *sc;
6096 	if_t ifp;
6097 
6098 	sc = device_get_softc(dev);
6099 	BGE_LOCK(sc);
6100 	ifp = sc->bge_ifp;
6101 	if (if_getflags(ifp) & IFF_UP) {
6102 		bge_init_locked(sc);
6103 		if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
6104 			bge_start_locked(ifp);
6105 	}
6106 	BGE_UNLOCK(sc);
6107 
6108 	return (0);
6109 }
6110 
6111 static void
6112 bge_link_upd(struct bge_softc *sc)
6113 {
6114 	struct mii_data *mii;
6115 	uint32_t link, status;
6116 
6117 	BGE_LOCK_ASSERT(sc);
6118 
6119 	/* Clear 'pending link event' flag. */
6120 	sc->bge_link_evt = 0;
6121 
6122 	/*
6123 	 * Process link state changes.
6124 	 * Grrr. The link status word in the status block does
6125 	 * not work correctly on the BCM5700 rev AX and BX chips,
6126 	 * according to all available information. Hence, we have
6127 	 * to enable MII interrupts in order to properly obtain
6128 	 * async link changes. Unfortunately, this also means that
6129 	 * we have to read the MAC status register to detect link
6130 	 * changes, thereby adding an additional register access to
6131 	 * the interrupt handler.
6132 	 *
6133 	 * XXX: perhaps link state detection procedure used for
6134 	 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
6135 	 */
6136 
6137 	if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6138 	    sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
6139 		status = CSR_READ_4(sc, BGE_MAC_STS);
6140 		if (status & BGE_MACSTAT_MI_INTERRUPT) {
6141 			mii = device_get_softc(sc->bge_miibus);
6142 			mii_pollstat(mii);
6143 			if (!sc->bge_link &&
6144 			    mii->mii_media_status & IFM_ACTIVE &&
6145 			    IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6146 				sc->bge_link++;
6147 				if (bootverbose)
6148 					if_printf(sc->bge_ifp, "link UP\n");
6149 			} else if (sc->bge_link &&
6150 			    (!(mii->mii_media_status & IFM_ACTIVE) ||
6151 			    IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6152 				sc->bge_link = 0;
6153 				if (bootverbose)
6154 					if_printf(sc->bge_ifp, "link DOWN\n");
6155 			}
6156 
6157 			/* Clear the interrupt. */
6158 			CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
6159 			    BGE_EVTENB_MI_INTERRUPT);
6160 			bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr,
6161 			    BRGPHY_MII_ISR);
6162 			bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr,
6163 			    BRGPHY_MII_IMR, BRGPHY_INTRS);
6164 		}
6165 		return;
6166 	}
6167 
6168 	if (sc->bge_flags & BGE_FLAG_TBI) {
6169 		status = CSR_READ_4(sc, BGE_MAC_STS);
6170 		if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
6171 			if (!sc->bge_link) {
6172 				sc->bge_link++;
6173 				if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
6174 					BGE_CLRBIT(sc, BGE_MAC_MODE,
6175 					    BGE_MACMODE_TBI_SEND_CFGS);
6176 					DELAY(40);
6177 				}
6178 				CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
6179 				if (bootverbose)
6180 					if_printf(sc->bge_ifp, "link UP\n");
6181 				if_link_state_change(sc->bge_ifp,
6182 				    LINK_STATE_UP);
6183 			}
6184 		} else if (sc->bge_link) {
6185 			sc->bge_link = 0;
6186 			if (bootverbose)
6187 				if_printf(sc->bge_ifp, "link DOWN\n");
6188 			if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
6189 		}
6190 	} else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
6191 		/*
6192 		 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
6193 		 * in status word always set. Workaround this bug by reading
6194 		 * PHY link status directly.
6195 		 */
6196 		link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
6197 
6198 		if (link != sc->bge_link ||
6199 		    sc->bge_asicrev == BGE_ASICREV_BCM5700) {
6200 			mii = device_get_softc(sc->bge_miibus);
6201 			mii_pollstat(mii);
6202 			if (!sc->bge_link &&
6203 			    mii->mii_media_status & IFM_ACTIVE &&
6204 			    IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6205 				sc->bge_link++;
6206 				if (bootverbose)
6207 					if_printf(sc->bge_ifp, "link UP\n");
6208 			} else if (sc->bge_link &&
6209 			    (!(mii->mii_media_status & IFM_ACTIVE) ||
6210 			    IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6211 				sc->bge_link = 0;
6212 				if (bootverbose)
6213 					if_printf(sc->bge_ifp, "link DOWN\n");
6214 			}
6215 		}
6216 	} else {
6217 		/*
6218 		 * For controllers that call mii_tick, we have to poll
6219 		 * link status.
6220 		 */
6221 		mii = device_get_softc(sc->bge_miibus);
6222 		mii_pollstat(mii);
6223 		bge_miibus_statchg(sc->bge_dev);
6224 	}
6225 
6226 	/* Disable MAC attention when link is up. */
6227 	CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
6228 	    BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
6229 	    BGE_MACSTAT_LINK_CHANGED);
6230 }
6231 
6232 static void
6233 bge_add_sysctls(struct bge_softc *sc)
6234 {
6235 	struct sysctl_ctx_list *ctx;
6236 	struct sysctl_oid_list *children;
6237 
6238 	ctx = device_get_sysctl_ctx(sc->bge_dev);
6239 	children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
6240 
6241 #ifdef BGE_REGISTER_DEBUG
6242 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
6243 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
6244 	    bge_sysctl_debug_info, "I", "Debug Information");
6245 
6246 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
6247 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
6248 	    bge_sysctl_reg_read, "I", "MAC Register Read");
6249 
6250 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read",
6251 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
6252 	    bge_sysctl_ape_read, "I", "APE Register Read");
6253 
6254 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
6255 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
6256 	    bge_sysctl_mem_read, "I", "Memory Read");
6257 
6258 #endif
6259 
6260 	/*
6261 	 * A common design characteristic for many Broadcom client controllers
6262 	 * is that they only support a single outstanding DMA read operation
6263 	 * on the PCIe bus. This means that it will take twice as long to fetch
6264 	 * a TX frame that is split into header and payload buffers as it does
6265 	 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
6266 	 * these controllers, coalescing buffers to reduce the number of memory
6267 	 * reads is effective way to get maximum performance(about 940Mbps).
6268 	 * Without collapsing TX buffers the maximum TCP bulk transfer
6269 	 * performance is about 850Mbps. However forcing coalescing mbufs
6270 	 * consumes a lot of CPU cycles, so leave it off by default.
6271 	 */
6272 	sc->bge_forced_collapse = 0;
6273 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse",
6274 	    CTLFLAG_RWTUN, &sc->bge_forced_collapse, 0,
6275 	    "Number of fragmented TX buffers of a frame allowed before "
6276 	    "forced collapsing");
6277 
6278 	sc->bge_msi = 1;
6279 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi",
6280 	    CTLFLAG_RDTUN, &sc->bge_msi, 0, "Enable MSI");
6281 
6282 	/*
6283 	 * It seems all Broadcom controllers have a bug that can generate UDP
6284 	 * datagrams with checksum value 0 when TX UDP checksum offloading is
6285 	 * enabled.  Generating UDP checksum value 0 is RFC 768 violation.
6286 	 * Even though the probability of generating such UDP datagrams is
6287 	 * low, I don't want to see FreeBSD boxes to inject such datagrams
6288 	 * into network so disable UDP checksum offloading by default.  Users
6289 	 * still override this behavior by setting a sysctl variable,
6290 	 * dev.bge.0.forced_udpcsum.
6291 	 */
6292 	sc->bge_forced_udpcsum = 0;
6293 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum",
6294 	    CTLFLAG_RWTUN, &sc->bge_forced_udpcsum, 0,
6295 	    "Enable UDP checksum offloading even if controller can "
6296 	    "generate UDP checksum value 0");
6297 
6298 	if (BGE_IS_5705_PLUS(sc))
6299 		bge_add_sysctl_stats_regs(sc, ctx, children);
6300 	else
6301 		bge_add_sysctl_stats(sc, ctx, children);
6302 }
6303 
6304 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
6305     SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, \
6306         CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, \
6307 	offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", desc)
6308 
6309 static void
6310 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6311     struct sysctl_oid_list *parent)
6312 {
6313 	struct sysctl_oid *tree;
6314 	struct sysctl_oid_list *children, *schildren;
6315 
6316 	tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats",
6317 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE Statistics");
6318 	schildren = children = SYSCTL_CHILDREN(tree);
6319 	BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
6320 	    children, COSFramesDroppedDueToFilters,
6321 	    "FramesDroppedDueToFilters");
6322 	BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
6323 	    children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
6324 	BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
6325 	    children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
6326 	BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
6327 	    children, nicNoMoreRxBDs, "NoMoreRxBDs");
6328 	BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
6329 	    children, ifInDiscards, "InputDiscards");
6330 	BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
6331 	    children, ifInErrors, "InputErrors");
6332 	BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
6333 	    children, nicRecvThresholdHit, "RecvThresholdHit");
6334 	BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
6335 	    children, nicDmaReadQueueFull, "DmaReadQueueFull");
6336 	BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
6337 	    children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
6338 	BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
6339 	    children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
6340 	BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
6341 	    children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
6342 	BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
6343 	    children, nicRingStatusUpdate, "RingStatusUpdate");
6344 	BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
6345 	    children, nicInterrupts, "Interrupts");
6346 	BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
6347 	    children, nicAvoidedInterrupts, "AvoidedInterrupts");
6348 	BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
6349 	    children, nicSendThresholdHit, "SendThresholdHit");
6350 
6351 	tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx",
6352 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE RX Statistics");
6353 	children = SYSCTL_CHILDREN(tree);
6354 	BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
6355 	    children, rxstats.ifHCInOctets, "ifHCInOctets");
6356 	BGE_SYSCTL_STAT(sc, ctx, "Fragments",
6357 	    children, rxstats.etherStatsFragments, "Fragments");
6358 	BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
6359 	    children, rxstats.ifHCInUcastPkts, "UnicastPkts");
6360 	BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
6361 	    children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
6362 	BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
6363 	    children, rxstats.dot3StatsFCSErrors, "FCSErrors");
6364 	BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
6365 	    children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
6366 	BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
6367 	    children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
6368 	BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
6369 	    children, rxstats.xoffPauseFramesReceived,
6370 	    "xoffPauseFramesReceived");
6371 	BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
6372 	    children, rxstats.macControlFramesReceived,
6373 	    "ControlFramesReceived");
6374 	BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
6375 	    children, rxstats.xoffStateEntered, "xoffStateEntered");
6376 	BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
6377 	    children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
6378 	BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
6379 	    children, rxstats.etherStatsJabbers, "Jabbers");
6380 	BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
6381 	    children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
6382 	BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
6383 	    children, rxstats.inRangeLengthError, "inRangeLengthError");
6384 	BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
6385 	    children, rxstats.outRangeLengthError, "outRangeLengthError");
6386 
6387 	tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx",
6388 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE TX Statistics");
6389 	children = SYSCTL_CHILDREN(tree);
6390 	BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
6391 	    children, txstats.ifHCOutOctets, "ifHCOutOctets");
6392 	BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
6393 	    children, txstats.etherStatsCollisions, "Collisions");
6394 	BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
6395 	    children, txstats.outXonSent, "XonSent");
6396 	BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
6397 	    children, txstats.outXoffSent, "XoffSent");
6398 	BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
6399 	    children, txstats.flowControlDone, "flowControlDone");
6400 	BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
6401 	    children, txstats.dot3StatsInternalMacTransmitErrors,
6402 	    "InternalMacTransmitErrors");
6403 	BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
6404 	    children, txstats.dot3StatsSingleCollisionFrames,
6405 	    "SingleCollisionFrames");
6406 	BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
6407 	    children, txstats.dot3StatsMultipleCollisionFrames,
6408 	    "MultipleCollisionFrames");
6409 	BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
6410 	    children, txstats.dot3StatsDeferredTransmissions,
6411 	    "DeferredTransmissions");
6412 	BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
6413 	    children, txstats.dot3StatsExcessiveCollisions,
6414 	    "ExcessiveCollisions");
6415 	BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
6416 	    children, txstats.dot3StatsLateCollisions,
6417 	    "LateCollisions");
6418 	BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
6419 	    children, txstats.ifHCOutUcastPkts, "UnicastPkts");
6420 	BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
6421 	    children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
6422 	BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
6423 	    children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
6424 	BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
6425 	    children, txstats.dot3StatsCarrierSenseErrors,
6426 	    "CarrierSenseErrors");
6427 	BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
6428 	    children, txstats.ifOutDiscards, "Discards");
6429 	BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
6430 	    children, txstats.ifOutErrors, "Errors");
6431 }
6432 
6433 #undef BGE_SYSCTL_STAT
6434 
6435 #define	BGE_SYSCTL_STAT_ADD64(c, h, n, p, d)	\
6436 	    SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
6437 
6438 static void
6439 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6440     struct sysctl_oid_list *parent)
6441 {
6442 	struct sysctl_oid *tree;
6443 	struct sysctl_oid_list *child, *schild;
6444 	struct bge_mac_stats *stats;
6445 
6446 	stats = &sc->bge_mac_stats;
6447 	tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats",
6448 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE Statistics");
6449 	schild = child = SYSCTL_CHILDREN(tree);
6450 	BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters",
6451 	    &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters");
6452 	BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull",
6453 	    &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full");
6454 	BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull",
6455 	    &stats->DmaWriteHighPriQueueFull,
6456 	    "NIC DMA Write High Priority Queue Full");
6457 	BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs",
6458 	    &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors");
6459 	BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards",
6460 	    &stats->InputDiscards, "Discarded Input Frames");
6461 	BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors",
6462 	    &stats->InputErrors, "Input Errors");
6463 	BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit",
6464 	    &stats->RecvThresholdHit, "NIC Recv Threshold Hit");
6465 
6466 	tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx",
6467 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE RX Statistics");
6468 	child = SYSCTL_CHILDREN(tree);
6469 	BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets",
6470 	    &stats->ifHCInOctets, "Inbound Octets");
6471 	BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments",
6472 	    &stats->etherStatsFragments, "Fragments");
6473 	BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6474 	    &stats->ifHCInUcastPkts, "Inbound Unicast Packets");
6475 	BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6476 	    &stats->ifHCInMulticastPkts, "Inbound Multicast Packets");
6477 	BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6478 	    &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets");
6479 	BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors",
6480 	    &stats->dot3StatsFCSErrors, "FCS Errors");
6481 	BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors",
6482 	    &stats->dot3StatsAlignmentErrors, "Alignment Errors");
6483 	BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived",
6484 	    &stats->xonPauseFramesReceived, "XON Pause Frames Received");
6485 	BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived",
6486 	    &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received");
6487 	BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived",
6488 	    &stats->macControlFramesReceived, "MAC Control Frames Received");
6489 	BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered",
6490 	    &stats->xoffStateEntered, "XOFF State Entered");
6491 	BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong",
6492 	    &stats->dot3StatsFramesTooLong, "Frames Too Long");
6493 	BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers",
6494 	    &stats->etherStatsJabbers, "Jabbers");
6495 	BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts",
6496 	    &stats->etherStatsUndersizePkts, "Undersized Packets");
6497 
6498 	tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx",
6499 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE TX Statistics");
6500 	child = SYSCTL_CHILDREN(tree);
6501 	BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets",
6502 	    &stats->ifHCOutOctets, "Outbound Octets");
6503 	BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions",
6504 	    &stats->etherStatsCollisions, "TX Collisions");
6505 	BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent",
6506 	    &stats->outXonSent, "XON Sent");
6507 	BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent",
6508 	    &stats->outXoffSent, "XOFF Sent");
6509 	BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors",
6510 	    &stats->dot3StatsInternalMacTransmitErrors,
6511 	    "Internal MAC TX Errors");
6512 	BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames",
6513 	    &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames");
6514 	BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames",
6515 	    &stats->dot3StatsMultipleCollisionFrames,
6516 	    "Multiple Collision Frames");
6517 	BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions",
6518 	    &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions");
6519 	BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions",
6520 	    &stats->dot3StatsExcessiveCollisions, "Excessive Collisions");
6521 	BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions",
6522 	    &stats->dot3StatsLateCollisions, "Late Collisions");
6523 	BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6524 	    &stats->ifHCOutUcastPkts, "Outbound Unicast Packets");
6525 	BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6526 	    &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets");
6527 	BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6528 	    &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets");
6529 }
6530 
6531 #undef	BGE_SYSCTL_STAT_ADD64
6532 
6533 static int
6534 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
6535 {
6536 	struct bge_softc *sc;
6537 	uint32_t result;
6538 	int offset;
6539 
6540 	sc = (struct bge_softc *)arg1;
6541 	offset = arg2;
6542 	result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
6543 	    offsetof(bge_hostaddr, bge_addr_lo));
6544 	return (sysctl_handle_int(oidp, &result, 0, req));
6545 }
6546 
6547 #ifdef BGE_REGISTER_DEBUG
6548 static int
6549 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
6550 {
6551 	struct bge_softc *sc;
6552 	uint16_t *sbdata;
6553 	int error, result, sbsz;
6554 	int i, j;
6555 
6556 	result = -1;
6557 	error = sysctl_handle_int(oidp, &result, 0, req);
6558 	if (error || (req->newptr == NULL))
6559 		return (error);
6560 
6561 	if (result == 1) {
6562 		sc = (struct bge_softc *)arg1;
6563 
6564 		if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6565 		    sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
6566 			sbsz = BGE_STATUS_BLK_SZ;
6567 		else
6568 			sbsz = 32;
6569 		sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
6570 		printf("Status Block:\n");
6571 		BGE_LOCK(sc);
6572 		bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6573 		    sc->bge_cdata.bge_status_map,
6574 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6575 		for (i = 0x0; i < sbsz / sizeof(uint16_t); ) {
6576 			printf("%06x:", i);
6577 			for (j = 0; j < 8; j++)
6578 				printf(" %04x", sbdata[i++]);
6579 			printf("\n");
6580 		}
6581 
6582 		printf("Registers:\n");
6583 		for (i = 0x800; i < 0xA00; ) {
6584 			printf("%06x:", i);
6585 			for (j = 0; j < 8; j++) {
6586 				printf(" %08x", CSR_READ_4(sc, i));
6587 				i += 4;
6588 			}
6589 			printf("\n");
6590 		}
6591 		BGE_UNLOCK(sc);
6592 
6593 		printf("Hardware Flags:\n");
6594 		if (BGE_IS_5717_PLUS(sc))
6595 			printf(" - 5717 Plus\n");
6596 		if (BGE_IS_5755_PLUS(sc))
6597 			printf(" - 5755 Plus\n");
6598 		if (BGE_IS_575X_PLUS(sc))
6599 			printf(" - 575X Plus\n");
6600 		if (BGE_IS_5705_PLUS(sc))
6601 			printf(" - 5705 Plus\n");
6602 		if (BGE_IS_5714_FAMILY(sc))
6603 			printf(" - 5714 Family\n");
6604 		if (BGE_IS_5700_FAMILY(sc))
6605 			printf(" - 5700 Family\n");
6606 		if (sc->bge_flags & BGE_FLAG_JUMBO)
6607 			printf(" - Supports Jumbo Frames\n");
6608 		if (sc->bge_flags & BGE_FLAG_PCIX)
6609 			printf(" - PCI-X Bus\n");
6610 		if (sc->bge_flags & BGE_FLAG_PCIE)
6611 			printf(" - PCI Express Bus\n");
6612 		if (sc->bge_phy_flags & BGE_PHY_NO_3LED)
6613 			printf(" - No 3 LEDs\n");
6614 		if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
6615 			printf(" - RX Alignment Bug\n");
6616 	}
6617 
6618 	return (error);
6619 }
6620 
6621 static int
6622 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
6623 {
6624 	struct bge_softc *sc;
6625 	int error;
6626 	uint16_t result;
6627 	uint32_t val;
6628 
6629 	result = -1;
6630 	error = sysctl_handle_int(oidp, &result, 0, req);
6631 	if (error || (req->newptr == NULL))
6632 		return (error);
6633 
6634 	if (result < 0x8000) {
6635 		sc = (struct bge_softc *)arg1;
6636 		val = CSR_READ_4(sc, result);
6637 		printf("reg 0x%06X = 0x%08X\n", result, val);
6638 	}
6639 
6640 	return (error);
6641 }
6642 
6643 static int
6644 bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS)
6645 {
6646 	struct bge_softc *sc;
6647 	int error;
6648 	uint16_t result;
6649 	uint32_t val;
6650 
6651 	result = -1;
6652 	error = sysctl_handle_int(oidp, &result, 0, req);
6653 	if (error || (req->newptr == NULL))
6654 		return (error);
6655 
6656 	if (result < 0x8000) {
6657 		sc = (struct bge_softc *)arg1;
6658 		val = APE_READ_4(sc, result);
6659 		printf("reg 0x%06X = 0x%08X\n", result, val);
6660 	}
6661 
6662 	return (error);
6663 }
6664 
6665 static int
6666 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
6667 {
6668 	struct bge_softc *sc;
6669 	int error;
6670 	uint16_t result;
6671 	uint32_t val;
6672 
6673 	result = -1;
6674 	error = sysctl_handle_int(oidp, &result, 0, req);
6675 	if (error || (req->newptr == NULL))
6676 		return (error);
6677 
6678 	if (result < 0x8000) {
6679 		sc = (struct bge_softc *)arg1;
6680 		val = bge_readmem_ind(sc, result);
6681 		printf("mem 0x%06X = 0x%08X\n", result, val);
6682 	}
6683 
6684 	return (error);
6685 }
6686 #endif
6687 
6688 static int
6689 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
6690 {
6691 	return (1);
6692 }
6693 
6694 static int
6695 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
6696 {
6697 	uint32_t mac_addr;
6698 
6699 	mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB);
6700 	if ((mac_addr >> 16) == 0x484b) {
6701 		ether_addr[0] = (uint8_t)(mac_addr >> 8);
6702 		ether_addr[1] = (uint8_t)mac_addr;
6703 		mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB);
6704 		ether_addr[2] = (uint8_t)(mac_addr >> 24);
6705 		ether_addr[3] = (uint8_t)(mac_addr >> 16);
6706 		ether_addr[4] = (uint8_t)(mac_addr >> 8);
6707 		ether_addr[5] = (uint8_t)mac_addr;
6708 		return (0);
6709 	}
6710 	return (1);
6711 }
6712 
6713 static int
6714 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
6715 {
6716 	int mac_offset = BGE_EE_MAC_OFFSET;
6717 
6718 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6719 		mac_offset = BGE_EE_MAC_OFFSET_5906;
6720 
6721 	return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
6722 	    ETHER_ADDR_LEN));
6723 }
6724 
6725 static int
6726 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
6727 {
6728 
6729 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6730 		return (1);
6731 
6732 	return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
6733 	   ETHER_ADDR_LEN));
6734 }
6735 
6736 static int
6737 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
6738 {
6739 	static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
6740 		/* NOTE: Order is critical */
6741 		bge_get_eaddr_fw,
6742 		bge_get_eaddr_mem,
6743 		bge_get_eaddr_nvram,
6744 		bge_get_eaddr_eeprom,
6745 		NULL
6746 	};
6747 	const bge_eaddr_fcn_t *func;
6748 
6749 	for (func = bge_eaddr_funcs; *func != NULL; ++func) {
6750 		if ((*func)(sc, eaddr) == 0)
6751 			break;
6752 	}
6753 	return (*func == NULL ? ENXIO : 0);
6754 }
6755 
6756 static uint64_t
6757 bge_get_counter(if_t ifp, ift_counter cnt)
6758 {
6759 	struct bge_softc *sc;
6760 	struct bge_mac_stats *stats;
6761 
6762 	sc = if_getsoftc(ifp);
6763 	if (!BGE_IS_5705_PLUS(sc))
6764 		return (if_get_counter_default(ifp, cnt));
6765 	stats = &sc->bge_mac_stats;
6766 
6767 	switch (cnt) {
6768 	case IFCOUNTER_IERRORS:
6769 		return (stats->NoMoreRxBDs + stats->InputDiscards +
6770 		    stats->InputErrors);
6771 	case IFCOUNTER_COLLISIONS:
6772 		return (stats->etherStatsCollisions);
6773 	default:
6774 		return (if_get_counter_default(ifp, cnt));
6775 	}
6776 }
6777 
6778 #ifdef DEBUGNET
6779 static void
6780 bge_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
6781 {
6782 	struct bge_softc *sc;
6783 
6784 	sc = if_getsoftc(ifp);
6785 	BGE_LOCK(sc);
6786 	/*
6787 	 * There is only one logical receive ring, but it is backed
6788 	 * by two actual rings, for cluster- and jumbo-sized mbufs.
6789 	 * Debugnet expects only one size, so if jumbo is in use,
6790 	 * this says we have two rings of jumbo mbufs, but that's
6791 	 * only a little wasteful.
6792 	 */
6793 	*nrxr = 2;
6794 	*ncl = DEBUGNET_MAX_IN_FLIGHT;
6795 	if ((sc->bge_flags & BGE_FLAG_JUMBO_STD) != 0 &&
6796 	    (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
6797 	    ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)))
6798 		*clsize = MJUM9BYTES;
6799 	else
6800 		*clsize = MCLBYTES;
6801 	BGE_UNLOCK(sc);
6802 }
6803 
6804 static void
6805 bge_debugnet_event(if_t ifp __unused, enum debugnet_ev event __unused)
6806 {
6807 }
6808 
6809 static int
6810 bge_debugnet_transmit(if_t ifp, struct mbuf *m)
6811 {
6812 	struct bge_softc *sc;
6813 	uint32_t prodidx;
6814 	int error;
6815 
6816 	sc = if_getsoftc(ifp);
6817 	if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6818 	    IFF_DRV_RUNNING)
6819 		return (1);
6820 
6821 	prodidx = sc->bge_tx_prodidx;
6822 	error = bge_encap(sc, &m, &prodidx);
6823 	if (error == 0)
6824 		bge_start_tx(sc, prodidx);
6825 	return (error);
6826 }
6827 
6828 static int
6829 bge_debugnet_poll(if_t ifp, int count)
6830 {
6831 	struct bge_softc *sc;
6832 	uint32_t rx_prod, tx_cons;
6833 
6834 	sc = if_getsoftc(ifp);
6835 	if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6836 	    IFF_DRV_RUNNING)
6837 		return (1);
6838 
6839 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6840 	    sc->bge_cdata.bge_status_map,
6841 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6842 
6843 	rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
6844 	tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
6845 
6846 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6847 	    sc->bge_cdata.bge_status_map,
6848 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
6849 
6850 	(void)bge_rxeof(sc, rx_prod, 0);
6851 	bge_txeof(sc, tx_cons);
6852 	return (0);
6853 }
6854 #endif /* DEBUGNET */
6855