14ad7e9b0SAdrian Chadd /*-
24d846d26SWarner Losh * SPDX-License-Identifier: BSD-2-Clause
36e778a7eSPedro F. Giffuni *
4f4a3eb02SAdrian Chadd * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
5f4a3eb02SAdrian Chadd * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com>
68e35bf83SLandon J. Fuller * Copyright (c) 2017 The FreeBSD Foundation
74ad7e9b0SAdrian Chadd * All rights reserved.
84ad7e9b0SAdrian Chadd *
94e96bf3aSLandon J. Fuller * Portions of this software were developed by Landon Fuller
104e96bf3aSLandon J. Fuller * under sponsorship from the FreeBSD Foundation.
118e35bf83SLandon J. Fuller *
124ad7e9b0SAdrian Chadd * Redistribution and use in source and binary forms, with or without
134ad7e9b0SAdrian Chadd * modification, are permitted provided that the following conditions
144ad7e9b0SAdrian Chadd * are met:
154ad7e9b0SAdrian Chadd * 1. Redistributions of source code must retain the above copyright
164ad7e9b0SAdrian Chadd * notice, this list of conditions and the following disclaimer,
174ad7e9b0SAdrian Chadd * without modification.
184ad7e9b0SAdrian Chadd * 2. Redistributions in binary form must reproduce at minimum a disclaimer
194ad7e9b0SAdrian Chadd * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
204ad7e9b0SAdrian Chadd * redistribution must be conditioned upon including a substantially
214ad7e9b0SAdrian Chadd * similar Disclaimer requirement for further binary redistribution.
224ad7e9b0SAdrian Chadd *
234ad7e9b0SAdrian Chadd * NO WARRANTY
244ad7e9b0SAdrian Chadd * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
254ad7e9b0SAdrian Chadd * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
264ad7e9b0SAdrian Chadd * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
274ad7e9b0SAdrian Chadd * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
284ad7e9b0SAdrian Chadd * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
294ad7e9b0SAdrian Chadd * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
304ad7e9b0SAdrian Chadd * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
314ad7e9b0SAdrian Chadd * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
324ad7e9b0SAdrian Chadd * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
334ad7e9b0SAdrian Chadd * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
344ad7e9b0SAdrian Chadd * THE POSSIBILITY OF SUCH DAMAGES.
354ad7e9b0SAdrian Chadd */
364ad7e9b0SAdrian Chadd
374ad7e9b0SAdrian Chadd #include <sys/cdefs.h>
384ad7e9b0SAdrian Chadd /*
394ad7e9b0SAdrian Chadd * Broadcom ChipCommon driver.
404ad7e9b0SAdrian Chadd *
414ad7e9b0SAdrian Chadd * With the exception of some very early chipsets, the ChipCommon core
424ad7e9b0SAdrian Chadd * has been included in all HND SoCs and chipsets based on the siba(4)
434ad7e9b0SAdrian Chadd * and bcma(4) interconnects, providing a common interface to chipset
440c91e892SLandon J. Fuller * identification, bus enumeration, UARTs, clocks, watchdog interrupts,
450c91e892SLandon J. Fuller * GPIO, flash, etc.
464ad7e9b0SAdrian Chadd */
474ad7e9b0SAdrian Chadd
484ad7e9b0SAdrian Chadd #include <sys/param.h>
494ad7e9b0SAdrian Chadd #include <sys/kernel.h>
50f4a3eb02SAdrian Chadd #include <sys/lock.h>
514ad7e9b0SAdrian Chadd #include <sys/bus.h>
52e129bcd6SLandon J. Fuller #include <sys/rman.h>
53f4a3eb02SAdrian Chadd #include <sys/malloc.h>
544ad7e9b0SAdrian Chadd #include <sys/module.h>
55f4a3eb02SAdrian Chadd #include <sys/mutex.h>
564ad7e9b0SAdrian Chadd #include <sys/systm.h>
574ad7e9b0SAdrian Chadd
584ad7e9b0SAdrian Chadd #include <machine/bus.h>
594ad7e9b0SAdrian Chadd #include <machine/resource.h>
604ad7e9b0SAdrian Chadd
614ad7e9b0SAdrian Chadd #include <dev/bhnd/bhnd.h>
62f4a3eb02SAdrian Chadd #include <dev/bhnd/bhndvar.h>
63e83ce340SAdrian Chadd
644ad7e9b0SAdrian Chadd #include "chipcreg.h"
654ad7e9b0SAdrian Chadd #include "chipcvar.h"
660c91e892SLandon J. Fuller
67f4a3eb02SAdrian Chadd #include "chipc_private.h"
684ad7e9b0SAdrian Chadd
6936e4410aSAdrian Chadd static struct bhnd_device_quirk chipc_quirks[];
7036e4410aSAdrian Chadd
714ad7e9b0SAdrian Chadd /* Supported device identifiers */
7236e4410aSAdrian Chadd static const struct bhnd_device chipc_devices[] = {
73b0b9c854SLandon J. Fuller BHND_DEVICE(BCM, CC, NULL, chipc_quirks),
744cb7084eSLandon J. Fuller BHND_DEVICE(BCM, 4706_CC, NULL, chipc_quirks),
7536e4410aSAdrian Chadd BHND_DEVICE_END
764ad7e9b0SAdrian Chadd };
774ad7e9b0SAdrian Chadd
784ad7e9b0SAdrian Chadd /* Device quirks table */
794ad7e9b0SAdrian Chadd static struct bhnd_device_quirk chipc_quirks[] = {
8056a4cdd1SLandon J. Fuller /* HND OTP controller revisions */
8156a4cdd1SLandon J. Fuller BHND_CORE_QUIRK (HWREV_EQ (12), CHIPC_QUIRK_OTP_HND), /* (?) */
8256a4cdd1SLandon J. Fuller BHND_CORE_QUIRK (HWREV_EQ (17), CHIPC_QUIRK_OTP_HND), /* BCM4311 */
8356a4cdd1SLandon J. Fuller BHND_CORE_QUIRK (HWREV_EQ (22), CHIPC_QUIRK_OTP_HND), /* BCM4312 */
8456a4cdd1SLandon J. Fuller
8556a4cdd1SLandon J. Fuller /* IPX OTP controller revisions */
8656a4cdd1SLandon J. Fuller BHND_CORE_QUIRK (HWREV_EQ (21), CHIPC_QUIRK_OTP_IPX),
8756a4cdd1SLandon J. Fuller BHND_CORE_QUIRK (HWREV_GTE(23), CHIPC_QUIRK_OTP_IPX),
8856a4cdd1SLandon J. Fuller
895ad9ac03SAdrian Chadd BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM),
905ad9ac03SAdrian Chadd BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT),
9156a4cdd1SLandon J. Fuller BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPL_SIZE),
925ad9ac03SAdrian Chadd
935ad9ac03SAdrian Chadd /* 4706 variant quirks */
945ad9ac03SAdrian Chadd BHND_CORE_QUIRK (HWREV_EQ (38), CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */
955ad9ac03SAdrian Chadd BHND_CHIP_QUIRK (4706, HWREV_ANY, CHIPC_QUIRK_4706_NFLASH),
965ad9ac03SAdrian Chadd
975ad9ac03SAdrian Chadd /* 4331 quirks*/
985ad9ac03SAdrian Chadd BHND_CHIP_QUIRK (4331, HWREV_ANY, CHIPC_QUIRK_4331_EXTPA_MUX_SPROM),
995ad9ac03SAdrian Chadd BHND_PKG_QUIRK (4331, TN, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM),
1005ad9ac03SAdrian Chadd BHND_PKG_QUIRK (4331, TNA0, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM),
1015ad9ac03SAdrian Chadd BHND_PKG_QUIRK (4331, TT, CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM),
1025ad9ac03SAdrian Chadd
1035ad9ac03SAdrian Chadd /* 4360 quirks */
1045ad9ac03SAdrian Chadd BHND_CHIP_QUIRK (4352, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
1055ad9ac03SAdrian Chadd BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
1065ad9ac03SAdrian Chadd BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
1075ad9ac03SAdrian Chadd BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
108f4a3eb02SAdrian Chadd
10936e4410aSAdrian Chadd BHND_DEVICE_QUIRK_END
1104ad7e9b0SAdrian Chadd };
1114ad7e9b0SAdrian Chadd
1120c91e892SLandon J. Fuller static int chipc_add_children(struct chipc_softc *sc);
113f4a3eb02SAdrian Chadd
11456a4cdd1SLandon J. Fuller static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc,
11556a4cdd1SLandon J. Fuller struct chipc_caps *caps);
116f4a3eb02SAdrian Chadd static int chipc_read_caps(struct chipc_softc *sc,
117f4a3eb02SAdrian Chadd struct chipc_caps *caps);
118f4a3eb02SAdrian Chadd
119f90f4b65SLandon J. Fuller static bool chipc_should_enable_muxed_sprom(
120f4a3eb02SAdrian Chadd struct chipc_softc *sc);
121f90f4b65SLandon J. Fuller static int chipc_enable_otp_power(struct chipc_softc *sc);
122f90f4b65SLandon J. Fuller static void chipc_disable_otp_power(struct chipc_softc *sc);
123f90f4b65SLandon J. Fuller static int chipc_enable_sprom_pins(struct chipc_softc *sc);
124f90f4b65SLandon J. Fuller static void chipc_disable_sprom_pins(struct chipc_softc *sc);
125f4a3eb02SAdrian Chadd
1263a48dfe1SJohn Baldwin static int chipc_try_activate_resource(device_t dev,
1272baed46eSJohn Baldwin device_t child, struct resource *r,
1282baed46eSJohn Baldwin bool req_direct);
1290c91e892SLandon J. Fuller
130f4a3eb02SAdrian Chadd static int chipc_init_rman(struct chipc_softc *sc);
131f4a3eb02SAdrian Chadd static void chipc_free_rman(struct chipc_softc *sc);
1323a48dfe1SJohn Baldwin static struct rman *chipc_get_rman(device_t dev, int type, u_int flags);
133f4a3eb02SAdrian Chadd
1344ad7e9b0SAdrian Chadd /* quirk and capability flag convenience macros */
1354ad7e9b0SAdrian Chadd #define CHIPC_QUIRK(_sc, _name) \
1364ad7e9b0SAdrian Chadd ((_sc)->quirks & CHIPC_QUIRK_ ## _name)
1374ad7e9b0SAdrian Chadd
1384ad7e9b0SAdrian Chadd #define CHIPC_CAP(_sc, _name) \
139f4a3eb02SAdrian Chadd ((_sc)->caps._name)
1404ad7e9b0SAdrian Chadd
1414ad7e9b0SAdrian Chadd #define CHIPC_ASSERT_QUIRK(_sc, name) \
1424ad7e9b0SAdrian Chadd KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set"))
1434ad7e9b0SAdrian Chadd
1444ad7e9b0SAdrian Chadd #define CHIPC_ASSERT_CAP(_sc, name) \
1454ad7e9b0SAdrian Chadd KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set"))
1464ad7e9b0SAdrian Chadd
1474ad7e9b0SAdrian Chadd static int
chipc_probe(device_t dev)1484ad7e9b0SAdrian Chadd chipc_probe(device_t dev)
1494ad7e9b0SAdrian Chadd {
15036e4410aSAdrian Chadd const struct bhnd_device *id;
1514ad7e9b0SAdrian Chadd
15236e4410aSAdrian Chadd id = bhnd_device_lookup(dev, chipc_devices, sizeof(chipc_devices[0]));
15336e4410aSAdrian Chadd if (id == NULL)
1544ad7e9b0SAdrian Chadd return (ENXIO);
15536e4410aSAdrian Chadd
15636e4410aSAdrian Chadd bhnd_set_default_core_desc(dev);
15736e4410aSAdrian Chadd return (BUS_PROBE_DEFAULT);
1584ad7e9b0SAdrian Chadd }
1594ad7e9b0SAdrian Chadd
1604ad7e9b0SAdrian Chadd static int
chipc_attach(device_t dev)1614ad7e9b0SAdrian Chadd chipc_attach(device_t dev)
1624ad7e9b0SAdrian Chadd {
1634ad7e9b0SAdrian Chadd struct chipc_softc *sc;
1644ad7e9b0SAdrian Chadd int error;
1654ad7e9b0SAdrian Chadd
1664ad7e9b0SAdrian Chadd sc = device_get_softc(dev);
1674ad7e9b0SAdrian Chadd sc->dev = dev;
16836e4410aSAdrian Chadd sc->quirks = bhnd_device_quirks(dev, chipc_devices,
16936e4410aSAdrian Chadd sizeof(chipc_devices[0]));
170f4a3eb02SAdrian Chadd sc->sprom_refcnt = 0;
171e83ce340SAdrian Chadd
172e83ce340SAdrian Chadd CHIPC_LOCK_INIT(sc);
173f4a3eb02SAdrian Chadd STAILQ_INIT(&sc->mem_regions);
1744ad7e9b0SAdrian Chadd
175f4a3eb02SAdrian Chadd /* Set up resource management */
176f4a3eb02SAdrian Chadd if ((error = chipc_init_rman(sc))) {
177f4a3eb02SAdrian Chadd device_printf(sc->dev,
178f4a3eb02SAdrian Chadd "failed to initialize chipc resource state: %d\n", error);
179f4a3eb02SAdrian Chadd goto failed;
180f4a3eb02SAdrian Chadd }
1814ad7e9b0SAdrian Chadd
1820c91e892SLandon J. Fuller /* Allocate the region containing the chipc register block */
183f4a3eb02SAdrian Chadd if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) {
184f4a3eb02SAdrian Chadd error = ENXIO;
185f4a3eb02SAdrian Chadd goto failed;
186f4a3eb02SAdrian Chadd }
187f4a3eb02SAdrian Chadd
188f4a3eb02SAdrian Chadd error = chipc_retain_region(sc, sc->core_region,
189f4a3eb02SAdrian Chadd RF_ALLOCATED|RF_ACTIVE);
190f4a3eb02SAdrian Chadd if (error) {
191f4a3eb02SAdrian Chadd sc->core_region = NULL;
192f4a3eb02SAdrian Chadd goto failed;
1930c91e892SLandon J. Fuller }
1940c91e892SLandon J. Fuller
1950c91e892SLandon J. Fuller /* Save a direct reference to our chipc registers */
196f4a3eb02SAdrian Chadd sc->core = sc->core_region->cr_res;
1974ad7e9b0SAdrian Chadd
198f4a3eb02SAdrian Chadd /* Fetch and parse capability register(s) */
199f4a3eb02SAdrian Chadd if ((error = chipc_read_caps(sc, &sc->caps)))
200f4a3eb02SAdrian Chadd goto failed;
2014ad7e9b0SAdrian Chadd
202f4a3eb02SAdrian Chadd if (bootverbose)
203f4a3eb02SAdrian Chadd chipc_print_caps(sc->dev, &sc->caps);
204f4a3eb02SAdrian Chadd
2050c91e892SLandon J. Fuller /* Attach all supported child devices */
2060c91e892SLandon J. Fuller if ((error = chipc_add_children(sc)))
2070c91e892SLandon J. Fuller goto failed;
2080c91e892SLandon J. Fuller
2094e96bf3aSLandon J. Fuller /*
2104e96bf3aSLandon J. Fuller * Register ourselves with the bus; we're fully initialized and can
2114e96bf3aSLandon J. Fuller * response to ChipCommin API requests.
2124e96bf3aSLandon J. Fuller *
2134e96bf3aSLandon J. Fuller * Since our children may need access to ChipCommon, this must be done
2144e96bf3aSLandon J. Fuller * before attaching our children below (via bus_generic_attach).
2154e96bf3aSLandon J. Fuller */
2164e96bf3aSLandon J. Fuller if ((error = bhnd_register_provider(dev, BHND_SERVICE_CHIPC)))
217f4a3eb02SAdrian Chadd goto failed;
2184ad7e9b0SAdrian Chadd
2194e96bf3aSLandon J. Fuller if ((error = bus_generic_attach(dev)))
2208e35bf83SLandon J. Fuller goto failed;
2218e35bf83SLandon J. Fuller
2224ad7e9b0SAdrian Chadd return (0);
2234ad7e9b0SAdrian Chadd
224f4a3eb02SAdrian Chadd failed:
2257d1fb1aaSLandon J. Fuller device_delete_children(sc->dev);
2267d1fb1aaSLandon J. Fuller
227f4a3eb02SAdrian Chadd if (sc->core_region != NULL) {
228f4a3eb02SAdrian Chadd chipc_release_region(sc, sc->core_region,
229f4a3eb02SAdrian Chadd RF_ALLOCATED|RF_ACTIVE);
230f4a3eb02SAdrian Chadd }
231f4a3eb02SAdrian Chadd
232f4a3eb02SAdrian Chadd chipc_free_rman(sc);
233e83ce340SAdrian Chadd CHIPC_LOCK_DESTROY(sc);
2344ad7e9b0SAdrian Chadd return (error);
2354ad7e9b0SAdrian Chadd }
2364ad7e9b0SAdrian Chadd
2374ad7e9b0SAdrian Chadd static int
chipc_detach(device_t dev)2384ad7e9b0SAdrian Chadd chipc_detach(device_t dev)
2394ad7e9b0SAdrian Chadd {
2404ad7e9b0SAdrian Chadd struct chipc_softc *sc;
241f4a3eb02SAdrian Chadd int error;
2424ad7e9b0SAdrian Chadd
2434ad7e9b0SAdrian Chadd sc = device_get_softc(dev);
244f4a3eb02SAdrian Chadd
24519b3e4aaSLandon J. Fuller if ((error = bus_generic_detach(dev)))
2468e35bf83SLandon J. Fuller return (error);
2478e35bf83SLandon J. Fuller
248f248a99aSLandon J. Fuller if ((error = device_delete_children(dev)))
249f248a99aSLandon J. Fuller return (error);
250f248a99aSLandon J. Fuller
25119b3e4aaSLandon J. Fuller if ((error = bhnd_deregister_provider(dev, BHND_SERVICE_ANY)))
252f4a3eb02SAdrian Chadd return (error);
253f4a3eb02SAdrian Chadd
254f4a3eb02SAdrian Chadd chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE);
255f4a3eb02SAdrian Chadd chipc_free_rman(sc);
256e83ce340SAdrian Chadd
257e83ce340SAdrian Chadd CHIPC_LOCK_DESTROY(sc);
2584ad7e9b0SAdrian Chadd
2594ad7e9b0SAdrian Chadd return (0);
2604ad7e9b0SAdrian Chadd }
2614ad7e9b0SAdrian Chadd
2620c91e892SLandon J. Fuller static int
chipc_add_children(struct chipc_softc * sc)2630c91e892SLandon J. Fuller chipc_add_children(struct chipc_softc *sc)
2640c91e892SLandon J. Fuller {
2650c91e892SLandon J. Fuller device_t child;
2660c91e892SLandon J. Fuller const char *flash_bus;
2670c91e892SLandon J. Fuller int error;
2680c91e892SLandon J. Fuller
2690c91e892SLandon J. Fuller /* SPROM/OTP */
2700c91e892SLandon J. Fuller if (sc->caps.nvram_src == BHND_NVRAM_SRC_SPROM ||
2710c91e892SLandon J. Fuller sc->caps.nvram_src == BHND_NVRAM_SRC_OTP)
2720c91e892SLandon J. Fuller {
2730c91e892SLandon J. Fuller child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_nvram", -1);
2740c91e892SLandon J. Fuller if (child == NULL) {
2750c91e892SLandon J. Fuller device_printf(sc->dev, "failed to add nvram device\n");
2760c91e892SLandon J. Fuller return (ENXIO);
2770c91e892SLandon J. Fuller }
2780c91e892SLandon J. Fuller
2790c91e892SLandon J. Fuller /* Both OTP and external SPROM are mapped at CHIPC_SPROM_OTP */
280caeff9a3SLandon J. Fuller error = chipc_set_mem_resource(sc, child, 0, CHIPC_SPROM_OTP,
281caeff9a3SLandon J. Fuller CHIPC_SPROM_OTP_SIZE, 0, 0);
282caeff9a3SLandon J. Fuller if (error) {
283caeff9a3SLandon J. Fuller device_printf(sc->dev, "failed to set OTP memory "
284caeff9a3SLandon J. Fuller "resource: %d\n", error);
2850c91e892SLandon J. Fuller return (error);
2860c91e892SLandon J. Fuller }
287caeff9a3SLandon J. Fuller }
2880c91e892SLandon J. Fuller
2890c91e892SLandon J. Fuller /*
290f90f4b65SLandon J. Fuller * PMU/PWR_CTRL
2910c91e892SLandon J. Fuller *
292f90f4b65SLandon J. Fuller * On AOB ("Always on Bus") devices, the PMU core (if it exists) is
293f90f4b65SLandon J. Fuller * attached directly to the bhnd(4) bus -- not chipc.
2940c91e892SLandon J. Fuller */
2954e96bf3aSLandon J. Fuller if (sc->caps.pmu && !sc->caps.aob) {
2965ad00fa2SLandon J. Fuller child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pmu", -1);
2970c91e892SLandon J. Fuller if (child == NULL) {
2980c91e892SLandon J. Fuller device_printf(sc->dev, "failed to add pmu\n");
2990c91e892SLandon J. Fuller return (ENXIO);
3000c91e892SLandon J. Fuller }
3014e96bf3aSLandon J. Fuller } else if (sc->caps.pwr_ctrl) {
3025ad00fa2SLandon J. Fuller child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pwrctl", -1);
3034e96bf3aSLandon J. Fuller if (child == NULL) {
3044e96bf3aSLandon J. Fuller device_printf(sc->dev, "failed to add pwrctl\n");
3054e96bf3aSLandon J. Fuller return (ENXIO);
3064e96bf3aSLandon J. Fuller }
3070c91e892SLandon J. Fuller }
3080c91e892SLandon J. Fuller
3092f909a9fSLandon J. Fuller /* GPIO */
3105ad00fa2SLandon J. Fuller child = BUS_ADD_CHILD(sc->dev, 0, "gpio", -1);
3112f909a9fSLandon J. Fuller if (child == NULL) {
3122f909a9fSLandon J. Fuller device_printf(sc->dev, "failed to add gpio\n");
3132f909a9fSLandon J. Fuller return (ENXIO);
3142f909a9fSLandon J. Fuller }
3152f909a9fSLandon J. Fuller
3162f909a9fSLandon J. Fuller error = chipc_set_mem_resource(sc, child, 0, 0, RM_MAX_END, 0, 0);
3172f909a9fSLandon J. Fuller if (error) {
3182f909a9fSLandon J. Fuller device_printf(sc->dev, "failed to set gpio memory resource: "
3192f909a9fSLandon J. Fuller "%d\n", error);
3202f909a9fSLandon J. Fuller return (error);
3212f909a9fSLandon J. Fuller }
3222f909a9fSLandon J. Fuller
3230c91e892SLandon J. Fuller /* All remaining devices are SoC-only */
3240c91e892SLandon J. Fuller if (bhnd_get_attach_type(sc->dev) != BHND_ATTACH_NATIVE)
3250c91e892SLandon J. Fuller return (0);
3260c91e892SLandon J. Fuller
3270c91e892SLandon J. Fuller /* UARTs */
3280c91e892SLandon J. Fuller for (u_int i = 0; i < min(sc->caps.num_uarts, CHIPC_UART_MAX); i++) {
329caeff9a3SLandon J. Fuller int irq_rid, mem_rid;
330caeff9a3SLandon J. Fuller
331caeff9a3SLandon J. Fuller irq_rid = 0;
332caeff9a3SLandon J. Fuller mem_rid = 0;
333caeff9a3SLandon J. Fuller
3340c91e892SLandon J. Fuller child = BUS_ADD_CHILD(sc->dev, 0, "uart", -1);
3350c91e892SLandon J. Fuller if (child == NULL) {
3360c91e892SLandon J. Fuller device_printf(sc->dev, "failed to add uart%u\n", i);
3370c91e892SLandon J. Fuller return (ENXIO);
3380c91e892SLandon J. Fuller }
3390c91e892SLandon J. Fuller
3400c91e892SLandon J. Fuller /* Shared IRQ */
341caeff9a3SLandon J. Fuller error = chipc_set_irq_resource(sc, child, irq_rid, 0);
3420c91e892SLandon J. Fuller if (error) {
3430c91e892SLandon J. Fuller device_printf(sc->dev, "failed to set uart%u irq %u\n",
344caeff9a3SLandon J. Fuller i, 0);
3450c91e892SLandon J. Fuller return (error);
3460c91e892SLandon J. Fuller }
3470c91e892SLandon J. Fuller
3480c91e892SLandon J. Fuller /* UART registers are mapped sequentially */
349caeff9a3SLandon J. Fuller error = chipc_set_mem_resource(sc, child, mem_rid,
3500c91e892SLandon J. Fuller CHIPC_UART(i), CHIPC_UART_SIZE, 0, 0);
351caeff9a3SLandon J. Fuller if (error) {
352caeff9a3SLandon J. Fuller device_printf(sc->dev, "failed to set uart%u memory "
353caeff9a3SLandon J. Fuller "resource: %d\n", i, error);
3540c91e892SLandon J. Fuller return (error);
3550c91e892SLandon J. Fuller }
356caeff9a3SLandon J. Fuller }
3570c91e892SLandon J. Fuller
3580c91e892SLandon J. Fuller /* Flash */
3590c91e892SLandon J. Fuller flash_bus = chipc_flash_bus_name(sc->caps.flash_type);
3600c91e892SLandon J. Fuller if (flash_bus != NULL) {
361caeff9a3SLandon J. Fuller int rid;
362caeff9a3SLandon J. Fuller
3630c91e892SLandon J. Fuller child = BUS_ADD_CHILD(sc->dev, 0, flash_bus, -1);
3640c91e892SLandon J. Fuller if (child == NULL) {
3650c91e892SLandon J. Fuller device_printf(sc->dev, "failed to add %s device\n",
3660c91e892SLandon J. Fuller flash_bus);
3670c91e892SLandon J. Fuller return (ENXIO);
3680c91e892SLandon J. Fuller }
3690c91e892SLandon J. Fuller
3700c91e892SLandon J. Fuller /* flash memory mapping */
371caeff9a3SLandon J. Fuller rid = 0;
372caeff9a3SLandon J. Fuller error = chipc_set_mem_resource(sc, child, rid, 0, RM_MAX_END, 1,
373caeff9a3SLandon J. Fuller 1);
374caeff9a3SLandon J. Fuller if (error) {
375caeff9a3SLandon J. Fuller device_printf(sc->dev, "failed to set flash memory "
376caeff9a3SLandon J. Fuller "resource %d: %d\n", rid, error);
3770c91e892SLandon J. Fuller return (error);
378caeff9a3SLandon J. Fuller }
3790c91e892SLandon J. Fuller
3800c91e892SLandon J. Fuller /* flashctrl registers */
381caeff9a3SLandon J. Fuller rid++;
382caeff9a3SLandon J. Fuller error = chipc_set_mem_resource(sc, child, rid,
3830c91e892SLandon J. Fuller CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0, 0);
384caeff9a3SLandon J. Fuller if (error) {
385caeff9a3SLandon J. Fuller device_printf(sc->dev, "failed to set flash memory "
386caeff9a3SLandon J. Fuller "resource %d: %d\n", rid, error);
3870c91e892SLandon J. Fuller return (error);
3880c91e892SLandon J. Fuller }
389caeff9a3SLandon J. Fuller }
3900c91e892SLandon J. Fuller
3910c91e892SLandon J. Fuller return (0);
3920c91e892SLandon J. Fuller }
3930c91e892SLandon J. Fuller
39456a4cdd1SLandon J. Fuller /**
39556a4cdd1SLandon J. Fuller * Determine the NVRAM data source for this device.
39656a4cdd1SLandon J. Fuller *
39756a4cdd1SLandon J. Fuller * The SPROM, OTP, and flash capability flags must be fully populated in
39856a4cdd1SLandon J. Fuller * @p caps.
39956a4cdd1SLandon J. Fuller *
40056a4cdd1SLandon J. Fuller * @param sc chipc driver state.
40156a4cdd1SLandon J. Fuller * @param caps capability flags to be used to derive NVRAM configuration.
40256a4cdd1SLandon J. Fuller */
40356a4cdd1SLandon J. Fuller static bhnd_nvram_src
chipc_find_nvram_src(struct chipc_softc * sc,struct chipc_caps * caps)40456a4cdd1SLandon J. Fuller chipc_find_nvram_src(struct chipc_softc *sc, struct chipc_caps *caps)
40556a4cdd1SLandon J. Fuller {
40656a4cdd1SLandon J. Fuller uint32_t otp_st, srom_ctrl;
40756a4cdd1SLandon J. Fuller
40856a4cdd1SLandon J. Fuller /*
40956a4cdd1SLandon J. Fuller * We check for hardware presence in order of precedence. For example,
410060f5c02SGordon Bergling * SPROM is always used in preference to internal OTP if found.
41156a4cdd1SLandon J. Fuller */
4121728aef2SLandon J. Fuller if (CHIPC_QUIRK(sc, SUPPORTS_SPROM) && caps->sprom) {
41356a4cdd1SLandon J. Fuller srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL);
41456a4cdd1SLandon J. Fuller if (srom_ctrl & CHIPC_SRC_PRESENT)
41556a4cdd1SLandon J. Fuller return (BHND_NVRAM_SRC_SPROM);
41656a4cdd1SLandon J. Fuller }
41756a4cdd1SLandon J. Fuller
41856a4cdd1SLandon J. Fuller /* Check for programmed OTP H/W subregion (contains SROM data) */
41956a4cdd1SLandon J. Fuller if (CHIPC_QUIRK(sc, SUPPORTS_OTP) && caps->otp_size > 0) {
42056a4cdd1SLandon J. Fuller /* TODO: need access to HND-OTP device */
42156a4cdd1SLandon J. Fuller if (!CHIPC_QUIRK(sc, OTP_HND)) {
42256a4cdd1SLandon J. Fuller device_printf(sc->dev,
42356a4cdd1SLandon J. Fuller "NVRAM unavailable: unsupported OTP controller.\n");
42456a4cdd1SLandon J. Fuller return (BHND_NVRAM_SRC_UNKNOWN);
42556a4cdd1SLandon J. Fuller }
42656a4cdd1SLandon J. Fuller
42756a4cdd1SLandon J. Fuller otp_st = bhnd_bus_read_4(sc->core, CHIPC_OTPST);
42856a4cdd1SLandon J. Fuller if (otp_st & CHIPC_OTPS_GUP_HW)
42956a4cdd1SLandon J. Fuller return (BHND_NVRAM_SRC_OTP);
43056a4cdd1SLandon J. Fuller }
43156a4cdd1SLandon J. Fuller
43256a4cdd1SLandon J. Fuller /* Check for flash */
43356a4cdd1SLandon J. Fuller if (caps->flash_type != CHIPC_FLASH_NONE)
43456a4cdd1SLandon J. Fuller return (BHND_NVRAM_SRC_FLASH);
43556a4cdd1SLandon J. Fuller
43656a4cdd1SLandon J. Fuller /* No NVRAM hardware capability declared */
43756a4cdd1SLandon J. Fuller return (BHND_NVRAM_SRC_UNKNOWN);
43856a4cdd1SLandon J. Fuller }
43956a4cdd1SLandon J. Fuller
440f4a3eb02SAdrian Chadd /* Read and parse chipc capabilities */
4414ad7e9b0SAdrian Chadd static int
chipc_read_caps(struct chipc_softc * sc,struct chipc_caps * caps)442f4a3eb02SAdrian Chadd chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps)
4434ad7e9b0SAdrian Chadd {
444f4a3eb02SAdrian Chadd uint32_t cap_reg;
445f4a3eb02SAdrian Chadd uint32_t cap_ext_reg;
446f4a3eb02SAdrian Chadd uint32_t regval;
447f4a3eb02SAdrian Chadd
448f4a3eb02SAdrian Chadd /* Fetch cap registers */
449f4a3eb02SAdrian Chadd cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES);
450f4a3eb02SAdrian Chadd cap_ext_reg = 0;
451f4a3eb02SAdrian Chadd if (CHIPC_QUIRK(sc, SUPPORTS_CAP_EXT))
452f4a3eb02SAdrian Chadd cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT);
453f4a3eb02SAdrian Chadd
454f4a3eb02SAdrian Chadd /* Extract values */
455f4a3eb02SAdrian Chadd caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART);
456f4a3eb02SAdrian Chadd caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB);
457f4a3eb02SAdrian Chadd caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO);
458f4a3eb02SAdrian Chadd caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL);
459f4a3eb02SAdrian Chadd
460f4a3eb02SAdrian Chadd caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS);
461f90f4b65SLandon J. Fuller caps->pwr_ctrl = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL);
462f4a3eb02SAdrian Chadd caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP);
463f4a3eb02SAdrian Chadd
464f4a3eb02SAdrian Chadd caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL);
465f4a3eb02SAdrian Chadd caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64);
466f4a3eb02SAdrian Chadd caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM);
467f4a3eb02SAdrian Chadd caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU);
468f4a3eb02SAdrian Chadd caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI);
469f4a3eb02SAdrian Chadd caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM);
470f4a3eb02SAdrian Chadd caps->otp_size = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_OTP_SIZE);
471f4a3eb02SAdrian Chadd
472f4a3eb02SAdrian Chadd caps->seci = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_SECI);
473f4a3eb02SAdrian Chadd caps->gsio = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_GSIO);
474f4a3eb02SAdrian Chadd caps->aob = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_AOB);
475f4a3eb02SAdrian Chadd
476f4a3eb02SAdrian Chadd /* Fetch OTP size for later IPX controller revisions */
47756a4cdd1SLandon J. Fuller if (CHIPC_QUIRK(sc, IPX_OTPL_SIZE)) {
478f4a3eb02SAdrian Chadd regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT);
479f4a3eb02SAdrian Chadd caps->otp_size = CHIPC_GET_BITS(regval, CHIPC_OTPL_SIZE);
4804ad7e9b0SAdrian Chadd }
4814ad7e9b0SAdrian Chadd
4825ad9ac03SAdrian Chadd /* Determine flash type and parameters */
483f4a3eb02SAdrian Chadd caps->cfi_width = 0;
484f4a3eb02SAdrian Chadd switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) {
485f4a3eb02SAdrian Chadd case CHIPC_CAP_SFLASH_ST:
486f4a3eb02SAdrian Chadd caps->flash_type = CHIPC_SFLASH_ST;
487f4a3eb02SAdrian Chadd break;
488f4a3eb02SAdrian Chadd case CHIPC_CAP_SFLASH_AT:
489f4a3eb02SAdrian Chadd caps->flash_type = CHIPC_SFLASH_AT;
490f4a3eb02SAdrian Chadd break;
491f4a3eb02SAdrian Chadd case CHIPC_CAP_NFLASH:
4920c91e892SLandon J. Fuller /* unimplemented */
493f4a3eb02SAdrian Chadd caps->flash_type = CHIPC_NFLASH;
494f4a3eb02SAdrian Chadd break;
495f4a3eb02SAdrian Chadd case CHIPC_CAP_PFLASH:
496f4a3eb02SAdrian Chadd caps->flash_type = CHIPC_PFLASH_CFI;
497f4a3eb02SAdrian Chadd
498f4a3eb02SAdrian Chadd /* determine cfi width */
499f4a3eb02SAdrian Chadd regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG);
500f4a3eb02SAdrian Chadd if (CHIPC_GET_FLAG(regval, CHIPC_FLASH_CFG_DS))
501f4a3eb02SAdrian Chadd caps->cfi_width = 2;
502f4a3eb02SAdrian Chadd else
503f4a3eb02SAdrian Chadd caps->cfi_width = 1;
504f4a3eb02SAdrian Chadd
505f4a3eb02SAdrian Chadd break;
506f4a3eb02SAdrian Chadd case CHIPC_CAP_FLASH_NONE:
507f4a3eb02SAdrian Chadd caps->flash_type = CHIPC_FLASH_NONE;
508f4a3eb02SAdrian Chadd break;
509f4a3eb02SAdrian Chadd
510f4a3eb02SAdrian Chadd }
511f4a3eb02SAdrian Chadd
512f4a3eb02SAdrian Chadd /* Handle 4706_NFLASH fallback */
513f4a3eb02SAdrian Chadd if (CHIPC_QUIRK(sc, 4706_NFLASH) &&
514f4a3eb02SAdrian Chadd CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_4706_NFLASH))
5154ad7e9b0SAdrian Chadd {
516f4a3eb02SAdrian Chadd caps->flash_type = CHIPC_NFLASH_4706;
517f4a3eb02SAdrian Chadd }
518f4a3eb02SAdrian Chadd
51956a4cdd1SLandon J. Fuller /* Determine NVRAM source. Must occur after the SPROM/OTP/flash
52056a4cdd1SLandon J. Fuller * capability flags have been populated. */
52156a4cdd1SLandon J. Fuller caps->nvram_src = chipc_find_nvram_src(sc, caps);
52256a4cdd1SLandon J. Fuller
52356a4cdd1SLandon J. Fuller /* Determine the SPROM offset within OTP (if any). SPROM-formatted
52456a4cdd1SLandon J. Fuller * data is placed within the OTP general use region. */
52556a4cdd1SLandon J. Fuller caps->sprom_offset = 0;
52656a4cdd1SLandon J. Fuller if (caps->nvram_src == BHND_NVRAM_SRC_OTP) {
52756a4cdd1SLandon J. Fuller CHIPC_ASSERT_QUIRK(sc, OTP_IPX);
52856a4cdd1SLandon J. Fuller
52956a4cdd1SLandon J. Fuller /* Bit offset to GUP HW subregion containing SPROM data */
53056a4cdd1SLandon J. Fuller regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT);
53156a4cdd1SLandon J. Fuller caps->sprom_offset = CHIPC_GET_BITS(regval, CHIPC_OTPL_GUP);
53256a4cdd1SLandon J. Fuller
53356a4cdd1SLandon J. Fuller /* Convert to bytes */
53456a4cdd1SLandon J. Fuller caps->sprom_offset /= 8;
53556a4cdd1SLandon J. Fuller }
53656a4cdd1SLandon J. Fuller
5374ad7e9b0SAdrian Chadd return (0);
5384ad7e9b0SAdrian Chadd }
5394ad7e9b0SAdrian Chadd
540f4a3eb02SAdrian Chadd static int
chipc_suspend(device_t dev)541f4a3eb02SAdrian Chadd chipc_suspend(device_t dev)
542f4a3eb02SAdrian Chadd {
543f4a3eb02SAdrian Chadd return (bus_generic_suspend(dev));
544f4a3eb02SAdrian Chadd }
545f4a3eb02SAdrian Chadd
546f4a3eb02SAdrian Chadd static int
chipc_resume(device_t dev)547f4a3eb02SAdrian Chadd chipc_resume(device_t dev)
548f4a3eb02SAdrian Chadd {
549f4a3eb02SAdrian Chadd return (bus_generic_resume(dev));
550f4a3eb02SAdrian Chadd }
551f4a3eb02SAdrian Chadd
552f4a3eb02SAdrian Chadd static void
chipc_probe_nomatch(device_t dev,device_t child)553f4a3eb02SAdrian Chadd chipc_probe_nomatch(device_t dev, device_t child)
554f4a3eb02SAdrian Chadd {
555f4a3eb02SAdrian Chadd struct resource_list *rl;
556f4a3eb02SAdrian Chadd const char *name;
557f4a3eb02SAdrian Chadd
558f4a3eb02SAdrian Chadd name = device_get_name(child);
559f4a3eb02SAdrian Chadd if (name == NULL)
560f4a3eb02SAdrian Chadd name = "unknown device";
561f4a3eb02SAdrian Chadd
562f4a3eb02SAdrian Chadd device_printf(dev, "<%s> at", name);
563f4a3eb02SAdrian Chadd
564f4a3eb02SAdrian Chadd rl = BUS_GET_RESOURCE_LIST(dev, child);
565f4a3eb02SAdrian Chadd if (rl != NULL) {
566f4a3eb02SAdrian Chadd resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx");
567f4a3eb02SAdrian Chadd resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd");
568f4a3eb02SAdrian Chadd }
569f4a3eb02SAdrian Chadd
570f4a3eb02SAdrian Chadd printf(" (no driver attached)\n");
571f4a3eb02SAdrian Chadd }
572f4a3eb02SAdrian Chadd
573f4a3eb02SAdrian Chadd static int
chipc_print_child(device_t dev,device_t child)574f4a3eb02SAdrian Chadd chipc_print_child(device_t dev, device_t child)
575f4a3eb02SAdrian Chadd {
576f4a3eb02SAdrian Chadd struct resource_list *rl;
577f4a3eb02SAdrian Chadd int retval = 0;
578f4a3eb02SAdrian Chadd
579f4a3eb02SAdrian Chadd retval += bus_print_child_header(dev, child);
580f4a3eb02SAdrian Chadd
581f4a3eb02SAdrian Chadd rl = BUS_GET_RESOURCE_LIST(dev, child);
582f4a3eb02SAdrian Chadd if (rl != NULL) {
583f4a3eb02SAdrian Chadd retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY,
584f4a3eb02SAdrian Chadd "%#jx");
585f4a3eb02SAdrian Chadd retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ,
586f4a3eb02SAdrian Chadd "%jd");
587f4a3eb02SAdrian Chadd }
588f4a3eb02SAdrian Chadd
589f4a3eb02SAdrian Chadd retval += bus_print_child_domain(dev, child);
590f4a3eb02SAdrian Chadd retval += bus_print_child_footer(dev, child);
591f4a3eb02SAdrian Chadd
592f4a3eb02SAdrian Chadd return (retval);
593f4a3eb02SAdrian Chadd }
594f4a3eb02SAdrian Chadd
595f4a3eb02SAdrian Chadd static device_t
chipc_add_child(device_t dev,u_int order,const char * name,int unit)596f4a3eb02SAdrian Chadd chipc_add_child(device_t dev, u_int order, const char *name, int unit)
597f4a3eb02SAdrian Chadd {
598f4a3eb02SAdrian Chadd struct chipc_devinfo *dinfo;
599f4a3eb02SAdrian Chadd device_t child;
6000c91e892SLandon J. Fuller
601f4a3eb02SAdrian Chadd child = device_add_child_ordered(dev, order, name, unit);
602f4a3eb02SAdrian Chadd if (child == NULL)
603f4a3eb02SAdrian Chadd return (NULL);
604f4a3eb02SAdrian Chadd
605f4a3eb02SAdrian Chadd dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT);
606f4a3eb02SAdrian Chadd if (dinfo == NULL) {
607f4a3eb02SAdrian Chadd device_delete_child(dev, child);
608f4a3eb02SAdrian Chadd return (NULL);
609f4a3eb02SAdrian Chadd }
610f4a3eb02SAdrian Chadd
611f4a3eb02SAdrian Chadd resource_list_init(&dinfo->resources);
612caeff9a3SLandon J. Fuller dinfo->irq_mapped = false;
613f4a3eb02SAdrian Chadd device_set_ivars(child, dinfo);
614f4a3eb02SAdrian Chadd
615f4a3eb02SAdrian Chadd return (child);
616f4a3eb02SAdrian Chadd }
617f4a3eb02SAdrian Chadd
618f4a3eb02SAdrian Chadd static void
chipc_child_deleted(device_t dev,device_t child)619f4a3eb02SAdrian Chadd chipc_child_deleted(device_t dev, device_t child)
620f4a3eb02SAdrian Chadd {
621f4a3eb02SAdrian Chadd struct chipc_devinfo *dinfo = device_get_ivars(child);
622f4a3eb02SAdrian Chadd
623f4a3eb02SAdrian Chadd if (dinfo != NULL) {
624caeff9a3SLandon J. Fuller /* Free the child's resource list */
625f4a3eb02SAdrian Chadd resource_list_free(&dinfo->resources);
626caeff9a3SLandon J. Fuller
627caeff9a3SLandon J. Fuller /* Unmap the child's IRQ */
628caeff9a3SLandon J. Fuller if (dinfo->irq_mapped) {
629caeff9a3SLandon J. Fuller bhnd_unmap_intr(dev, dinfo->irq);
630caeff9a3SLandon J. Fuller dinfo->irq_mapped = false;
631caeff9a3SLandon J. Fuller }
632caeff9a3SLandon J. Fuller
633f4a3eb02SAdrian Chadd free(dinfo, M_BHND);
634f4a3eb02SAdrian Chadd }
635f4a3eb02SAdrian Chadd
636f4a3eb02SAdrian Chadd device_set_ivars(child, NULL);
637f4a3eb02SAdrian Chadd }
638f4a3eb02SAdrian Chadd
639f4a3eb02SAdrian Chadd static struct resource_list *
chipc_get_resource_list(device_t dev,device_t child)640f4a3eb02SAdrian Chadd chipc_get_resource_list(device_t dev, device_t child)
641f4a3eb02SAdrian Chadd {
642f4a3eb02SAdrian Chadd struct chipc_devinfo *dinfo = device_get_ivars(child);
643f4a3eb02SAdrian Chadd return (&dinfo->resources);
644f4a3eb02SAdrian Chadd }
645f4a3eb02SAdrian Chadd
646f4a3eb02SAdrian Chadd /* Allocate region records for the given port, and add the port's memory
647f4a3eb02SAdrian Chadd * range to the mem_rman */
648f4a3eb02SAdrian Chadd static int
chipc_rman_init_regions(struct chipc_softc * sc,bhnd_port_type type,u_int port)649f4a3eb02SAdrian Chadd chipc_rman_init_regions (struct chipc_softc *sc, bhnd_port_type type,
650f4a3eb02SAdrian Chadd u_int port)
651f4a3eb02SAdrian Chadd {
652f4a3eb02SAdrian Chadd struct chipc_region *cr;
653f4a3eb02SAdrian Chadd rman_res_t start, end;
654f4a3eb02SAdrian Chadd u_int num_regions;
655f4a3eb02SAdrian Chadd int error;
656f4a3eb02SAdrian Chadd
6570c91e892SLandon J. Fuller num_regions = bhnd_get_region_count(sc->dev, type, port);
658f4a3eb02SAdrian Chadd for (u_int region = 0; region < num_regions; region++) {
659f4a3eb02SAdrian Chadd /* Allocate new region record */
660f4a3eb02SAdrian Chadd cr = chipc_alloc_region(sc, type, port, region);
661f4a3eb02SAdrian Chadd if (cr == NULL)
662f4a3eb02SAdrian Chadd return (ENODEV);
663f4a3eb02SAdrian Chadd
664f4a3eb02SAdrian Chadd /* Can't manage regions that cannot be allocated */
665f4a3eb02SAdrian Chadd if (cr->cr_rid < 0) {
666f4a3eb02SAdrian Chadd BHND_DEBUG_DEV(sc->dev, "no rid for chipc region "
667f4a3eb02SAdrian Chadd "%s%u.%u", bhnd_port_type_name(type), port, region);
668f4a3eb02SAdrian Chadd chipc_free_region(sc, cr);
669f4a3eb02SAdrian Chadd continue;
670f4a3eb02SAdrian Chadd }
671f4a3eb02SAdrian Chadd
672f4a3eb02SAdrian Chadd /* Add to rman's managed range */
673f4a3eb02SAdrian Chadd start = cr->cr_addr;
674f4a3eb02SAdrian Chadd end = cr->cr_end;
675f4a3eb02SAdrian Chadd if ((error = rman_manage_region(&sc->mem_rman, start, end))) {
676f4a3eb02SAdrian Chadd chipc_free_region(sc, cr);
677f4a3eb02SAdrian Chadd return (error);
678f4a3eb02SAdrian Chadd }
679f4a3eb02SAdrian Chadd
680f4a3eb02SAdrian Chadd /* Add to region list */
681f4a3eb02SAdrian Chadd STAILQ_INSERT_TAIL(&sc->mem_regions, cr, cr_link);
682f4a3eb02SAdrian Chadd }
683f4a3eb02SAdrian Chadd
684f4a3eb02SAdrian Chadd return (0);
685f4a3eb02SAdrian Chadd }
686f4a3eb02SAdrian Chadd
687f4a3eb02SAdrian Chadd /* Initialize memory state for all chipc port regions */
688f4a3eb02SAdrian Chadd static int
chipc_init_rman(struct chipc_softc * sc)689f4a3eb02SAdrian Chadd chipc_init_rman(struct chipc_softc *sc)
690f4a3eb02SAdrian Chadd {
691f4a3eb02SAdrian Chadd u_int num_ports;
692f4a3eb02SAdrian Chadd int error;
693f4a3eb02SAdrian Chadd
694f4a3eb02SAdrian Chadd /* Port types for which we'll register chipc_region mappings */
695f4a3eb02SAdrian Chadd bhnd_port_type types[] = {
696f4a3eb02SAdrian Chadd BHND_PORT_DEVICE
697f4a3eb02SAdrian Chadd };
698f4a3eb02SAdrian Chadd
699f4a3eb02SAdrian Chadd /* Initialize resource manager */
700f4a3eb02SAdrian Chadd sc->mem_rman.rm_start = 0;
701f4a3eb02SAdrian Chadd sc->mem_rman.rm_end = BUS_SPACE_MAXADDR;
702f4a3eb02SAdrian Chadd sc->mem_rman.rm_type = RMAN_ARRAY;
703f4a3eb02SAdrian Chadd sc->mem_rman.rm_descr = "ChipCommon Device Memory";
704f4a3eb02SAdrian Chadd if ((error = rman_init(&sc->mem_rman))) {
705f4a3eb02SAdrian Chadd device_printf(sc->dev, "could not initialize mem_rman: %d\n",
706f4a3eb02SAdrian Chadd error);
707f4a3eb02SAdrian Chadd return (error);
708f4a3eb02SAdrian Chadd }
709f4a3eb02SAdrian Chadd
710f4a3eb02SAdrian Chadd /* Populate per-port-region state */
711f4a3eb02SAdrian Chadd for (u_int i = 0; i < nitems(types); i++) {
712f4a3eb02SAdrian Chadd num_ports = bhnd_get_port_count(sc->dev, types[i]);
713f4a3eb02SAdrian Chadd for (u_int port = 0; port < num_ports; port++) {
714f4a3eb02SAdrian Chadd error = chipc_rman_init_regions(sc, types[i], port);
715f4a3eb02SAdrian Chadd if (error) {
716f4a3eb02SAdrian Chadd device_printf(sc->dev,
717f4a3eb02SAdrian Chadd "region init failed for %s%u: %d\n",
718f4a3eb02SAdrian Chadd bhnd_port_type_name(types[i]), port,
719f4a3eb02SAdrian Chadd error);
720f4a3eb02SAdrian Chadd
721f4a3eb02SAdrian Chadd goto failed;
722f4a3eb02SAdrian Chadd }
723f4a3eb02SAdrian Chadd }
724f4a3eb02SAdrian Chadd }
725f4a3eb02SAdrian Chadd
726f4a3eb02SAdrian Chadd return (0);
727f4a3eb02SAdrian Chadd
728f4a3eb02SAdrian Chadd failed:
729f4a3eb02SAdrian Chadd chipc_free_rman(sc);
730f4a3eb02SAdrian Chadd return (error);
731f4a3eb02SAdrian Chadd }
732f4a3eb02SAdrian Chadd
733f4a3eb02SAdrian Chadd /* Free memory management state */
734f4a3eb02SAdrian Chadd static void
chipc_free_rman(struct chipc_softc * sc)735f4a3eb02SAdrian Chadd chipc_free_rman(struct chipc_softc *sc)
736f4a3eb02SAdrian Chadd {
737f4a3eb02SAdrian Chadd struct chipc_region *cr, *cr_next;
738f4a3eb02SAdrian Chadd
739f4a3eb02SAdrian Chadd STAILQ_FOREACH_SAFE(cr, &sc->mem_regions, cr_link, cr_next)
740f4a3eb02SAdrian Chadd chipc_free_region(sc, cr);
741f4a3eb02SAdrian Chadd
742f4a3eb02SAdrian Chadd rman_fini(&sc->mem_rman);
743f4a3eb02SAdrian Chadd }
744f4a3eb02SAdrian Chadd
745f4a3eb02SAdrian Chadd /**
746f4a3eb02SAdrian Chadd * Return the rman instance for a given resource @p type, if any.
747f4a3eb02SAdrian Chadd *
748f4a3eb02SAdrian Chadd * @param sc The chipc device state.
749f4a3eb02SAdrian Chadd * @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...)
7503a48dfe1SJohn Baldwin * @param flags Resource flags (e.g. RF_PREFETCHABLE)
751f4a3eb02SAdrian Chadd */
752f4a3eb02SAdrian Chadd static struct rman *
chipc_get_rman(device_t dev,int type,u_int flags)7533a48dfe1SJohn Baldwin chipc_get_rman(device_t dev, int type, u_int flags)
754f4a3eb02SAdrian Chadd {
7553a48dfe1SJohn Baldwin struct chipc_softc *sc = device_get_softc(dev);
7563a48dfe1SJohn Baldwin
757f4a3eb02SAdrian Chadd switch (type) {
758f4a3eb02SAdrian Chadd case SYS_RES_MEMORY:
759f4a3eb02SAdrian Chadd return (&sc->mem_rman);
760f4a3eb02SAdrian Chadd
761f4a3eb02SAdrian Chadd case SYS_RES_IRQ:
762caeff9a3SLandon J. Fuller /* We delegate IRQ resource management to the parent bus */
763f4a3eb02SAdrian Chadd return (NULL);
764f4a3eb02SAdrian Chadd
765f4a3eb02SAdrian Chadd default:
766f4a3eb02SAdrian Chadd return (NULL);
767f4a3eb02SAdrian Chadd };
768f4a3eb02SAdrian Chadd }
769f4a3eb02SAdrian Chadd
770f4a3eb02SAdrian Chadd static struct resource *
chipc_alloc_resource(device_t dev,device_t child,int type,int * rid,rman_res_t start,rman_res_t end,rman_res_t count,u_int flags)771f4a3eb02SAdrian Chadd chipc_alloc_resource(device_t dev, device_t child, int type,
772f4a3eb02SAdrian Chadd int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
773f4a3eb02SAdrian Chadd {
774f4a3eb02SAdrian Chadd struct chipc_softc *sc;
775f4a3eb02SAdrian Chadd struct chipc_region *cr;
776f4a3eb02SAdrian Chadd struct resource_list_entry *rle;
777f4a3eb02SAdrian Chadd struct resource *rv;
778f4a3eb02SAdrian Chadd struct rman *rm;
779f4a3eb02SAdrian Chadd int error;
780f4a3eb02SAdrian Chadd bool passthrough, isdefault;
781f4a3eb02SAdrian Chadd
782f4a3eb02SAdrian Chadd sc = device_get_softc(dev);
783f4a3eb02SAdrian Chadd passthrough = (device_get_parent(child) != dev);
784f4a3eb02SAdrian Chadd isdefault = RMAN_IS_DEFAULT_RANGE(start, end);
785f4a3eb02SAdrian Chadd rle = NULL;
786f4a3eb02SAdrian Chadd
787f4a3eb02SAdrian Chadd /* Fetch the resource manager, delegate request if necessary */
7883a48dfe1SJohn Baldwin rm = chipc_get_rman(dev, type, flags);
789f4a3eb02SAdrian Chadd if (rm == NULL) {
790f4a3eb02SAdrian Chadd /* Requested resource type is delegated to our parent */
791f4a3eb02SAdrian Chadd rv = bus_generic_rl_alloc_resource(dev, child, type, rid,
792f4a3eb02SAdrian Chadd start, end, count, flags);
793f4a3eb02SAdrian Chadd return (rv);
794f4a3eb02SAdrian Chadd }
795f4a3eb02SAdrian Chadd
796f4a3eb02SAdrian Chadd /* Populate defaults */
797f4a3eb02SAdrian Chadd if (!passthrough && isdefault) {
798f4a3eb02SAdrian Chadd /* Fetch the resource list entry. */
799f4a3eb02SAdrian Chadd rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child),
800f4a3eb02SAdrian Chadd type, *rid);
801f4a3eb02SAdrian Chadd if (rle == NULL) {
802f4a3eb02SAdrian Chadd device_printf(dev,
803f4a3eb02SAdrian Chadd "default resource %#x type %d for child %s "
804f4a3eb02SAdrian Chadd "not found\n", *rid, type,
805f4a3eb02SAdrian Chadd device_get_nameunit(child));
806f4a3eb02SAdrian Chadd return (NULL);
807f4a3eb02SAdrian Chadd }
808f4a3eb02SAdrian Chadd
809f4a3eb02SAdrian Chadd if (rle->res != NULL) {
810f4a3eb02SAdrian Chadd device_printf(dev,
8112b693a88SLandon J. Fuller "resource entry %#x type %d for child %s is busy "
8122b693a88SLandon J. Fuller "[%d]\n",
8132b693a88SLandon J. Fuller *rid, type, device_get_nameunit(child),
8142b693a88SLandon J. Fuller rman_get_flags(rle->res));
815f4a3eb02SAdrian Chadd
816f4a3eb02SAdrian Chadd return (NULL);
817f4a3eb02SAdrian Chadd }
818f4a3eb02SAdrian Chadd
819f4a3eb02SAdrian Chadd start = rle->start;
820f4a3eb02SAdrian Chadd end = rle->end;
821f4a3eb02SAdrian Chadd count = ulmax(count, rle->count);
822f4a3eb02SAdrian Chadd }
823f4a3eb02SAdrian Chadd
824f4a3eb02SAdrian Chadd /* Locate a mapping region */
825f4a3eb02SAdrian Chadd if ((cr = chipc_find_region(sc, start, end)) == NULL) {
826f4a3eb02SAdrian Chadd /* Resource requests outside our shared port regions can be
827f4a3eb02SAdrian Chadd * delegated to our parent. */
828f4a3eb02SAdrian Chadd rv = bus_generic_rl_alloc_resource(dev, child, type, rid,
829f4a3eb02SAdrian Chadd start, end, count, flags);
830f4a3eb02SAdrian Chadd return (rv);
831f4a3eb02SAdrian Chadd }
832f4a3eb02SAdrian Chadd
8332f909a9fSLandon J. Fuller /*
8342f909a9fSLandon J. Fuller * As a special case, children that map the complete ChipCommon register
8352f909a9fSLandon J. Fuller * block are delegated to our parent.
8362f909a9fSLandon J. Fuller *
8372f909a9fSLandon J. Fuller * The rman API does not support sharing resources that are not
8382f909a9fSLandon J. Fuller * identical in size; since we allocate subregions to various children,
8392f909a9fSLandon J. Fuller * any children that need to map the entire register block (e.g. because
8402f909a9fSLandon J. Fuller * they require access to discontiguous register ranges) must make the
8412f909a9fSLandon J. Fuller * allocation through our parent, where we hold a compatible
8422f909a9fSLandon J. Fuller * RF_SHAREABLE allocation.
8432f909a9fSLandon J. Fuller */
8442f909a9fSLandon J. Fuller if (cr == sc->core_region && cr->cr_addr == start &&
8452f909a9fSLandon J. Fuller cr->cr_end == end && cr->cr_count == count)
8462f909a9fSLandon J. Fuller {
8472f909a9fSLandon J. Fuller rv = bus_generic_rl_alloc_resource(dev, child, type, rid,
8482f909a9fSLandon J. Fuller start, end, count, flags);
8492f909a9fSLandon J. Fuller return (rv);
8502f909a9fSLandon J. Fuller }
8512f909a9fSLandon J. Fuller
852f4a3eb02SAdrian Chadd /* Try to retain a region reference */
8537d1fb1aaSLandon J. Fuller if ((error = chipc_retain_region(sc, cr, RF_ALLOCATED)))
854f4a3eb02SAdrian Chadd return (NULL);
855f4a3eb02SAdrian Chadd
856f4a3eb02SAdrian Chadd /* Make our rman reservation */
8573a48dfe1SJohn Baldwin rv = bus_generic_rman_alloc_resource(dev, child, type, rid, start, end,
8583a48dfe1SJohn Baldwin count, flags);
859f4a3eb02SAdrian Chadd if (rv == NULL) {
860f4a3eb02SAdrian Chadd chipc_release_region(sc, cr, RF_ALLOCATED);
861f4a3eb02SAdrian Chadd return (NULL);
862f4a3eb02SAdrian Chadd }
863f4a3eb02SAdrian Chadd
864f4a3eb02SAdrian Chadd /* Update child's resource list entry */
865f4a3eb02SAdrian Chadd if (rle != NULL) {
866f4a3eb02SAdrian Chadd rle->res = rv;
867f4a3eb02SAdrian Chadd rle->start = rman_get_start(rv);
868f4a3eb02SAdrian Chadd rle->end = rman_get_end(rv);
869f4a3eb02SAdrian Chadd rle->count = rman_get_size(rv);
870f4a3eb02SAdrian Chadd }
871f4a3eb02SAdrian Chadd
872f4a3eb02SAdrian Chadd return (rv);
873f4a3eb02SAdrian Chadd }
874f4a3eb02SAdrian Chadd
875f4a3eb02SAdrian Chadd static int
chipc_release_resource(device_t dev,device_t child,struct resource * r)8769dbf5b0eSJohn Baldwin chipc_release_resource(device_t dev, device_t child, struct resource *r)
877f4a3eb02SAdrian Chadd {
878f4a3eb02SAdrian Chadd struct chipc_softc *sc;
879f4a3eb02SAdrian Chadd struct chipc_region *cr;
880f4a3eb02SAdrian Chadd struct rman *rm;
8812b693a88SLandon J. Fuller struct resource_list_entry *rle;
882f4a3eb02SAdrian Chadd int error;
883f4a3eb02SAdrian Chadd
884f4a3eb02SAdrian Chadd sc = device_get_softc(dev);
885f4a3eb02SAdrian Chadd
886f4a3eb02SAdrian Chadd /* Handled by parent bus? */
8879dbf5b0eSJohn Baldwin rm = chipc_get_rman(dev, rman_get_type(r), rman_get_flags(r));
888f4a3eb02SAdrian Chadd if (rm == NULL || !rman_is_region_manager(r, rm)) {
8899dbf5b0eSJohn Baldwin return (bus_generic_rl_release_resource(dev, child, r));
890f4a3eb02SAdrian Chadd }
891f4a3eb02SAdrian Chadd
892f4a3eb02SAdrian Chadd /* Locate the mapping region */
893f4a3eb02SAdrian Chadd cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r));
894f4a3eb02SAdrian Chadd if (cr == NULL)
895f4a3eb02SAdrian Chadd return (EINVAL);
896f4a3eb02SAdrian Chadd
897f4a3eb02SAdrian Chadd /* Deactivate resources */
8989dbf5b0eSJohn Baldwin error = bus_generic_rman_release_resource(dev, child, r);
8993a48dfe1SJohn Baldwin if (error != 0)
900f4a3eb02SAdrian Chadd return (error);
901f4a3eb02SAdrian Chadd
902f4a3eb02SAdrian Chadd /* Drop allocation reference */
903f4a3eb02SAdrian Chadd chipc_release_region(sc, cr, RF_ALLOCATED);
904f4a3eb02SAdrian Chadd
9052b693a88SLandon J. Fuller /* Clear reference from the resource list entry if exists */
9069dbf5b0eSJohn Baldwin rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child),
9079dbf5b0eSJohn Baldwin rman_get_type(r), rman_get_rid(r));
9082b693a88SLandon J. Fuller if (rle != NULL)
9092b693a88SLandon J. Fuller rle->res = NULL;
9102b693a88SLandon J. Fuller
911f4a3eb02SAdrian Chadd return (0);
912f4a3eb02SAdrian Chadd }
913f4a3eb02SAdrian Chadd
914f4a3eb02SAdrian Chadd static int
chipc_adjust_resource(device_t dev,device_t child,struct resource * r,rman_res_t start,rman_res_t end)915fef01f04SJohn Baldwin chipc_adjust_resource(device_t dev, device_t child,
916f4a3eb02SAdrian Chadd struct resource *r, rman_res_t start, rman_res_t end)
917f4a3eb02SAdrian Chadd {
918f4a3eb02SAdrian Chadd struct chipc_softc *sc;
919f4a3eb02SAdrian Chadd struct chipc_region *cr;
920f4a3eb02SAdrian Chadd struct rman *rm;
921f4a3eb02SAdrian Chadd
922f4a3eb02SAdrian Chadd sc = device_get_softc(dev);
923f4a3eb02SAdrian Chadd
924f4a3eb02SAdrian Chadd /* Handled by parent bus? */
925fef01f04SJohn Baldwin rm = chipc_get_rman(dev, rman_get_type(r), rman_get_flags(r));
926f4a3eb02SAdrian Chadd if (rm == NULL || !rman_is_region_manager(r, rm)) {
927fef01f04SJohn Baldwin return (bus_generic_adjust_resource(dev, child, r, start, end));
928f4a3eb02SAdrian Chadd }
929f4a3eb02SAdrian Chadd
930f4a3eb02SAdrian Chadd /* The range is limited to the existing region mapping */
931f4a3eb02SAdrian Chadd cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r));
932f4a3eb02SAdrian Chadd if (cr == NULL)
933f4a3eb02SAdrian Chadd return (EINVAL);
934f4a3eb02SAdrian Chadd
935f4a3eb02SAdrian Chadd if (end <= start)
936f4a3eb02SAdrian Chadd return (EINVAL);
937f4a3eb02SAdrian Chadd
938f4a3eb02SAdrian Chadd if (start < cr->cr_addr || end > cr->cr_end)
939f4a3eb02SAdrian Chadd return (EINVAL);
940f4a3eb02SAdrian Chadd
941f4a3eb02SAdrian Chadd /* Range falls within the existing region */
942f4a3eb02SAdrian Chadd return (rman_adjust_resource(r, start, end));
943f4a3eb02SAdrian Chadd }
944f4a3eb02SAdrian Chadd
945f4a3eb02SAdrian Chadd /**
946f4a3eb02SAdrian Chadd * Retain an RF_ACTIVE reference to the region mapping @p r, and
947f4a3eb02SAdrian Chadd * configure @p r with its subregion values.
948f4a3eb02SAdrian Chadd *
949f4a3eb02SAdrian Chadd * @param sc Driver instance state.
950f4a3eb02SAdrian Chadd * @param child Requesting child device.
951f4a3eb02SAdrian Chadd * @param r resource to be activated.
952f4a3eb02SAdrian Chadd * @param req_direct If true, failure to allocate a direct bhnd resource
953f4a3eb02SAdrian Chadd * will be treated as an error. If false, the resource will not be marked
954f4a3eb02SAdrian Chadd * as RF_ACTIVE if bhnd direct resource allocation fails.
955f4a3eb02SAdrian Chadd */
956f4a3eb02SAdrian Chadd static int
chipc_try_activate_resource(device_t dev,device_t child,struct resource * r,bool req_direct)9572baed46eSJohn Baldwin chipc_try_activate_resource(device_t dev, device_t child,
9582baed46eSJohn Baldwin struct resource *r, bool req_direct)
959f4a3eb02SAdrian Chadd {
9603a48dfe1SJohn Baldwin struct chipc_softc *sc = device_get_softc(dev);
961f4a3eb02SAdrian Chadd struct rman *rm;
962f4a3eb02SAdrian Chadd struct chipc_region *cr;
963f4a3eb02SAdrian Chadd bhnd_size_t cr_offset;
964f4a3eb02SAdrian Chadd rman_res_t r_start, r_end, r_size;
965f4a3eb02SAdrian Chadd int error;
966f4a3eb02SAdrian Chadd
9672baed46eSJohn Baldwin rm = chipc_get_rman(dev, rman_get_type(r), rman_get_flags(r));
968f4a3eb02SAdrian Chadd if (rm == NULL || !rman_is_region_manager(r, rm))
969f4a3eb02SAdrian Chadd return (EINVAL);
970f4a3eb02SAdrian Chadd
971f4a3eb02SAdrian Chadd r_start = rman_get_start(r);
972f4a3eb02SAdrian Chadd r_end = rman_get_end(r);
973f4a3eb02SAdrian Chadd r_size = rman_get_size(r);
974f4a3eb02SAdrian Chadd
975f4a3eb02SAdrian Chadd /* Find the corresponding chipc region */
976f4a3eb02SAdrian Chadd cr = chipc_find_region(sc, r_start, r_end);
977f4a3eb02SAdrian Chadd if (cr == NULL)
978f4a3eb02SAdrian Chadd return (EINVAL);
979f4a3eb02SAdrian Chadd
980f4a3eb02SAdrian Chadd /* Calculate subregion offset within the chipc region */
981f4a3eb02SAdrian Chadd cr_offset = r_start - cr->cr_addr;
982f4a3eb02SAdrian Chadd
983f4a3eb02SAdrian Chadd /* Retain (and activate, if necessary) the chipc region */
984f4a3eb02SAdrian Chadd if ((error = chipc_retain_region(sc, cr, RF_ACTIVE)))
985f4a3eb02SAdrian Chadd return (error);
986f4a3eb02SAdrian Chadd
987f4a3eb02SAdrian Chadd /* Configure child resource with its subregion values. */
988f4a3eb02SAdrian Chadd if (cr->cr_res->direct) {
989f4a3eb02SAdrian Chadd error = chipc_init_child_resource(r, cr->cr_res->res,
990f4a3eb02SAdrian Chadd cr_offset, r_size);
991f4a3eb02SAdrian Chadd if (error)
992f4a3eb02SAdrian Chadd goto cleanup;
993f4a3eb02SAdrian Chadd
994f4a3eb02SAdrian Chadd /* Mark active */
995f4a3eb02SAdrian Chadd if ((error = rman_activate_resource(r)))
996f4a3eb02SAdrian Chadd goto cleanup;
997f4a3eb02SAdrian Chadd } else if (req_direct) {
998f4a3eb02SAdrian Chadd error = ENOMEM;
999f4a3eb02SAdrian Chadd goto cleanup;
1000f4a3eb02SAdrian Chadd }
1001f4a3eb02SAdrian Chadd
1002f4a3eb02SAdrian Chadd return (0);
1003f4a3eb02SAdrian Chadd
1004f4a3eb02SAdrian Chadd cleanup:
1005f4a3eb02SAdrian Chadd chipc_release_region(sc, cr, RF_ACTIVE);
1006f4a3eb02SAdrian Chadd return (error);
1007f4a3eb02SAdrian Chadd }
1008f4a3eb02SAdrian Chadd
1009f4a3eb02SAdrian Chadd static int
chipc_activate_bhnd_resource(device_t dev,device_t child,int type,int rid,struct bhnd_resource * r)1010f4a3eb02SAdrian Chadd chipc_activate_bhnd_resource(device_t dev, device_t child, int type,
1011f4a3eb02SAdrian Chadd int rid, struct bhnd_resource *r)
1012f4a3eb02SAdrian Chadd {
1013f4a3eb02SAdrian Chadd struct rman *rm;
1014f4a3eb02SAdrian Chadd int error;
1015f4a3eb02SAdrian Chadd
1016f4a3eb02SAdrian Chadd /* Delegate non-locally managed resources to parent */
10173a48dfe1SJohn Baldwin rm = chipc_get_rman(dev, type, rman_get_flags(r->res));
1018f4a3eb02SAdrian Chadd if (rm == NULL || !rman_is_region_manager(r->res, rm)) {
1019f4a3eb02SAdrian Chadd return (bhnd_bus_generic_activate_resource(dev, child, type,
1020f4a3eb02SAdrian Chadd rid, r));
1021f4a3eb02SAdrian Chadd }
1022f4a3eb02SAdrian Chadd
1023f4a3eb02SAdrian Chadd /* Try activating the chipc region resource */
10242baed46eSJohn Baldwin error = chipc_try_activate_resource(dev, child, r->res, false);
1025f4a3eb02SAdrian Chadd if (error)
1026f4a3eb02SAdrian Chadd return (error);
1027f4a3eb02SAdrian Chadd
1028f4a3eb02SAdrian Chadd /* Mark the child resource as direct according to the returned resource
1029f4a3eb02SAdrian Chadd * state */
1030f4a3eb02SAdrian Chadd if (rman_get_flags(r->res) & RF_ACTIVE)
1031f4a3eb02SAdrian Chadd r->direct = true;
1032f4a3eb02SAdrian Chadd
1033f4a3eb02SAdrian Chadd return (0);
1034f4a3eb02SAdrian Chadd }
1035f4a3eb02SAdrian Chadd
1036f4a3eb02SAdrian Chadd static int
chipc_activate_resource(device_t dev,device_t child,struct resource * r)10372baed46eSJohn Baldwin chipc_activate_resource(device_t dev, device_t child, struct resource *r)
1038f4a3eb02SAdrian Chadd {
1039f4a3eb02SAdrian Chadd struct rman *rm;
1040f4a3eb02SAdrian Chadd
1041f4a3eb02SAdrian Chadd /* Delegate non-locally managed resources to parent */
10422baed46eSJohn Baldwin rm = chipc_get_rman(dev, rman_get_type(r), rman_get_flags(r));
1043f4a3eb02SAdrian Chadd if (rm == NULL || !rman_is_region_manager(r, rm)) {
10442baed46eSJohn Baldwin return (bus_generic_activate_resource(dev, child, r));
1045f4a3eb02SAdrian Chadd }
1046f4a3eb02SAdrian Chadd
1047f4a3eb02SAdrian Chadd /* Try activating the chipc region-based resource */
10482baed46eSJohn Baldwin return (chipc_try_activate_resource(dev, child, r, true));
1049f4a3eb02SAdrian Chadd }
1050f4a3eb02SAdrian Chadd
1051f4a3eb02SAdrian Chadd /**
1052f4a3eb02SAdrian Chadd * Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE().
1053f4a3eb02SAdrian Chadd */
1054f4a3eb02SAdrian Chadd static int
chipc_deactivate_resource(device_t dev,device_t child,struct resource * r)10552baed46eSJohn Baldwin chipc_deactivate_resource(device_t dev, device_t child,
10562baed46eSJohn Baldwin struct resource *r)
1057f4a3eb02SAdrian Chadd {
1058f4a3eb02SAdrian Chadd struct chipc_softc *sc;
1059f4a3eb02SAdrian Chadd struct chipc_region *cr;
1060f4a3eb02SAdrian Chadd struct rman *rm;
1061f4a3eb02SAdrian Chadd int error;
1062f4a3eb02SAdrian Chadd
1063f4a3eb02SAdrian Chadd sc = device_get_softc(dev);
1064f4a3eb02SAdrian Chadd
1065f4a3eb02SAdrian Chadd /* Handled by parent bus? */
10662baed46eSJohn Baldwin rm = chipc_get_rman(dev, rman_get_type(r), rman_get_flags(r));
1067f4a3eb02SAdrian Chadd if (rm == NULL || !rman_is_region_manager(r, rm)) {
10682baed46eSJohn Baldwin return (bus_generic_deactivate_resource(dev, child, r));
1069f4a3eb02SAdrian Chadd }
1070f4a3eb02SAdrian Chadd
1071f4a3eb02SAdrian Chadd /* Find the corresponding chipc region */
1072f4a3eb02SAdrian Chadd cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r));
1073f4a3eb02SAdrian Chadd if (cr == NULL)
1074f4a3eb02SAdrian Chadd return (EINVAL);
1075f4a3eb02SAdrian Chadd
1076f4a3eb02SAdrian Chadd /* Mark inactive */
1077f4a3eb02SAdrian Chadd if ((error = rman_deactivate_resource(r)))
1078f4a3eb02SAdrian Chadd return (error);
1079f4a3eb02SAdrian Chadd
1080f4a3eb02SAdrian Chadd /* Drop associated RF_ACTIVE reference */
1081f4a3eb02SAdrian Chadd chipc_release_region(sc, cr, RF_ACTIVE);
1082f4a3eb02SAdrian Chadd
1083f4a3eb02SAdrian Chadd return (0);
1084f4a3eb02SAdrian Chadd }
1085f4a3eb02SAdrian Chadd
1086f4a3eb02SAdrian Chadd /**
1087f4a3eb02SAdrian Chadd * Examine bus state and make a best effort determination of whether it's
1088f4a3eb02SAdrian Chadd * likely safe to enable the muxed SPROM pins.
1089f4a3eb02SAdrian Chadd *
1090f4a3eb02SAdrian Chadd * On devices that do not use SPROM pin muxing, always returns true.
1091f4a3eb02SAdrian Chadd *
1092f4a3eb02SAdrian Chadd * @param sc chipc driver state.
1093f4a3eb02SAdrian Chadd */
1094f4a3eb02SAdrian Chadd static bool
chipc_should_enable_muxed_sprom(struct chipc_softc * sc)1095f90f4b65SLandon J. Fuller chipc_should_enable_muxed_sprom(struct chipc_softc *sc)
1096f4a3eb02SAdrian Chadd {
1097f4a3eb02SAdrian Chadd device_t *devs;
1098f4a3eb02SAdrian Chadd device_t hostb;
1099f4a3eb02SAdrian Chadd device_t parent;
1100f4a3eb02SAdrian Chadd int devcount;
1101f4a3eb02SAdrian Chadd int error;
1102f4a3eb02SAdrian Chadd bool result;
1103f4a3eb02SAdrian Chadd
1104f4a3eb02SAdrian Chadd /* Nothing to do? */
1105f4a3eb02SAdrian Chadd if (!CHIPC_QUIRK(sc, MUX_SPROM))
1106f4a3eb02SAdrian Chadd return (true);
1107f4a3eb02SAdrian Chadd
1108c6df6f53SWarner Losh bus_topo_lock();
1109f90f4b65SLandon J. Fuller
1110f4a3eb02SAdrian Chadd parent = device_get_parent(sc->dev);
11118e35bf83SLandon J. Fuller hostb = bhnd_bus_find_hostb_device(parent);
1112f4a3eb02SAdrian Chadd
1113f90f4b65SLandon J. Fuller if ((error = device_get_children(parent, &devs, &devcount))) {
1114c6df6f53SWarner Losh bus_topo_unlock();
1115f4a3eb02SAdrian Chadd return (false);
1116f90f4b65SLandon J. Fuller }
1117f4a3eb02SAdrian Chadd
1118f4a3eb02SAdrian Chadd /* Reject any active devices other than ChipCommon, or the
1119f4a3eb02SAdrian Chadd * host bridge (if any). */
1120f4a3eb02SAdrian Chadd result = true;
1121f4a3eb02SAdrian Chadd for (int i = 0; i < devcount; i++) {
1122f4a3eb02SAdrian Chadd if (devs[i] == hostb || devs[i] == sc->dev)
1123f4a3eb02SAdrian Chadd continue;
1124f4a3eb02SAdrian Chadd
1125f4a3eb02SAdrian Chadd if (!device_is_attached(devs[i]))
1126f4a3eb02SAdrian Chadd continue;
1127f4a3eb02SAdrian Chadd
1128f4a3eb02SAdrian Chadd if (device_is_suspended(devs[i]))
1129f4a3eb02SAdrian Chadd continue;
1130f4a3eb02SAdrian Chadd
1131f4a3eb02SAdrian Chadd /* Active device; assume SPROM is busy */
1132f4a3eb02SAdrian Chadd result = false;
1133f4a3eb02SAdrian Chadd break;
1134f4a3eb02SAdrian Chadd }
1135f4a3eb02SAdrian Chadd
1136f4a3eb02SAdrian Chadd free(devs, M_TEMP);
1137c6df6f53SWarner Losh bus_topo_unlock();
1138f4a3eb02SAdrian Chadd return (result);
1139f4a3eb02SAdrian Chadd }
1140e83ce340SAdrian Chadd
1141f90f4b65SLandon J. Fuller static int
chipc_enable_sprom(device_t dev)1142f90f4b65SLandon J. Fuller chipc_enable_sprom(device_t dev)
1143f90f4b65SLandon J. Fuller {
1144f90f4b65SLandon J. Fuller struct chipc_softc *sc;
1145f90f4b65SLandon J. Fuller int error;
1146f90f4b65SLandon J. Fuller
1147f90f4b65SLandon J. Fuller sc = device_get_softc(dev);
1148f90f4b65SLandon J. Fuller CHIPC_LOCK(sc);
1149f90f4b65SLandon J. Fuller
1150f90f4b65SLandon J. Fuller /* Already enabled? */
1151f90f4b65SLandon J. Fuller if (sc->sprom_refcnt >= 1) {
1152f90f4b65SLandon J. Fuller sc->sprom_refcnt++;
1153f90f4b65SLandon J. Fuller CHIPC_UNLOCK(sc);
1154f90f4b65SLandon J. Fuller
1155f90f4b65SLandon J. Fuller return (0);
1156f90f4b65SLandon J. Fuller }
1157f90f4b65SLandon J. Fuller
1158f90f4b65SLandon J. Fuller switch (sc->caps.nvram_src) {
1159f90f4b65SLandon J. Fuller case BHND_NVRAM_SRC_SPROM:
1160f90f4b65SLandon J. Fuller error = chipc_enable_sprom_pins(sc);
1161f90f4b65SLandon J. Fuller break;
1162f90f4b65SLandon J. Fuller case BHND_NVRAM_SRC_OTP:
1163f90f4b65SLandon J. Fuller error = chipc_enable_otp_power(sc);
1164f90f4b65SLandon J. Fuller break;
1165f90f4b65SLandon J. Fuller default:
1166f90f4b65SLandon J. Fuller error = 0;
1167f90f4b65SLandon J. Fuller break;
1168f90f4b65SLandon J. Fuller }
1169f90f4b65SLandon J. Fuller
1170f90f4b65SLandon J. Fuller /* Bump the reference count */
1171f90f4b65SLandon J. Fuller if (error == 0)
1172f90f4b65SLandon J. Fuller sc->sprom_refcnt++;
1173f90f4b65SLandon J. Fuller
1174f90f4b65SLandon J. Fuller CHIPC_UNLOCK(sc);
1175f90f4b65SLandon J. Fuller return (error);
1176f90f4b65SLandon J. Fuller }
1177f90f4b65SLandon J. Fuller
1178f90f4b65SLandon J. Fuller static void
chipc_disable_sprom(device_t dev)1179f90f4b65SLandon J. Fuller chipc_disable_sprom(device_t dev)
1180f90f4b65SLandon J. Fuller {
1181f90f4b65SLandon J. Fuller struct chipc_softc *sc;
1182f90f4b65SLandon J. Fuller
1183f90f4b65SLandon J. Fuller sc = device_get_softc(dev);
1184f90f4b65SLandon J. Fuller CHIPC_LOCK(sc);
1185f90f4b65SLandon J. Fuller
1186f90f4b65SLandon J. Fuller /* Check reference count, skip disable if in-use. */
1187f90f4b65SLandon J. Fuller KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease"));
1188f90f4b65SLandon J. Fuller sc->sprom_refcnt--;
1189f90f4b65SLandon J. Fuller if (sc->sprom_refcnt > 0) {
1190f90f4b65SLandon J. Fuller CHIPC_UNLOCK(sc);
1191f90f4b65SLandon J. Fuller return;
1192f90f4b65SLandon J. Fuller }
1193f90f4b65SLandon J. Fuller
1194f90f4b65SLandon J. Fuller switch (sc->caps.nvram_src) {
1195f90f4b65SLandon J. Fuller case BHND_NVRAM_SRC_SPROM:
1196f90f4b65SLandon J. Fuller chipc_disable_sprom_pins(sc);
1197f90f4b65SLandon J. Fuller break;
1198f90f4b65SLandon J. Fuller case BHND_NVRAM_SRC_OTP:
1199f90f4b65SLandon J. Fuller chipc_disable_otp_power(sc);
1200f90f4b65SLandon J. Fuller break;
1201f90f4b65SLandon J. Fuller default:
1202f90f4b65SLandon J. Fuller break;
1203f90f4b65SLandon J. Fuller }
1204f90f4b65SLandon J. Fuller
1205f90f4b65SLandon J. Fuller CHIPC_UNLOCK(sc);
1206f90f4b65SLandon J. Fuller }
1207f90f4b65SLandon J. Fuller
1208f90f4b65SLandon J. Fuller static int
chipc_enable_otp_power(struct chipc_softc * sc)1209f90f4b65SLandon J. Fuller chipc_enable_otp_power(struct chipc_softc *sc)
1210f90f4b65SLandon J. Fuller {
1211f90f4b65SLandon J. Fuller // TODO: Enable OTP resource via PMU, and wait up to 100 usec for
1212f90f4b65SLandon J. Fuller // OTPS_READY to be set in `optstatus`.
1213f90f4b65SLandon J. Fuller return (0);
1214f90f4b65SLandon J. Fuller }
1215f90f4b65SLandon J. Fuller
1216f90f4b65SLandon J. Fuller static void
chipc_disable_otp_power(struct chipc_softc * sc)1217f90f4b65SLandon J. Fuller chipc_disable_otp_power(struct chipc_softc *sc)
1218f90f4b65SLandon J. Fuller {
1219f90f4b65SLandon J. Fuller // TODO: Disable OTP resource via PMU
1220f90f4b65SLandon J. Fuller }
1221f90f4b65SLandon J. Fuller
1222e83ce340SAdrian Chadd /**
1223e83ce340SAdrian Chadd * If required by this device, enable access to the SPROM.
1224e83ce340SAdrian Chadd *
1225e83ce340SAdrian Chadd * @param sc chipc driver state.
1226e83ce340SAdrian Chadd */
1227e83ce340SAdrian Chadd static int
chipc_enable_sprom_pins(struct chipc_softc * sc)1228f90f4b65SLandon J. Fuller chipc_enable_sprom_pins(struct chipc_softc *sc)
1229e83ce340SAdrian Chadd {
1230e83ce340SAdrian Chadd uint32_t cctrl;
1231e83ce340SAdrian Chadd
1232f90f4b65SLandon J. Fuller CHIPC_LOCK_ASSERT(sc, MA_OWNED);
1233f90f4b65SLandon J. Fuller KASSERT(sc->sprom_refcnt == 0, ("sprom pins already enabled"));
1234e83ce340SAdrian Chadd
1235e83ce340SAdrian Chadd /* Nothing to do? */
1236e83ce340SAdrian Chadd if (!CHIPC_QUIRK(sc, MUX_SPROM))
1237e83ce340SAdrian Chadd return (0);
1238e83ce340SAdrian Chadd
1239f4a3eb02SAdrian Chadd /* Check whether bus is busy */
1240f90f4b65SLandon J. Fuller if (!chipc_should_enable_muxed_sprom(sc))
1241f90f4b65SLandon J. Fuller return (EBUSY);
1242f4a3eb02SAdrian Chadd
1243e83ce340SAdrian Chadd cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);
1244e83ce340SAdrian Chadd
1245e83ce340SAdrian Chadd /* 4331 devices */
1246e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) {
1247e83ce340SAdrian Chadd cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN;
1248e83ce340SAdrian Chadd
1249e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM))
1250e83ce340SAdrian Chadd cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5;
1251e83ce340SAdrian Chadd
1252e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM))
1253e83ce340SAdrian Chadd cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2;
1254e83ce340SAdrian Chadd
1255e83ce340SAdrian Chadd bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl);
1256f90f4b65SLandon J. Fuller return (0);
1257e83ce340SAdrian Chadd }
1258e83ce340SAdrian Chadd
1259e83ce340SAdrian Chadd /* 4360 devices */
1260e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) {
1261e83ce340SAdrian Chadd /* Unimplemented */
1262e83ce340SAdrian Chadd }
1263e83ce340SAdrian Chadd
1264e83ce340SAdrian Chadd /* Refuse to proceed on unsupported devices with muxed SPROM pins */
1265e83ce340SAdrian Chadd device_printf(sc->dev, "muxed sprom lines on unrecognized device\n");
1266f90f4b65SLandon J. Fuller return (ENXIO);
1267e83ce340SAdrian Chadd }
1268e83ce340SAdrian Chadd
1269e83ce340SAdrian Chadd /**
1270e83ce340SAdrian Chadd * If required by this device, revert any GPIO/pin configuration applied
1271e83ce340SAdrian Chadd * to allow SPROM access.
1272e83ce340SAdrian Chadd *
1273e83ce340SAdrian Chadd * @param sc chipc driver state.
1274e83ce340SAdrian Chadd */
1275f4a3eb02SAdrian Chadd static void
chipc_disable_sprom_pins(struct chipc_softc * sc)1276f90f4b65SLandon J. Fuller chipc_disable_sprom_pins(struct chipc_softc *sc)
1277e83ce340SAdrian Chadd {
1278e83ce340SAdrian Chadd uint32_t cctrl;
1279e83ce340SAdrian Chadd
1280e83ce340SAdrian Chadd /* Nothing to do? */
1281e83ce340SAdrian Chadd if (!CHIPC_QUIRK(sc, MUX_SPROM))
1282f4a3eb02SAdrian Chadd return;
1283f4a3eb02SAdrian Chadd
1284f90f4b65SLandon J. Fuller CHIPC_LOCK_ASSERT(sc, MA_OWNED);
1285315cf4daSLandon J. Fuller KASSERT(sc->sprom_refcnt == 0, ("sprom pins in use"));
1286e83ce340SAdrian Chadd
1287e83ce340SAdrian Chadd cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);
1288e83ce340SAdrian Chadd
1289e83ce340SAdrian Chadd /* 4331 devices */
1290e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) {
1291e83ce340SAdrian Chadd cctrl |= CHIPC_CCTRL4331_EXTPA_EN;
1292e83ce340SAdrian Chadd
1293e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM))
1294e83ce340SAdrian Chadd cctrl |= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5;
1295e83ce340SAdrian Chadd
1296e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM))
1297e83ce340SAdrian Chadd cctrl |= CHIPC_CCTRL4331_EXTPA_EN2;
1298e83ce340SAdrian Chadd
1299e83ce340SAdrian Chadd bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl);
1300f90f4b65SLandon J. Fuller return;
1301e83ce340SAdrian Chadd }
1302e83ce340SAdrian Chadd
1303e83ce340SAdrian Chadd /* 4360 devices */
1304e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) {
1305e83ce340SAdrian Chadd /* Unimplemented */
1306e83ce340SAdrian Chadd }
1307f90f4b65SLandon J. Fuller }
1308e83ce340SAdrian Chadd
1309f90f4b65SLandon J. Fuller static uint32_t
chipc_read_chipst(device_t dev)1310f90f4b65SLandon J. Fuller chipc_read_chipst(device_t dev)
1311f90f4b65SLandon J. Fuller {
1312f90f4b65SLandon J. Fuller struct chipc_softc *sc = device_get_softc(dev);
1313f90f4b65SLandon J. Fuller return (bhnd_bus_read_4(sc->core, CHIPC_CHIPST));
1314e83ce340SAdrian Chadd }
1315e83ce340SAdrian Chadd
13168ef24a0dSAdrian Chadd static void
chipc_write_chipctrl(device_t dev,uint32_t value,uint32_t mask)13178ef24a0dSAdrian Chadd chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask)
13188ef24a0dSAdrian Chadd {
13198ef24a0dSAdrian Chadd struct chipc_softc *sc;
13208ef24a0dSAdrian Chadd uint32_t cctrl;
13218ef24a0dSAdrian Chadd
13228ef24a0dSAdrian Chadd sc = device_get_softc(dev);
13238ef24a0dSAdrian Chadd
13248ef24a0dSAdrian Chadd CHIPC_LOCK(sc);
13258ef24a0dSAdrian Chadd
13268ef24a0dSAdrian Chadd cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);
13278ef24a0dSAdrian Chadd cctrl = (cctrl & ~mask) | (value | mask);
13288ef24a0dSAdrian Chadd bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl);
13298ef24a0dSAdrian Chadd
13308ef24a0dSAdrian Chadd CHIPC_UNLOCK(sc);
13318ef24a0dSAdrian Chadd }
13328ef24a0dSAdrian Chadd
13332b693a88SLandon J. Fuller static struct chipc_caps *
chipc_get_caps(device_t dev)13342b693a88SLandon J. Fuller chipc_get_caps(device_t dev)
13352b693a88SLandon J. Fuller {
13362b693a88SLandon J. Fuller struct chipc_softc *sc;
13372b693a88SLandon J. Fuller
13382b693a88SLandon J. Fuller sc = device_get_softc(dev);
13392b693a88SLandon J. Fuller return (&sc->caps);
13402b693a88SLandon J. Fuller }
13412b693a88SLandon J. Fuller
13424ad7e9b0SAdrian Chadd static device_method_t chipc_methods[] = {
13434ad7e9b0SAdrian Chadd /* Device interface */
13444ad7e9b0SAdrian Chadd DEVMETHOD(device_probe, chipc_probe),
13454ad7e9b0SAdrian Chadd DEVMETHOD(device_attach, chipc_attach),
13464ad7e9b0SAdrian Chadd DEVMETHOD(device_detach, chipc_detach),
13474ad7e9b0SAdrian Chadd DEVMETHOD(device_suspend, chipc_suspend),
13484ad7e9b0SAdrian Chadd DEVMETHOD(device_resume, chipc_resume),
13494ad7e9b0SAdrian Chadd
1350f4a3eb02SAdrian Chadd /* Bus interface */
1351f4a3eb02SAdrian Chadd DEVMETHOD(bus_probe_nomatch, chipc_probe_nomatch),
1352f4a3eb02SAdrian Chadd DEVMETHOD(bus_print_child, chipc_print_child),
1353f4a3eb02SAdrian Chadd
1354f4a3eb02SAdrian Chadd DEVMETHOD(bus_add_child, chipc_add_child),
1355f4a3eb02SAdrian Chadd DEVMETHOD(bus_child_deleted, chipc_child_deleted),
1356f4a3eb02SAdrian Chadd
1357f4a3eb02SAdrian Chadd DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
1358f4a3eb02SAdrian Chadd DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
1359f4a3eb02SAdrian Chadd DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource),
1360f4a3eb02SAdrian Chadd DEVMETHOD(bus_alloc_resource, chipc_alloc_resource),
1361f4a3eb02SAdrian Chadd DEVMETHOD(bus_release_resource, chipc_release_resource),
1362f4a3eb02SAdrian Chadd DEVMETHOD(bus_adjust_resource, chipc_adjust_resource),
1363f4a3eb02SAdrian Chadd DEVMETHOD(bus_activate_resource, chipc_activate_resource),
1364f4a3eb02SAdrian Chadd DEVMETHOD(bus_deactivate_resource, chipc_deactivate_resource),
1365f4a3eb02SAdrian Chadd DEVMETHOD(bus_get_resource_list, chipc_get_resource_list),
13663a48dfe1SJohn Baldwin DEVMETHOD(bus_get_rman, chipc_get_rman),
1367f4a3eb02SAdrian Chadd
1368f4a3eb02SAdrian Chadd DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
1369f4a3eb02SAdrian Chadd DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
1370f4a3eb02SAdrian Chadd DEVMETHOD(bus_config_intr, bus_generic_config_intr),
1371f4a3eb02SAdrian Chadd DEVMETHOD(bus_bind_intr, bus_generic_bind_intr),
1372f4a3eb02SAdrian Chadd DEVMETHOD(bus_describe_intr, bus_generic_describe_intr),
1373f4a3eb02SAdrian Chadd
1374f4a3eb02SAdrian Chadd /* BHND bus inteface */
1375f4a3eb02SAdrian Chadd DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource),
1376f4a3eb02SAdrian Chadd
13774ad7e9b0SAdrian Chadd /* ChipCommon interface */
1378f90f4b65SLandon J. Fuller DEVMETHOD(bhnd_chipc_read_chipst, chipc_read_chipst),
13798ef24a0dSAdrian Chadd DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl),
1380f90f4b65SLandon J. Fuller DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom),
1381f90f4b65SLandon J. Fuller DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom),
13822b693a88SLandon J. Fuller DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps),
1383e83ce340SAdrian Chadd
13844ad7e9b0SAdrian Chadd DEVMETHOD_END
13854ad7e9b0SAdrian Chadd };
13864ad7e9b0SAdrian Chadd
1387f90f4b65SLandon J. Fuller DEFINE_CLASS_0(bhnd_chipc, bhnd_chipc_driver, chipc_methods, sizeof(struct chipc_softc));
1388162c26adSJohn Baldwin EARLY_DRIVER_MODULE(bhnd_chipc, bhnd, bhnd_chipc_driver, 0, 0,
1389e129bcd6SLandon J. Fuller BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
139096546b75SAdrian Chadd MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1);
13914ad7e9b0SAdrian Chadd MODULE_VERSION(bhnd_chipc, 1);
1392