14ad7e9b0SAdrian Chadd /*- 26e778a7eSPedro F. Giffuni * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 36e778a7eSPedro F. Giffuni * 4f4a3eb02SAdrian Chadd * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 5f4a3eb02SAdrian Chadd * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com> 68e35bf83SLandon J. Fuller * Copyright (c) 2017 The FreeBSD Foundation 74ad7e9b0SAdrian Chadd * All rights reserved. 84ad7e9b0SAdrian Chadd * 94e96bf3aSLandon J. Fuller * Portions of this software were developed by Landon Fuller 104e96bf3aSLandon J. Fuller * under sponsorship from the FreeBSD Foundation. 118e35bf83SLandon J. Fuller * 124ad7e9b0SAdrian Chadd * Redistribution and use in source and binary forms, with or without 134ad7e9b0SAdrian Chadd * modification, are permitted provided that the following conditions 144ad7e9b0SAdrian Chadd * are met: 154ad7e9b0SAdrian Chadd * 1. Redistributions of source code must retain the above copyright 164ad7e9b0SAdrian Chadd * notice, this list of conditions and the following disclaimer, 174ad7e9b0SAdrian Chadd * without modification. 184ad7e9b0SAdrian Chadd * 2. Redistributions in binary form must reproduce at minimum a disclaimer 194ad7e9b0SAdrian Chadd * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 204ad7e9b0SAdrian Chadd * redistribution must be conditioned upon including a substantially 214ad7e9b0SAdrian Chadd * similar Disclaimer requirement for further binary redistribution. 224ad7e9b0SAdrian Chadd * 234ad7e9b0SAdrian Chadd * NO WARRANTY 244ad7e9b0SAdrian Chadd * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 254ad7e9b0SAdrian Chadd * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 264ad7e9b0SAdrian Chadd * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 274ad7e9b0SAdrian Chadd * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 284ad7e9b0SAdrian Chadd * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 294ad7e9b0SAdrian Chadd * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 304ad7e9b0SAdrian Chadd * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 314ad7e9b0SAdrian Chadd * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 324ad7e9b0SAdrian Chadd * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 334ad7e9b0SAdrian Chadd * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 344ad7e9b0SAdrian Chadd * THE POSSIBILITY OF SUCH DAMAGES. 354ad7e9b0SAdrian Chadd */ 364ad7e9b0SAdrian Chadd 374ad7e9b0SAdrian Chadd #include <sys/cdefs.h> 384ad7e9b0SAdrian Chadd __FBSDID("$FreeBSD$"); 394ad7e9b0SAdrian Chadd 404ad7e9b0SAdrian Chadd /* 414ad7e9b0SAdrian Chadd * Broadcom ChipCommon driver. 424ad7e9b0SAdrian Chadd * 434ad7e9b0SAdrian Chadd * With the exception of some very early chipsets, the ChipCommon core 444ad7e9b0SAdrian Chadd * has been included in all HND SoCs and chipsets based on the siba(4) 454ad7e9b0SAdrian Chadd * and bcma(4) interconnects, providing a common interface to chipset 460c91e892SLandon J. Fuller * identification, bus enumeration, UARTs, clocks, watchdog interrupts, 470c91e892SLandon J. Fuller * GPIO, flash, etc. 484ad7e9b0SAdrian Chadd */ 494ad7e9b0SAdrian Chadd 504ad7e9b0SAdrian Chadd #include <sys/param.h> 514ad7e9b0SAdrian Chadd #include <sys/kernel.h> 52f4a3eb02SAdrian Chadd #include <sys/lock.h> 534ad7e9b0SAdrian Chadd #include <sys/bus.h> 54e129bcd6SLandon J. Fuller #include <sys/rman.h> 55f4a3eb02SAdrian Chadd #include <sys/malloc.h> 564ad7e9b0SAdrian Chadd #include <sys/module.h> 57f4a3eb02SAdrian Chadd #include <sys/mutex.h> 584ad7e9b0SAdrian Chadd #include <sys/systm.h> 594ad7e9b0SAdrian Chadd 604ad7e9b0SAdrian Chadd #include <machine/bus.h> 614ad7e9b0SAdrian Chadd #include <machine/resource.h> 624ad7e9b0SAdrian Chadd 634ad7e9b0SAdrian Chadd #include <dev/bhnd/bhnd.h> 64f4a3eb02SAdrian Chadd #include <dev/bhnd/bhndvar.h> 65e83ce340SAdrian Chadd 664ad7e9b0SAdrian Chadd #include "chipcreg.h" 674ad7e9b0SAdrian Chadd #include "chipcvar.h" 680c91e892SLandon J. Fuller 69f4a3eb02SAdrian Chadd #include "chipc_private.h" 704ad7e9b0SAdrian Chadd 7136e4410aSAdrian Chadd static struct bhnd_device_quirk chipc_quirks[]; 7236e4410aSAdrian Chadd 734ad7e9b0SAdrian Chadd /* Supported device identifiers */ 7436e4410aSAdrian Chadd static const struct bhnd_device chipc_devices[] = { 75b0b9c854SLandon J. Fuller BHND_DEVICE(BCM, CC, NULL, chipc_quirks), 764cb7084eSLandon J. Fuller BHND_DEVICE(BCM, 4706_CC, NULL, chipc_quirks), 7736e4410aSAdrian Chadd BHND_DEVICE_END 784ad7e9b0SAdrian Chadd }; 794ad7e9b0SAdrian Chadd 804ad7e9b0SAdrian Chadd /* Device quirks table */ 814ad7e9b0SAdrian Chadd static struct bhnd_device_quirk chipc_quirks[] = { 8256a4cdd1SLandon J. Fuller /* HND OTP controller revisions */ 8356a4cdd1SLandon J. Fuller BHND_CORE_QUIRK (HWREV_EQ (12), CHIPC_QUIRK_OTP_HND), /* (?) */ 8456a4cdd1SLandon J. Fuller BHND_CORE_QUIRK (HWREV_EQ (17), CHIPC_QUIRK_OTP_HND), /* BCM4311 */ 8556a4cdd1SLandon J. Fuller BHND_CORE_QUIRK (HWREV_EQ (22), CHIPC_QUIRK_OTP_HND), /* BCM4312 */ 8656a4cdd1SLandon J. Fuller 8756a4cdd1SLandon J. Fuller /* IPX OTP controller revisions */ 8856a4cdd1SLandon J. Fuller BHND_CORE_QUIRK (HWREV_EQ (21), CHIPC_QUIRK_OTP_IPX), 8956a4cdd1SLandon J. Fuller BHND_CORE_QUIRK (HWREV_GTE(23), CHIPC_QUIRK_OTP_IPX), 9056a4cdd1SLandon J. Fuller 915ad9ac03SAdrian Chadd BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM), 925ad9ac03SAdrian Chadd BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT), 9356a4cdd1SLandon J. Fuller BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPL_SIZE), 945ad9ac03SAdrian Chadd 955ad9ac03SAdrian Chadd /* 4706 variant quirks */ 965ad9ac03SAdrian Chadd BHND_CORE_QUIRK (HWREV_EQ (38), CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */ 975ad9ac03SAdrian Chadd BHND_CHIP_QUIRK (4706, HWREV_ANY, CHIPC_QUIRK_4706_NFLASH), 985ad9ac03SAdrian Chadd 995ad9ac03SAdrian Chadd /* 4331 quirks*/ 1005ad9ac03SAdrian Chadd BHND_CHIP_QUIRK (4331, HWREV_ANY, CHIPC_QUIRK_4331_EXTPA_MUX_SPROM), 1015ad9ac03SAdrian Chadd BHND_PKG_QUIRK (4331, TN, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 1025ad9ac03SAdrian Chadd BHND_PKG_QUIRK (4331, TNA0, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 1035ad9ac03SAdrian Chadd BHND_PKG_QUIRK (4331, TT, CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM), 1045ad9ac03SAdrian Chadd 1055ad9ac03SAdrian Chadd /* 4360 quirks */ 1065ad9ac03SAdrian Chadd BHND_CHIP_QUIRK (4352, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 1075ad9ac03SAdrian Chadd BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 1085ad9ac03SAdrian Chadd BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 1095ad9ac03SAdrian Chadd BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 110f4a3eb02SAdrian Chadd 11136e4410aSAdrian Chadd BHND_DEVICE_QUIRK_END 1124ad7e9b0SAdrian Chadd }; 1134ad7e9b0SAdrian Chadd 1140c91e892SLandon J. Fuller static int chipc_add_children(struct chipc_softc *sc); 115f4a3eb02SAdrian Chadd 11656a4cdd1SLandon J. Fuller static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc, 11756a4cdd1SLandon J. Fuller struct chipc_caps *caps); 118f4a3eb02SAdrian Chadd static int chipc_read_caps(struct chipc_softc *sc, 119f4a3eb02SAdrian Chadd struct chipc_caps *caps); 120f4a3eb02SAdrian Chadd 121f90f4b65SLandon J. Fuller static bool chipc_should_enable_muxed_sprom( 122f4a3eb02SAdrian Chadd struct chipc_softc *sc); 123f90f4b65SLandon J. Fuller static int chipc_enable_otp_power(struct chipc_softc *sc); 124f90f4b65SLandon J. Fuller static void chipc_disable_otp_power(struct chipc_softc *sc); 125f90f4b65SLandon J. Fuller static int chipc_enable_sprom_pins(struct chipc_softc *sc); 126f90f4b65SLandon J. Fuller static void chipc_disable_sprom_pins(struct chipc_softc *sc); 127f4a3eb02SAdrian Chadd 128f90f4b65SLandon J. Fuller static int chipc_try_activate_resource(struct chipc_softc *sc, 129f90f4b65SLandon J. Fuller device_t child, int type, int rid, 130f90f4b65SLandon J. Fuller struct resource *r, bool req_direct); 1310c91e892SLandon J. Fuller 132f4a3eb02SAdrian Chadd static int chipc_init_rman(struct chipc_softc *sc); 133f4a3eb02SAdrian Chadd static void chipc_free_rman(struct chipc_softc *sc); 134f90f4b65SLandon J. Fuller static struct rman *chipc_get_rman(struct chipc_softc *sc, int type); 135f4a3eb02SAdrian Chadd 1364ad7e9b0SAdrian Chadd /* quirk and capability flag convenience macros */ 1374ad7e9b0SAdrian Chadd #define CHIPC_QUIRK(_sc, _name) \ 1384ad7e9b0SAdrian Chadd ((_sc)->quirks & CHIPC_QUIRK_ ## _name) 1394ad7e9b0SAdrian Chadd 1404ad7e9b0SAdrian Chadd #define CHIPC_CAP(_sc, _name) \ 141f4a3eb02SAdrian Chadd ((_sc)->caps._name) 1424ad7e9b0SAdrian Chadd 1434ad7e9b0SAdrian Chadd #define CHIPC_ASSERT_QUIRK(_sc, name) \ 1444ad7e9b0SAdrian Chadd KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set")) 1454ad7e9b0SAdrian Chadd 1464ad7e9b0SAdrian Chadd #define CHIPC_ASSERT_CAP(_sc, name) \ 1474ad7e9b0SAdrian Chadd KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set")) 1484ad7e9b0SAdrian Chadd 1494ad7e9b0SAdrian Chadd static int 1504ad7e9b0SAdrian Chadd chipc_probe(device_t dev) 1514ad7e9b0SAdrian Chadd { 15236e4410aSAdrian Chadd const struct bhnd_device *id; 1534ad7e9b0SAdrian Chadd 15436e4410aSAdrian Chadd id = bhnd_device_lookup(dev, chipc_devices, sizeof(chipc_devices[0])); 15536e4410aSAdrian Chadd if (id == NULL) 1564ad7e9b0SAdrian Chadd return (ENXIO); 15736e4410aSAdrian Chadd 15836e4410aSAdrian Chadd bhnd_set_default_core_desc(dev); 15936e4410aSAdrian Chadd return (BUS_PROBE_DEFAULT); 1604ad7e9b0SAdrian Chadd } 1614ad7e9b0SAdrian Chadd 1624ad7e9b0SAdrian Chadd static int 1634ad7e9b0SAdrian Chadd chipc_attach(device_t dev) 1644ad7e9b0SAdrian Chadd { 1654ad7e9b0SAdrian Chadd struct chipc_softc *sc; 1664ad7e9b0SAdrian Chadd int error; 1674ad7e9b0SAdrian Chadd 1684ad7e9b0SAdrian Chadd sc = device_get_softc(dev); 1694ad7e9b0SAdrian Chadd sc->dev = dev; 17036e4410aSAdrian Chadd sc->quirks = bhnd_device_quirks(dev, chipc_devices, 17136e4410aSAdrian Chadd sizeof(chipc_devices[0])); 172f4a3eb02SAdrian Chadd sc->sprom_refcnt = 0; 173e83ce340SAdrian Chadd 174e83ce340SAdrian Chadd CHIPC_LOCK_INIT(sc); 175f4a3eb02SAdrian Chadd STAILQ_INIT(&sc->mem_regions); 1764ad7e9b0SAdrian Chadd 177f4a3eb02SAdrian Chadd /* Set up resource management */ 178f4a3eb02SAdrian Chadd if ((error = chipc_init_rman(sc))) { 179f4a3eb02SAdrian Chadd device_printf(sc->dev, 180f4a3eb02SAdrian Chadd "failed to initialize chipc resource state: %d\n", error); 181f4a3eb02SAdrian Chadd goto failed; 182f4a3eb02SAdrian Chadd } 1834ad7e9b0SAdrian Chadd 1840c91e892SLandon J. Fuller /* Allocate the region containing the chipc register block */ 185f4a3eb02SAdrian Chadd if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) { 186f4a3eb02SAdrian Chadd error = ENXIO; 187f4a3eb02SAdrian Chadd goto failed; 188f4a3eb02SAdrian Chadd } 189f4a3eb02SAdrian Chadd 190f4a3eb02SAdrian Chadd error = chipc_retain_region(sc, sc->core_region, 191f4a3eb02SAdrian Chadd RF_ALLOCATED|RF_ACTIVE); 192f4a3eb02SAdrian Chadd if (error) { 193f4a3eb02SAdrian Chadd sc->core_region = NULL; 194f4a3eb02SAdrian Chadd goto failed; 1950c91e892SLandon J. Fuller } 1960c91e892SLandon J. Fuller 1970c91e892SLandon J. Fuller /* Save a direct reference to our chipc registers */ 198f4a3eb02SAdrian Chadd sc->core = sc->core_region->cr_res; 1994ad7e9b0SAdrian Chadd 200f4a3eb02SAdrian Chadd /* Fetch and parse capability register(s) */ 201f4a3eb02SAdrian Chadd if ((error = chipc_read_caps(sc, &sc->caps))) 202f4a3eb02SAdrian Chadd goto failed; 2034ad7e9b0SAdrian Chadd 204f4a3eb02SAdrian Chadd if (bootverbose) 205f4a3eb02SAdrian Chadd chipc_print_caps(sc->dev, &sc->caps); 206f4a3eb02SAdrian Chadd 2070c91e892SLandon J. Fuller /* Attach all supported child devices */ 2080c91e892SLandon J. Fuller if ((error = chipc_add_children(sc))) 2090c91e892SLandon J. Fuller goto failed; 2100c91e892SLandon J. Fuller 2114e96bf3aSLandon J. Fuller /* 2124e96bf3aSLandon J. Fuller * Register ourselves with the bus; we're fully initialized and can 2134e96bf3aSLandon J. Fuller * response to ChipCommin API requests. 2144e96bf3aSLandon J. Fuller * 2154e96bf3aSLandon J. Fuller * Since our children may need access to ChipCommon, this must be done 2164e96bf3aSLandon J. Fuller * before attaching our children below (via bus_generic_attach). 2174e96bf3aSLandon J. Fuller */ 2184e96bf3aSLandon J. Fuller if ((error = bhnd_register_provider(dev, BHND_SERVICE_CHIPC))) 219f4a3eb02SAdrian Chadd goto failed; 2204ad7e9b0SAdrian Chadd 2214e96bf3aSLandon J. Fuller if ((error = bus_generic_attach(dev))) 2228e35bf83SLandon J. Fuller goto failed; 2238e35bf83SLandon J. Fuller 2244ad7e9b0SAdrian Chadd return (0); 2254ad7e9b0SAdrian Chadd 226f4a3eb02SAdrian Chadd failed: 2277d1fb1aaSLandon J. Fuller device_delete_children(sc->dev); 2287d1fb1aaSLandon J. Fuller 229f4a3eb02SAdrian Chadd if (sc->core_region != NULL) { 230f4a3eb02SAdrian Chadd chipc_release_region(sc, sc->core_region, 231f4a3eb02SAdrian Chadd RF_ALLOCATED|RF_ACTIVE); 232f4a3eb02SAdrian Chadd } 233f4a3eb02SAdrian Chadd 234f4a3eb02SAdrian Chadd chipc_free_rman(sc); 235e83ce340SAdrian Chadd CHIPC_LOCK_DESTROY(sc); 2364ad7e9b0SAdrian Chadd return (error); 2374ad7e9b0SAdrian Chadd } 2384ad7e9b0SAdrian Chadd 2394ad7e9b0SAdrian Chadd static int 2404ad7e9b0SAdrian Chadd chipc_detach(device_t dev) 2414ad7e9b0SAdrian Chadd { 2424ad7e9b0SAdrian Chadd struct chipc_softc *sc; 243f4a3eb02SAdrian Chadd int error; 2444ad7e9b0SAdrian Chadd 2454ad7e9b0SAdrian Chadd sc = device_get_softc(dev); 246f4a3eb02SAdrian Chadd 24719b3e4aaSLandon J. Fuller if ((error = bus_generic_detach(dev))) 2488e35bf83SLandon J. Fuller return (error); 2498e35bf83SLandon J. Fuller 250f248a99aSLandon J. Fuller if ((error = device_delete_children(dev))) 251f248a99aSLandon J. Fuller return (error); 252f248a99aSLandon J. Fuller 25319b3e4aaSLandon J. Fuller if ((error = bhnd_deregister_provider(dev, BHND_SERVICE_ANY))) 254f4a3eb02SAdrian Chadd return (error); 255f4a3eb02SAdrian Chadd 256f4a3eb02SAdrian Chadd chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE); 257f4a3eb02SAdrian Chadd chipc_free_rman(sc); 258e83ce340SAdrian Chadd 259e83ce340SAdrian Chadd CHIPC_LOCK_DESTROY(sc); 2604ad7e9b0SAdrian Chadd 2614ad7e9b0SAdrian Chadd return (0); 2624ad7e9b0SAdrian Chadd } 2634ad7e9b0SAdrian Chadd 2640c91e892SLandon J. Fuller static int 2650c91e892SLandon J. Fuller chipc_add_children(struct chipc_softc *sc) 2660c91e892SLandon J. Fuller { 2670c91e892SLandon J. Fuller device_t child; 2680c91e892SLandon J. Fuller const char *flash_bus; 2690c91e892SLandon J. Fuller int error; 2700c91e892SLandon J. Fuller 2710c91e892SLandon J. Fuller /* SPROM/OTP */ 2720c91e892SLandon J. Fuller if (sc->caps.nvram_src == BHND_NVRAM_SRC_SPROM || 2730c91e892SLandon J. Fuller sc->caps.nvram_src == BHND_NVRAM_SRC_OTP) 2740c91e892SLandon J. Fuller { 2750c91e892SLandon J. Fuller child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_nvram", -1); 2760c91e892SLandon J. Fuller if (child == NULL) { 2770c91e892SLandon J. Fuller device_printf(sc->dev, "failed to add nvram device\n"); 2780c91e892SLandon J. Fuller return (ENXIO); 2790c91e892SLandon J. Fuller } 2800c91e892SLandon J. Fuller 2810c91e892SLandon J. Fuller /* Both OTP and external SPROM are mapped at CHIPC_SPROM_OTP */ 282caeff9a3SLandon J. Fuller error = chipc_set_mem_resource(sc, child, 0, CHIPC_SPROM_OTP, 283caeff9a3SLandon J. Fuller CHIPC_SPROM_OTP_SIZE, 0, 0); 284caeff9a3SLandon J. Fuller if (error) { 285caeff9a3SLandon J. Fuller device_printf(sc->dev, "failed to set OTP memory " 286caeff9a3SLandon J. Fuller "resource: %d\n", error); 2870c91e892SLandon J. Fuller return (error); 2880c91e892SLandon J. Fuller } 289caeff9a3SLandon J. Fuller } 2900c91e892SLandon J. Fuller 2910c91e892SLandon J. Fuller /* 292f90f4b65SLandon J. Fuller * PMU/PWR_CTRL 2930c91e892SLandon J. Fuller * 294f90f4b65SLandon J. Fuller * On AOB ("Always on Bus") devices, the PMU core (if it exists) is 295f90f4b65SLandon J. Fuller * attached directly to the bhnd(4) bus -- not chipc. 2960c91e892SLandon J. Fuller */ 2974e96bf3aSLandon J. Fuller if (sc->caps.pmu && !sc->caps.aob) { 2985ad00fa2SLandon J. Fuller child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pmu", -1); 2990c91e892SLandon J. Fuller if (child == NULL) { 3000c91e892SLandon J. Fuller device_printf(sc->dev, "failed to add pmu\n"); 3010c91e892SLandon J. Fuller return (ENXIO); 3020c91e892SLandon J. Fuller } 3034e96bf3aSLandon J. Fuller } else if (sc->caps.pwr_ctrl) { 3045ad00fa2SLandon J. Fuller child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pwrctl", -1); 3054e96bf3aSLandon J. Fuller if (child == NULL) { 3064e96bf3aSLandon J. Fuller device_printf(sc->dev, "failed to add pwrctl\n"); 3074e96bf3aSLandon J. Fuller return (ENXIO); 3084e96bf3aSLandon J. Fuller } 3090c91e892SLandon J. Fuller } 3100c91e892SLandon J. Fuller 3112f909a9fSLandon J. Fuller /* GPIO */ 3125ad00fa2SLandon J. Fuller child = BUS_ADD_CHILD(sc->dev, 0, "gpio", -1); 3132f909a9fSLandon J. Fuller if (child == NULL) { 3142f909a9fSLandon J. Fuller device_printf(sc->dev, "failed to add gpio\n"); 3152f909a9fSLandon J. Fuller return (ENXIO); 3162f909a9fSLandon J. Fuller } 3172f909a9fSLandon J. Fuller 3182f909a9fSLandon J. Fuller error = chipc_set_mem_resource(sc, child, 0, 0, RM_MAX_END, 0, 0); 3192f909a9fSLandon J. Fuller if (error) { 3202f909a9fSLandon J. Fuller device_printf(sc->dev, "failed to set gpio memory resource: " 3212f909a9fSLandon J. Fuller "%d\n", error); 3222f909a9fSLandon J. Fuller return (error); 3232f909a9fSLandon J. Fuller } 3242f909a9fSLandon J. Fuller 3250c91e892SLandon J. Fuller /* All remaining devices are SoC-only */ 3260c91e892SLandon J. Fuller if (bhnd_get_attach_type(sc->dev) != BHND_ATTACH_NATIVE) 3270c91e892SLandon J. Fuller return (0); 3280c91e892SLandon J. Fuller 3290c91e892SLandon J. Fuller /* UARTs */ 3300c91e892SLandon J. Fuller for (u_int i = 0; i < min(sc->caps.num_uarts, CHIPC_UART_MAX); i++) { 331caeff9a3SLandon J. Fuller int irq_rid, mem_rid; 332caeff9a3SLandon J. Fuller 333caeff9a3SLandon J. Fuller irq_rid = 0; 334caeff9a3SLandon J. Fuller mem_rid = 0; 335caeff9a3SLandon J. Fuller 3360c91e892SLandon J. Fuller child = BUS_ADD_CHILD(sc->dev, 0, "uart", -1); 3370c91e892SLandon J. Fuller if (child == NULL) { 3380c91e892SLandon J. Fuller device_printf(sc->dev, "failed to add uart%u\n", i); 3390c91e892SLandon J. Fuller return (ENXIO); 3400c91e892SLandon J. Fuller } 3410c91e892SLandon J. Fuller 3420c91e892SLandon J. Fuller /* Shared IRQ */ 343caeff9a3SLandon J. Fuller error = chipc_set_irq_resource(sc, child, irq_rid, 0); 3440c91e892SLandon J. Fuller if (error) { 3450c91e892SLandon J. Fuller device_printf(sc->dev, "failed to set uart%u irq %u\n", 346caeff9a3SLandon J. Fuller i, 0); 3470c91e892SLandon J. Fuller return (error); 3480c91e892SLandon J. Fuller } 3490c91e892SLandon J. Fuller 3500c91e892SLandon J. Fuller /* UART registers are mapped sequentially */ 351caeff9a3SLandon J. Fuller error = chipc_set_mem_resource(sc, child, mem_rid, 3520c91e892SLandon J. Fuller CHIPC_UART(i), CHIPC_UART_SIZE, 0, 0); 353caeff9a3SLandon J. Fuller if (error) { 354caeff9a3SLandon J. Fuller device_printf(sc->dev, "failed to set uart%u memory " 355caeff9a3SLandon J. Fuller "resource: %d\n", i, error); 3560c91e892SLandon J. Fuller return (error); 3570c91e892SLandon J. Fuller } 358caeff9a3SLandon J. Fuller } 3590c91e892SLandon J. Fuller 3600c91e892SLandon J. Fuller /* Flash */ 3610c91e892SLandon J. Fuller flash_bus = chipc_flash_bus_name(sc->caps.flash_type); 3620c91e892SLandon J. Fuller if (flash_bus != NULL) { 363caeff9a3SLandon J. Fuller int rid; 364caeff9a3SLandon J. Fuller 3650c91e892SLandon J. Fuller child = BUS_ADD_CHILD(sc->dev, 0, flash_bus, -1); 3660c91e892SLandon J. Fuller if (child == NULL) { 3670c91e892SLandon J. Fuller device_printf(sc->dev, "failed to add %s device\n", 3680c91e892SLandon J. Fuller flash_bus); 3690c91e892SLandon J. Fuller return (ENXIO); 3700c91e892SLandon J. Fuller } 3710c91e892SLandon J. Fuller 3720c91e892SLandon J. Fuller /* flash memory mapping */ 373caeff9a3SLandon J. Fuller rid = 0; 374caeff9a3SLandon J. Fuller error = chipc_set_mem_resource(sc, child, rid, 0, RM_MAX_END, 1, 375caeff9a3SLandon J. Fuller 1); 376caeff9a3SLandon J. Fuller if (error) { 377caeff9a3SLandon J. Fuller device_printf(sc->dev, "failed to set flash memory " 378caeff9a3SLandon J. Fuller "resource %d: %d\n", rid, error); 3790c91e892SLandon J. Fuller return (error); 380caeff9a3SLandon J. Fuller } 3810c91e892SLandon J. Fuller 3820c91e892SLandon J. Fuller /* flashctrl registers */ 383caeff9a3SLandon J. Fuller rid++; 384caeff9a3SLandon J. Fuller error = chipc_set_mem_resource(sc, child, rid, 3850c91e892SLandon J. Fuller CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0, 0); 386caeff9a3SLandon J. Fuller if (error) { 387caeff9a3SLandon J. Fuller device_printf(sc->dev, "failed to set flash memory " 388caeff9a3SLandon J. Fuller "resource %d: %d\n", rid, error); 3890c91e892SLandon J. Fuller return (error); 3900c91e892SLandon J. Fuller } 391caeff9a3SLandon J. Fuller } 3920c91e892SLandon J. Fuller 3930c91e892SLandon J. Fuller return (0); 3940c91e892SLandon J. Fuller } 3950c91e892SLandon J. Fuller 39656a4cdd1SLandon J. Fuller /** 39756a4cdd1SLandon J. Fuller * Determine the NVRAM data source for this device. 39856a4cdd1SLandon J. Fuller * 39956a4cdd1SLandon J. Fuller * The SPROM, OTP, and flash capability flags must be fully populated in 40056a4cdd1SLandon J. Fuller * @p caps. 40156a4cdd1SLandon J. Fuller * 40256a4cdd1SLandon J. Fuller * @param sc chipc driver state. 40356a4cdd1SLandon J. Fuller * @param caps capability flags to be used to derive NVRAM configuration. 40456a4cdd1SLandon J. Fuller */ 40556a4cdd1SLandon J. Fuller static bhnd_nvram_src 40656a4cdd1SLandon J. Fuller chipc_find_nvram_src(struct chipc_softc *sc, struct chipc_caps *caps) 40756a4cdd1SLandon J. Fuller { 40856a4cdd1SLandon J. Fuller uint32_t otp_st, srom_ctrl; 40956a4cdd1SLandon J. Fuller 41056a4cdd1SLandon J. Fuller /* 41156a4cdd1SLandon J. Fuller * We check for hardware presence in order of precedence. For example, 412060f5c02SGordon Bergling * SPROM is always used in preference to internal OTP if found. 41356a4cdd1SLandon J. Fuller */ 4141728aef2SLandon J. Fuller if (CHIPC_QUIRK(sc, SUPPORTS_SPROM) && caps->sprom) { 41556a4cdd1SLandon J. Fuller srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL); 41656a4cdd1SLandon J. Fuller if (srom_ctrl & CHIPC_SRC_PRESENT) 41756a4cdd1SLandon J. Fuller return (BHND_NVRAM_SRC_SPROM); 41856a4cdd1SLandon J. Fuller } 41956a4cdd1SLandon J. Fuller 42056a4cdd1SLandon J. Fuller /* Check for programmed OTP H/W subregion (contains SROM data) */ 42156a4cdd1SLandon J. Fuller if (CHIPC_QUIRK(sc, SUPPORTS_OTP) && caps->otp_size > 0) { 42256a4cdd1SLandon J. Fuller /* TODO: need access to HND-OTP device */ 42356a4cdd1SLandon J. Fuller if (!CHIPC_QUIRK(sc, OTP_HND)) { 42456a4cdd1SLandon J. Fuller device_printf(sc->dev, 42556a4cdd1SLandon J. Fuller "NVRAM unavailable: unsupported OTP controller.\n"); 42656a4cdd1SLandon J. Fuller return (BHND_NVRAM_SRC_UNKNOWN); 42756a4cdd1SLandon J. Fuller } 42856a4cdd1SLandon J. Fuller 42956a4cdd1SLandon J. Fuller otp_st = bhnd_bus_read_4(sc->core, CHIPC_OTPST); 43056a4cdd1SLandon J. Fuller if (otp_st & CHIPC_OTPS_GUP_HW) 43156a4cdd1SLandon J. Fuller return (BHND_NVRAM_SRC_OTP); 43256a4cdd1SLandon J. Fuller } 43356a4cdd1SLandon J. Fuller 43456a4cdd1SLandon J. Fuller /* Check for flash */ 43556a4cdd1SLandon J. Fuller if (caps->flash_type != CHIPC_FLASH_NONE) 43656a4cdd1SLandon J. Fuller return (BHND_NVRAM_SRC_FLASH); 43756a4cdd1SLandon J. Fuller 43856a4cdd1SLandon J. Fuller /* No NVRAM hardware capability declared */ 43956a4cdd1SLandon J. Fuller return (BHND_NVRAM_SRC_UNKNOWN); 44056a4cdd1SLandon J. Fuller } 44156a4cdd1SLandon J. Fuller 442f4a3eb02SAdrian Chadd /* Read and parse chipc capabilities */ 4434ad7e9b0SAdrian Chadd static int 444f4a3eb02SAdrian Chadd chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps) 4454ad7e9b0SAdrian Chadd { 446f4a3eb02SAdrian Chadd uint32_t cap_reg; 447f4a3eb02SAdrian Chadd uint32_t cap_ext_reg; 448f4a3eb02SAdrian Chadd uint32_t regval; 449f4a3eb02SAdrian Chadd 450f4a3eb02SAdrian Chadd /* Fetch cap registers */ 451f4a3eb02SAdrian Chadd cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES); 452f4a3eb02SAdrian Chadd cap_ext_reg = 0; 453f4a3eb02SAdrian Chadd if (CHIPC_QUIRK(sc, SUPPORTS_CAP_EXT)) 454f4a3eb02SAdrian Chadd cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT); 455f4a3eb02SAdrian Chadd 456f4a3eb02SAdrian Chadd /* Extract values */ 457f4a3eb02SAdrian Chadd caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART); 458f4a3eb02SAdrian Chadd caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB); 459f4a3eb02SAdrian Chadd caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO); 460f4a3eb02SAdrian Chadd caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL); 461f4a3eb02SAdrian Chadd 462f4a3eb02SAdrian Chadd caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS); 463f90f4b65SLandon J. Fuller caps->pwr_ctrl = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL); 464f4a3eb02SAdrian Chadd caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP); 465f4a3eb02SAdrian Chadd 466f4a3eb02SAdrian Chadd caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL); 467f4a3eb02SAdrian Chadd caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64); 468f4a3eb02SAdrian Chadd caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM); 469f4a3eb02SAdrian Chadd caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU); 470f4a3eb02SAdrian Chadd caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI); 471f4a3eb02SAdrian Chadd caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM); 472f4a3eb02SAdrian Chadd caps->otp_size = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_OTP_SIZE); 473f4a3eb02SAdrian Chadd 474f4a3eb02SAdrian Chadd caps->seci = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_SECI); 475f4a3eb02SAdrian Chadd caps->gsio = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_GSIO); 476f4a3eb02SAdrian Chadd caps->aob = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_AOB); 477f4a3eb02SAdrian Chadd 478f4a3eb02SAdrian Chadd /* Fetch OTP size for later IPX controller revisions */ 47956a4cdd1SLandon J. Fuller if (CHIPC_QUIRK(sc, IPX_OTPL_SIZE)) { 480f4a3eb02SAdrian Chadd regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 481f4a3eb02SAdrian Chadd caps->otp_size = CHIPC_GET_BITS(regval, CHIPC_OTPL_SIZE); 4824ad7e9b0SAdrian Chadd } 4834ad7e9b0SAdrian Chadd 4845ad9ac03SAdrian Chadd /* Determine flash type and parameters */ 485f4a3eb02SAdrian Chadd caps->cfi_width = 0; 486f4a3eb02SAdrian Chadd switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) { 487f4a3eb02SAdrian Chadd case CHIPC_CAP_SFLASH_ST: 488f4a3eb02SAdrian Chadd caps->flash_type = CHIPC_SFLASH_ST; 489f4a3eb02SAdrian Chadd break; 490f4a3eb02SAdrian Chadd case CHIPC_CAP_SFLASH_AT: 491f4a3eb02SAdrian Chadd caps->flash_type = CHIPC_SFLASH_AT; 492f4a3eb02SAdrian Chadd break; 493f4a3eb02SAdrian Chadd case CHIPC_CAP_NFLASH: 4940c91e892SLandon J. Fuller /* unimplemented */ 495f4a3eb02SAdrian Chadd caps->flash_type = CHIPC_NFLASH; 496f4a3eb02SAdrian Chadd break; 497f4a3eb02SAdrian Chadd case CHIPC_CAP_PFLASH: 498f4a3eb02SAdrian Chadd caps->flash_type = CHIPC_PFLASH_CFI; 499f4a3eb02SAdrian Chadd 500f4a3eb02SAdrian Chadd /* determine cfi width */ 501f4a3eb02SAdrian Chadd regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG); 502f4a3eb02SAdrian Chadd if (CHIPC_GET_FLAG(regval, CHIPC_FLASH_CFG_DS)) 503f4a3eb02SAdrian Chadd caps->cfi_width = 2; 504f4a3eb02SAdrian Chadd else 505f4a3eb02SAdrian Chadd caps->cfi_width = 1; 506f4a3eb02SAdrian Chadd 507f4a3eb02SAdrian Chadd break; 508f4a3eb02SAdrian Chadd case CHIPC_CAP_FLASH_NONE: 509f4a3eb02SAdrian Chadd caps->flash_type = CHIPC_FLASH_NONE; 510f4a3eb02SAdrian Chadd break; 511f4a3eb02SAdrian Chadd 512f4a3eb02SAdrian Chadd } 513f4a3eb02SAdrian Chadd 514f4a3eb02SAdrian Chadd /* Handle 4706_NFLASH fallback */ 515f4a3eb02SAdrian Chadd if (CHIPC_QUIRK(sc, 4706_NFLASH) && 516f4a3eb02SAdrian Chadd CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_4706_NFLASH)) 5174ad7e9b0SAdrian Chadd { 518f4a3eb02SAdrian Chadd caps->flash_type = CHIPC_NFLASH_4706; 519f4a3eb02SAdrian Chadd } 520f4a3eb02SAdrian Chadd 52156a4cdd1SLandon J. Fuller /* Determine NVRAM source. Must occur after the SPROM/OTP/flash 52256a4cdd1SLandon J. Fuller * capability flags have been populated. */ 52356a4cdd1SLandon J. Fuller caps->nvram_src = chipc_find_nvram_src(sc, caps); 52456a4cdd1SLandon J. Fuller 52556a4cdd1SLandon J. Fuller /* Determine the SPROM offset within OTP (if any). SPROM-formatted 52656a4cdd1SLandon J. Fuller * data is placed within the OTP general use region. */ 52756a4cdd1SLandon J. Fuller caps->sprom_offset = 0; 52856a4cdd1SLandon J. Fuller if (caps->nvram_src == BHND_NVRAM_SRC_OTP) { 52956a4cdd1SLandon J. Fuller CHIPC_ASSERT_QUIRK(sc, OTP_IPX); 53056a4cdd1SLandon J. Fuller 53156a4cdd1SLandon J. Fuller /* Bit offset to GUP HW subregion containing SPROM data */ 53256a4cdd1SLandon J. Fuller regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 53356a4cdd1SLandon J. Fuller caps->sprom_offset = CHIPC_GET_BITS(regval, CHIPC_OTPL_GUP); 53456a4cdd1SLandon J. Fuller 53556a4cdd1SLandon J. Fuller /* Convert to bytes */ 53656a4cdd1SLandon J. Fuller caps->sprom_offset /= 8; 53756a4cdd1SLandon J. Fuller } 53856a4cdd1SLandon J. Fuller 5394ad7e9b0SAdrian Chadd return (0); 5404ad7e9b0SAdrian Chadd } 5414ad7e9b0SAdrian Chadd 542f4a3eb02SAdrian Chadd static int 543f4a3eb02SAdrian Chadd chipc_suspend(device_t dev) 544f4a3eb02SAdrian Chadd { 545f4a3eb02SAdrian Chadd return (bus_generic_suspend(dev)); 546f4a3eb02SAdrian Chadd } 547f4a3eb02SAdrian Chadd 548f4a3eb02SAdrian Chadd static int 549f4a3eb02SAdrian Chadd chipc_resume(device_t dev) 550f4a3eb02SAdrian Chadd { 551f4a3eb02SAdrian Chadd return (bus_generic_resume(dev)); 552f4a3eb02SAdrian Chadd } 553f4a3eb02SAdrian Chadd 554f4a3eb02SAdrian Chadd static void 555f4a3eb02SAdrian Chadd chipc_probe_nomatch(device_t dev, device_t child) 556f4a3eb02SAdrian Chadd { 557f4a3eb02SAdrian Chadd struct resource_list *rl; 558f4a3eb02SAdrian Chadd const char *name; 559f4a3eb02SAdrian Chadd 560f4a3eb02SAdrian Chadd name = device_get_name(child); 561f4a3eb02SAdrian Chadd if (name == NULL) 562f4a3eb02SAdrian Chadd name = "unknown device"; 563f4a3eb02SAdrian Chadd 564f4a3eb02SAdrian Chadd device_printf(dev, "<%s> at", name); 565f4a3eb02SAdrian Chadd 566f4a3eb02SAdrian Chadd rl = BUS_GET_RESOURCE_LIST(dev, child); 567f4a3eb02SAdrian Chadd if (rl != NULL) { 568f4a3eb02SAdrian Chadd resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 569f4a3eb02SAdrian Chadd resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 570f4a3eb02SAdrian Chadd } 571f4a3eb02SAdrian Chadd 572f4a3eb02SAdrian Chadd printf(" (no driver attached)\n"); 573f4a3eb02SAdrian Chadd } 574f4a3eb02SAdrian Chadd 575f4a3eb02SAdrian Chadd static int 576f4a3eb02SAdrian Chadd chipc_print_child(device_t dev, device_t child) 577f4a3eb02SAdrian Chadd { 578f4a3eb02SAdrian Chadd struct resource_list *rl; 579f4a3eb02SAdrian Chadd int retval = 0; 580f4a3eb02SAdrian Chadd 581f4a3eb02SAdrian Chadd retval += bus_print_child_header(dev, child); 582f4a3eb02SAdrian Chadd 583f4a3eb02SAdrian Chadd rl = BUS_GET_RESOURCE_LIST(dev, child); 584f4a3eb02SAdrian Chadd if (rl != NULL) { 585f4a3eb02SAdrian Chadd retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, 586f4a3eb02SAdrian Chadd "%#jx"); 587f4a3eb02SAdrian Chadd retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, 588f4a3eb02SAdrian Chadd "%jd"); 589f4a3eb02SAdrian Chadd } 590f4a3eb02SAdrian Chadd 591f4a3eb02SAdrian Chadd retval += bus_print_child_domain(dev, child); 592f4a3eb02SAdrian Chadd retval += bus_print_child_footer(dev, child); 593f4a3eb02SAdrian Chadd 594f4a3eb02SAdrian Chadd return (retval); 595f4a3eb02SAdrian Chadd } 596f4a3eb02SAdrian Chadd 597f4a3eb02SAdrian Chadd static device_t 598f4a3eb02SAdrian Chadd chipc_add_child(device_t dev, u_int order, const char *name, int unit) 599f4a3eb02SAdrian Chadd { 600f4a3eb02SAdrian Chadd struct chipc_devinfo *dinfo; 601f4a3eb02SAdrian Chadd device_t child; 6020c91e892SLandon J. Fuller 603f4a3eb02SAdrian Chadd child = device_add_child_ordered(dev, order, name, unit); 604f4a3eb02SAdrian Chadd if (child == NULL) 605f4a3eb02SAdrian Chadd return (NULL); 606f4a3eb02SAdrian Chadd 607f4a3eb02SAdrian Chadd dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT); 608f4a3eb02SAdrian Chadd if (dinfo == NULL) { 609f4a3eb02SAdrian Chadd device_delete_child(dev, child); 610f4a3eb02SAdrian Chadd return (NULL); 611f4a3eb02SAdrian Chadd } 612f4a3eb02SAdrian Chadd 613f4a3eb02SAdrian Chadd resource_list_init(&dinfo->resources); 614caeff9a3SLandon J. Fuller dinfo->irq_mapped = false; 615f4a3eb02SAdrian Chadd device_set_ivars(child, dinfo); 616f4a3eb02SAdrian Chadd 617f4a3eb02SAdrian Chadd return (child); 618f4a3eb02SAdrian Chadd } 619f4a3eb02SAdrian Chadd 620f4a3eb02SAdrian Chadd static void 621f4a3eb02SAdrian Chadd chipc_child_deleted(device_t dev, device_t child) 622f4a3eb02SAdrian Chadd { 623f4a3eb02SAdrian Chadd struct chipc_devinfo *dinfo = device_get_ivars(child); 624f4a3eb02SAdrian Chadd 625f4a3eb02SAdrian Chadd if (dinfo != NULL) { 626caeff9a3SLandon J. Fuller /* Free the child's resource list */ 627f4a3eb02SAdrian Chadd resource_list_free(&dinfo->resources); 628caeff9a3SLandon J. Fuller 629caeff9a3SLandon J. Fuller /* Unmap the child's IRQ */ 630caeff9a3SLandon J. Fuller if (dinfo->irq_mapped) { 631caeff9a3SLandon J. Fuller bhnd_unmap_intr(dev, dinfo->irq); 632caeff9a3SLandon J. Fuller dinfo->irq_mapped = false; 633caeff9a3SLandon J. Fuller } 634caeff9a3SLandon J. Fuller 635f4a3eb02SAdrian Chadd free(dinfo, M_BHND); 636f4a3eb02SAdrian Chadd } 637f4a3eb02SAdrian Chadd 638f4a3eb02SAdrian Chadd device_set_ivars(child, NULL); 639f4a3eb02SAdrian Chadd } 640f4a3eb02SAdrian Chadd 641f4a3eb02SAdrian Chadd static struct resource_list * 642f4a3eb02SAdrian Chadd chipc_get_resource_list(device_t dev, device_t child) 643f4a3eb02SAdrian Chadd { 644f4a3eb02SAdrian Chadd struct chipc_devinfo *dinfo = device_get_ivars(child); 645f4a3eb02SAdrian Chadd return (&dinfo->resources); 646f4a3eb02SAdrian Chadd } 647f4a3eb02SAdrian Chadd 648f4a3eb02SAdrian Chadd /* Allocate region records for the given port, and add the port's memory 649f4a3eb02SAdrian Chadd * range to the mem_rman */ 650f4a3eb02SAdrian Chadd static int 651f4a3eb02SAdrian Chadd chipc_rman_init_regions (struct chipc_softc *sc, bhnd_port_type type, 652f4a3eb02SAdrian Chadd u_int port) 653f4a3eb02SAdrian Chadd { 654f4a3eb02SAdrian Chadd struct chipc_region *cr; 655f4a3eb02SAdrian Chadd rman_res_t start, end; 656f4a3eb02SAdrian Chadd u_int num_regions; 657f4a3eb02SAdrian Chadd int error; 658f4a3eb02SAdrian Chadd 6590c91e892SLandon J. Fuller num_regions = bhnd_get_region_count(sc->dev, type, port); 660f4a3eb02SAdrian Chadd for (u_int region = 0; region < num_regions; region++) { 661f4a3eb02SAdrian Chadd /* Allocate new region record */ 662f4a3eb02SAdrian Chadd cr = chipc_alloc_region(sc, type, port, region); 663f4a3eb02SAdrian Chadd if (cr == NULL) 664f4a3eb02SAdrian Chadd return (ENODEV); 665f4a3eb02SAdrian Chadd 666f4a3eb02SAdrian Chadd /* Can't manage regions that cannot be allocated */ 667f4a3eb02SAdrian Chadd if (cr->cr_rid < 0) { 668f4a3eb02SAdrian Chadd BHND_DEBUG_DEV(sc->dev, "no rid for chipc region " 669f4a3eb02SAdrian Chadd "%s%u.%u", bhnd_port_type_name(type), port, region); 670f4a3eb02SAdrian Chadd chipc_free_region(sc, cr); 671f4a3eb02SAdrian Chadd continue; 672f4a3eb02SAdrian Chadd } 673f4a3eb02SAdrian Chadd 674f4a3eb02SAdrian Chadd /* Add to rman's managed range */ 675f4a3eb02SAdrian Chadd start = cr->cr_addr; 676f4a3eb02SAdrian Chadd end = cr->cr_end; 677f4a3eb02SAdrian Chadd if ((error = rman_manage_region(&sc->mem_rman, start, end))) { 678f4a3eb02SAdrian Chadd chipc_free_region(sc, cr); 679f4a3eb02SAdrian Chadd return (error); 680f4a3eb02SAdrian Chadd } 681f4a3eb02SAdrian Chadd 682f4a3eb02SAdrian Chadd /* Add to region list */ 683f4a3eb02SAdrian Chadd STAILQ_INSERT_TAIL(&sc->mem_regions, cr, cr_link); 684f4a3eb02SAdrian Chadd } 685f4a3eb02SAdrian Chadd 686f4a3eb02SAdrian Chadd return (0); 687f4a3eb02SAdrian Chadd } 688f4a3eb02SAdrian Chadd 689f4a3eb02SAdrian Chadd /* Initialize memory state for all chipc port regions */ 690f4a3eb02SAdrian Chadd static int 691f4a3eb02SAdrian Chadd chipc_init_rman(struct chipc_softc *sc) 692f4a3eb02SAdrian Chadd { 693f4a3eb02SAdrian Chadd u_int num_ports; 694f4a3eb02SAdrian Chadd int error; 695f4a3eb02SAdrian Chadd 696f4a3eb02SAdrian Chadd /* Port types for which we'll register chipc_region mappings */ 697f4a3eb02SAdrian Chadd bhnd_port_type types[] = { 698f4a3eb02SAdrian Chadd BHND_PORT_DEVICE 699f4a3eb02SAdrian Chadd }; 700f4a3eb02SAdrian Chadd 701f4a3eb02SAdrian Chadd /* Initialize resource manager */ 702f4a3eb02SAdrian Chadd sc->mem_rman.rm_start = 0; 703f4a3eb02SAdrian Chadd sc->mem_rman.rm_end = BUS_SPACE_MAXADDR; 704f4a3eb02SAdrian Chadd sc->mem_rman.rm_type = RMAN_ARRAY; 705f4a3eb02SAdrian Chadd sc->mem_rman.rm_descr = "ChipCommon Device Memory"; 706f4a3eb02SAdrian Chadd if ((error = rman_init(&sc->mem_rman))) { 707f4a3eb02SAdrian Chadd device_printf(sc->dev, "could not initialize mem_rman: %d\n", 708f4a3eb02SAdrian Chadd error); 709f4a3eb02SAdrian Chadd return (error); 710f4a3eb02SAdrian Chadd } 711f4a3eb02SAdrian Chadd 712f4a3eb02SAdrian Chadd /* Populate per-port-region state */ 713f4a3eb02SAdrian Chadd for (u_int i = 0; i < nitems(types); i++) { 714f4a3eb02SAdrian Chadd num_ports = bhnd_get_port_count(sc->dev, types[i]); 715f4a3eb02SAdrian Chadd for (u_int port = 0; port < num_ports; port++) { 716f4a3eb02SAdrian Chadd error = chipc_rman_init_regions(sc, types[i], port); 717f4a3eb02SAdrian Chadd if (error) { 718f4a3eb02SAdrian Chadd device_printf(sc->dev, 719f4a3eb02SAdrian Chadd "region init failed for %s%u: %d\n", 720f4a3eb02SAdrian Chadd bhnd_port_type_name(types[i]), port, 721f4a3eb02SAdrian Chadd error); 722f4a3eb02SAdrian Chadd 723f4a3eb02SAdrian Chadd goto failed; 724f4a3eb02SAdrian Chadd } 725f4a3eb02SAdrian Chadd } 726f4a3eb02SAdrian Chadd } 727f4a3eb02SAdrian Chadd 728f4a3eb02SAdrian Chadd return (0); 729f4a3eb02SAdrian Chadd 730f4a3eb02SAdrian Chadd failed: 731f4a3eb02SAdrian Chadd chipc_free_rman(sc); 732f4a3eb02SAdrian Chadd return (error); 733f4a3eb02SAdrian Chadd } 734f4a3eb02SAdrian Chadd 735f4a3eb02SAdrian Chadd /* Free memory management state */ 736f4a3eb02SAdrian Chadd static void 737f4a3eb02SAdrian Chadd chipc_free_rman(struct chipc_softc *sc) 738f4a3eb02SAdrian Chadd { 739f4a3eb02SAdrian Chadd struct chipc_region *cr, *cr_next; 740f4a3eb02SAdrian Chadd 741f4a3eb02SAdrian Chadd STAILQ_FOREACH_SAFE(cr, &sc->mem_regions, cr_link, cr_next) 742f4a3eb02SAdrian Chadd chipc_free_region(sc, cr); 743f4a3eb02SAdrian Chadd 744f4a3eb02SAdrian Chadd rman_fini(&sc->mem_rman); 745f4a3eb02SAdrian Chadd } 746f4a3eb02SAdrian Chadd 747f4a3eb02SAdrian Chadd /** 748f4a3eb02SAdrian Chadd * Return the rman instance for a given resource @p type, if any. 749f4a3eb02SAdrian Chadd * 750f4a3eb02SAdrian Chadd * @param sc The chipc device state. 751f4a3eb02SAdrian Chadd * @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...) 752f4a3eb02SAdrian Chadd */ 753f4a3eb02SAdrian Chadd static struct rman * 754f4a3eb02SAdrian Chadd chipc_get_rman(struct chipc_softc *sc, int type) 755f4a3eb02SAdrian Chadd { 756f4a3eb02SAdrian Chadd switch (type) { 757f4a3eb02SAdrian Chadd case SYS_RES_MEMORY: 758f4a3eb02SAdrian Chadd return (&sc->mem_rman); 759f4a3eb02SAdrian Chadd 760f4a3eb02SAdrian Chadd case SYS_RES_IRQ: 761caeff9a3SLandon J. Fuller /* We delegate IRQ resource management to the parent bus */ 762f4a3eb02SAdrian Chadd return (NULL); 763f4a3eb02SAdrian Chadd 764f4a3eb02SAdrian Chadd default: 765f4a3eb02SAdrian Chadd return (NULL); 766f4a3eb02SAdrian Chadd }; 767f4a3eb02SAdrian Chadd } 768f4a3eb02SAdrian Chadd 769f4a3eb02SAdrian Chadd static struct resource * 770f4a3eb02SAdrian Chadd chipc_alloc_resource(device_t dev, device_t child, int type, 771f4a3eb02SAdrian Chadd int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 772f4a3eb02SAdrian Chadd { 773f4a3eb02SAdrian Chadd struct chipc_softc *sc; 774f4a3eb02SAdrian Chadd struct chipc_region *cr; 775f4a3eb02SAdrian Chadd struct resource_list_entry *rle; 776f4a3eb02SAdrian Chadd struct resource *rv; 777f4a3eb02SAdrian Chadd struct rman *rm; 778f4a3eb02SAdrian Chadd int error; 779f4a3eb02SAdrian Chadd bool passthrough, isdefault; 780f4a3eb02SAdrian Chadd 781f4a3eb02SAdrian Chadd sc = device_get_softc(dev); 782f4a3eb02SAdrian Chadd passthrough = (device_get_parent(child) != dev); 783f4a3eb02SAdrian Chadd isdefault = RMAN_IS_DEFAULT_RANGE(start, end); 784f4a3eb02SAdrian Chadd rle = NULL; 785f4a3eb02SAdrian Chadd 786f4a3eb02SAdrian Chadd /* Fetch the resource manager, delegate request if necessary */ 787f4a3eb02SAdrian Chadd rm = chipc_get_rman(sc, type); 788f4a3eb02SAdrian Chadd if (rm == NULL) { 789f4a3eb02SAdrian Chadd /* Requested resource type is delegated to our parent */ 790f4a3eb02SAdrian Chadd rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 791f4a3eb02SAdrian Chadd start, end, count, flags); 792f4a3eb02SAdrian Chadd return (rv); 793f4a3eb02SAdrian Chadd } 794f4a3eb02SAdrian Chadd 795f4a3eb02SAdrian Chadd /* Populate defaults */ 796f4a3eb02SAdrian Chadd if (!passthrough && isdefault) { 797f4a3eb02SAdrian Chadd /* Fetch the resource list entry. */ 798f4a3eb02SAdrian Chadd rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), 799f4a3eb02SAdrian Chadd type, *rid); 800f4a3eb02SAdrian Chadd if (rle == NULL) { 801f4a3eb02SAdrian Chadd device_printf(dev, 802f4a3eb02SAdrian Chadd "default resource %#x type %d for child %s " 803f4a3eb02SAdrian Chadd "not found\n", *rid, type, 804f4a3eb02SAdrian Chadd device_get_nameunit(child)); 805f4a3eb02SAdrian Chadd return (NULL); 806f4a3eb02SAdrian Chadd } 807f4a3eb02SAdrian Chadd 808f4a3eb02SAdrian Chadd if (rle->res != NULL) { 809f4a3eb02SAdrian Chadd device_printf(dev, 8102b693a88SLandon J. Fuller "resource entry %#x type %d for child %s is busy " 8112b693a88SLandon J. Fuller "[%d]\n", 8122b693a88SLandon J. Fuller *rid, type, device_get_nameunit(child), 8132b693a88SLandon J. Fuller rman_get_flags(rle->res)); 814f4a3eb02SAdrian Chadd 815f4a3eb02SAdrian Chadd return (NULL); 816f4a3eb02SAdrian Chadd } 817f4a3eb02SAdrian Chadd 818f4a3eb02SAdrian Chadd start = rle->start; 819f4a3eb02SAdrian Chadd end = rle->end; 820f4a3eb02SAdrian Chadd count = ulmax(count, rle->count); 821f4a3eb02SAdrian Chadd } 822f4a3eb02SAdrian Chadd 823f4a3eb02SAdrian Chadd /* Locate a mapping region */ 824f4a3eb02SAdrian Chadd if ((cr = chipc_find_region(sc, start, end)) == NULL) { 825f4a3eb02SAdrian Chadd /* Resource requests outside our shared port regions can be 826f4a3eb02SAdrian Chadd * delegated to our parent. */ 827f4a3eb02SAdrian Chadd rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 828f4a3eb02SAdrian Chadd start, end, count, flags); 829f4a3eb02SAdrian Chadd return (rv); 830f4a3eb02SAdrian Chadd } 831f4a3eb02SAdrian Chadd 8322f909a9fSLandon J. Fuller /* 8332f909a9fSLandon J. Fuller * As a special case, children that map the complete ChipCommon register 8342f909a9fSLandon J. Fuller * block are delegated to our parent. 8352f909a9fSLandon J. Fuller * 8362f909a9fSLandon J. Fuller * The rman API does not support sharing resources that are not 8372f909a9fSLandon J. Fuller * identical in size; since we allocate subregions to various children, 8382f909a9fSLandon J. Fuller * any children that need to map the entire register block (e.g. because 8392f909a9fSLandon J. Fuller * they require access to discontiguous register ranges) must make the 8402f909a9fSLandon J. Fuller * allocation through our parent, where we hold a compatible 8412f909a9fSLandon J. Fuller * RF_SHAREABLE allocation. 8422f909a9fSLandon J. Fuller */ 8432f909a9fSLandon J. Fuller if (cr == sc->core_region && cr->cr_addr == start && 8442f909a9fSLandon J. Fuller cr->cr_end == end && cr->cr_count == count) 8452f909a9fSLandon J. Fuller { 8462f909a9fSLandon J. Fuller rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 8472f909a9fSLandon J. Fuller start, end, count, flags); 8482f909a9fSLandon J. Fuller return (rv); 8492f909a9fSLandon J. Fuller } 8502f909a9fSLandon J. Fuller 851f4a3eb02SAdrian Chadd /* Try to retain a region reference */ 8527d1fb1aaSLandon J. Fuller if ((error = chipc_retain_region(sc, cr, RF_ALLOCATED))) 853f4a3eb02SAdrian Chadd return (NULL); 854f4a3eb02SAdrian Chadd 855f4a3eb02SAdrian Chadd /* Make our rman reservation */ 856f4a3eb02SAdrian Chadd rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE, 857f4a3eb02SAdrian Chadd child); 858f4a3eb02SAdrian Chadd if (rv == NULL) { 859f4a3eb02SAdrian Chadd chipc_release_region(sc, cr, RF_ALLOCATED); 860f4a3eb02SAdrian Chadd return (NULL); 861f4a3eb02SAdrian Chadd } 862f4a3eb02SAdrian Chadd 863f4a3eb02SAdrian Chadd rman_set_rid(rv, *rid); 864f4a3eb02SAdrian Chadd 865f4a3eb02SAdrian Chadd /* Activate */ 866f4a3eb02SAdrian Chadd if (flags & RF_ACTIVE) { 867f4a3eb02SAdrian Chadd error = bus_activate_resource(child, type, *rid, rv); 868f4a3eb02SAdrian Chadd if (error) { 869f4a3eb02SAdrian Chadd device_printf(dev, 870f4a3eb02SAdrian Chadd "failed to activate entry %#x type %d for " 871f4a3eb02SAdrian Chadd "child %s: %d\n", 872f4a3eb02SAdrian Chadd *rid, type, device_get_nameunit(child), error); 873f4a3eb02SAdrian Chadd 874f4a3eb02SAdrian Chadd chipc_release_region(sc, cr, RF_ALLOCATED); 875f4a3eb02SAdrian Chadd rman_release_resource(rv); 876f4a3eb02SAdrian Chadd 877f4a3eb02SAdrian Chadd return (NULL); 878f4a3eb02SAdrian Chadd } 879f4a3eb02SAdrian Chadd } 880f4a3eb02SAdrian Chadd 881f4a3eb02SAdrian Chadd /* Update child's resource list entry */ 882f4a3eb02SAdrian Chadd if (rle != NULL) { 883f4a3eb02SAdrian Chadd rle->res = rv; 884f4a3eb02SAdrian Chadd rle->start = rman_get_start(rv); 885f4a3eb02SAdrian Chadd rle->end = rman_get_end(rv); 886f4a3eb02SAdrian Chadd rle->count = rman_get_size(rv); 887f4a3eb02SAdrian Chadd } 888f4a3eb02SAdrian Chadd 889f4a3eb02SAdrian Chadd return (rv); 890f4a3eb02SAdrian Chadd } 891f4a3eb02SAdrian Chadd 892f4a3eb02SAdrian Chadd static int 893f4a3eb02SAdrian Chadd chipc_release_resource(device_t dev, device_t child, int type, int rid, 894f4a3eb02SAdrian Chadd struct resource *r) 895f4a3eb02SAdrian Chadd { 896f4a3eb02SAdrian Chadd struct chipc_softc *sc; 897f4a3eb02SAdrian Chadd struct chipc_region *cr; 898f4a3eb02SAdrian Chadd struct rman *rm; 8992b693a88SLandon J. Fuller struct resource_list_entry *rle; 900f4a3eb02SAdrian Chadd int error; 901f4a3eb02SAdrian Chadd 902f4a3eb02SAdrian Chadd sc = device_get_softc(dev); 903f4a3eb02SAdrian Chadd 904f4a3eb02SAdrian Chadd /* Handled by parent bus? */ 905f4a3eb02SAdrian Chadd rm = chipc_get_rman(sc, type); 906f4a3eb02SAdrian Chadd if (rm == NULL || !rman_is_region_manager(r, rm)) { 907f4a3eb02SAdrian Chadd return (bus_generic_rl_release_resource(dev, child, type, rid, 908f4a3eb02SAdrian Chadd r)); 909f4a3eb02SAdrian Chadd } 910f4a3eb02SAdrian Chadd 911f4a3eb02SAdrian Chadd /* Locate the mapping region */ 912f4a3eb02SAdrian Chadd cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 913f4a3eb02SAdrian Chadd if (cr == NULL) 914f4a3eb02SAdrian Chadd return (EINVAL); 915f4a3eb02SAdrian Chadd 916f4a3eb02SAdrian Chadd /* Deactivate resources */ 917f4a3eb02SAdrian Chadd if (rman_get_flags(r) & RF_ACTIVE) { 918f4a3eb02SAdrian Chadd error = BUS_DEACTIVATE_RESOURCE(dev, child, type, rid, r); 919f4a3eb02SAdrian Chadd if (error) 920f4a3eb02SAdrian Chadd return (error); 921f4a3eb02SAdrian Chadd } 922f4a3eb02SAdrian Chadd 923f4a3eb02SAdrian Chadd if ((error = rman_release_resource(r))) 924f4a3eb02SAdrian Chadd return (error); 925f4a3eb02SAdrian Chadd 926f4a3eb02SAdrian Chadd /* Drop allocation reference */ 927f4a3eb02SAdrian Chadd chipc_release_region(sc, cr, RF_ALLOCATED); 928f4a3eb02SAdrian Chadd 9292b693a88SLandon J. Fuller /* Clear reference from the resource list entry if exists */ 9302b693a88SLandon J. Fuller rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), type, rid); 9312b693a88SLandon J. Fuller if (rle != NULL) 9322b693a88SLandon J. Fuller rle->res = NULL; 9332b693a88SLandon J. Fuller 934f4a3eb02SAdrian Chadd return (0); 935f4a3eb02SAdrian Chadd } 936f4a3eb02SAdrian Chadd 937f4a3eb02SAdrian Chadd static int 938f4a3eb02SAdrian Chadd chipc_adjust_resource(device_t dev, device_t child, int type, 939f4a3eb02SAdrian Chadd struct resource *r, rman_res_t start, rman_res_t end) 940f4a3eb02SAdrian Chadd { 941f4a3eb02SAdrian Chadd struct chipc_softc *sc; 942f4a3eb02SAdrian Chadd struct chipc_region *cr; 943f4a3eb02SAdrian Chadd struct rman *rm; 944f4a3eb02SAdrian Chadd 945f4a3eb02SAdrian Chadd sc = device_get_softc(dev); 946f4a3eb02SAdrian Chadd 947f4a3eb02SAdrian Chadd /* Handled by parent bus? */ 948f4a3eb02SAdrian Chadd rm = chipc_get_rman(sc, type); 949f4a3eb02SAdrian Chadd if (rm == NULL || !rman_is_region_manager(r, rm)) { 950f4a3eb02SAdrian Chadd return (bus_generic_adjust_resource(dev, child, type, r, start, 951f4a3eb02SAdrian Chadd end)); 952f4a3eb02SAdrian Chadd } 953f4a3eb02SAdrian Chadd 954f4a3eb02SAdrian Chadd /* The range is limited to the existing region mapping */ 955f4a3eb02SAdrian Chadd cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 956f4a3eb02SAdrian Chadd if (cr == NULL) 957f4a3eb02SAdrian Chadd return (EINVAL); 958f4a3eb02SAdrian Chadd 959f4a3eb02SAdrian Chadd if (end <= start) 960f4a3eb02SAdrian Chadd return (EINVAL); 961f4a3eb02SAdrian Chadd 962f4a3eb02SAdrian Chadd if (start < cr->cr_addr || end > cr->cr_end) 963f4a3eb02SAdrian Chadd return (EINVAL); 964f4a3eb02SAdrian Chadd 965f4a3eb02SAdrian Chadd /* Range falls within the existing region */ 966f4a3eb02SAdrian Chadd return (rman_adjust_resource(r, start, end)); 967f4a3eb02SAdrian Chadd } 968f4a3eb02SAdrian Chadd 969f4a3eb02SAdrian Chadd /** 970f4a3eb02SAdrian Chadd * Retain an RF_ACTIVE reference to the region mapping @p r, and 971f4a3eb02SAdrian Chadd * configure @p r with its subregion values. 972f4a3eb02SAdrian Chadd * 973f4a3eb02SAdrian Chadd * @param sc Driver instance state. 974f4a3eb02SAdrian Chadd * @param child Requesting child device. 975f4a3eb02SAdrian Chadd * @param type resource type of @p r. 976f4a3eb02SAdrian Chadd * @param rid resource id of @p r 977f4a3eb02SAdrian Chadd * @param r resource to be activated. 978f4a3eb02SAdrian Chadd * @param req_direct If true, failure to allocate a direct bhnd resource 979f4a3eb02SAdrian Chadd * will be treated as an error. If false, the resource will not be marked 980f4a3eb02SAdrian Chadd * as RF_ACTIVE if bhnd direct resource allocation fails. 981f4a3eb02SAdrian Chadd */ 982f4a3eb02SAdrian Chadd static int 983f4a3eb02SAdrian Chadd chipc_try_activate_resource(struct chipc_softc *sc, device_t child, int type, 984f4a3eb02SAdrian Chadd int rid, struct resource *r, bool req_direct) 985f4a3eb02SAdrian Chadd { 986f4a3eb02SAdrian Chadd struct rman *rm; 987f4a3eb02SAdrian Chadd struct chipc_region *cr; 988f4a3eb02SAdrian Chadd bhnd_size_t cr_offset; 989f4a3eb02SAdrian Chadd rman_res_t r_start, r_end, r_size; 990f4a3eb02SAdrian Chadd int error; 991f4a3eb02SAdrian Chadd 992f4a3eb02SAdrian Chadd rm = chipc_get_rman(sc, type); 993f4a3eb02SAdrian Chadd if (rm == NULL || !rman_is_region_manager(r, rm)) 994f4a3eb02SAdrian Chadd return (EINVAL); 995f4a3eb02SAdrian Chadd 996f4a3eb02SAdrian Chadd r_start = rman_get_start(r); 997f4a3eb02SAdrian Chadd r_end = rman_get_end(r); 998f4a3eb02SAdrian Chadd r_size = rman_get_size(r); 999f4a3eb02SAdrian Chadd 1000f4a3eb02SAdrian Chadd /* Find the corresponding chipc region */ 1001f4a3eb02SAdrian Chadd cr = chipc_find_region(sc, r_start, r_end); 1002f4a3eb02SAdrian Chadd if (cr == NULL) 1003f4a3eb02SAdrian Chadd return (EINVAL); 1004f4a3eb02SAdrian Chadd 1005f4a3eb02SAdrian Chadd /* Calculate subregion offset within the chipc region */ 1006f4a3eb02SAdrian Chadd cr_offset = r_start - cr->cr_addr; 1007f4a3eb02SAdrian Chadd 1008f4a3eb02SAdrian Chadd /* Retain (and activate, if necessary) the chipc region */ 1009f4a3eb02SAdrian Chadd if ((error = chipc_retain_region(sc, cr, RF_ACTIVE))) 1010f4a3eb02SAdrian Chadd return (error); 1011f4a3eb02SAdrian Chadd 1012f4a3eb02SAdrian Chadd /* Configure child resource with its subregion values. */ 1013f4a3eb02SAdrian Chadd if (cr->cr_res->direct) { 1014f4a3eb02SAdrian Chadd error = chipc_init_child_resource(r, cr->cr_res->res, 1015f4a3eb02SAdrian Chadd cr_offset, r_size); 1016f4a3eb02SAdrian Chadd if (error) 1017f4a3eb02SAdrian Chadd goto cleanup; 1018f4a3eb02SAdrian Chadd 1019f4a3eb02SAdrian Chadd /* Mark active */ 1020f4a3eb02SAdrian Chadd if ((error = rman_activate_resource(r))) 1021f4a3eb02SAdrian Chadd goto cleanup; 1022f4a3eb02SAdrian Chadd } else if (req_direct) { 1023f4a3eb02SAdrian Chadd error = ENOMEM; 1024f4a3eb02SAdrian Chadd goto cleanup; 1025f4a3eb02SAdrian Chadd } 1026f4a3eb02SAdrian Chadd 1027f4a3eb02SAdrian Chadd return (0); 1028f4a3eb02SAdrian Chadd 1029f4a3eb02SAdrian Chadd cleanup: 1030f4a3eb02SAdrian Chadd chipc_release_region(sc, cr, RF_ACTIVE); 1031f4a3eb02SAdrian Chadd return (error); 1032f4a3eb02SAdrian Chadd } 1033f4a3eb02SAdrian Chadd 1034f4a3eb02SAdrian Chadd static int 1035f4a3eb02SAdrian Chadd chipc_activate_bhnd_resource(device_t dev, device_t child, int type, 1036f4a3eb02SAdrian Chadd int rid, struct bhnd_resource *r) 1037f4a3eb02SAdrian Chadd { 1038f4a3eb02SAdrian Chadd struct chipc_softc *sc; 1039f4a3eb02SAdrian Chadd struct rman *rm; 1040f4a3eb02SAdrian Chadd int error; 1041f4a3eb02SAdrian Chadd 1042f4a3eb02SAdrian Chadd sc = device_get_softc(dev); 1043f4a3eb02SAdrian Chadd 1044f4a3eb02SAdrian Chadd /* Delegate non-locally managed resources to parent */ 1045f4a3eb02SAdrian Chadd rm = chipc_get_rman(sc, type); 1046f4a3eb02SAdrian Chadd if (rm == NULL || !rman_is_region_manager(r->res, rm)) { 1047f4a3eb02SAdrian Chadd return (bhnd_bus_generic_activate_resource(dev, child, type, 1048f4a3eb02SAdrian Chadd rid, r)); 1049f4a3eb02SAdrian Chadd } 1050f4a3eb02SAdrian Chadd 1051f4a3eb02SAdrian Chadd /* Try activating the chipc region resource */ 1052f4a3eb02SAdrian Chadd error = chipc_try_activate_resource(sc, child, type, rid, r->res, 1053f4a3eb02SAdrian Chadd false); 1054f4a3eb02SAdrian Chadd if (error) 1055f4a3eb02SAdrian Chadd return (error); 1056f4a3eb02SAdrian Chadd 1057f4a3eb02SAdrian Chadd /* Mark the child resource as direct according to the returned resource 1058f4a3eb02SAdrian Chadd * state */ 1059f4a3eb02SAdrian Chadd if (rman_get_flags(r->res) & RF_ACTIVE) 1060f4a3eb02SAdrian Chadd r->direct = true; 1061f4a3eb02SAdrian Chadd 1062f4a3eb02SAdrian Chadd return (0); 1063f4a3eb02SAdrian Chadd } 1064f4a3eb02SAdrian Chadd 1065f4a3eb02SAdrian Chadd static int 1066f4a3eb02SAdrian Chadd chipc_activate_resource(device_t dev, device_t child, int type, int rid, 1067f4a3eb02SAdrian Chadd struct resource *r) 1068f4a3eb02SAdrian Chadd { 1069f4a3eb02SAdrian Chadd struct chipc_softc *sc; 1070f4a3eb02SAdrian Chadd struct rman *rm; 1071f4a3eb02SAdrian Chadd 1072f4a3eb02SAdrian Chadd sc = device_get_softc(dev); 1073f4a3eb02SAdrian Chadd 1074f4a3eb02SAdrian Chadd /* Delegate non-locally managed resources to parent */ 1075f4a3eb02SAdrian Chadd rm = chipc_get_rman(sc, type); 1076f4a3eb02SAdrian Chadd if (rm == NULL || !rman_is_region_manager(r, rm)) { 1077f4a3eb02SAdrian Chadd return (bus_generic_activate_resource(dev, child, type, rid, 1078f4a3eb02SAdrian Chadd r)); 1079f4a3eb02SAdrian Chadd } 1080f4a3eb02SAdrian Chadd 1081f4a3eb02SAdrian Chadd /* Try activating the chipc region-based resource */ 1082f4a3eb02SAdrian Chadd return (chipc_try_activate_resource(sc, child, type, rid, r, true)); 1083f4a3eb02SAdrian Chadd } 1084f4a3eb02SAdrian Chadd 1085f4a3eb02SAdrian Chadd /** 1086f4a3eb02SAdrian Chadd * Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE(). 1087f4a3eb02SAdrian Chadd */ 1088f4a3eb02SAdrian Chadd static int 1089f4a3eb02SAdrian Chadd chipc_deactivate_resource(device_t dev, device_t child, int type, 1090f4a3eb02SAdrian Chadd int rid, struct resource *r) 1091f4a3eb02SAdrian Chadd { 1092f4a3eb02SAdrian Chadd struct chipc_softc *sc; 1093f4a3eb02SAdrian Chadd struct chipc_region *cr; 1094f4a3eb02SAdrian Chadd struct rman *rm; 1095f4a3eb02SAdrian Chadd int error; 1096f4a3eb02SAdrian Chadd 1097f4a3eb02SAdrian Chadd sc = device_get_softc(dev); 1098f4a3eb02SAdrian Chadd 1099f4a3eb02SAdrian Chadd /* Handled by parent bus? */ 1100f4a3eb02SAdrian Chadd rm = chipc_get_rman(sc, type); 1101f4a3eb02SAdrian Chadd if (rm == NULL || !rman_is_region_manager(r, rm)) { 1102f4a3eb02SAdrian Chadd return (bus_generic_deactivate_resource(dev, child, type, rid, 1103f4a3eb02SAdrian Chadd r)); 1104f4a3eb02SAdrian Chadd } 1105f4a3eb02SAdrian Chadd 1106f4a3eb02SAdrian Chadd /* Find the corresponding chipc region */ 1107f4a3eb02SAdrian Chadd cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 1108f4a3eb02SAdrian Chadd if (cr == NULL) 1109f4a3eb02SAdrian Chadd return (EINVAL); 1110f4a3eb02SAdrian Chadd 1111f4a3eb02SAdrian Chadd /* Mark inactive */ 1112f4a3eb02SAdrian Chadd if ((error = rman_deactivate_resource(r))) 1113f4a3eb02SAdrian Chadd return (error); 1114f4a3eb02SAdrian Chadd 1115f4a3eb02SAdrian Chadd /* Drop associated RF_ACTIVE reference */ 1116f4a3eb02SAdrian Chadd chipc_release_region(sc, cr, RF_ACTIVE); 1117f4a3eb02SAdrian Chadd 1118f4a3eb02SAdrian Chadd return (0); 1119f4a3eb02SAdrian Chadd } 1120f4a3eb02SAdrian Chadd 1121f4a3eb02SAdrian Chadd /** 1122f4a3eb02SAdrian Chadd * Examine bus state and make a best effort determination of whether it's 1123f4a3eb02SAdrian Chadd * likely safe to enable the muxed SPROM pins. 1124f4a3eb02SAdrian Chadd * 1125f4a3eb02SAdrian Chadd * On devices that do not use SPROM pin muxing, always returns true. 1126f4a3eb02SAdrian Chadd * 1127f4a3eb02SAdrian Chadd * @param sc chipc driver state. 1128f4a3eb02SAdrian Chadd */ 1129f4a3eb02SAdrian Chadd static bool 1130f90f4b65SLandon J. Fuller chipc_should_enable_muxed_sprom(struct chipc_softc *sc) 1131f4a3eb02SAdrian Chadd { 1132f4a3eb02SAdrian Chadd device_t *devs; 1133f4a3eb02SAdrian Chadd device_t hostb; 1134f4a3eb02SAdrian Chadd device_t parent; 1135f4a3eb02SAdrian Chadd int devcount; 1136f4a3eb02SAdrian Chadd int error; 1137f4a3eb02SAdrian Chadd bool result; 1138f4a3eb02SAdrian Chadd 1139f4a3eb02SAdrian Chadd /* Nothing to do? */ 1140f4a3eb02SAdrian Chadd if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1141f4a3eb02SAdrian Chadd return (true); 1142f4a3eb02SAdrian Chadd 1143c6df6f53SWarner Losh bus_topo_lock(); 1144f90f4b65SLandon J. Fuller 1145f4a3eb02SAdrian Chadd parent = device_get_parent(sc->dev); 11468e35bf83SLandon J. Fuller hostb = bhnd_bus_find_hostb_device(parent); 1147f4a3eb02SAdrian Chadd 1148f90f4b65SLandon J. Fuller if ((error = device_get_children(parent, &devs, &devcount))) { 1149c6df6f53SWarner Losh bus_topo_unlock(); 1150f4a3eb02SAdrian Chadd return (false); 1151f90f4b65SLandon J. Fuller } 1152f4a3eb02SAdrian Chadd 1153f4a3eb02SAdrian Chadd /* Reject any active devices other than ChipCommon, or the 1154f4a3eb02SAdrian Chadd * host bridge (if any). */ 1155f4a3eb02SAdrian Chadd result = true; 1156f4a3eb02SAdrian Chadd for (int i = 0; i < devcount; i++) { 1157f4a3eb02SAdrian Chadd if (devs[i] == hostb || devs[i] == sc->dev) 1158f4a3eb02SAdrian Chadd continue; 1159f4a3eb02SAdrian Chadd 1160f4a3eb02SAdrian Chadd if (!device_is_attached(devs[i])) 1161f4a3eb02SAdrian Chadd continue; 1162f4a3eb02SAdrian Chadd 1163f4a3eb02SAdrian Chadd if (device_is_suspended(devs[i])) 1164f4a3eb02SAdrian Chadd continue; 1165f4a3eb02SAdrian Chadd 1166f4a3eb02SAdrian Chadd /* Active device; assume SPROM is busy */ 1167f4a3eb02SAdrian Chadd result = false; 1168f4a3eb02SAdrian Chadd break; 1169f4a3eb02SAdrian Chadd } 1170f4a3eb02SAdrian Chadd 1171f4a3eb02SAdrian Chadd free(devs, M_TEMP); 1172c6df6f53SWarner Losh bus_topo_unlock(); 1173f4a3eb02SAdrian Chadd return (result); 1174f4a3eb02SAdrian Chadd } 1175e83ce340SAdrian Chadd 1176f90f4b65SLandon J. Fuller static int 1177f90f4b65SLandon J. Fuller chipc_enable_sprom(device_t dev) 1178f90f4b65SLandon J. Fuller { 1179f90f4b65SLandon J. Fuller struct chipc_softc *sc; 1180f90f4b65SLandon J. Fuller int error; 1181f90f4b65SLandon J. Fuller 1182f90f4b65SLandon J. Fuller sc = device_get_softc(dev); 1183f90f4b65SLandon J. Fuller CHIPC_LOCK(sc); 1184f90f4b65SLandon J. Fuller 1185f90f4b65SLandon J. Fuller /* Already enabled? */ 1186f90f4b65SLandon J. Fuller if (sc->sprom_refcnt >= 1) { 1187f90f4b65SLandon J. Fuller sc->sprom_refcnt++; 1188f90f4b65SLandon J. Fuller CHIPC_UNLOCK(sc); 1189f90f4b65SLandon J. Fuller 1190f90f4b65SLandon J. Fuller return (0); 1191f90f4b65SLandon J. Fuller } 1192f90f4b65SLandon J. Fuller 1193f90f4b65SLandon J. Fuller switch (sc->caps.nvram_src) { 1194f90f4b65SLandon J. Fuller case BHND_NVRAM_SRC_SPROM: 1195f90f4b65SLandon J. Fuller error = chipc_enable_sprom_pins(sc); 1196f90f4b65SLandon J. Fuller break; 1197f90f4b65SLandon J. Fuller case BHND_NVRAM_SRC_OTP: 1198f90f4b65SLandon J. Fuller error = chipc_enable_otp_power(sc); 1199f90f4b65SLandon J. Fuller break; 1200f90f4b65SLandon J. Fuller default: 1201f90f4b65SLandon J. Fuller error = 0; 1202f90f4b65SLandon J. Fuller break; 1203f90f4b65SLandon J. Fuller } 1204f90f4b65SLandon J. Fuller 1205f90f4b65SLandon J. Fuller /* Bump the reference count */ 1206f90f4b65SLandon J. Fuller if (error == 0) 1207f90f4b65SLandon J. Fuller sc->sprom_refcnt++; 1208f90f4b65SLandon J. Fuller 1209f90f4b65SLandon J. Fuller CHIPC_UNLOCK(sc); 1210f90f4b65SLandon J. Fuller return (error); 1211f90f4b65SLandon J. Fuller } 1212f90f4b65SLandon J. Fuller 1213f90f4b65SLandon J. Fuller static void 1214f90f4b65SLandon J. Fuller chipc_disable_sprom(device_t dev) 1215f90f4b65SLandon J. Fuller { 1216f90f4b65SLandon J. Fuller struct chipc_softc *sc; 1217f90f4b65SLandon J. Fuller 1218f90f4b65SLandon J. Fuller sc = device_get_softc(dev); 1219f90f4b65SLandon J. Fuller CHIPC_LOCK(sc); 1220f90f4b65SLandon J. Fuller 1221f90f4b65SLandon J. Fuller /* Check reference count, skip disable if in-use. */ 1222f90f4b65SLandon J. Fuller KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease")); 1223f90f4b65SLandon J. Fuller sc->sprom_refcnt--; 1224f90f4b65SLandon J. Fuller if (sc->sprom_refcnt > 0) { 1225f90f4b65SLandon J. Fuller CHIPC_UNLOCK(sc); 1226f90f4b65SLandon J. Fuller return; 1227f90f4b65SLandon J. Fuller } 1228f90f4b65SLandon J. Fuller 1229f90f4b65SLandon J. Fuller switch (sc->caps.nvram_src) { 1230f90f4b65SLandon J. Fuller case BHND_NVRAM_SRC_SPROM: 1231f90f4b65SLandon J. Fuller chipc_disable_sprom_pins(sc); 1232f90f4b65SLandon J. Fuller break; 1233f90f4b65SLandon J. Fuller case BHND_NVRAM_SRC_OTP: 1234f90f4b65SLandon J. Fuller chipc_disable_otp_power(sc); 1235f90f4b65SLandon J. Fuller break; 1236f90f4b65SLandon J. Fuller default: 1237f90f4b65SLandon J. Fuller break; 1238f90f4b65SLandon J. Fuller } 1239f90f4b65SLandon J. Fuller 1240f90f4b65SLandon J. Fuller CHIPC_UNLOCK(sc); 1241f90f4b65SLandon J. Fuller } 1242f90f4b65SLandon J. Fuller 1243f90f4b65SLandon J. Fuller static int 1244f90f4b65SLandon J. Fuller chipc_enable_otp_power(struct chipc_softc *sc) 1245f90f4b65SLandon J. Fuller { 1246f90f4b65SLandon J. Fuller // TODO: Enable OTP resource via PMU, and wait up to 100 usec for 1247f90f4b65SLandon J. Fuller // OTPS_READY to be set in `optstatus`. 1248f90f4b65SLandon J. Fuller return (0); 1249f90f4b65SLandon J. Fuller } 1250f90f4b65SLandon J. Fuller 1251f90f4b65SLandon J. Fuller static void 1252f90f4b65SLandon J. Fuller chipc_disable_otp_power(struct chipc_softc *sc) 1253f90f4b65SLandon J. Fuller { 1254f90f4b65SLandon J. Fuller // TODO: Disable OTP resource via PMU 1255f90f4b65SLandon J. Fuller } 1256f90f4b65SLandon J. Fuller 1257e83ce340SAdrian Chadd /** 1258e83ce340SAdrian Chadd * If required by this device, enable access to the SPROM. 1259e83ce340SAdrian Chadd * 1260e83ce340SAdrian Chadd * @param sc chipc driver state. 1261e83ce340SAdrian Chadd */ 1262e83ce340SAdrian Chadd static int 1263f90f4b65SLandon J. Fuller chipc_enable_sprom_pins(struct chipc_softc *sc) 1264e83ce340SAdrian Chadd { 1265e83ce340SAdrian Chadd uint32_t cctrl; 1266e83ce340SAdrian Chadd 1267f90f4b65SLandon J. Fuller CHIPC_LOCK_ASSERT(sc, MA_OWNED); 1268f90f4b65SLandon J. Fuller KASSERT(sc->sprom_refcnt == 0, ("sprom pins already enabled")); 1269e83ce340SAdrian Chadd 1270e83ce340SAdrian Chadd /* Nothing to do? */ 1271e83ce340SAdrian Chadd if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1272e83ce340SAdrian Chadd return (0); 1273e83ce340SAdrian Chadd 1274f4a3eb02SAdrian Chadd /* Check whether bus is busy */ 1275f90f4b65SLandon J. Fuller if (!chipc_should_enable_muxed_sprom(sc)) 1276f90f4b65SLandon J. Fuller return (EBUSY); 1277f4a3eb02SAdrian Chadd 1278e83ce340SAdrian Chadd cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1279e83ce340SAdrian Chadd 1280e83ce340SAdrian Chadd /* 4331 devices */ 1281e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1282e83ce340SAdrian Chadd cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN; 1283e83ce340SAdrian Chadd 1284e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1285e83ce340SAdrian Chadd cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1286e83ce340SAdrian Chadd 1287e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1288e83ce340SAdrian Chadd cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2; 1289e83ce340SAdrian Chadd 1290e83ce340SAdrian Chadd bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1291f90f4b65SLandon J. Fuller return (0); 1292e83ce340SAdrian Chadd } 1293e83ce340SAdrian Chadd 1294e83ce340SAdrian Chadd /* 4360 devices */ 1295e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1296e83ce340SAdrian Chadd /* Unimplemented */ 1297e83ce340SAdrian Chadd } 1298e83ce340SAdrian Chadd 1299e83ce340SAdrian Chadd /* Refuse to proceed on unsupported devices with muxed SPROM pins */ 1300e83ce340SAdrian Chadd device_printf(sc->dev, "muxed sprom lines on unrecognized device\n"); 1301f90f4b65SLandon J. Fuller return (ENXIO); 1302e83ce340SAdrian Chadd } 1303e83ce340SAdrian Chadd 1304e83ce340SAdrian Chadd /** 1305e83ce340SAdrian Chadd * If required by this device, revert any GPIO/pin configuration applied 1306e83ce340SAdrian Chadd * to allow SPROM access. 1307e83ce340SAdrian Chadd * 1308e83ce340SAdrian Chadd * @param sc chipc driver state. 1309e83ce340SAdrian Chadd */ 1310f4a3eb02SAdrian Chadd static void 1311f90f4b65SLandon J. Fuller chipc_disable_sprom_pins(struct chipc_softc *sc) 1312e83ce340SAdrian Chadd { 1313e83ce340SAdrian Chadd uint32_t cctrl; 1314e83ce340SAdrian Chadd 1315e83ce340SAdrian Chadd /* Nothing to do? */ 1316e83ce340SAdrian Chadd if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1317f4a3eb02SAdrian Chadd return; 1318f4a3eb02SAdrian Chadd 1319f90f4b65SLandon J. Fuller CHIPC_LOCK_ASSERT(sc, MA_OWNED); 1320315cf4daSLandon J. Fuller KASSERT(sc->sprom_refcnt == 0, ("sprom pins in use")); 1321e83ce340SAdrian Chadd 1322e83ce340SAdrian Chadd cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1323e83ce340SAdrian Chadd 1324e83ce340SAdrian Chadd /* 4331 devices */ 1325e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1326e83ce340SAdrian Chadd cctrl |= CHIPC_CCTRL4331_EXTPA_EN; 1327e83ce340SAdrian Chadd 1328e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1329e83ce340SAdrian Chadd cctrl |= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1330e83ce340SAdrian Chadd 1331e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1332e83ce340SAdrian Chadd cctrl |= CHIPC_CCTRL4331_EXTPA_EN2; 1333e83ce340SAdrian Chadd 1334e83ce340SAdrian Chadd bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1335f90f4b65SLandon J. Fuller return; 1336e83ce340SAdrian Chadd } 1337e83ce340SAdrian Chadd 1338e83ce340SAdrian Chadd /* 4360 devices */ 1339e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1340e83ce340SAdrian Chadd /* Unimplemented */ 1341e83ce340SAdrian Chadd } 1342f90f4b65SLandon J. Fuller } 1343e83ce340SAdrian Chadd 1344f90f4b65SLandon J. Fuller static uint32_t 1345f90f4b65SLandon J. Fuller chipc_read_chipst(device_t dev) 1346f90f4b65SLandon J. Fuller { 1347f90f4b65SLandon J. Fuller struct chipc_softc *sc = device_get_softc(dev); 1348f90f4b65SLandon J. Fuller return (bhnd_bus_read_4(sc->core, CHIPC_CHIPST)); 1349e83ce340SAdrian Chadd } 1350e83ce340SAdrian Chadd 13518ef24a0dSAdrian Chadd static void 13528ef24a0dSAdrian Chadd chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask) 13538ef24a0dSAdrian Chadd { 13548ef24a0dSAdrian Chadd struct chipc_softc *sc; 13558ef24a0dSAdrian Chadd uint32_t cctrl; 13568ef24a0dSAdrian Chadd 13578ef24a0dSAdrian Chadd sc = device_get_softc(dev); 13588ef24a0dSAdrian Chadd 13598ef24a0dSAdrian Chadd CHIPC_LOCK(sc); 13608ef24a0dSAdrian Chadd 13618ef24a0dSAdrian Chadd cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 13628ef24a0dSAdrian Chadd cctrl = (cctrl & ~mask) | (value | mask); 13638ef24a0dSAdrian Chadd bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 13648ef24a0dSAdrian Chadd 13658ef24a0dSAdrian Chadd CHIPC_UNLOCK(sc); 13668ef24a0dSAdrian Chadd } 13678ef24a0dSAdrian Chadd 13682b693a88SLandon J. Fuller static struct chipc_caps * 13692b693a88SLandon J. Fuller chipc_get_caps(device_t dev) 13702b693a88SLandon J. Fuller { 13712b693a88SLandon J. Fuller struct chipc_softc *sc; 13722b693a88SLandon J. Fuller 13732b693a88SLandon J. Fuller sc = device_get_softc(dev); 13742b693a88SLandon J. Fuller return (&sc->caps); 13752b693a88SLandon J. Fuller } 13762b693a88SLandon J. Fuller 13774ad7e9b0SAdrian Chadd static device_method_t chipc_methods[] = { 13784ad7e9b0SAdrian Chadd /* Device interface */ 13794ad7e9b0SAdrian Chadd DEVMETHOD(device_probe, chipc_probe), 13804ad7e9b0SAdrian Chadd DEVMETHOD(device_attach, chipc_attach), 13814ad7e9b0SAdrian Chadd DEVMETHOD(device_detach, chipc_detach), 13824ad7e9b0SAdrian Chadd DEVMETHOD(device_suspend, chipc_suspend), 13834ad7e9b0SAdrian Chadd DEVMETHOD(device_resume, chipc_resume), 13844ad7e9b0SAdrian Chadd 1385f4a3eb02SAdrian Chadd /* Bus interface */ 1386f4a3eb02SAdrian Chadd DEVMETHOD(bus_probe_nomatch, chipc_probe_nomatch), 1387f4a3eb02SAdrian Chadd DEVMETHOD(bus_print_child, chipc_print_child), 1388f4a3eb02SAdrian Chadd 1389f4a3eb02SAdrian Chadd DEVMETHOD(bus_add_child, chipc_add_child), 1390f4a3eb02SAdrian Chadd DEVMETHOD(bus_child_deleted, chipc_child_deleted), 1391f4a3eb02SAdrian Chadd 1392f4a3eb02SAdrian Chadd DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 1393f4a3eb02SAdrian Chadd DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 1394f4a3eb02SAdrian Chadd DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource), 1395f4a3eb02SAdrian Chadd DEVMETHOD(bus_alloc_resource, chipc_alloc_resource), 1396f4a3eb02SAdrian Chadd DEVMETHOD(bus_release_resource, chipc_release_resource), 1397f4a3eb02SAdrian Chadd DEVMETHOD(bus_adjust_resource, chipc_adjust_resource), 1398f4a3eb02SAdrian Chadd DEVMETHOD(bus_activate_resource, chipc_activate_resource), 1399f4a3eb02SAdrian Chadd DEVMETHOD(bus_deactivate_resource, chipc_deactivate_resource), 1400f4a3eb02SAdrian Chadd DEVMETHOD(bus_get_resource_list, chipc_get_resource_list), 1401f4a3eb02SAdrian Chadd 1402f4a3eb02SAdrian Chadd DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1403f4a3eb02SAdrian Chadd DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1404f4a3eb02SAdrian Chadd DEVMETHOD(bus_config_intr, bus_generic_config_intr), 1405f4a3eb02SAdrian Chadd DEVMETHOD(bus_bind_intr, bus_generic_bind_intr), 1406f4a3eb02SAdrian Chadd DEVMETHOD(bus_describe_intr, bus_generic_describe_intr), 1407f4a3eb02SAdrian Chadd 1408f4a3eb02SAdrian Chadd /* BHND bus inteface */ 1409f4a3eb02SAdrian Chadd DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource), 1410f4a3eb02SAdrian Chadd 14114ad7e9b0SAdrian Chadd /* ChipCommon interface */ 1412f90f4b65SLandon J. Fuller DEVMETHOD(bhnd_chipc_read_chipst, chipc_read_chipst), 14138ef24a0dSAdrian Chadd DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl), 1414f90f4b65SLandon J. Fuller DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom), 1415f90f4b65SLandon J. Fuller DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom), 14162b693a88SLandon J. Fuller DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps), 1417e83ce340SAdrian Chadd 14184ad7e9b0SAdrian Chadd DEVMETHOD_END 14194ad7e9b0SAdrian Chadd }; 14204ad7e9b0SAdrian Chadd 1421f90f4b65SLandon J. Fuller DEFINE_CLASS_0(bhnd_chipc, bhnd_chipc_driver, chipc_methods, sizeof(struct chipc_softc)); 1422162c26adSJohn Baldwin EARLY_DRIVER_MODULE(bhnd_chipc, bhnd, bhnd_chipc_driver, 0, 0, 1423e129bcd6SLandon J. Fuller BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 142496546b75SAdrian Chadd MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1); 14254ad7e9b0SAdrian Chadd MODULE_VERSION(bhnd_chipc, 1); 1426