14ad7e9b0SAdrian Chadd /*- 2f4a3eb02SAdrian Chadd * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 3f4a3eb02SAdrian Chadd * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com> 44ad7e9b0SAdrian Chadd * All rights reserved. 54ad7e9b0SAdrian Chadd * 64ad7e9b0SAdrian Chadd * Redistribution and use in source and binary forms, with or without 74ad7e9b0SAdrian Chadd * modification, are permitted provided that the following conditions 84ad7e9b0SAdrian Chadd * are met: 94ad7e9b0SAdrian Chadd * 1. Redistributions of source code must retain the above copyright 104ad7e9b0SAdrian Chadd * notice, this list of conditions and the following disclaimer, 114ad7e9b0SAdrian Chadd * without modification. 124ad7e9b0SAdrian Chadd * 2. Redistributions in binary form must reproduce at minimum a disclaimer 134ad7e9b0SAdrian Chadd * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 144ad7e9b0SAdrian Chadd * redistribution must be conditioned upon including a substantially 154ad7e9b0SAdrian Chadd * similar Disclaimer requirement for further binary redistribution. 164ad7e9b0SAdrian Chadd * 174ad7e9b0SAdrian Chadd * NO WARRANTY 184ad7e9b0SAdrian Chadd * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 194ad7e9b0SAdrian Chadd * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 204ad7e9b0SAdrian Chadd * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 214ad7e9b0SAdrian Chadd * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 224ad7e9b0SAdrian Chadd * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 234ad7e9b0SAdrian Chadd * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 244ad7e9b0SAdrian Chadd * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 254ad7e9b0SAdrian Chadd * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 264ad7e9b0SAdrian Chadd * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 274ad7e9b0SAdrian Chadd * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 284ad7e9b0SAdrian Chadd * THE POSSIBILITY OF SUCH DAMAGES. 294ad7e9b0SAdrian Chadd */ 304ad7e9b0SAdrian Chadd 314ad7e9b0SAdrian Chadd #include <sys/cdefs.h> 324ad7e9b0SAdrian Chadd __FBSDID("$FreeBSD$"); 334ad7e9b0SAdrian Chadd 344ad7e9b0SAdrian Chadd /* 354ad7e9b0SAdrian Chadd * Broadcom ChipCommon driver. 364ad7e9b0SAdrian Chadd * 374ad7e9b0SAdrian Chadd * With the exception of some very early chipsets, the ChipCommon core 384ad7e9b0SAdrian Chadd * has been included in all HND SoCs and chipsets based on the siba(4) 394ad7e9b0SAdrian Chadd * and bcma(4) interconnects, providing a common interface to chipset 404ad7e9b0SAdrian Chadd * identification, bus enumeration, UARTs, clocks, watchdog interrupts, GPIO, 414ad7e9b0SAdrian Chadd * flash, etc. 424ad7e9b0SAdrian Chadd */ 434ad7e9b0SAdrian Chadd 444ad7e9b0SAdrian Chadd #include <sys/param.h> 454ad7e9b0SAdrian Chadd #include <sys/kernel.h> 46f4a3eb02SAdrian Chadd #include <sys/lock.h> 474ad7e9b0SAdrian Chadd #include <sys/bus.h> 48f4a3eb02SAdrian Chadd #include <sys/malloc.h> 494ad7e9b0SAdrian Chadd #include <sys/module.h> 50f4a3eb02SAdrian Chadd #include <sys/mutex.h> 514ad7e9b0SAdrian Chadd #include <sys/systm.h> 524ad7e9b0SAdrian Chadd 534ad7e9b0SAdrian Chadd #include <machine/bus.h> 544ad7e9b0SAdrian Chadd #include <sys/rman.h> 554ad7e9b0SAdrian Chadd #include <machine/resource.h> 564ad7e9b0SAdrian Chadd 574ad7e9b0SAdrian Chadd #include <dev/bhnd/bhnd.h> 58f4a3eb02SAdrian Chadd #include <dev/bhnd/bhndvar.h> 59e83ce340SAdrian Chadd 604ad7e9b0SAdrian Chadd #include "chipcreg.h" 614ad7e9b0SAdrian Chadd #include "chipcvar.h" 62f4a3eb02SAdrian Chadd #include "chipc_private.h" 634ad7e9b0SAdrian Chadd 644ad7e9b0SAdrian Chadd devclass_t bhnd_chipc_devclass; /**< bhnd(4) chipcommon device class */ 654ad7e9b0SAdrian Chadd 6636e4410aSAdrian Chadd static struct bhnd_device_quirk chipc_quirks[]; 6736e4410aSAdrian Chadd 684ad7e9b0SAdrian Chadd /* Supported device identifiers */ 6936e4410aSAdrian Chadd static const struct bhnd_device chipc_devices[] = { 705ad9ac03SAdrian Chadd BHND_DEVICE(CC, NULL, chipc_quirks), 7136e4410aSAdrian Chadd BHND_DEVICE_END 724ad7e9b0SAdrian Chadd }; 734ad7e9b0SAdrian Chadd 7436e4410aSAdrian Chadd 754ad7e9b0SAdrian Chadd /* Device quirks table */ 764ad7e9b0SAdrian Chadd static struct bhnd_device_quirk chipc_quirks[] = { 775ad9ac03SAdrian Chadd /* core revision quirks */ 785ad9ac03SAdrian Chadd BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM), 795ad9ac03SAdrian Chadd BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT), 805ad9ac03SAdrian Chadd BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPLAYOUT_SIZE), 815ad9ac03SAdrian Chadd 825ad9ac03SAdrian Chadd /* 4706 variant quirks */ 835ad9ac03SAdrian Chadd BHND_CORE_QUIRK (HWREV_EQ (38), CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */ 845ad9ac03SAdrian Chadd BHND_CHIP_QUIRK (4706, HWREV_ANY, CHIPC_QUIRK_4706_NFLASH), 855ad9ac03SAdrian Chadd 865ad9ac03SAdrian Chadd /* 4331 quirks*/ 875ad9ac03SAdrian Chadd BHND_CHIP_QUIRK (4331, HWREV_ANY, CHIPC_QUIRK_4331_EXTPA_MUX_SPROM), 885ad9ac03SAdrian Chadd BHND_PKG_QUIRK (4331, TN, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 895ad9ac03SAdrian Chadd BHND_PKG_QUIRK (4331, TNA0, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 905ad9ac03SAdrian Chadd BHND_PKG_QUIRK (4331, TT, CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM), 915ad9ac03SAdrian Chadd 925ad9ac03SAdrian Chadd /* 4360 quirks */ 935ad9ac03SAdrian Chadd BHND_CHIP_QUIRK (4352, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 945ad9ac03SAdrian Chadd BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 955ad9ac03SAdrian Chadd BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 965ad9ac03SAdrian Chadd BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 97f4a3eb02SAdrian Chadd 9836e4410aSAdrian Chadd BHND_DEVICE_QUIRK_END 994ad7e9b0SAdrian Chadd }; 1004ad7e9b0SAdrian Chadd 101f4a3eb02SAdrian Chadd static int chipc_try_activate_resource( 102f4a3eb02SAdrian Chadd struct chipc_softc *sc, device_t child, 103f4a3eb02SAdrian Chadd int type, int rid, struct resource *r, 104f4a3eb02SAdrian Chadd bool req_direct); 105f4a3eb02SAdrian Chadd 106f4a3eb02SAdrian Chadd static int chipc_read_caps(struct chipc_softc *sc, 107f4a3eb02SAdrian Chadd struct chipc_caps *caps); 108f4a3eb02SAdrian Chadd 109f4a3eb02SAdrian Chadd static int chipc_nvram_attach(struct chipc_softc *sc); 110f4a3eb02SAdrian Chadd static bhnd_nvram_src_t chipc_nvram_identify(struct chipc_softc *sc); 111f4a3eb02SAdrian Chadd static bool chipc_should_enable_sprom( 112f4a3eb02SAdrian Chadd struct chipc_softc *sc); 113f4a3eb02SAdrian Chadd 114f4a3eb02SAdrian Chadd static int chipc_init_rman(struct chipc_softc *sc); 115f4a3eb02SAdrian Chadd static void chipc_free_rman(struct chipc_softc *sc); 116f4a3eb02SAdrian Chadd static struct rman *chipc_get_rman(struct chipc_softc *sc, 117f4a3eb02SAdrian Chadd int type); 118f4a3eb02SAdrian Chadd 1194ad7e9b0SAdrian Chadd /* quirk and capability flag convenience macros */ 1204ad7e9b0SAdrian Chadd #define CHIPC_QUIRK(_sc, _name) \ 1214ad7e9b0SAdrian Chadd ((_sc)->quirks & CHIPC_QUIRK_ ## _name) 1224ad7e9b0SAdrian Chadd 1234ad7e9b0SAdrian Chadd #define CHIPC_CAP(_sc, _name) \ 124f4a3eb02SAdrian Chadd ((_sc)->caps._name) 1254ad7e9b0SAdrian Chadd 1264ad7e9b0SAdrian Chadd #define CHIPC_ASSERT_QUIRK(_sc, name) \ 1274ad7e9b0SAdrian Chadd KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set")) 1284ad7e9b0SAdrian Chadd 1294ad7e9b0SAdrian Chadd #define CHIPC_ASSERT_CAP(_sc, name) \ 1304ad7e9b0SAdrian Chadd KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set")) 1314ad7e9b0SAdrian Chadd 1324ad7e9b0SAdrian Chadd static int 1334ad7e9b0SAdrian Chadd chipc_probe(device_t dev) 1344ad7e9b0SAdrian Chadd { 13536e4410aSAdrian Chadd const struct bhnd_device *id; 1364ad7e9b0SAdrian Chadd 13736e4410aSAdrian Chadd id = bhnd_device_lookup(dev, chipc_devices, sizeof(chipc_devices[0])); 13836e4410aSAdrian Chadd if (id == NULL) 1394ad7e9b0SAdrian Chadd return (ENXIO); 14036e4410aSAdrian Chadd 14136e4410aSAdrian Chadd bhnd_set_default_core_desc(dev); 14236e4410aSAdrian Chadd return (BUS_PROBE_DEFAULT); 1434ad7e9b0SAdrian Chadd } 1444ad7e9b0SAdrian Chadd 1454ad7e9b0SAdrian Chadd static int 1464ad7e9b0SAdrian Chadd chipc_attach(device_t dev) 1474ad7e9b0SAdrian Chadd { 1484ad7e9b0SAdrian Chadd struct chipc_softc *sc; 1494ad7e9b0SAdrian Chadd bhnd_addr_t enum_addr; 1504ad7e9b0SAdrian Chadd uint32_t ccid_reg; 1514ad7e9b0SAdrian Chadd uint8_t chip_type; 1524ad7e9b0SAdrian Chadd int error; 1534ad7e9b0SAdrian Chadd 1544ad7e9b0SAdrian Chadd sc = device_get_softc(dev); 1554ad7e9b0SAdrian Chadd sc->dev = dev; 15636e4410aSAdrian Chadd sc->quirks = bhnd_device_quirks(dev, chipc_devices, 15736e4410aSAdrian Chadd sizeof(chipc_devices[0])); 158f4a3eb02SAdrian Chadd sc->sprom_refcnt = 0; 159e83ce340SAdrian Chadd 160e83ce340SAdrian Chadd CHIPC_LOCK_INIT(sc); 161f4a3eb02SAdrian Chadd STAILQ_INIT(&sc->mem_regions); 1624ad7e9b0SAdrian Chadd 163f4a3eb02SAdrian Chadd /* Set up resource management */ 164f4a3eb02SAdrian Chadd if ((error = chipc_init_rman(sc))) { 165f4a3eb02SAdrian Chadd device_printf(sc->dev, 166f4a3eb02SAdrian Chadd "failed to initialize chipc resource state: %d\n", error); 167f4a3eb02SAdrian Chadd goto failed; 168f4a3eb02SAdrian Chadd } 1694ad7e9b0SAdrian Chadd 170f4a3eb02SAdrian Chadd /* Allocate the region containing our core registers */ 171f4a3eb02SAdrian Chadd if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) { 172f4a3eb02SAdrian Chadd error = ENXIO; 173f4a3eb02SAdrian Chadd goto failed; 174f4a3eb02SAdrian Chadd } 175f4a3eb02SAdrian Chadd 176f4a3eb02SAdrian Chadd error = chipc_retain_region(sc, sc->core_region, 177f4a3eb02SAdrian Chadd RF_ALLOCATED|RF_ACTIVE); 178f4a3eb02SAdrian Chadd if (error) { 179f4a3eb02SAdrian Chadd sc->core_region = NULL; 180f4a3eb02SAdrian Chadd goto failed; 181f4a3eb02SAdrian Chadd } else { 182f4a3eb02SAdrian Chadd sc->core = sc->core_region->cr_res; 183f4a3eb02SAdrian Chadd } 1844ad7e9b0SAdrian Chadd 1854ad7e9b0SAdrian Chadd /* Fetch our chipset identification data */ 1864ad7e9b0SAdrian Chadd ccid_reg = bhnd_bus_read_4(sc->core, CHIPC_ID); 187f4a3eb02SAdrian Chadd chip_type = CHIPC_GET_BITS(ccid_reg, CHIPC_ID_BUS); 1884ad7e9b0SAdrian Chadd 1894ad7e9b0SAdrian Chadd switch (chip_type) { 1904ad7e9b0SAdrian Chadd case BHND_CHIPTYPE_SIBA: 1914ad7e9b0SAdrian Chadd /* enumeration space starts at the ChipCommon register base. */ 1924ad7e9b0SAdrian Chadd enum_addr = rman_get_start(sc->core->res); 1934ad7e9b0SAdrian Chadd break; 1944ad7e9b0SAdrian Chadd case BHND_CHIPTYPE_BCMA: 1954ad7e9b0SAdrian Chadd case BHND_CHIPTYPE_BCMA_ALT: 1964ad7e9b0SAdrian Chadd enum_addr = bhnd_bus_read_4(sc->core, CHIPC_EROMPTR); 1974ad7e9b0SAdrian Chadd break; 1984ad7e9b0SAdrian Chadd default: 1994ad7e9b0SAdrian Chadd device_printf(dev, "unsupported chip type %hhu\n", chip_type); 2004ad7e9b0SAdrian Chadd error = ENODEV; 201f4a3eb02SAdrian Chadd goto failed; 2024ad7e9b0SAdrian Chadd } 2034ad7e9b0SAdrian Chadd 2044ad7e9b0SAdrian Chadd sc->ccid = bhnd_parse_chipid(ccid_reg, enum_addr); 2054ad7e9b0SAdrian Chadd 206f4a3eb02SAdrian Chadd /* Fetch and parse capability register(s) */ 207f4a3eb02SAdrian Chadd if ((error = chipc_read_caps(sc, &sc->caps))) 208f4a3eb02SAdrian Chadd goto failed; 2094ad7e9b0SAdrian Chadd 210f4a3eb02SAdrian Chadd if (bootverbose) 211f4a3eb02SAdrian Chadd chipc_print_caps(sc->dev, &sc->caps); 212f4a3eb02SAdrian Chadd 213f4a3eb02SAdrian Chadd /* Identify NVRAM source and add child device. */ 214e83ce340SAdrian Chadd sc->nvram_src = chipc_nvram_identify(sc); 215f4a3eb02SAdrian Chadd if ((error = chipc_nvram_attach(sc))) 216f4a3eb02SAdrian Chadd goto failed; 217e83ce340SAdrian Chadd 218f4a3eb02SAdrian Chadd /* Standard bus probe */ 219f4a3eb02SAdrian Chadd if ((error = bus_generic_attach(dev))) 220f4a3eb02SAdrian Chadd goto failed; 2214ad7e9b0SAdrian Chadd 2224ad7e9b0SAdrian Chadd return (0); 2234ad7e9b0SAdrian Chadd 224f4a3eb02SAdrian Chadd failed: 225f4a3eb02SAdrian Chadd if (sc->core_region != NULL) { 226f4a3eb02SAdrian Chadd chipc_release_region(sc, sc->core_region, 227f4a3eb02SAdrian Chadd RF_ALLOCATED|RF_ACTIVE); 228f4a3eb02SAdrian Chadd } 229f4a3eb02SAdrian Chadd 230f4a3eb02SAdrian Chadd chipc_free_rman(sc); 231e83ce340SAdrian Chadd CHIPC_LOCK_DESTROY(sc); 2324ad7e9b0SAdrian Chadd return (error); 2334ad7e9b0SAdrian Chadd } 2344ad7e9b0SAdrian Chadd 2354ad7e9b0SAdrian Chadd static int 2364ad7e9b0SAdrian Chadd chipc_detach(device_t dev) 2374ad7e9b0SAdrian Chadd { 2384ad7e9b0SAdrian Chadd struct chipc_softc *sc; 239f4a3eb02SAdrian Chadd int error; 2404ad7e9b0SAdrian Chadd 2414ad7e9b0SAdrian Chadd sc = device_get_softc(dev); 242f4a3eb02SAdrian Chadd 243f4a3eb02SAdrian Chadd if ((error = bus_generic_detach(dev))) 244f4a3eb02SAdrian Chadd return (error); 245f4a3eb02SAdrian Chadd 246f4a3eb02SAdrian Chadd chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE); 247f4a3eb02SAdrian Chadd chipc_free_rman(sc); 248e83ce340SAdrian Chadd bhnd_sprom_fini(&sc->sprom); 249e83ce340SAdrian Chadd 250e83ce340SAdrian Chadd CHIPC_LOCK_DESTROY(sc); 2514ad7e9b0SAdrian Chadd 2524ad7e9b0SAdrian Chadd return (0); 2534ad7e9b0SAdrian Chadd } 2544ad7e9b0SAdrian Chadd 255f4a3eb02SAdrian Chadd /* Read and parse chipc capabilities */ 2564ad7e9b0SAdrian Chadd static int 257f4a3eb02SAdrian Chadd chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps) 2584ad7e9b0SAdrian Chadd { 259f4a3eb02SAdrian Chadd uint32_t cap_reg; 260f4a3eb02SAdrian Chadd uint32_t cap_ext_reg; 261f4a3eb02SAdrian Chadd uint32_t regval; 262f4a3eb02SAdrian Chadd 263f4a3eb02SAdrian Chadd /* Fetch cap registers */ 264f4a3eb02SAdrian Chadd cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES); 265f4a3eb02SAdrian Chadd cap_ext_reg = 0; 266f4a3eb02SAdrian Chadd if (CHIPC_QUIRK(sc, SUPPORTS_CAP_EXT)) 267f4a3eb02SAdrian Chadd cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT); 268f4a3eb02SAdrian Chadd 269f4a3eb02SAdrian Chadd /* Extract values */ 270f4a3eb02SAdrian Chadd caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART); 271f4a3eb02SAdrian Chadd caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB); 272f4a3eb02SAdrian Chadd caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO); 273f4a3eb02SAdrian Chadd caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL); 274f4a3eb02SAdrian Chadd 275f4a3eb02SAdrian Chadd caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS); 276f4a3eb02SAdrian Chadd caps->power_control = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL); 277f4a3eb02SAdrian Chadd caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP); 278f4a3eb02SAdrian Chadd 279f4a3eb02SAdrian Chadd caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL); 280f4a3eb02SAdrian Chadd caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64); 281f4a3eb02SAdrian Chadd caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM); 282f4a3eb02SAdrian Chadd caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU); 283f4a3eb02SAdrian Chadd caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI); 284f4a3eb02SAdrian Chadd caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM); 285f4a3eb02SAdrian Chadd caps->otp_size = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_OTP_SIZE); 286f4a3eb02SAdrian Chadd 287f4a3eb02SAdrian Chadd caps->seci = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_SECI); 288f4a3eb02SAdrian Chadd caps->gsio = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_GSIO); 289f4a3eb02SAdrian Chadd caps->aob = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_AOB); 290f4a3eb02SAdrian Chadd 291f4a3eb02SAdrian Chadd /* Fetch OTP size for later IPX controller revisions */ 292f4a3eb02SAdrian Chadd if (CHIPC_QUIRK(sc, IPX_OTPLAYOUT_SIZE)) { 293f4a3eb02SAdrian Chadd regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 294f4a3eb02SAdrian Chadd caps->otp_size = CHIPC_GET_BITS(regval, CHIPC_OTPL_SIZE); 2954ad7e9b0SAdrian Chadd } 2964ad7e9b0SAdrian Chadd 2975ad9ac03SAdrian Chadd /* Determine flash type and parameters */ 298f4a3eb02SAdrian Chadd caps->cfi_width = 0; 299f4a3eb02SAdrian Chadd 300f4a3eb02SAdrian Chadd switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) { 301f4a3eb02SAdrian Chadd case CHIPC_CAP_SFLASH_ST: 302f4a3eb02SAdrian Chadd caps->flash_type = CHIPC_SFLASH_ST; 303f4a3eb02SAdrian Chadd break; 304f4a3eb02SAdrian Chadd case CHIPC_CAP_SFLASH_AT: 305f4a3eb02SAdrian Chadd caps->flash_type = CHIPC_SFLASH_AT; 306f4a3eb02SAdrian Chadd break; 307f4a3eb02SAdrian Chadd case CHIPC_CAP_NFLASH: 308f4a3eb02SAdrian Chadd caps->flash_type = CHIPC_NFLASH; 309f4a3eb02SAdrian Chadd break; 310f4a3eb02SAdrian Chadd case CHIPC_CAP_PFLASH: 311f4a3eb02SAdrian Chadd caps->flash_type = CHIPC_PFLASH_CFI; 312f4a3eb02SAdrian Chadd 313f4a3eb02SAdrian Chadd /* determine cfi width */ 314f4a3eb02SAdrian Chadd regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG); 315f4a3eb02SAdrian Chadd if (CHIPC_GET_FLAG(regval, CHIPC_FLASH_CFG_DS)) 316f4a3eb02SAdrian Chadd caps->cfi_width = 2; 317f4a3eb02SAdrian Chadd else 318f4a3eb02SAdrian Chadd caps->cfi_width = 1; 319f4a3eb02SAdrian Chadd 320f4a3eb02SAdrian Chadd break; 321f4a3eb02SAdrian Chadd case CHIPC_CAP_FLASH_NONE: 322f4a3eb02SAdrian Chadd caps->flash_type = CHIPC_FLASH_NONE; 323f4a3eb02SAdrian Chadd break; 324f4a3eb02SAdrian Chadd 325f4a3eb02SAdrian Chadd } 326f4a3eb02SAdrian Chadd 327f4a3eb02SAdrian Chadd /* Handle 4706_NFLASH fallback */ 328f4a3eb02SAdrian Chadd if (CHIPC_QUIRK(sc, 4706_NFLASH) && 329f4a3eb02SAdrian Chadd CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_4706_NFLASH)) 3304ad7e9b0SAdrian Chadd { 331f4a3eb02SAdrian Chadd caps->flash_type = CHIPC_NFLASH_4706; 332f4a3eb02SAdrian Chadd } 333f4a3eb02SAdrian Chadd 3344ad7e9b0SAdrian Chadd return (0); 3354ad7e9b0SAdrian Chadd } 3364ad7e9b0SAdrian Chadd 3374ad7e9b0SAdrian Chadd /** 338f4a3eb02SAdrian Chadd * If supported, add an appropriate NVRAM child device. 3394ad7e9b0SAdrian Chadd */ 340e83ce340SAdrian Chadd static int 341f4a3eb02SAdrian Chadd chipc_nvram_attach(struct chipc_softc *sc) 3424ad7e9b0SAdrian Chadd { 343f4a3eb02SAdrian Chadd device_t nvram_dev; 344f4a3eb02SAdrian Chadd rman_res_t start; 345e83ce340SAdrian Chadd int error; 3464ad7e9b0SAdrian Chadd 347f4a3eb02SAdrian Chadd switch (sc->nvram_src) { 348f4a3eb02SAdrian Chadd case BHND_NVRAM_SRC_OTP: 349f4a3eb02SAdrian Chadd // TODO OTP support 350f4a3eb02SAdrian Chadd device_printf(sc->dev, "OTP nvram source unsupported\n"); 351e83ce340SAdrian Chadd return (0); 352e83ce340SAdrian Chadd 353f4a3eb02SAdrian Chadd case BHND_NVRAM_SRC_SPROM: 354f4a3eb02SAdrian Chadd /* Add OTP/SPROM device */ 355f4a3eb02SAdrian Chadd nvram_dev = BUS_ADD_CHILD(sc->dev, 0, "bhnd_nvram", -1); 356f4a3eb02SAdrian Chadd if (nvram_dev == NULL) { 357f4a3eb02SAdrian Chadd device_printf(sc->dev, "failed to add NVRAM device\n"); 358f4a3eb02SAdrian Chadd return (ENXIO); 359f4a3eb02SAdrian Chadd } 360f4a3eb02SAdrian Chadd 361f4a3eb02SAdrian Chadd start = rman_get_start(sc->core->res) + CHIPC_SPROM_OTP; 362f4a3eb02SAdrian Chadd error = bus_set_resource(nvram_dev, SYS_RES_MEMORY, 0, start, 363f4a3eb02SAdrian Chadd CHIPC_SPROM_OTP_SIZE); 364e83ce340SAdrian Chadd return (error); 365f4a3eb02SAdrian Chadd 366f4a3eb02SAdrian Chadd case BHND_NVRAM_SRC_FLASH: 367f4a3eb02SAdrian Chadd // TODO flash support 368f4a3eb02SAdrian Chadd device_printf(sc->dev, "flash nvram source unsupported\n"); 369f4a3eb02SAdrian Chadd return (0); 370f4a3eb02SAdrian Chadd 371f4a3eb02SAdrian Chadd case BHND_NVRAM_SRC_UNKNOWN: 372f4a3eb02SAdrian Chadd /* Handled externally */ 373f4a3eb02SAdrian Chadd return (0); 374f4a3eb02SAdrian Chadd 375f4a3eb02SAdrian Chadd default: 376f4a3eb02SAdrian Chadd device_printf(sc->dev, "invalid nvram source: %u\n", 377f4a3eb02SAdrian Chadd sc->nvram_src); 378f4a3eb02SAdrian Chadd return (ENXIO); 379f4a3eb02SAdrian Chadd } 3804ad7e9b0SAdrian Chadd } 3814ad7e9b0SAdrian Chadd 3824ad7e9b0SAdrian Chadd /** 383e83ce340SAdrian Chadd * Determine the NVRAM data source for this device. 384e83ce340SAdrian Chadd * 385e83ce340SAdrian Chadd * @param sc chipc driver state. 3864ad7e9b0SAdrian Chadd */ 3874ad7e9b0SAdrian Chadd static bhnd_nvram_src_t 388e83ce340SAdrian Chadd chipc_nvram_identify(struct chipc_softc *sc) 3894ad7e9b0SAdrian Chadd { 3904ad7e9b0SAdrian Chadd uint32_t srom_ctrl; 3914ad7e9b0SAdrian Chadd 392e83ce340SAdrian Chadd /* Very early devices vend SPROM/OTP/CIS (if at all) via the 393e83ce340SAdrian Chadd * host bridge interface instead of ChipCommon. */ 394e83ce340SAdrian Chadd if (!CHIPC_QUIRK(sc, SUPPORTS_SPROM)) 395e83ce340SAdrian Chadd return (BHND_NVRAM_SRC_UNKNOWN); 3964ad7e9b0SAdrian Chadd 3974ad7e9b0SAdrian Chadd /* 398e83ce340SAdrian Chadd * Later chipset revisions standardized the SPROM capability flags and 3994ad7e9b0SAdrian Chadd * register interfaces. 4004ad7e9b0SAdrian Chadd * 4014ad7e9b0SAdrian Chadd * We check for hardware presence in order of precedence. For example, 4024ad7e9b0SAdrian Chadd * SPROM is is always used in preference to internal OTP if found. 4034ad7e9b0SAdrian Chadd */ 404f4a3eb02SAdrian Chadd if (CHIPC_CAP(sc, sprom)) { 4054ad7e9b0SAdrian Chadd srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL); 4064ad7e9b0SAdrian Chadd if (srom_ctrl & CHIPC_SRC_PRESENT) 4074ad7e9b0SAdrian Chadd return (BHND_NVRAM_SRC_SPROM); 4084ad7e9b0SAdrian Chadd } 4094ad7e9b0SAdrian Chadd 4104ad7e9b0SAdrian Chadd /* Check for OTP */ 411f4a3eb02SAdrian Chadd if (CHIPC_CAP(sc, otp_size) != 0) 4124ad7e9b0SAdrian Chadd return (BHND_NVRAM_SRC_OTP); 4134ad7e9b0SAdrian Chadd 414f4a3eb02SAdrian Chadd /* Check for flash */ 415f4a3eb02SAdrian Chadd if (CHIPC_CAP(sc, flash_type) != CHIPC_FLASH_NONE) 416f4a3eb02SAdrian Chadd return (BHND_NVRAM_SRC_FLASH); 4174ad7e9b0SAdrian Chadd 4184ad7e9b0SAdrian Chadd /* No NVRAM hardware capability declared */ 419e83ce340SAdrian Chadd return (BHND_NVRAM_SRC_UNKNOWN); 420e83ce340SAdrian Chadd } 421e83ce340SAdrian Chadd 422f4a3eb02SAdrian Chadd static int 423f4a3eb02SAdrian Chadd chipc_suspend(device_t dev) 424f4a3eb02SAdrian Chadd { 425f4a3eb02SAdrian Chadd return (bus_generic_suspend(dev)); 426f4a3eb02SAdrian Chadd } 427f4a3eb02SAdrian Chadd 428f4a3eb02SAdrian Chadd static int 429f4a3eb02SAdrian Chadd chipc_resume(device_t dev) 430f4a3eb02SAdrian Chadd { 431f4a3eb02SAdrian Chadd return (bus_generic_resume(dev)); 432f4a3eb02SAdrian Chadd } 433f4a3eb02SAdrian Chadd 434f4a3eb02SAdrian Chadd static void 435f4a3eb02SAdrian Chadd chipc_probe_nomatch(device_t dev, device_t child) 436f4a3eb02SAdrian Chadd { 437f4a3eb02SAdrian Chadd struct resource_list *rl; 438f4a3eb02SAdrian Chadd const char *name; 439f4a3eb02SAdrian Chadd 440f4a3eb02SAdrian Chadd name = device_get_name(child); 441f4a3eb02SAdrian Chadd if (name == NULL) 442f4a3eb02SAdrian Chadd name = "unknown device"; 443f4a3eb02SAdrian Chadd 444f4a3eb02SAdrian Chadd device_printf(dev, "<%s> at", name); 445f4a3eb02SAdrian Chadd 446f4a3eb02SAdrian Chadd rl = BUS_GET_RESOURCE_LIST(dev, child); 447f4a3eb02SAdrian Chadd if (rl != NULL) { 448f4a3eb02SAdrian Chadd resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 449f4a3eb02SAdrian Chadd resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 450f4a3eb02SAdrian Chadd } 451f4a3eb02SAdrian Chadd 452f4a3eb02SAdrian Chadd printf(" (no driver attached)\n"); 453f4a3eb02SAdrian Chadd } 454f4a3eb02SAdrian Chadd 455f4a3eb02SAdrian Chadd static int 456f4a3eb02SAdrian Chadd chipc_print_child(device_t dev, device_t child) 457f4a3eb02SAdrian Chadd { 458f4a3eb02SAdrian Chadd struct resource_list *rl; 459f4a3eb02SAdrian Chadd int retval = 0; 460f4a3eb02SAdrian Chadd 461f4a3eb02SAdrian Chadd retval += bus_print_child_header(dev, child); 462f4a3eb02SAdrian Chadd 463f4a3eb02SAdrian Chadd rl = BUS_GET_RESOURCE_LIST(dev, child); 464f4a3eb02SAdrian Chadd if (rl != NULL) { 465f4a3eb02SAdrian Chadd retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, 466f4a3eb02SAdrian Chadd "%#jx"); 467f4a3eb02SAdrian Chadd retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, 468f4a3eb02SAdrian Chadd "%jd"); 469f4a3eb02SAdrian Chadd } 470f4a3eb02SAdrian Chadd 471f4a3eb02SAdrian Chadd retval += bus_print_child_domain(dev, child); 472f4a3eb02SAdrian Chadd retval += bus_print_child_footer(dev, child); 473f4a3eb02SAdrian Chadd 474f4a3eb02SAdrian Chadd return (retval); 475f4a3eb02SAdrian Chadd } 476f4a3eb02SAdrian Chadd 477f4a3eb02SAdrian Chadd static int 478f4a3eb02SAdrian Chadd chipc_child_pnpinfo_str(device_t dev, device_t child, char *buf, 479f4a3eb02SAdrian Chadd size_t buflen) 480f4a3eb02SAdrian Chadd { 481f4a3eb02SAdrian Chadd if (buflen == 0) 482f4a3eb02SAdrian Chadd return (EOVERFLOW); 483f4a3eb02SAdrian Chadd 484f4a3eb02SAdrian Chadd *buf = '\0'; 485f4a3eb02SAdrian Chadd return (0); 486f4a3eb02SAdrian Chadd } 487f4a3eb02SAdrian Chadd 488f4a3eb02SAdrian Chadd static int 489f4a3eb02SAdrian Chadd chipc_child_location_str(device_t dev, device_t child, char *buf, 490f4a3eb02SAdrian Chadd size_t buflen) 491f4a3eb02SAdrian Chadd { 492f4a3eb02SAdrian Chadd if (buflen == 0) 493f4a3eb02SAdrian Chadd return (EOVERFLOW); 494f4a3eb02SAdrian Chadd 495f4a3eb02SAdrian Chadd *buf = '\0'; 496f4a3eb02SAdrian Chadd return (ENXIO); 497f4a3eb02SAdrian Chadd } 498f4a3eb02SAdrian Chadd 499f4a3eb02SAdrian Chadd static device_t 500f4a3eb02SAdrian Chadd chipc_add_child(device_t dev, u_int order, const char *name, int unit) 501f4a3eb02SAdrian Chadd { 502f4a3eb02SAdrian Chadd struct chipc_devinfo *dinfo; 503f4a3eb02SAdrian Chadd device_t child; 504f4a3eb02SAdrian Chadd 505f4a3eb02SAdrian Chadd child = device_add_child_ordered(dev, order, name, unit); 506f4a3eb02SAdrian Chadd if (child == NULL) 507f4a3eb02SAdrian Chadd return (NULL); 508f4a3eb02SAdrian Chadd 509f4a3eb02SAdrian Chadd dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT); 510f4a3eb02SAdrian Chadd if (dinfo == NULL) { 511f4a3eb02SAdrian Chadd device_delete_child(dev, child); 512f4a3eb02SAdrian Chadd return (NULL); 513f4a3eb02SAdrian Chadd } 514f4a3eb02SAdrian Chadd 515f4a3eb02SAdrian Chadd resource_list_init(&dinfo->resources); 516f4a3eb02SAdrian Chadd 517f4a3eb02SAdrian Chadd device_set_ivars(child, dinfo); 518f4a3eb02SAdrian Chadd 519f4a3eb02SAdrian Chadd return (child); 520f4a3eb02SAdrian Chadd } 521f4a3eb02SAdrian Chadd 522f4a3eb02SAdrian Chadd static void 523f4a3eb02SAdrian Chadd chipc_child_deleted(device_t dev, device_t child) 524f4a3eb02SAdrian Chadd { 525f4a3eb02SAdrian Chadd struct chipc_devinfo *dinfo = device_get_ivars(child); 526f4a3eb02SAdrian Chadd 527f4a3eb02SAdrian Chadd if (dinfo != NULL) { 528f4a3eb02SAdrian Chadd resource_list_free(&dinfo->resources); 529f4a3eb02SAdrian Chadd free(dinfo, M_BHND); 530f4a3eb02SAdrian Chadd } 531f4a3eb02SAdrian Chadd 532f4a3eb02SAdrian Chadd device_set_ivars(child, NULL); 533f4a3eb02SAdrian Chadd } 534f4a3eb02SAdrian Chadd 535f4a3eb02SAdrian Chadd static struct resource_list * 536f4a3eb02SAdrian Chadd chipc_get_resource_list(device_t dev, device_t child) 537f4a3eb02SAdrian Chadd { 538f4a3eb02SAdrian Chadd struct chipc_devinfo *dinfo = device_get_ivars(child); 539f4a3eb02SAdrian Chadd return (&dinfo->resources); 540f4a3eb02SAdrian Chadd } 541f4a3eb02SAdrian Chadd 542f4a3eb02SAdrian Chadd 543f4a3eb02SAdrian Chadd /* Allocate region records for the given port, and add the port's memory 544f4a3eb02SAdrian Chadd * range to the mem_rman */ 545f4a3eb02SAdrian Chadd static int 546f4a3eb02SAdrian Chadd chipc_rman_init_regions (struct chipc_softc *sc, bhnd_port_type type, 547f4a3eb02SAdrian Chadd u_int port) 548f4a3eb02SAdrian Chadd { 549f4a3eb02SAdrian Chadd struct chipc_region *cr; 550f4a3eb02SAdrian Chadd rman_res_t start, end; 551f4a3eb02SAdrian Chadd u_int num_regions; 552f4a3eb02SAdrian Chadd int error; 553f4a3eb02SAdrian Chadd 554f4a3eb02SAdrian Chadd num_regions = bhnd_get_region_count(sc->dev, port, port); 555f4a3eb02SAdrian Chadd for (u_int region = 0; region < num_regions; region++) { 556f4a3eb02SAdrian Chadd /* Allocate new region record */ 557f4a3eb02SAdrian Chadd cr = chipc_alloc_region(sc, type, port, region); 558f4a3eb02SAdrian Chadd if (cr == NULL) 559f4a3eb02SAdrian Chadd return (ENODEV); 560f4a3eb02SAdrian Chadd 561f4a3eb02SAdrian Chadd /* Can't manage regions that cannot be allocated */ 562f4a3eb02SAdrian Chadd if (cr->cr_rid < 0) { 563f4a3eb02SAdrian Chadd BHND_DEBUG_DEV(sc->dev, "no rid for chipc region " 564f4a3eb02SAdrian Chadd "%s%u.%u", bhnd_port_type_name(type), port, region); 565f4a3eb02SAdrian Chadd chipc_free_region(sc, cr); 566f4a3eb02SAdrian Chadd continue; 567f4a3eb02SAdrian Chadd } 568f4a3eb02SAdrian Chadd 569f4a3eb02SAdrian Chadd /* Add to rman's managed range */ 570f4a3eb02SAdrian Chadd start = cr->cr_addr; 571f4a3eb02SAdrian Chadd end = cr->cr_end; 572f4a3eb02SAdrian Chadd if ((error = rman_manage_region(&sc->mem_rman, start, end))) { 573f4a3eb02SAdrian Chadd chipc_free_region(sc, cr); 574f4a3eb02SAdrian Chadd return (error); 575f4a3eb02SAdrian Chadd } 576f4a3eb02SAdrian Chadd 577f4a3eb02SAdrian Chadd /* Add to region list */ 578f4a3eb02SAdrian Chadd STAILQ_INSERT_TAIL(&sc->mem_regions, cr, cr_link); 579f4a3eb02SAdrian Chadd } 580f4a3eb02SAdrian Chadd 581f4a3eb02SAdrian Chadd return (0); 582f4a3eb02SAdrian Chadd } 583f4a3eb02SAdrian Chadd 584f4a3eb02SAdrian Chadd /* Initialize memory state for all chipc port regions */ 585f4a3eb02SAdrian Chadd static int 586f4a3eb02SAdrian Chadd chipc_init_rman(struct chipc_softc *sc) 587f4a3eb02SAdrian Chadd { 588f4a3eb02SAdrian Chadd u_int num_ports; 589f4a3eb02SAdrian Chadd int error; 590f4a3eb02SAdrian Chadd 591f4a3eb02SAdrian Chadd /* Port types for which we'll register chipc_region mappings */ 592f4a3eb02SAdrian Chadd bhnd_port_type types[] = { 593f4a3eb02SAdrian Chadd BHND_PORT_DEVICE 594f4a3eb02SAdrian Chadd }; 595f4a3eb02SAdrian Chadd 596f4a3eb02SAdrian Chadd /* Initialize resource manager */ 597f4a3eb02SAdrian Chadd sc->mem_rman.rm_start = 0; 598f4a3eb02SAdrian Chadd sc->mem_rman.rm_end = BUS_SPACE_MAXADDR; 599f4a3eb02SAdrian Chadd sc->mem_rman.rm_type = RMAN_ARRAY; 600f4a3eb02SAdrian Chadd sc->mem_rman.rm_descr = "ChipCommon Device Memory"; 601f4a3eb02SAdrian Chadd if ((error = rman_init(&sc->mem_rman))) { 602f4a3eb02SAdrian Chadd device_printf(sc->dev, "could not initialize mem_rman: %d\n", 603f4a3eb02SAdrian Chadd error); 604f4a3eb02SAdrian Chadd return (error); 605f4a3eb02SAdrian Chadd } 606f4a3eb02SAdrian Chadd 607f4a3eb02SAdrian Chadd /* Populate per-port-region state */ 608f4a3eb02SAdrian Chadd for (u_int i = 0; i < nitems(types); i++) { 609f4a3eb02SAdrian Chadd num_ports = bhnd_get_port_count(sc->dev, types[i]); 610f4a3eb02SAdrian Chadd for (u_int port = 0; port < num_ports; port++) { 611f4a3eb02SAdrian Chadd error = chipc_rman_init_regions(sc, types[i], port); 612f4a3eb02SAdrian Chadd if (error) { 613f4a3eb02SAdrian Chadd device_printf(sc->dev, 614f4a3eb02SAdrian Chadd "region init failed for %s%u: %d\n", 615f4a3eb02SAdrian Chadd bhnd_port_type_name(types[i]), port, 616f4a3eb02SAdrian Chadd error); 617f4a3eb02SAdrian Chadd 618f4a3eb02SAdrian Chadd goto failed; 619f4a3eb02SAdrian Chadd } 620f4a3eb02SAdrian Chadd } 621f4a3eb02SAdrian Chadd } 622f4a3eb02SAdrian Chadd 623f4a3eb02SAdrian Chadd return (0); 624f4a3eb02SAdrian Chadd 625f4a3eb02SAdrian Chadd failed: 626f4a3eb02SAdrian Chadd chipc_free_rman(sc); 627f4a3eb02SAdrian Chadd return (error); 628f4a3eb02SAdrian Chadd } 629f4a3eb02SAdrian Chadd 630f4a3eb02SAdrian Chadd /* Free memory management state */ 631f4a3eb02SAdrian Chadd static void 632f4a3eb02SAdrian Chadd chipc_free_rman(struct chipc_softc *sc) 633f4a3eb02SAdrian Chadd { 634f4a3eb02SAdrian Chadd struct chipc_region *cr, *cr_next; 635f4a3eb02SAdrian Chadd 636f4a3eb02SAdrian Chadd STAILQ_FOREACH_SAFE(cr, &sc->mem_regions, cr_link, cr_next) 637f4a3eb02SAdrian Chadd chipc_free_region(sc, cr); 638f4a3eb02SAdrian Chadd 639f4a3eb02SAdrian Chadd rman_fini(&sc->mem_rman); 640f4a3eb02SAdrian Chadd } 641f4a3eb02SAdrian Chadd 642f4a3eb02SAdrian Chadd /** 643f4a3eb02SAdrian Chadd * Return the rman instance for a given resource @p type, if any. 644f4a3eb02SAdrian Chadd * 645f4a3eb02SAdrian Chadd * @param sc The chipc device state. 646f4a3eb02SAdrian Chadd * @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...) 647f4a3eb02SAdrian Chadd */ 648f4a3eb02SAdrian Chadd static struct rman * 649f4a3eb02SAdrian Chadd chipc_get_rman(struct chipc_softc *sc, int type) 650f4a3eb02SAdrian Chadd { 651f4a3eb02SAdrian Chadd switch (type) { 652f4a3eb02SAdrian Chadd case SYS_RES_MEMORY: 653f4a3eb02SAdrian Chadd return (&sc->mem_rman); 654f4a3eb02SAdrian Chadd 655f4a3eb02SAdrian Chadd case SYS_RES_IRQ: 656f4a3eb02SAdrian Chadd /* IRQs can be used with RF_SHAREABLE, so we don't perform 657f4a3eb02SAdrian Chadd * any local proxying of resource requests. */ 658f4a3eb02SAdrian Chadd return (NULL); 659f4a3eb02SAdrian Chadd 660f4a3eb02SAdrian Chadd default: 661f4a3eb02SAdrian Chadd return (NULL); 662f4a3eb02SAdrian Chadd }; 663f4a3eb02SAdrian Chadd } 664f4a3eb02SAdrian Chadd 665f4a3eb02SAdrian Chadd static struct resource * 666f4a3eb02SAdrian Chadd chipc_alloc_resource(device_t dev, device_t child, int type, 667f4a3eb02SAdrian Chadd int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 668f4a3eb02SAdrian Chadd { 669f4a3eb02SAdrian Chadd struct chipc_softc *sc; 670f4a3eb02SAdrian Chadd struct chipc_region *cr; 671f4a3eb02SAdrian Chadd struct resource_list_entry *rle; 672f4a3eb02SAdrian Chadd struct resource *rv; 673f4a3eb02SAdrian Chadd struct rman *rm; 674f4a3eb02SAdrian Chadd int error; 675f4a3eb02SAdrian Chadd bool passthrough, isdefault; 676f4a3eb02SAdrian Chadd 677f4a3eb02SAdrian Chadd sc = device_get_softc(dev); 678f4a3eb02SAdrian Chadd passthrough = (device_get_parent(child) != dev); 679f4a3eb02SAdrian Chadd isdefault = RMAN_IS_DEFAULT_RANGE(start, end); 680f4a3eb02SAdrian Chadd rle = NULL; 681f4a3eb02SAdrian Chadd 682f4a3eb02SAdrian Chadd /* Fetch the resource manager, delegate request if necessary */ 683f4a3eb02SAdrian Chadd rm = chipc_get_rman(sc, type); 684f4a3eb02SAdrian Chadd if (rm == NULL) { 685f4a3eb02SAdrian Chadd /* Requested resource type is delegated to our parent */ 686f4a3eb02SAdrian Chadd rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 687f4a3eb02SAdrian Chadd start, end, count, flags); 688f4a3eb02SAdrian Chadd return (rv); 689f4a3eb02SAdrian Chadd } 690f4a3eb02SAdrian Chadd 691f4a3eb02SAdrian Chadd /* Populate defaults */ 692f4a3eb02SAdrian Chadd if (!passthrough && isdefault) { 693f4a3eb02SAdrian Chadd /* Fetch the resource list entry. */ 694f4a3eb02SAdrian Chadd rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), 695f4a3eb02SAdrian Chadd type, *rid); 696f4a3eb02SAdrian Chadd if (rle == NULL) { 697f4a3eb02SAdrian Chadd device_printf(dev, 698f4a3eb02SAdrian Chadd "default resource %#x type %d for child %s " 699f4a3eb02SAdrian Chadd "not found\n", *rid, type, 700f4a3eb02SAdrian Chadd device_get_nameunit(child)); 701f4a3eb02SAdrian Chadd return (NULL); 702f4a3eb02SAdrian Chadd } 703f4a3eb02SAdrian Chadd 704f4a3eb02SAdrian Chadd if (rle->res != NULL) { 705f4a3eb02SAdrian Chadd device_printf(dev, 706f4a3eb02SAdrian Chadd "resource entry %#x type %d for child %s is busy\n", 707f4a3eb02SAdrian Chadd *rid, type, device_get_nameunit(child)); 708f4a3eb02SAdrian Chadd 709f4a3eb02SAdrian Chadd return (NULL); 710f4a3eb02SAdrian Chadd } 711f4a3eb02SAdrian Chadd 712f4a3eb02SAdrian Chadd start = rle->start; 713f4a3eb02SAdrian Chadd end = rle->end; 714f4a3eb02SAdrian Chadd count = ulmax(count, rle->count); 715f4a3eb02SAdrian Chadd } 716f4a3eb02SAdrian Chadd 717f4a3eb02SAdrian Chadd /* Locate a mapping region */ 718f4a3eb02SAdrian Chadd if ((cr = chipc_find_region(sc, start, end)) == NULL) { 719f4a3eb02SAdrian Chadd /* Resource requests outside our shared port regions can be 720f4a3eb02SAdrian Chadd * delegated to our parent. */ 721f4a3eb02SAdrian Chadd rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 722f4a3eb02SAdrian Chadd start, end, count, flags); 723f4a3eb02SAdrian Chadd return (rv); 724f4a3eb02SAdrian Chadd } 725f4a3eb02SAdrian Chadd 726f4a3eb02SAdrian Chadd /* Try to retain a region reference */ 727f4a3eb02SAdrian Chadd if ((error = chipc_retain_region(sc, cr, RF_ALLOCATED))) { 728f4a3eb02SAdrian Chadd CHIPC_UNLOCK(sc); 729f4a3eb02SAdrian Chadd return (NULL); 730f4a3eb02SAdrian Chadd } 731f4a3eb02SAdrian Chadd 732f4a3eb02SAdrian Chadd /* Make our rman reservation */ 733f4a3eb02SAdrian Chadd rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE, 734f4a3eb02SAdrian Chadd child); 735f4a3eb02SAdrian Chadd if (rv == NULL) { 736f4a3eb02SAdrian Chadd chipc_release_region(sc, cr, RF_ALLOCATED); 737f4a3eb02SAdrian Chadd return (NULL); 738f4a3eb02SAdrian Chadd } 739f4a3eb02SAdrian Chadd 740f4a3eb02SAdrian Chadd rman_set_rid(rv, *rid); 741f4a3eb02SAdrian Chadd 742f4a3eb02SAdrian Chadd /* Activate */ 743f4a3eb02SAdrian Chadd if (flags & RF_ACTIVE) { 744f4a3eb02SAdrian Chadd error = bus_activate_resource(child, type, *rid, rv); 745f4a3eb02SAdrian Chadd if (error) { 746f4a3eb02SAdrian Chadd device_printf(dev, 747f4a3eb02SAdrian Chadd "failed to activate entry %#x type %d for " 748f4a3eb02SAdrian Chadd "child %s: %d\n", 749f4a3eb02SAdrian Chadd *rid, type, device_get_nameunit(child), error); 750f4a3eb02SAdrian Chadd 751f4a3eb02SAdrian Chadd chipc_release_region(sc, cr, RF_ALLOCATED); 752f4a3eb02SAdrian Chadd rman_release_resource(rv); 753f4a3eb02SAdrian Chadd 754f4a3eb02SAdrian Chadd return (NULL); 755f4a3eb02SAdrian Chadd } 756f4a3eb02SAdrian Chadd } 757f4a3eb02SAdrian Chadd 758f4a3eb02SAdrian Chadd /* Update child's resource list entry */ 759f4a3eb02SAdrian Chadd if (rle != NULL) { 760f4a3eb02SAdrian Chadd rle->res = rv; 761f4a3eb02SAdrian Chadd rle->start = rman_get_start(rv); 762f4a3eb02SAdrian Chadd rle->end = rman_get_end(rv); 763f4a3eb02SAdrian Chadd rle->count = rman_get_size(rv); 764f4a3eb02SAdrian Chadd } 765f4a3eb02SAdrian Chadd 766f4a3eb02SAdrian Chadd return (rv); 767f4a3eb02SAdrian Chadd } 768f4a3eb02SAdrian Chadd 769f4a3eb02SAdrian Chadd static int 770f4a3eb02SAdrian Chadd chipc_release_resource(device_t dev, device_t child, int type, int rid, 771f4a3eb02SAdrian Chadd struct resource *r) 772f4a3eb02SAdrian Chadd { 773f4a3eb02SAdrian Chadd struct chipc_softc *sc; 774f4a3eb02SAdrian Chadd struct chipc_region *cr; 775f4a3eb02SAdrian Chadd struct rman *rm; 776f4a3eb02SAdrian Chadd int error; 777f4a3eb02SAdrian Chadd 778f4a3eb02SAdrian Chadd sc = device_get_softc(dev); 779f4a3eb02SAdrian Chadd 780f4a3eb02SAdrian Chadd /* Handled by parent bus? */ 781f4a3eb02SAdrian Chadd rm = chipc_get_rman(sc, type); 782f4a3eb02SAdrian Chadd if (rm == NULL || !rman_is_region_manager(r, rm)) { 783f4a3eb02SAdrian Chadd return (bus_generic_rl_release_resource(dev, child, type, rid, 784f4a3eb02SAdrian Chadd r)); 785f4a3eb02SAdrian Chadd } 786f4a3eb02SAdrian Chadd 787f4a3eb02SAdrian Chadd /* Locate the mapping region */ 788f4a3eb02SAdrian Chadd cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 789f4a3eb02SAdrian Chadd if (cr == NULL) 790f4a3eb02SAdrian Chadd return (EINVAL); 791f4a3eb02SAdrian Chadd 792f4a3eb02SAdrian Chadd /* Deactivate resources */ 793f4a3eb02SAdrian Chadd if (rman_get_flags(r) & RF_ACTIVE) { 794f4a3eb02SAdrian Chadd error = BUS_DEACTIVATE_RESOURCE(dev, child, type, rid, r); 795f4a3eb02SAdrian Chadd if (error) 796f4a3eb02SAdrian Chadd return (error); 797f4a3eb02SAdrian Chadd } 798f4a3eb02SAdrian Chadd 799f4a3eb02SAdrian Chadd if ((error = rman_release_resource(r))) 800f4a3eb02SAdrian Chadd return (error); 801f4a3eb02SAdrian Chadd 802f4a3eb02SAdrian Chadd /* Drop allocation reference */ 803f4a3eb02SAdrian Chadd chipc_release_region(sc, cr, RF_ALLOCATED); 804f4a3eb02SAdrian Chadd 805f4a3eb02SAdrian Chadd return (0); 806f4a3eb02SAdrian Chadd } 807f4a3eb02SAdrian Chadd 808f4a3eb02SAdrian Chadd static int 809f4a3eb02SAdrian Chadd chipc_adjust_resource(device_t dev, device_t child, int type, 810f4a3eb02SAdrian Chadd struct resource *r, rman_res_t start, rman_res_t end) 811f4a3eb02SAdrian Chadd { 812f4a3eb02SAdrian Chadd struct chipc_softc *sc; 813f4a3eb02SAdrian Chadd struct chipc_region *cr; 814f4a3eb02SAdrian Chadd struct rman *rm; 815f4a3eb02SAdrian Chadd 816f4a3eb02SAdrian Chadd sc = device_get_softc(dev); 817f4a3eb02SAdrian Chadd 818f4a3eb02SAdrian Chadd /* Handled by parent bus? */ 819f4a3eb02SAdrian Chadd rm = chipc_get_rman(sc, type); 820f4a3eb02SAdrian Chadd if (rm == NULL || !rman_is_region_manager(r, rm)) { 821f4a3eb02SAdrian Chadd return (bus_generic_adjust_resource(dev, child, type, r, start, 822f4a3eb02SAdrian Chadd end)); 823f4a3eb02SAdrian Chadd } 824f4a3eb02SAdrian Chadd 825f4a3eb02SAdrian Chadd /* The range is limited to the existing region mapping */ 826f4a3eb02SAdrian Chadd cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 827f4a3eb02SAdrian Chadd if (cr == NULL) 828f4a3eb02SAdrian Chadd return (EINVAL); 829f4a3eb02SAdrian Chadd 830f4a3eb02SAdrian Chadd if (end <= start) 831f4a3eb02SAdrian Chadd return (EINVAL); 832f4a3eb02SAdrian Chadd 833f4a3eb02SAdrian Chadd if (start < cr->cr_addr || end > cr->cr_end) 834f4a3eb02SAdrian Chadd return (EINVAL); 835f4a3eb02SAdrian Chadd 836f4a3eb02SAdrian Chadd /* Range falls within the existing region */ 837f4a3eb02SAdrian Chadd return (rman_adjust_resource(r, start, end)); 838f4a3eb02SAdrian Chadd } 839f4a3eb02SAdrian Chadd 840f4a3eb02SAdrian Chadd /** 841f4a3eb02SAdrian Chadd * Retain an RF_ACTIVE reference to the region mapping @p r, and 842f4a3eb02SAdrian Chadd * configure @p r with its subregion values. 843f4a3eb02SAdrian Chadd * 844f4a3eb02SAdrian Chadd * @param sc Driver instance state. 845f4a3eb02SAdrian Chadd * @param child Requesting child device. 846f4a3eb02SAdrian Chadd * @param type resource type of @p r. 847f4a3eb02SAdrian Chadd * @param rid resource id of @p r 848f4a3eb02SAdrian Chadd * @param r resource to be activated. 849f4a3eb02SAdrian Chadd * @param req_direct If true, failure to allocate a direct bhnd resource 850f4a3eb02SAdrian Chadd * will be treated as an error. If false, the resource will not be marked 851f4a3eb02SAdrian Chadd * as RF_ACTIVE if bhnd direct resource allocation fails. 852f4a3eb02SAdrian Chadd */ 853f4a3eb02SAdrian Chadd static int 854f4a3eb02SAdrian Chadd chipc_try_activate_resource(struct chipc_softc *sc, device_t child, int type, 855f4a3eb02SAdrian Chadd int rid, struct resource *r, bool req_direct) 856f4a3eb02SAdrian Chadd { 857f4a3eb02SAdrian Chadd struct rman *rm; 858f4a3eb02SAdrian Chadd struct chipc_region *cr; 859f4a3eb02SAdrian Chadd bhnd_size_t cr_offset; 860f4a3eb02SAdrian Chadd rman_res_t r_start, r_end, r_size; 861f4a3eb02SAdrian Chadd int error; 862f4a3eb02SAdrian Chadd 863f4a3eb02SAdrian Chadd rm = chipc_get_rman(sc, type); 864f4a3eb02SAdrian Chadd if (rm == NULL || !rman_is_region_manager(r, rm)) 865f4a3eb02SAdrian Chadd return (EINVAL); 866f4a3eb02SAdrian Chadd 867f4a3eb02SAdrian Chadd r_start = rman_get_start(r); 868f4a3eb02SAdrian Chadd r_end = rman_get_end(r); 869f4a3eb02SAdrian Chadd r_size = rman_get_size(r); 870f4a3eb02SAdrian Chadd 871f4a3eb02SAdrian Chadd /* Find the corresponding chipc region */ 872f4a3eb02SAdrian Chadd cr = chipc_find_region(sc, r_start, r_end); 873f4a3eb02SAdrian Chadd if (cr == NULL) 874f4a3eb02SAdrian Chadd return (EINVAL); 875f4a3eb02SAdrian Chadd 876f4a3eb02SAdrian Chadd /* Calculate subregion offset within the chipc region */ 877f4a3eb02SAdrian Chadd cr_offset = r_start - cr->cr_addr; 878f4a3eb02SAdrian Chadd 879f4a3eb02SAdrian Chadd /* Retain (and activate, if necessary) the chipc region */ 880f4a3eb02SAdrian Chadd if ((error = chipc_retain_region(sc, cr, RF_ACTIVE))) 881f4a3eb02SAdrian Chadd return (error); 882f4a3eb02SAdrian Chadd 883f4a3eb02SAdrian Chadd /* Configure child resource with its subregion values. */ 884f4a3eb02SAdrian Chadd if (cr->cr_res->direct) { 885f4a3eb02SAdrian Chadd error = chipc_init_child_resource(r, cr->cr_res->res, 886f4a3eb02SAdrian Chadd cr_offset, r_size); 887f4a3eb02SAdrian Chadd if (error) 888f4a3eb02SAdrian Chadd goto cleanup; 889f4a3eb02SAdrian Chadd 890f4a3eb02SAdrian Chadd /* Mark active */ 891f4a3eb02SAdrian Chadd if ((error = rman_activate_resource(r))) 892f4a3eb02SAdrian Chadd goto cleanup; 893f4a3eb02SAdrian Chadd } else if (req_direct) { 894f4a3eb02SAdrian Chadd error = ENOMEM; 895f4a3eb02SAdrian Chadd goto cleanup; 896f4a3eb02SAdrian Chadd } 897f4a3eb02SAdrian Chadd 898f4a3eb02SAdrian Chadd return (0); 899f4a3eb02SAdrian Chadd 900f4a3eb02SAdrian Chadd cleanup: 901f4a3eb02SAdrian Chadd chipc_release_region(sc, cr, RF_ACTIVE); 902f4a3eb02SAdrian Chadd return (error); 903f4a3eb02SAdrian Chadd } 904f4a3eb02SAdrian Chadd 905f4a3eb02SAdrian Chadd static int 906f4a3eb02SAdrian Chadd chipc_activate_bhnd_resource(device_t dev, device_t child, int type, 907f4a3eb02SAdrian Chadd int rid, struct bhnd_resource *r) 908f4a3eb02SAdrian Chadd { 909f4a3eb02SAdrian Chadd struct chipc_softc *sc; 910f4a3eb02SAdrian Chadd struct rman *rm; 911f4a3eb02SAdrian Chadd int error; 912f4a3eb02SAdrian Chadd 913f4a3eb02SAdrian Chadd sc = device_get_softc(dev); 914f4a3eb02SAdrian Chadd 915f4a3eb02SAdrian Chadd /* Delegate non-locally managed resources to parent */ 916f4a3eb02SAdrian Chadd rm = chipc_get_rman(sc, type); 917f4a3eb02SAdrian Chadd if (rm == NULL || !rman_is_region_manager(r->res, rm)) { 918f4a3eb02SAdrian Chadd return (bhnd_bus_generic_activate_resource(dev, child, type, 919f4a3eb02SAdrian Chadd rid, r)); 920f4a3eb02SAdrian Chadd } 921f4a3eb02SAdrian Chadd 922f4a3eb02SAdrian Chadd /* Try activating the chipc region resource */ 923f4a3eb02SAdrian Chadd error = chipc_try_activate_resource(sc, child, type, rid, r->res, 924f4a3eb02SAdrian Chadd false); 925f4a3eb02SAdrian Chadd if (error) 926f4a3eb02SAdrian Chadd return (error); 927f4a3eb02SAdrian Chadd 928f4a3eb02SAdrian Chadd /* Mark the child resource as direct according to the returned resource 929f4a3eb02SAdrian Chadd * state */ 930f4a3eb02SAdrian Chadd if (rman_get_flags(r->res) & RF_ACTIVE) 931f4a3eb02SAdrian Chadd r->direct = true; 932f4a3eb02SAdrian Chadd 933f4a3eb02SAdrian Chadd return (0); 934f4a3eb02SAdrian Chadd } 935f4a3eb02SAdrian Chadd 936f4a3eb02SAdrian Chadd static int 937f4a3eb02SAdrian Chadd chipc_activate_resource(device_t dev, device_t child, int type, int rid, 938f4a3eb02SAdrian Chadd struct resource *r) 939f4a3eb02SAdrian Chadd { 940f4a3eb02SAdrian Chadd struct chipc_softc *sc; 941f4a3eb02SAdrian Chadd struct rman *rm; 942f4a3eb02SAdrian Chadd 943f4a3eb02SAdrian Chadd sc = device_get_softc(dev); 944f4a3eb02SAdrian Chadd 945f4a3eb02SAdrian Chadd /* Delegate non-locally managed resources to parent */ 946f4a3eb02SAdrian Chadd rm = chipc_get_rman(sc, type); 947f4a3eb02SAdrian Chadd if (rm == NULL || !rman_is_region_manager(r, rm)) { 948f4a3eb02SAdrian Chadd return (bus_generic_activate_resource(dev, child, type, rid, 949f4a3eb02SAdrian Chadd r)); 950f4a3eb02SAdrian Chadd } 951f4a3eb02SAdrian Chadd 952f4a3eb02SAdrian Chadd /* Try activating the chipc region-based resource */ 953f4a3eb02SAdrian Chadd return (chipc_try_activate_resource(sc, child, type, rid, r, true)); 954f4a3eb02SAdrian Chadd } 955f4a3eb02SAdrian Chadd 956f4a3eb02SAdrian Chadd /** 957f4a3eb02SAdrian Chadd * Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE(). 958f4a3eb02SAdrian Chadd */ 959f4a3eb02SAdrian Chadd static int 960f4a3eb02SAdrian Chadd chipc_deactivate_resource(device_t dev, device_t child, int type, 961f4a3eb02SAdrian Chadd int rid, struct resource *r) 962f4a3eb02SAdrian Chadd { 963f4a3eb02SAdrian Chadd struct chipc_softc *sc; 964f4a3eb02SAdrian Chadd struct chipc_region *cr; 965f4a3eb02SAdrian Chadd struct rman *rm; 966f4a3eb02SAdrian Chadd int error; 967f4a3eb02SAdrian Chadd 968f4a3eb02SAdrian Chadd sc = device_get_softc(dev); 969f4a3eb02SAdrian Chadd 970f4a3eb02SAdrian Chadd /* Handled by parent bus? */ 971f4a3eb02SAdrian Chadd rm = chipc_get_rman(sc, type); 972f4a3eb02SAdrian Chadd if (rm == NULL || !rman_is_region_manager(r, rm)) { 973f4a3eb02SAdrian Chadd return (bus_generic_deactivate_resource(dev, child, type, rid, 974f4a3eb02SAdrian Chadd r)); 975f4a3eb02SAdrian Chadd } 976f4a3eb02SAdrian Chadd 977f4a3eb02SAdrian Chadd /* Find the corresponding chipc region */ 978f4a3eb02SAdrian Chadd cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 979f4a3eb02SAdrian Chadd if (cr == NULL) 980f4a3eb02SAdrian Chadd return (EINVAL); 981f4a3eb02SAdrian Chadd 982f4a3eb02SAdrian Chadd /* Mark inactive */ 983f4a3eb02SAdrian Chadd if ((error = rman_deactivate_resource(r))) 984f4a3eb02SAdrian Chadd return (error); 985f4a3eb02SAdrian Chadd 986f4a3eb02SAdrian Chadd /* Drop associated RF_ACTIVE reference */ 987f4a3eb02SAdrian Chadd chipc_release_region(sc, cr, RF_ACTIVE); 988f4a3eb02SAdrian Chadd 989f4a3eb02SAdrian Chadd return (0); 990f4a3eb02SAdrian Chadd } 991f4a3eb02SAdrian Chadd 992f4a3eb02SAdrian Chadd /** 993f4a3eb02SAdrian Chadd * Examine bus state and make a best effort determination of whether it's 994f4a3eb02SAdrian Chadd * likely safe to enable the muxed SPROM pins. 995f4a3eb02SAdrian Chadd * 996f4a3eb02SAdrian Chadd * On devices that do not use SPROM pin muxing, always returns true. 997f4a3eb02SAdrian Chadd * 998f4a3eb02SAdrian Chadd * @param sc chipc driver state. 999f4a3eb02SAdrian Chadd */ 1000f4a3eb02SAdrian Chadd static bool 1001f4a3eb02SAdrian Chadd chipc_should_enable_sprom(struct chipc_softc *sc) 1002f4a3eb02SAdrian Chadd { 1003f4a3eb02SAdrian Chadd device_t *devs; 1004f4a3eb02SAdrian Chadd device_t hostb; 1005f4a3eb02SAdrian Chadd device_t parent; 1006f4a3eb02SAdrian Chadd int devcount; 1007f4a3eb02SAdrian Chadd int error; 1008f4a3eb02SAdrian Chadd bool result; 1009f4a3eb02SAdrian Chadd 1010f4a3eb02SAdrian Chadd mtx_assert(&Giant, MA_OWNED); /* for newbus */ 1011f4a3eb02SAdrian Chadd 1012f4a3eb02SAdrian Chadd /* Nothing to do? */ 1013f4a3eb02SAdrian Chadd if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1014f4a3eb02SAdrian Chadd return (true); 1015f4a3eb02SAdrian Chadd 1016f4a3eb02SAdrian Chadd parent = device_get_parent(sc->dev); 1017f4a3eb02SAdrian Chadd hostb = bhnd_find_hostb_device(parent); 1018f4a3eb02SAdrian Chadd 1019f4a3eb02SAdrian Chadd if ((error = device_get_children(parent, &devs, &devcount))) 1020f4a3eb02SAdrian Chadd return (false); 1021f4a3eb02SAdrian Chadd 1022f4a3eb02SAdrian Chadd /* Reject any active devices other than ChipCommon, or the 1023f4a3eb02SAdrian Chadd * host bridge (if any). */ 1024f4a3eb02SAdrian Chadd result = true; 1025f4a3eb02SAdrian Chadd for (int i = 0; i < devcount; i++) { 1026f4a3eb02SAdrian Chadd if (devs[i] == hostb || devs[i] == sc->dev) 1027f4a3eb02SAdrian Chadd continue; 1028f4a3eb02SAdrian Chadd 1029f4a3eb02SAdrian Chadd if (!device_is_attached(devs[i])) 1030f4a3eb02SAdrian Chadd continue; 1031f4a3eb02SAdrian Chadd 1032f4a3eb02SAdrian Chadd if (device_is_suspended(devs[i])) 1033f4a3eb02SAdrian Chadd continue; 1034f4a3eb02SAdrian Chadd 1035f4a3eb02SAdrian Chadd /* Active device; assume SPROM is busy */ 1036f4a3eb02SAdrian Chadd result = false; 1037f4a3eb02SAdrian Chadd break; 1038f4a3eb02SAdrian Chadd } 1039f4a3eb02SAdrian Chadd 1040f4a3eb02SAdrian Chadd free(devs, M_TEMP); 1041f4a3eb02SAdrian Chadd return (result); 1042f4a3eb02SAdrian Chadd } 1043e83ce340SAdrian Chadd 1044e83ce340SAdrian Chadd /** 1045e83ce340SAdrian Chadd * If required by this device, enable access to the SPROM. 1046e83ce340SAdrian Chadd * 1047e83ce340SAdrian Chadd * @param sc chipc driver state. 1048e83ce340SAdrian Chadd */ 1049e83ce340SAdrian Chadd static int 1050f4a3eb02SAdrian Chadd chipc_enable_sprom_pins(device_t dev) 1051e83ce340SAdrian Chadd { 1052f4a3eb02SAdrian Chadd struct chipc_softc *sc; 1053e83ce340SAdrian Chadd uint32_t cctrl; 1054f4a3eb02SAdrian Chadd int error; 1055e83ce340SAdrian Chadd 1056f4a3eb02SAdrian Chadd sc = device_get_softc(dev); 1057e83ce340SAdrian Chadd 1058e83ce340SAdrian Chadd /* Nothing to do? */ 1059e83ce340SAdrian Chadd if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1060e83ce340SAdrian Chadd return (0); 1061e83ce340SAdrian Chadd 1062f4a3eb02SAdrian Chadd /* Make sure we're holding Giant for newbus */ 1063f4a3eb02SAdrian Chadd mtx_lock(&Giant); 1064f4a3eb02SAdrian Chadd CHIPC_LOCK(sc); 1065f4a3eb02SAdrian Chadd 1066f4a3eb02SAdrian Chadd /* Already enabled? */ 1067f4a3eb02SAdrian Chadd if (sc->sprom_refcnt >= 1) { 1068f4a3eb02SAdrian Chadd error = 0; 1069f4a3eb02SAdrian Chadd goto finished; 1070f4a3eb02SAdrian Chadd } 1071f4a3eb02SAdrian Chadd 1072f4a3eb02SAdrian Chadd /* Check whether bus is busy */ 1073f4a3eb02SAdrian Chadd if (!chipc_should_enable_sprom(sc)) { 1074f4a3eb02SAdrian Chadd error = EBUSY; 1075f4a3eb02SAdrian Chadd goto finished; 1076f4a3eb02SAdrian Chadd } 1077f4a3eb02SAdrian Chadd 1078e83ce340SAdrian Chadd cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1079e83ce340SAdrian Chadd 1080e83ce340SAdrian Chadd /* 4331 devices */ 1081e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1082e83ce340SAdrian Chadd cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN; 1083e83ce340SAdrian Chadd 1084e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1085e83ce340SAdrian Chadd cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1086e83ce340SAdrian Chadd 1087e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1088e83ce340SAdrian Chadd cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2; 1089e83ce340SAdrian Chadd 1090e83ce340SAdrian Chadd bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1091f4a3eb02SAdrian Chadd error = 0; 1092f4a3eb02SAdrian Chadd goto finished; 1093e83ce340SAdrian Chadd } 1094e83ce340SAdrian Chadd 1095e83ce340SAdrian Chadd /* 4360 devices */ 1096e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1097e83ce340SAdrian Chadd /* Unimplemented */ 1098e83ce340SAdrian Chadd } 1099e83ce340SAdrian Chadd 1100e83ce340SAdrian Chadd /* Refuse to proceed on unsupported devices with muxed SPROM pins */ 1101e83ce340SAdrian Chadd device_printf(sc->dev, "muxed sprom lines on unrecognized device\n"); 1102f4a3eb02SAdrian Chadd error = ENXIO; 1103f4a3eb02SAdrian Chadd 1104f4a3eb02SAdrian Chadd finished: 1105f4a3eb02SAdrian Chadd /* Bump the reference count */ 1106f4a3eb02SAdrian Chadd if (error == 0) 1107f4a3eb02SAdrian Chadd sc->sprom_refcnt++; 1108f4a3eb02SAdrian Chadd 1109f4a3eb02SAdrian Chadd CHIPC_UNLOCK(sc); 1110f4a3eb02SAdrian Chadd mtx_unlock(&Giant); 1111f4a3eb02SAdrian Chadd 1112f4a3eb02SAdrian Chadd return (error); 1113e83ce340SAdrian Chadd } 1114e83ce340SAdrian Chadd 1115e83ce340SAdrian Chadd /** 1116e83ce340SAdrian Chadd * If required by this device, revert any GPIO/pin configuration applied 1117e83ce340SAdrian Chadd * to allow SPROM access. 1118e83ce340SAdrian Chadd * 1119e83ce340SAdrian Chadd * @param sc chipc driver state. 1120e83ce340SAdrian Chadd */ 1121f4a3eb02SAdrian Chadd static void 1122f4a3eb02SAdrian Chadd chipc_disable_sprom_pins(device_t dev) 1123e83ce340SAdrian Chadd { 1124f4a3eb02SAdrian Chadd struct chipc_softc *sc; 1125e83ce340SAdrian Chadd uint32_t cctrl; 1126e83ce340SAdrian Chadd 1127f4a3eb02SAdrian Chadd sc = device_get_softc(dev); 1128e83ce340SAdrian Chadd 1129e83ce340SAdrian Chadd /* Nothing to do? */ 1130e83ce340SAdrian Chadd if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1131f4a3eb02SAdrian Chadd return; 1132f4a3eb02SAdrian Chadd 1133f4a3eb02SAdrian Chadd CHIPC_LOCK(sc); 1134f4a3eb02SAdrian Chadd 1135f4a3eb02SAdrian Chadd /* Check reference count, skip disable if in-use. */ 1136f4a3eb02SAdrian Chadd KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease")); 1137f4a3eb02SAdrian Chadd sc->sprom_refcnt--; 1138f4a3eb02SAdrian Chadd if (sc->sprom_refcnt > 0) 1139f4a3eb02SAdrian Chadd goto finished; 1140e83ce340SAdrian Chadd 1141e83ce340SAdrian Chadd cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1142e83ce340SAdrian Chadd 1143e83ce340SAdrian Chadd /* 4331 devices */ 1144e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1145e83ce340SAdrian Chadd cctrl |= CHIPC_CCTRL4331_EXTPA_EN; 1146e83ce340SAdrian Chadd 1147e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1148e83ce340SAdrian Chadd cctrl |= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1149e83ce340SAdrian Chadd 1150e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1151e83ce340SAdrian Chadd cctrl |= CHIPC_CCTRL4331_EXTPA_EN2; 1152e83ce340SAdrian Chadd 1153e83ce340SAdrian Chadd bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1154f4a3eb02SAdrian Chadd goto finished; 1155e83ce340SAdrian Chadd } 1156e83ce340SAdrian Chadd 1157e83ce340SAdrian Chadd /* 4360 devices */ 1158e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1159e83ce340SAdrian Chadd /* Unimplemented */ 1160e83ce340SAdrian Chadd } 1161e83ce340SAdrian Chadd 1162f4a3eb02SAdrian Chadd finished: 1163f4a3eb02SAdrian Chadd CHIPC_UNLOCK(sc); 1164e83ce340SAdrian Chadd } 1165e83ce340SAdrian Chadd 1166e83ce340SAdrian Chadd static bhnd_nvram_src_t 1167e83ce340SAdrian Chadd chipc_nvram_src(device_t dev) 1168e83ce340SAdrian Chadd { 1169e83ce340SAdrian Chadd struct chipc_softc *sc = device_get_softc(dev); 1170e83ce340SAdrian Chadd return (sc->nvram_src); 1171e83ce340SAdrian Chadd } 1172e83ce340SAdrian Chadd 11738ef24a0dSAdrian Chadd static void 11748ef24a0dSAdrian Chadd chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask) 11758ef24a0dSAdrian Chadd { 11768ef24a0dSAdrian Chadd struct chipc_softc *sc; 11778ef24a0dSAdrian Chadd uint32_t cctrl; 11788ef24a0dSAdrian Chadd 11798ef24a0dSAdrian Chadd sc = device_get_softc(dev); 11808ef24a0dSAdrian Chadd 11818ef24a0dSAdrian Chadd CHIPC_LOCK(sc); 11828ef24a0dSAdrian Chadd 11838ef24a0dSAdrian Chadd cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 11848ef24a0dSAdrian Chadd cctrl = (cctrl & ~mask) | (value | mask); 11858ef24a0dSAdrian Chadd bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 11868ef24a0dSAdrian Chadd 11878ef24a0dSAdrian Chadd CHIPC_UNLOCK(sc); 11888ef24a0dSAdrian Chadd } 11898ef24a0dSAdrian Chadd 11904ad7e9b0SAdrian Chadd static device_method_t chipc_methods[] = { 11914ad7e9b0SAdrian Chadd /* Device interface */ 11924ad7e9b0SAdrian Chadd DEVMETHOD(device_probe, chipc_probe), 11934ad7e9b0SAdrian Chadd DEVMETHOD(device_attach, chipc_attach), 11944ad7e9b0SAdrian Chadd DEVMETHOD(device_detach, chipc_detach), 11954ad7e9b0SAdrian Chadd DEVMETHOD(device_suspend, chipc_suspend), 11964ad7e9b0SAdrian Chadd DEVMETHOD(device_resume, chipc_resume), 11974ad7e9b0SAdrian Chadd 1198f4a3eb02SAdrian Chadd /* Bus interface */ 1199f4a3eb02SAdrian Chadd DEVMETHOD(bus_probe_nomatch, chipc_probe_nomatch), 1200f4a3eb02SAdrian Chadd DEVMETHOD(bus_print_child, chipc_print_child), 1201f4a3eb02SAdrian Chadd DEVMETHOD(bus_child_pnpinfo_str, chipc_child_pnpinfo_str), 1202f4a3eb02SAdrian Chadd DEVMETHOD(bus_child_location_str, chipc_child_location_str), 1203f4a3eb02SAdrian Chadd 1204f4a3eb02SAdrian Chadd DEVMETHOD(bus_add_child, chipc_add_child), 1205f4a3eb02SAdrian Chadd DEVMETHOD(bus_child_deleted, chipc_child_deleted), 1206f4a3eb02SAdrian Chadd 1207f4a3eb02SAdrian Chadd DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 1208f4a3eb02SAdrian Chadd DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 1209f4a3eb02SAdrian Chadd DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource), 1210f4a3eb02SAdrian Chadd DEVMETHOD(bus_alloc_resource, chipc_alloc_resource), 1211f4a3eb02SAdrian Chadd DEVMETHOD(bus_release_resource, chipc_release_resource), 1212f4a3eb02SAdrian Chadd DEVMETHOD(bus_adjust_resource, chipc_adjust_resource), 1213f4a3eb02SAdrian Chadd DEVMETHOD(bus_activate_resource, chipc_activate_resource), 1214f4a3eb02SAdrian Chadd DEVMETHOD(bus_deactivate_resource, chipc_deactivate_resource), 1215f4a3eb02SAdrian Chadd DEVMETHOD(bus_get_resource_list, chipc_get_resource_list), 1216f4a3eb02SAdrian Chadd 1217f4a3eb02SAdrian Chadd DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1218f4a3eb02SAdrian Chadd DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1219f4a3eb02SAdrian Chadd DEVMETHOD(bus_config_intr, bus_generic_config_intr), 1220f4a3eb02SAdrian Chadd DEVMETHOD(bus_bind_intr, bus_generic_bind_intr), 1221f4a3eb02SAdrian Chadd DEVMETHOD(bus_describe_intr, bus_generic_describe_intr), 1222f4a3eb02SAdrian Chadd 1223f4a3eb02SAdrian Chadd /* BHND bus inteface */ 1224f4a3eb02SAdrian Chadd DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource), 1225f4a3eb02SAdrian Chadd 12264ad7e9b0SAdrian Chadd /* ChipCommon interface */ 12274ad7e9b0SAdrian Chadd DEVMETHOD(bhnd_chipc_nvram_src, chipc_nvram_src), 12288ef24a0dSAdrian Chadd DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl), 1229f4a3eb02SAdrian Chadd DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom_pins), 1230f4a3eb02SAdrian Chadd DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom_pins), 1231e83ce340SAdrian Chadd 12324ad7e9b0SAdrian Chadd DEVMETHOD_END 12334ad7e9b0SAdrian Chadd }; 12344ad7e9b0SAdrian Chadd 12354ad7e9b0SAdrian Chadd DEFINE_CLASS_0(bhnd_chipc, chipc_driver, chipc_methods, sizeof(struct chipc_softc)); 12364ad7e9b0SAdrian Chadd DRIVER_MODULE(bhnd_chipc, bhnd, chipc_driver, bhnd_chipc_devclass, 0, 0); 123796546b75SAdrian Chadd MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1); 12384ad7e9b0SAdrian Chadd MODULE_VERSION(bhnd_chipc, 1); 1239