14ad7e9b0SAdrian Chadd /*- 2f4a3eb02SAdrian Chadd * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 3f4a3eb02SAdrian Chadd * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com> 44ad7e9b0SAdrian Chadd * All rights reserved. 54ad7e9b0SAdrian Chadd * 64ad7e9b0SAdrian Chadd * Redistribution and use in source and binary forms, with or without 74ad7e9b0SAdrian Chadd * modification, are permitted provided that the following conditions 84ad7e9b0SAdrian Chadd * are met: 94ad7e9b0SAdrian Chadd * 1. Redistributions of source code must retain the above copyright 104ad7e9b0SAdrian Chadd * notice, this list of conditions and the following disclaimer, 114ad7e9b0SAdrian Chadd * without modification. 124ad7e9b0SAdrian Chadd * 2. Redistributions in binary form must reproduce at minimum a disclaimer 134ad7e9b0SAdrian Chadd * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 144ad7e9b0SAdrian Chadd * redistribution must be conditioned upon including a substantially 154ad7e9b0SAdrian Chadd * similar Disclaimer requirement for further binary redistribution. 164ad7e9b0SAdrian Chadd * 174ad7e9b0SAdrian Chadd * NO WARRANTY 184ad7e9b0SAdrian Chadd * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 194ad7e9b0SAdrian Chadd * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 204ad7e9b0SAdrian Chadd * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 214ad7e9b0SAdrian Chadd * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 224ad7e9b0SAdrian Chadd * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 234ad7e9b0SAdrian Chadd * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 244ad7e9b0SAdrian Chadd * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 254ad7e9b0SAdrian Chadd * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 264ad7e9b0SAdrian Chadd * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 274ad7e9b0SAdrian Chadd * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 284ad7e9b0SAdrian Chadd * THE POSSIBILITY OF SUCH DAMAGES. 294ad7e9b0SAdrian Chadd */ 304ad7e9b0SAdrian Chadd 314ad7e9b0SAdrian Chadd #include <sys/cdefs.h> 324ad7e9b0SAdrian Chadd __FBSDID("$FreeBSD$"); 334ad7e9b0SAdrian Chadd 344ad7e9b0SAdrian Chadd /* 354ad7e9b0SAdrian Chadd * Broadcom ChipCommon driver. 364ad7e9b0SAdrian Chadd * 374ad7e9b0SAdrian Chadd * With the exception of some very early chipsets, the ChipCommon core 384ad7e9b0SAdrian Chadd * has been included in all HND SoCs and chipsets based on the siba(4) 394ad7e9b0SAdrian Chadd * and bcma(4) interconnects, providing a common interface to chipset 400c91e892SLandon J. Fuller * identification, bus enumeration, UARTs, clocks, watchdog interrupts, 410c91e892SLandon J. Fuller * GPIO, flash, etc. 424ad7e9b0SAdrian Chadd */ 434ad7e9b0SAdrian Chadd 444ad7e9b0SAdrian Chadd #include <sys/param.h> 454ad7e9b0SAdrian Chadd #include <sys/kernel.h> 46f4a3eb02SAdrian Chadd #include <sys/lock.h> 474ad7e9b0SAdrian Chadd #include <sys/bus.h> 48e129bcd6SLandon J. Fuller #include <sys/rman.h> 49f4a3eb02SAdrian Chadd #include <sys/malloc.h> 504ad7e9b0SAdrian Chadd #include <sys/module.h> 51f4a3eb02SAdrian Chadd #include <sys/mutex.h> 524ad7e9b0SAdrian Chadd #include <sys/systm.h> 534ad7e9b0SAdrian Chadd 544ad7e9b0SAdrian Chadd #include <machine/bus.h> 554ad7e9b0SAdrian Chadd #include <machine/resource.h> 564ad7e9b0SAdrian Chadd 574ad7e9b0SAdrian Chadd #include <dev/bhnd/bhnd.h> 58f4a3eb02SAdrian Chadd #include <dev/bhnd/bhndvar.h> 59e83ce340SAdrian Chadd 604ad7e9b0SAdrian Chadd #include "chipcreg.h" 614ad7e9b0SAdrian Chadd #include "chipcvar.h" 620c91e892SLandon J. Fuller 63f4a3eb02SAdrian Chadd #include "chipc_private.h" 644ad7e9b0SAdrian Chadd 654ad7e9b0SAdrian Chadd devclass_t bhnd_chipc_devclass; /**< bhnd(4) chipcommon device class */ 664ad7e9b0SAdrian Chadd 6736e4410aSAdrian Chadd static struct bhnd_device_quirk chipc_quirks[]; 6836e4410aSAdrian Chadd 694ad7e9b0SAdrian Chadd /* Supported device identifiers */ 7036e4410aSAdrian Chadd static const struct bhnd_device chipc_devices[] = { 71b0b9c854SLandon J. Fuller BHND_DEVICE(BCM, CC, NULL, chipc_quirks), 7236e4410aSAdrian Chadd BHND_DEVICE_END 734ad7e9b0SAdrian Chadd }; 744ad7e9b0SAdrian Chadd 7536e4410aSAdrian Chadd 764ad7e9b0SAdrian Chadd /* Device quirks table */ 774ad7e9b0SAdrian Chadd static struct bhnd_device_quirk chipc_quirks[] = { 7856a4cdd1SLandon J. Fuller /* HND OTP controller revisions */ 7956a4cdd1SLandon J. Fuller BHND_CORE_QUIRK (HWREV_EQ (12), CHIPC_QUIRK_OTP_HND), /* (?) */ 8056a4cdd1SLandon J. Fuller BHND_CORE_QUIRK (HWREV_EQ (17), CHIPC_QUIRK_OTP_HND), /* BCM4311 */ 8156a4cdd1SLandon J. Fuller BHND_CORE_QUIRK (HWREV_EQ (22), CHIPC_QUIRK_OTP_HND), /* BCM4312 */ 8256a4cdd1SLandon J. Fuller 8356a4cdd1SLandon J. Fuller /* IPX OTP controller revisions */ 8456a4cdd1SLandon J. Fuller BHND_CORE_QUIRK (HWREV_EQ (21), CHIPC_QUIRK_OTP_IPX), 8556a4cdd1SLandon J. Fuller BHND_CORE_QUIRK (HWREV_GTE(23), CHIPC_QUIRK_OTP_IPX), 8656a4cdd1SLandon J. Fuller 875ad9ac03SAdrian Chadd BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM), 885ad9ac03SAdrian Chadd BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT), 8956a4cdd1SLandon J. Fuller BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPL_SIZE), 905ad9ac03SAdrian Chadd 915ad9ac03SAdrian Chadd /* 4706 variant quirks */ 925ad9ac03SAdrian Chadd BHND_CORE_QUIRK (HWREV_EQ (38), CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */ 935ad9ac03SAdrian Chadd BHND_CHIP_QUIRK (4706, HWREV_ANY, CHIPC_QUIRK_4706_NFLASH), 945ad9ac03SAdrian Chadd 955ad9ac03SAdrian Chadd /* 4331 quirks*/ 965ad9ac03SAdrian Chadd BHND_CHIP_QUIRK (4331, HWREV_ANY, CHIPC_QUIRK_4331_EXTPA_MUX_SPROM), 975ad9ac03SAdrian Chadd BHND_PKG_QUIRK (4331, TN, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 985ad9ac03SAdrian Chadd BHND_PKG_QUIRK (4331, TNA0, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 995ad9ac03SAdrian Chadd BHND_PKG_QUIRK (4331, TT, CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM), 1005ad9ac03SAdrian Chadd 1015ad9ac03SAdrian Chadd /* 4360 quirks */ 1025ad9ac03SAdrian Chadd BHND_CHIP_QUIRK (4352, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 1035ad9ac03SAdrian Chadd BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 1045ad9ac03SAdrian Chadd BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 1055ad9ac03SAdrian Chadd BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 106f4a3eb02SAdrian Chadd 10736e4410aSAdrian Chadd BHND_DEVICE_QUIRK_END 1084ad7e9b0SAdrian Chadd }; 1094ad7e9b0SAdrian Chadd 1100c91e892SLandon J. Fuller // FIXME: IRQ shouldn't be hard-coded 1110c91e892SLandon J. Fuller #define CHIPC_MIPS_IRQ 2 112785df0cbSAdrian Chadd 1130c91e892SLandon J. Fuller static int chipc_add_children(struct chipc_softc *sc); 114f4a3eb02SAdrian Chadd 11556a4cdd1SLandon J. Fuller static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc, 11656a4cdd1SLandon J. Fuller struct chipc_caps *caps); 117f4a3eb02SAdrian Chadd static int chipc_read_caps(struct chipc_softc *sc, 118f4a3eb02SAdrian Chadd struct chipc_caps *caps); 119f4a3eb02SAdrian Chadd 120f90f4b65SLandon J. Fuller static bool chipc_should_enable_muxed_sprom( 121f4a3eb02SAdrian Chadd struct chipc_softc *sc); 122f90f4b65SLandon J. Fuller static int chipc_enable_otp_power(struct chipc_softc *sc); 123f90f4b65SLandon J. Fuller static void chipc_disable_otp_power(struct chipc_softc *sc); 124f90f4b65SLandon J. Fuller static int chipc_enable_sprom_pins(struct chipc_softc *sc); 125f90f4b65SLandon J. Fuller static void chipc_disable_sprom_pins(struct chipc_softc *sc); 126f4a3eb02SAdrian Chadd 127f90f4b65SLandon J. Fuller static int chipc_try_activate_resource(struct chipc_softc *sc, 128f90f4b65SLandon J. Fuller device_t child, int type, int rid, 129f90f4b65SLandon J. Fuller struct resource *r, bool req_direct); 1300c91e892SLandon J. Fuller 131f4a3eb02SAdrian Chadd static int chipc_init_rman(struct chipc_softc *sc); 132f4a3eb02SAdrian Chadd static void chipc_free_rman(struct chipc_softc *sc); 133f90f4b65SLandon J. Fuller static struct rman *chipc_get_rman(struct chipc_softc *sc, int type); 134f4a3eb02SAdrian Chadd 1354ad7e9b0SAdrian Chadd /* quirk and capability flag convenience macros */ 1364ad7e9b0SAdrian Chadd #define CHIPC_QUIRK(_sc, _name) \ 1374ad7e9b0SAdrian Chadd ((_sc)->quirks & CHIPC_QUIRK_ ## _name) 1384ad7e9b0SAdrian Chadd 1394ad7e9b0SAdrian Chadd #define CHIPC_CAP(_sc, _name) \ 140f4a3eb02SAdrian Chadd ((_sc)->caps._name) 1414ad7e9b0SAdrian Chadd 1424ad7e9b0SAdrian Chadd #define CHIPC_ASSERT_QUIRK(_sc, name) \ 1434ad7e9b0SAdrian Chadd KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set")) 1444ad7e9b0SAdrian Chadd 1454ad7e9b0SAdrian Chadd #define CHIPC_ASSERT_CAP(_sc, name) \ 1464ad7e9b0SAdrian Chadd KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set")) 1474ad7e9b0SAdrian Chadd 1484ad7e9b0SAdrian Chadd static int 1494ad7e9b0SAdrian Chadd chipc_probe(device_t dev) 1504ad7e9b0SAdrian Chadd { 15136e4410aSAdrian Chadd const struct bhnd_device *id; 1524ad7e9b0SAdrian Chadd 15336e4410aSAdrian Chadd id = bhnd_device_lookup(dev, chipc_devices, sizeof(chipc_devices[0])); 15436e4410aSAdrian Chadd if (id == NULL) 1554ad7e9b0SAdrian Chadd return (ENXIO); 15636e4410aSAdrian Chadd 15736e4410aSAdrian Chadd bhnd_set_default_core_desc(dev); 15836e4410aSAdrian Chadd return (BUS_PROBE_DEFAULT); 1594ad7e9b0SAdrian Chadd } 1604ad7e9b0SAdrian Chadd 1614ad7e9b0SAdrian Chadd static int 1624ad7e9b0SAdrian Chadd chipc_attach(device_t dev) 1634ad7e9b0SAdrian Chadd { 1644ad7e9b0SAdrian Chadd struct chipc_softc *sc; 1654ad7e9b0SAdrian Chadd int error; 1664ad7e9b0SAdrian Chadd 1674ad7e9b0SAdrian Chadd sc = device_get_softc(dev); 1684ad7e9b0SAdrian Chadd sc->dev = dev; 16936e4410aSAdrian Chadd sc->quirks = bhnd_device_quirks(dev, chipc_devices, 17036e4410aSAdrian Chadd sizeof(chipc_devices[0])); 171f4a3eb02SAdrian Chadd sc->sprom_refcnt = 0; 172e83ce340SAdrian Chadd 173e83ce340SAdrian Chadd CHIPC_LOCK_INIT(sc); 174f4a3eb02SAdrian Chadd STAILQ_INIT(&sc->mem_regions); 1754ad7e9b0SAdrian Chadd 176f4a3eb02SAdrian Chadd /* Set up resource management */ 177f4a3eb02SAdrian Chadd if ((error = chipc_init_rman(sc))) { 178f4a3eb02SAdrian Chadd device_printf(sc->dev, 179f4a3eb02SAdrian Chadd "failed to initialize chipc resource state: %d\n", error); 180f4a3eb02SAdrian Chadd goto failed; 181f4a3eb02SAdrian Chadd } 1824ad7e9b0SAdrian Chadd 1830c91e892SLandon J. Fuller /* Allocate the region containing the chipc register block */ 184f4a3eb02SAdrian Chadd if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) { 185f4a3eb02SAdrian Chadd error = ENXIO; 186f4a3eb02SAdrian Chadd goto failed; 187f4a3eb02SAdrian Chadd } 188f4a3eb02SAdrian Chadd 189f4a3eb02SAdrian Chadd error = chipc_retain_region(sc, sc->core_region, 190f4a3eb02SAdrian Chadd RF_ALLOCATED|RF_ACTIVE); 191f4a3eb02SAdrian Chadd if (error) { 192f4a3eb02SAdrian Chadd sc->core_region = NULL; 193f4a3eb02SAdrian Chadd goto failed; 1940c91e892SLandon J. Fuller } 1950c91e892SLandon J. Fuller 1960c91e892SLandon J. Fuller /* Save a direct reference to our chipc registers */ 197f4a3eb02SAdrian Chadd sc->core = sc->core_region->cr_res; 1984ad7e9b0SAdrian Chadd 199f4a3eb02SAdrian Chadd /* Fetch and parse capability register(s) */ 200f4a3eb02SAdrian Chadd if ((error = chipc_read_caps(sc, &sc->caps))) 201f4a3eb02SAdrian Chadd goto failed; 2024ad7e9b0SAdrian Chadd 203f4a3eb02SAdrian Chadd if (bootverbose) 204f4a3eb02SAdrian Chadd chipc_print_caps(sc->dev, &sc->caps); 205f4a3eb02SAdrian Chadd 2060c91e892SLandon J. Fuller /* Attach all supported child devices */ 2070c91e892SLandon J. Fuller if ((error = chipc_add_children(sc))) 2080c91e892SLandon J. Fuller goto failed; 2090c91e892SLandon J. Fuller 210f4a3eb02SAdrian Chadd if ((error = bus_generic_attach(dev))) 211f4a3eb02SAdrian Chadd goto failed; 2124ad7e9b0SAdrian Chadd 2134ad7e9b0SAdrian Chadd return (0); 2144ad7e9b0SAdrian Chadd 215f4a3eb02SAdrian Chadd failed: 2167d1fb1aaSLandon J. Fuller device_delete_children(sc->dev); 2177d1fb1aaSLandon J. Fuller 218f4a3eb02SAdrian Chadd if (sc->core_region != NULL) { 219f4a3eb02SAdrian Chadd chipc_release_region(sc, sc->core_region, 220f4a3eb02SAdrian Chadd RF_ALLOCATED|RF_ACTIVE); 221f4a3eb02SAdrian Chadd } 222f4a3eb02SAdrian Chadd 223f4a3eb02SAdrian Chadd chipc_free_rman(sc); 224e83ce340SAdrian Chadd CHIPC_LOCK_DESTROY(sc); 2254ad7e9b0SAdrian Chadd return (error); 2264ad7e9b0SAdrian Chadd } 2274ad7e9b0SAdrian Chadd 2284ad7e9b0SAdrian Chadd static int 2294ad7e9b0SAdrian Chadd chipc_detach(device_t dev) 2304ad7e9b0SAdrian Chadd { 2314ad7e9b0SAdrian Chadd struct chipc_softc *sc; 232f4a3eb02SAdrian Chadd int error; 2334ad7e9b0SAdrian Chadd 2344ad7e9b0SAdrian Chadd sc = device_get_softc(dev); 235f4a3eb02SAdrian Chadd 236f4a3eb02SAdrian Chadd if ((error = bus_generic_detach(dev))) 237f4a3eb02SAdrian Chadd return (error); 238f4a3eb02SAdrian Chadd 239f4a3eb02SAdrian Chadd chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE); 240f4a3eb02SAdrian Chadd chipc_free_rman(sc); 241e83ce340SAdrian Chadd 242e83ce340SAdrian Chadd CHIPC_LOCK_DESTROY(sc); 2434ad7e9b0SAdrian Chadd 2444ad7e9b0SAdrian Chadd return (0); 2454ad7e9b0SAdrian Chadd } 2464ad7e9b0SAdrian Chadd 2470c91e892SLandon J. Fuller static int 2480c91e892SLandon J. Fuller chipc_add_children(struct chipc_softc *sc) 2490c91e892SLandon J. Fuller { 2500c91e892SLandon J. Fuller device_t child; 2510c91e892SLandon J. Fuller const char *flash_bus; 2520c91e892SLandon J. Fuller int error; 2530c91e892SLandon J. Fuller 2540c91e892SLandon J. Fuller /* SPROM/OTP */ 2550c91e892SLandon J. Fuller if (sc->caps.nvram_src == BHND_NVRAM_SRC_SPROM || 2560c91e892SLandon J. Fuller sc->caps.nvram_src == BHND_NVRAM_SRC_OTP) 2570c91e892SLandon J. Fuller { 2580c91e892SLandon J. Fuller child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_nvram", -1); 2590c91e892SLandon J. Fuller if (child == NULL) { 2600c91e892SLandon J. Fuller device_printf(sc->dev, "failed to add nvram device\n"); 2610c91e892SLandon J. Fuller return (ENXIO); 2620c91e892SLandon J. Fuller } 2630c91e892SLandon J. Fuller 2640c91e892SLandon J. Fuller /* Both OTP and external SPROM are mapped at CHIPC_SPROM_OTP */ 2650c91e892SLandon J. Fuller error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, 2660c91e892SLandon J. Fuller CHIPC_SPROM_OTP, CHIPC_SPROM_OTP_SIZE, 0, 0); 2670c91e892SLandon J. Fuller if (error) 2680c91e892SLandon J. Fuller return (error); 2690c91e892SLandon J. Fuller } 2700c91e892SLandon J. Fuller 2710c91e892SLandon J. Fuller /* 272f90f4b65SLandon J. Fuller * PMU/PWR_CTRL 2730c91e892SLandon J. Fuller * 274f90f4b65SLandon J. Fuller * On AOB ("Always on Bus") devices, the PMU core (if it exists) is 275f90f4b65SLandon J. Fuller * attached directly to the bhnd(4) bus -- not chipc. 2760c91e892SLandon J. Fuller */ 277f90f4b65SLandon J. Fuller if (sc->caps.pwr_ctrl || (sc->caps.pmu && !sc->caps.aob)) { 2780c91e892SLandon J. Fuller child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pmu", -1); 2790c91e892SLandon J. Fuller if (child == NULL) { 2800c91e892SLandon J. Fuller device_printf(sc->dev, "failed to add pmu\n"); 2810c91e892SLandon J. Fuller return (ENXIO); 2820c91e892SLandon J. Fuller } 2830c91e892SLandon J. Fuller } 2840c91e892SLandon J. Fuller 2850c91e892SLandon J. Fuller /* All remaining devices are SoC-only */ 2860c91e892SLandon J. Fuller if (bhnd_get_attach_type(sc->dev) != BHND_ATTACH_NATIVE) 2870c91e892SLandon J. Fuller return (0); 2880c91e892SLandon J. Fuller 2890c91e892SLandon J. Fuller /* UARTs */ 2900c91e892SLandon J. Fuller for (u_int i = 0; i < min(sc->caps.num_uarts, CHIPC_UART_MAX); i++) { 2910c91e892SLandon J. Fuller child = BUS_ADD_CHILD(sc->dev, 0, "uart", -1); 2920c91e892SLandon J. Fuller if (child == NULL) { 2930c91e892SLandon J. Fuller device_printf(sc->dev, "failed to add uart%u\n", i); 2940c91e892SLandon J. Fuller return (ENXIO); 2950c91e892SLandon J. Fuller } 2960c91e892SLandon J. Fuller 2970c91e892SLandon J. Fuller /* Shared IRQ */ 2980c91e892SLandon J. Fuller error = bus_set_resource(child, SYS_RES_IRQ, 0, CHIPC_MIPS_IRQ, 2990c91e892SLandon J. Fuller 1); 3000c91e892SLandon J. Fuller if (error) { 3010c91e892SLandon J. Fuller device_printf(sc->dev, "failed to set uart%u irq %u\n", 3020c91e892SLandon J. Fuller i, CHIPC_MIPS_IRQ); 3030c91e892SLandon J. Fuller return (error); 3040c91e892SLandon J. Fuller } 3050c91e892SLandon J. Fuller 3060c91e892SLandon J. Fuller /* UART registers are mapped sequentially */ 3070c91e892SLandon J. Fuller error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, 3080c91e892SLandon J. Fuller CHIPC_UART(i), CHIPC_UART_SIZE, 0, 0); 3090c91e892SLandon J. Fuller if (error) 3100c91e892SLandon J. Fuller return (error); 3110c91e892SLandon J. Fuller } 3120c91e892SLandon J. Fuller 3130c91e892SLandon J. Fuller /* Flash */ 3140c91e892SLandon J. Fuller flash_bus = chipc_flash_bus_name(sc->caps.flash_type); 3150c91e892SLandon J. Fuller if (flash_bus != NULL) { 3160c91e892SLandon J. Fuller child = BUS_ADD_CHILD(sc->dev, 0, flash_bus, -1); 3170c91e892SLandon J. Fuller if (child == NULL) { 3180c91e892SLandon J. Fuller device_printf(sc->dev, "failed to add %s device\n", 3190c91e892SLandon J. Fuller flash_bus); 3200c91e892SLandon J. Fuller return (ENXIO); 3210c91e892SLandon J. Fuller } 3220c91e892SLandon J. Fuller 3230c91e892SLandon J. Fuller /* flash memory mapping */ 3240c91e892SLandon J. Fuller error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, 3250c91e892SLandon J. Fuller 0, RM_MAX_END, 1, 1); 3260c91e892SLandon J. Fuller if (error) 3270c91e892SLandon J. Fuller return (error); 3280c91e892SLandon J. Fuller 3290c91e892SLandon J. Fuller /* flashctrl registers */ 3300c91e892SLandon J. Fuller error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 1, 3310c91e892SLandon J. Fuller CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0, 0); 3320c91e892SLandon J. Fuller if (error) 3330c91e892SLandon J. Fuller return (error); 3340c91e892SLandon J. Fuller } 3350c91e892SLandon J. Fuller 3360c91e892SLandon J. Fuller return (0); 3370c91e892SLandon J. Fuller } 3380c91e892SLandon J. Fuller 33956a4cdd1SLandon J. Fuller /** 34056a4cdd1SLandon J. Fuller * Determine the NVRAM data source for this device. 34156a4cdd1SLandon J. Fuller * 34256a4cdd1SLandon J. Fuller * The SPROM, OTP, and flash capability flags must be fully populated in 34356a4cdd1SLandon J. Fuller * @p caps. 34456a4cdd1SLandon J. Fuller * 34556a4cdd1SLandon J. Fuller * @param sc chipc driver state. 34656a4cdd1SLandon J. Fuller * @param caps capability flags to be used to derive NVRAM configuration. 34756a4cdd1SLandon J. Fuller */ 34856a4cdd1SLandon J. Fuller static bhnd_nvram_src 34956a4cdd1SLandon J. Fuller chipc_find_nvram_src(struct chipc_softc *sc, struct chipc_caps *caps) 35056a4cdd1SLandon J. Fuller { 35156a4cdd1SLandon J. Fuller uint32_t otp_st, srom_ctrl; 35256a4cdd1SLandon J. Fuller 35356a4cdd1SLandon J. Fuller /* 35456a4cdd1SLandon J. Fuller * We check for hardware presence in order of precedence. For example, 35556a4cdd1SLandon J. Fuller * SPROM is is always used in preference to internal OTP if found. 35656a4cdd1SLandon J. Fuller */ 3571728aef2SLandon J. Fuller if (CHIPC_QUIRK(sc, SUPPORTS_SPROM) && caps->sprom) { 35856a4cdd1SLandon J. Fuller srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL); 35956a4cdd1SLandon J. Fuller if (srom_ctrl & CHIPC_SRC_PRESENT) 36056a4cdd1SLandon J. Fuller return (BHND_NVRAM_SRC_SPROM); 36156a4cdd1SLandon J. Fuller } 36256a4cdd1SLandon J. Fuller 36356a4cdd1SLandon J. Fuller /* Check for programmed OTP H/W subregion (contains SROM data) */ 36456a4cdd1SLandon J. Fuller if (CHIPC_QUIRK(sc, SUPPORTS_OTP) && caps->otp_size > 0) { 36556a4cdd1SLandon J. Fuller /* TODO: need access to HND-OTP device */ 36656a4cdd1SLandon J. Fuller if (!CHIPC_QUIRK(sc, OTP_HND)) { 36756a4cdd1SLandon J. Fuller device_printf(sc->dev, 36856a4cdd1SLandon J. Fuller "NVRAM unavailable: unsupported OTP controller.\n"); 36956a4cdd1SLandon J. Fuller return (BHND_NVRAM_SRC_UNKNOWN); 37056a4cdd1SLandon J. Fuller } 37156a4cdd1SLandon J. Fuller 37256a4cdd1SLandon J. Fuller otp_st = bhnd_bus_read_4(sc->core, CHIPC_OTPST); 37356a4cdd1SLandon J. Fuller if (otp_st & CHIPC_OTPS_GUP_HW) 37456a4cdd1SLandon J. Fuller return (BHND_NVRAM_SRC_OTP); 37556a4cdd1SLandon J. Fuller } 37656a4cdd1SLandon J. Fuller 37756a4cdd1SLandon J. Fuller /* Check for flash */ 37856a4cdd1SLandon J. Fuller if (caps->flash_type != CHIPC_FLASH_NONE) 37956a4cdd1SLandon J. Fuller return (BHND_NVRAM_SRC_FLASH); 38056a4cdd1SLandon J. Fuller 38156a4cdd1SLandon J. Fuller /* No NVRAM hardware capability declared */ 38256a4cdd1SLandon J. Fuller return (BHND_NVRAM_SRC_UNKNOWN); 38356a4cdd1SLandon J. Fuller } 38456a4cdd1SLandon J. Fuller 385f4a3eb02SAdrian Chadd /* Read and parse chipc capabilities */ 3864ad7e9b0SAdrian Chadd static int 387f4a3eb02SAdrian Chadd chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps) 3884ad7e9b0SAdrian Chadd { 389f4a3eb02SAdrian Chadd uint32_t cap_reg; 390f4a3eb02SAdrian Chadd uint32_t cap_ext_reg; 391f4a3eb02SAdrian Chadd uint32_t regval; 392f4a3eb02SAdrian Chadd 393f4a3eb02SAdrian Chadd /* Fetch cap registers */ 394f4a3eb02SAdrian Chadd cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES); 395f4a3eb02SAdrian Chadd cap_ext_reg = 0; 396f4a3eb02SAdrian Chadd if (CHIPC_QUIRK(sc, SUPPORTS_CAP_EXT)) 397f4a3eb02SAdrian Chadd cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT); 398f4a3eb02SAdrian Chadd 399f4a3eb02SAdrian Chadd /* Extract values */ 400f4a3eb02SAdrian Chadd caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART); 401f4a3eb02SAdrian Chadd caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB); 402f4a3eb02SAdrian Chadd caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO); 403f4a3eb02SAdrian Chadd caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL); 404f4a3eb02SAdrian Chadd 405f4a3eb02SAdrian Chadd caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS); 406f90f4b65SLandon J. Fuller caps->pwr_ctrl = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL); 407f4a3eb02SAdrian Chadd caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP); 408f4a3eb02SAdrian Chadd 409f4a3eb02SAdrian Chadd caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL); 410f4a3eb02SAdrian Chadd caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64); 411f4a3eb02SAdrian Chadd caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM); 412f4a3eb02SAdrian Chadd caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU); 413f4a3eb02SAdrian Chadd caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI); 414f4a3eb02SAdrian Chadd caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM); 415f4a3eb02SAdrian Chadd caps->otp_size = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_OTP_SIZE); 416f4a3eb02SAdrian Chadd 417f4a3eb02SAdrian Chadd caps->seci = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_SECI); 418f4a3eb02SAdrian Chadd caps->gsio = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_GSIO); 419f4a3eb02SAdrian Chadd caps->aob = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_AOB); 420f4a3eb02SAdrian Chadd 421f4a3eb02SAdrian Chadd /* Fetch OTP size for later IPX controller revisions */ 42256a4cdd1SLandon J. Fuller if (CHIPC_QUIRK(sc, IPX_OTPL_SIZE)) { 423f4a3eb02SAdrian Chadd regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 424f4a3eb02SAdrian Chadd caps->otp_size = CHIPC_GET_BITS(regval, CHIPC_OTPL_SIZE); 4254ad7e9b0SAdrian Chadd } 4264ad7e9b0SAdrian Chadd 4275ad9ac03SAdrian Chadd /* Determine flash type and parameters */ 428f4a3eb02SAdrian Chadd caps->cfi_width = 0; 429f4a3eb02SAdrian Chadd switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) { 430f4a3eb02SAdrian Chadd case CHIPC_CAP_SFLASH_ST: 431f4a3eb02SAdrian Chadd caps->flash_type = CHIPC_SFLASH_ST; 432f4a3eb02SAdrian Chadd break; 433f4a3eb02SAdrian Chadd case CHIPC_CAP_SFLASH_AT: 434f4a3eb02SAdrian Chadd caps->flash_type = CHIPC_SFLASH_AT; 435f4a3eb02SAdrian Chadd break; 436f4a3eb02SAdrian Chadd case CHIPC_CAP_NFLASH: 4370c91e892SLandon J. Fuller /* unimplemented */ 438f4a3eb02SAdrian Chadd caps->flash_type = CHIPC_NFLASH; 439f4a3eb02SAdrian Chadd break; 440f4a3eb02SAdrian Chadd case CHIPC_CAP_PFLASH: 441f4a3eb02SAdrian Chadd caps->flash_type = CHIPC_PFLASH_CFI; 442f4a3eb02SAdrian Chadd 443f4a3eb02SAdrian Chadd /* determine cfi width */ 444f4a3eb02SAdrian Chadd regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG); 445f4a3eb02SAdrian Chadd if (CHIPC_GET_FLAG(regval, CHIPC_FLASH_CFG_DS)) 446f4a3eb02SAdrian Chadd caps->cfi_width = 2; 447f4a3eb02SAdrian Chadd else 448f4a3eb02SAdrian Chadd caps->cfi_width = 1; 449f4a3eb02SAdrian Chadd 450f4a3eb02SAdrian Chadd break; 451f4a3eb02SAdrian Chadd case CHIPC_CAP_FLASH_NONE: 452f4a3eb02SAdrian Chadd caps->flash_type = CHIPC_FLASH_NONE; 453f4a3eb02SAdrian Chadd break; 454f4a3eb02SAdrian Chadd 455f4a3eb02SAdrian Chadd } 456f4a3eb02SAdrian Chadd 457f4a3eb02SAdrian Chadd /* Handle 4706_NFLASH fallback */ 458f4a3eb02SAdrian Chadd if (CHIPC_QUIRK(sc, 4706_NFLASH) && 459f4a3eb02SAdrian Chadd CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_4706_NFLASH)) 4604ad7e9b0SAdrian Chadd { 461f4a3eb02SAdrian Chadd caps->flash_type = CHIPC_NFLASH_4706; 462f4a3eb02SAdrian Chadd } 463f4a3eb02SAdrian Chadd 46456a4cdd1SLandon J. Fuller 46556a4cdd1SLandon J. Fuller /* Determine NVRAM source. Must occur after the SPROM/OTP/flash 46656a4cdd1SLandon J. Fuller * capability flags have been populated. */ 46756a4cdd1SLandon J. Fuller caps->nvram_src = chipc_find_nvram_src(sc, caps); 46856a4cdd1SLandon J. Fuller 46956a4cdd1SLandon J. Fuller /* Determine the SPROM offset within OTP (if any). SPROM-formatted 47056a4cdd1SLandon J. Fuller * data is placed within the OTP general use region. */ 47156a4cdd1SLandon J. Fuller caps->sprom_offset = 0; 47256a4cdd1SLandon J. Fuller if (caps->nvram_src == BHND_NVRAM_SRC_OTP) { 47356a4cdd1SLandon J. Fuller CHIPC_ASSERT_QUIRK(sc, OTP_IPX); 47456a4cdd1SLandon J. Fuller 47556a4cdd1SLandon J. Fuller /* Bit offset to GUP HW subregion containing SPROM data */ 47656a4cdd1SLandon J. Fuller regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 47756a4cdd1SLandon J. Fuller caps->sprom_offset = CHIPC_GET_BITS(regval, CHIPC_OTPL_GUP); 47856a4cdd1SLandon J. Fuller 47956a4cdd1SLandon J. Fuller /* Convert to bytes */ 48056a4cdd1SLandon J. Fuller caps->sprom_offset /= 8; 48156a4cdd1SLandon J. Fuller } 48256a4cdd1SLandon J. Fuller 4834ad7e9b0SAdrian Chadd return (0); 4844ad7e9b0SAdrian Chadd } 4854ad7e9b0SAdrian Chadd 486f4a3eb02SAdrian Chadd static int 487f4a3eb02SAdrian Chadd chipc_suspend(device_t dev) 488f4a3eb02SAdrian Chadd { 489f4a3eb02SAdrian Chadd return (bus_generic_suspend(dev)); 490f4a3eb02SAdrian Chadd } 491f4a3eb02SAdrian Chadd 492f4a3eb02SAdrian Chadd static int 493f4a3eb02SAdrian Chadd chipc_resume(device_t dev) 494f4a3eb02SAdrian Chadd { 495f4a3eb02SAdrian Chadd return (bus_generic_resume(dev)); 496f4a3eb02SAdrian Chadd } 497f4a3eb02SAdrian Chadd 498f4a3eb02SAdrian Chadd static void 499f4a3eb02SAdrian Chadd chipc_probe_nomatch(device_t dev, device_t child) 500f4a3eb02SAdrian Chadd { 501f4a3eb02SAdrian Chadd struct resource_list *rl; 502f4a3eb02SAdrian Chadd const char *name; 503f4a3eb02SAdrian Chadd 504f4a3eb02SAdrian Chadd name = device_get_name(child); 505f4a3eb02SAdrian Chadd if (name == NULL) 506f4a3eb02SAdrian Chadd name = "unknown device"; 507f4a3eb02SAdrian Chadd 508f4a3eb02SAdrian Chadd device_printf(dev, "<%s> at", name); 509f4a3eb02SAdrian Chadd 510f4a3eb02SAdrian Chadd rl = BUS_GET_RESOURCE_LIST(dev, child); 511f4a3eb02SAdrian Chadd if (rl != NULL) { 512f4a3eb02SAdrian Chadd resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 513f4a3eb02SAdrian Chadd resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 514f4a3eb02SAdrian Chadd } 515f4a3eb02SAdrian Chadd 516f4a3eb02SAdrian Chadd printf(" (no driver attached)\n"); 517f4a3eb02SAdrian Chadd } 518f4a3eb02SAdrian Chadd 519f4a3eb02SAdrian Chadd static int 520f4a3eb02SAdrian Chadd chipc_print_child(device_t dev, device_t child) 521f4a3eb02SAdrian Chadd { 522f4a3eb02SAdrian Chadd struct resource_list *rl; 523f4a3eb02SAdrian Chadd int retval = 0; 524f4a3eb02SAdrian Chadd 525f4a3eb02SAdrian Chadd retval += bus_print_child_header(dev, child); 526f4a3eb02SAdrian Chadd 527f4a3eb02SAdrian Chadd rl = BUS_GET_RESOURCE_LIST(dev, child); 528f4a3eb02SAdrian Chadd if (rl != NULL) { 529f4a3eb02SAdrian Chadd retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, 530f4a3eb02SAdrian Chadd "%#jx"); 531f4a3eb02SAdrian Chadd retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, 532f4a3eb02SAdrian Chadd "%jd"); 533f4a3eb02SAdrian Chadd } 534f4a3eb02SAdrian Chadd 535f4a3eb02SAdrian Chadd retval += bus_print_child_domain(dev, child); 536f4a3eb02SAdrian Chadd retval += bus_print_child_footer(dev, child); 537f4a3eb02SAdrian Chadd 538f4a3eb02SAdrian Chadd return (retval); 539f4a3eb02SAdrian Chadd } 540f4a3eb02SAdrian Chadd 541f4a3eb02SAdrian Chadd static int 542f4a3eb02SAdrian Chadd chipc_child_pnpinfo_str(device_t dev, device_t child, char *buf, 543f4a3eb02SAdrian Chadd size_t buflen) 544f4a3eb02SAdrian Chadd { 545f4a3eb02SAdrian Chadd if (buflen == 0) 546f4a3eb02SAdrian Chadd return (EOVERFLOW); 547f4a3eb02SAdrian Chadd 548f4a3eb02SAdrian Chadd *buf = '\0'; 549f4a3eb02SAdrian Chadd return (0); 550f4a3eb02SAdrian Chadd } 551f4a3eb02SAdrian Chadd 552f4a3eb02SAdrian Chadd static int 553f4a3eb02SAdrian Chadd chipc_child_location_str(device_t dev, device_t child, char *buf, 554f4a3eb02SAdrian Chadd size_t buflen) 555f4a3eb02SAdrian Chadd { 556f4a3eb02SAdrian Chadd if (buflen == 0) 557f4a3eb02SAdrian Chadd return (EOVERFLOW); 558f4a3eb02SAdrian Chadd 559f4a3eb02SAdrian Chadd *buf = '\0'; 560f4a3eb02SAdrian Chadd return (ENXIO); 561f4a3eb02SAdrian Chadd } 562f4a3eb02SAdrian Chadd 563f4a3eb02SAdrian Chadd static device_t 564f4a3eb02SAdrian Chadd chipc_add_child(device_t dev, u_int order, const char *name, int unit) 565f4a3eb02SAdrian Chadd { 5660c91e892SLandon J. Fuller struct chipc_softc *sc; 567f4a3eb02SAdrian Chadd struct chipc_devinfo *dinfo; 568f4a3eb02SAdrian Chadd device_t child; 5690c91e892SLandon J. Fuller 5700c91e892SLandon J. Fuller sc = device_get_softc(dev); 571f4a3eb02SAdrian Chadd 572f4a3eb02SAdrian Chadd child = device_add_child_ordered(dev, order, name, unit); 573f4a3eb02SAdrian Chadd if (child == NULL) 574f4a3eb02SAdrian Chadd return (NULL); 575f4a3eb02SAdrian Chadd 576f4a3eb02SAdrian Chadd dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT); 577f4a3eb02SAdrian Chadd if (dinfo == NULL) { 578f4a3eb02SAdrian Chadd device_delete_child(dev, child); 579f4a3eb02SAdrian Chadd return (NULL); 580f4a3eb02SAdrian Chadd } 581f4a3eb02SAdrian Chadd 582f4a3eb02SAdrian Chadd resource_list_init(&dinfo->resources); 583f4a3eb02SAdrian Chadd device_set_ivars(child, dinfo); 584f4a3eb02SAdrian Chadd 585f4a3eb02SAdrian Chadd return (child); 586f4a3eb02SAdrian Chadd } 587f4a3eb02SAdrian Chadd 588f4a3eb02SAdrian Chadd static void 589f4a3eb02SAdrian Chadd chipc_child_deleted(device_t dev, device_t child) 590f4a3eb02SAdrian Chadd { 591f4a3eb02SAdrian Chadd struct chipc_devinfo *dinfo = device_get_ivars(child); 592f4a3eb02SAdrian Chadd 593f4a3eb02SAdrian Chadd if (dinfo != NULL) { 594f4a3eb02SAdrian Chadd resource_list_free(&dinfo->resources); 595f4a3eb02SAdrian Chadd free(dinfo, M_BHND); 596f4a3eb02SAdrian Chadd } 597f4a3eb02SAdrian Chadd 598f4a3eb02SAdrian Chadd device_set_ivars(child, NULL); 599f4a3eb02SAdrian Chadd } 600f4a3eb02SAdrian Chadd 601f4a3eb02SAdrian Chadd static struct resource_list * 602f4a3eb02SAdrian Chadd chipc_get_resource_list(device_t dev, device_t child) 603f4a3eb02SAdrian Chadd { 604f4a3eb02SAdrian Chadd struct chipc_devinfo *dinfo = device_get_ivars(child); 605f4a3eb02SAdrian Chadd return (&dinfo->resources); 606f4a3eb02SAdrian Chadd } 607f4a3eb02SAdrian Chadd 608f4a3eb02SAdrian Chadd 609f4a3eb02SAdrian Chadd /* Allocate region records for the given port, and add the port's memory 610f4a3eb02SAdrian Chadd * range to the mem_rman */ 611f4a3eb02SAdrian Chadd static int 612f4a3eb02SAdrian Chadd chipc_rman_init_regions (struct chipc_softc *sc, bhnd_port_type type, 613f4a3eb02SAdrian Chadd u_int port) 614f4a3eb02SAdrian Chadd { 615f4a3eb02SAdrian Chadd struct chipc_region *cr; 616f4a3eb02SAdrian Chadd rman_res_t start, end; 617f4a3eb02SAdrian Chadd u_int num_regions; 618f4a3eb02SAdrian Chadd int error; 619f4a3eb02SAdrian Chadd 6200c91e892SLandon J. Fuller num_regions = bhnd_get_region_count(sc->dev, type, port); 621f4a3eb02SAdrian Chadd for (u_int region = 0; region < num_regions; region++) { 622f4a3eb02SAdrian Chadd /* Allocate new region record */ 623f4a3eb02SAdrian Chadd cr = chipc_alloc_region(sc, type, port, region); 624f4a3eb02SAdrian Chadd if (cr == NULL) 625f4a3eb02SAdrian Chadd return (ENODEV); 626f4a3eb02SAdrian Chadd 627f4a3eb02SAdrian Chadd /* Can't manage regions that cannot be allocated */ 628f4a3eb02SAdrian Chadd if (cr->cr_rid < 0) { 629f4a3eb02SAdrian Chadd BHND_DEBUG_DEV(sc->dev, "no rid for chipc region " 630f4a3eb02SAdrian Chadd "%s%u.%u", bhnd_port_type_name(type), port, region); 631f4a3eb02SAdrian Chadd chipc_free_region(sc, cr); 632f4a3eb02SAdrian Chadd continue; 633f4a3eb02SAdrian Chadd } 634f4a3eb02SAdrian Chadd 635f4a3eb02SAdrian Chadd /* Add to rman's managed range */ 636f4a3eb02SAdrian Chadd start = cr->cr_addr; 637f4a3eb02SAdrian Chadd end = cr->cr_end; 638f4a3eb02SAdrian Chadd if ((error = rman_manage_region(&sc->mem_rman, start, end))) { 639f4a3eb02SAdrian Chadd chipc_free_region(sc, cr); 640f4a3eb02SAdrian Chadd return (error); 641f4a3eb02SAdrian Chadd } 642f4a3eb02SAdrian Chadd 643f4a3eb02SAdrian Chadd /* Add to region list */ 644f4a3eb02SAdrian Chadd STAILQ_INSERT_TAIL(&sc->mem_regions, cr, cr_link); 645f4a3eb02SAdrian Chadd } 646f4a3eb02SAdrian Chadd 647f4a3eb02SAdrian Chadd return (0); 648f4a3eb02SAdrian Chadd } 649f4a3eb02SAdrian Chadd 650f4a3eb02SAdrian Chadd /* Initialize memory state for all chipc port regions */ 651f4a3eb02SAdrian Chadd static int 652f4a3eb02SAdrian Chadd chipc_init_rman(struct chipc_softc *sc) 653f4a3eb02SAdrian Chadd { 654f4a3eb02SAdrian Chadd u_int num_ports; 655f4a3eb02SAdrian Chadd int error; 656f4a3eb02SAdrian Chadd 657f4a3eb02SAdrian Chadd /* Port types for which we'll register chipc_region mappings */ 658f4a3eb02SAdrian Chadd bhnd_port_type types[] = { 659f4a3eb02SAdrian Chadd BHND_PORT_DEVICE 660f4a3eb02SAdrian Chadd }; 661f4a3eb02SAdrian Chadd 662f4a3eb02SAdrian Chadd /* Initialize resource manager */ 663f4a3eb02SAdrian Chadd sc->mem_rman.rm_start = 0; 664f4a3eb02SAdrian Chadd sc->mem_rman.rm_end = BUS_SPACE_MAXADDR; 665f4a3eb02SAdrian Chadd sc->mem_rman.rm_type = RMAN_ARRAY; 666f4a3eb02SAdrian Chadd sc->mem_rman.rm_descr = "ChipCommon Device Memory"; 667f4a3eb02SAdrian Chadd if ((error = rman_init(&sc->mem_rman))) { 668f4a3eb02SAdrian Chadd device_printf(sc->dev, "could not initialize mem_rman: %d\n", 669f4a3eb02SAdrian Chadd error); 670f4a3eb02SAdrian Chadd return (error); 671f4a3eb02SAdrian Chadd } 672f4a3eb02SAdrian Chadd 673f4a3eb02SAdrian Chadd /* Populate per-port-region state */ 674f4a3eb02SAdrian Chadd for (u_int i = 0; i < nitems(types); i++) { 675f4a3eb02SAdrian Chadd num_ports = bhnd_get_port_count(sc->dev, types[i]); 676f4a3eb02SAdrian Chadd for (u_int port = 0; port < num_ports; port++) { 677f4a3eb02SAdrian Chadd error = chipc_rman_init_regions(sc, types[i], port); 678f4a3eb02SAdrian Chadd if (error) { 679f4a3eb02SAdrian Chadd device_printf(sc->dev, 680f4a3eb02SAdrian Chadd "region init failed for %s%u: %d\n", 681f4a3eb02SAdrian Chadd bhnd_port_type_name(types[i]), port, 682f4a3eb02SAdrian Chadd error); 683f4a3eb02SAdrian Chadd 684f4a3eb02SAdrian Chadd goto failed; 685f4a3eb02SAdrian Chadd } 686f4a3eb02SAdrian Chadd } 687f4a3eb02SAdrian Chadd } 688f4a3eb02SAdrian Chadd 689f4a3eb02SAdrian Chadd return (0); 690f4a3eb02SAdrian Chadd 691f4a3eb02SAdrian Chadd failed: 692f4a3eb02SAdrian Chadd chipc_free_rman(sc); 693f4a3eb02SAdrian Chadd return (error); 694f4a3eb02SAdrian Chadd } 695f4a3eb02SAdrian Chadd 696f4a3eb02SAdrian Chadd /* Free memory management state */ 697f4a3eb02SAdrian Chadd static void 698f4a3eb02SAdrian Chadd chipc_free_rman(struct chipc_softc *sc) 699f4a3eb02SAdrian Chadd { 700f4a3eb02SAdrian Chadd struct chipc_region *cr, *cr_next; 701f4a3eb02SAdrian Chadd 702f4a3eb02SAdrian Chadd STAILQ_FOREACH_SAFE(cr, &sc->mem_regions, cr_link, cr_next) 703f4a3eb02SAdrian Chadd chipc_free_region(sc, cr); 704f4a3eb02SAdrian Chadd 705f4a3eb02SAdrian Chadd rman_fini(&sc->mem_rman); 706f4a3eb02SAdrian Chadd } 707f4a3eb02SAdrian Chadd 708f4a3eb02SAdrian Chadd /** 709f4a3eb02SAdrian Chadd * Return the rman instance for a given resource @p type, if any. 710f4a3eb02SAdrian Chadd * 711f4a3eb02SAdrian Chadd * @param sc The chipc device state. 712f4a3eb02SAdrian Chadd * @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...) 713f4a3eb02SAdrian Chadd */ 714f4a3eb02SAdrian Chadd static struct rman * 715f4a3eb02SAdrian Chadd chipc_get_rman(struct chipc_softc *sc, int type) 716f4a3eb02SAdrian Chadd { 717f4a3eb02SAdrian Chadd switch (type) { 718f4a3eb02SAdrian Chadd case SYS_RES_MEMORY: 719f4a3eb02SAdrian Chadd return (&sc->mem_rman); 720f4a3eb02SAdrian Chadd 721f4a3eb02SAdrian Chadd case SYS_RES_IRQ: 722f4a3eb02SAdrian Chadd /* IRQs can be used with RF_SHAREABLE, so we don't perform 723f4a3eb02SAdrian Chadd * any local proxying of resource requests. */ 724f4a3eb02SAdrian Chadd return (NULL); 725f4a3eb02SAdrian Chadd 726f4a3eb02SAdrian Chadd default: 727f4a3eb02SAdrian Chadd return (NULL); 728f4a3eb02SAdrian Chadd }; 729f4a3eb02SAdrian Chadd } 730f4a3eb02SAdrian Chadd 731f4a3eb02SAdrian Chadd static struct resource * 732f4a3eb02SAdrian Chadd chipc_alloc_resource(device_t dev, device_t child, int type, 733f4a3eb02SAdrian Chadd int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 734f4a3eb02SAdrian Chadd { 735f4a3eb02SAdrian Chadd struct chipc_softc *sc; 736f4a3eb02SAdrian Chadd struct chipc_region *cr; 737f4a3eb02SAdrian Chadd struct resource_list_entry *rle; 738f4a3eb02SAdrian Chadd struct resource *rv; 739f4a3eb02SAdrian Chadd struct rman *rm; 740f4a3eb02SAdrian Chadd int error; 741f4a3eb02SAdrian Chadd bool passthrough, isdefault; 742f4a3eb02SAdrian Chadd 743f4a3eb02SAdrian Chadd sc = device_get_softc(dev); 744f4a3eb02SAdrian Chadd passthrough = (device_get_parent(child) != dev); 745f4a3eb02SAdrian Chadd isdefault = RMAN_IS_DEFAULT_RANGE(start, end); 746f4a3eb02SAdrian Chadd rle = NULL; 747f4a3eb02SAdrian Chadd 748f4a3eb02SAdrian Chadd /* Fetch the resource manager, delegate request if necessary */ 749f4a3eb02SAdrian Chadd rm = chipc_get_rman(sc, type); 750f4a3eb02SAdrian Chadd if (rm == NULL) { 751f4a3eb02SAdrian Chadd /* Requested resource type is delegated to our parent */ 752f4a3eb02SAdrian Chadd rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 753f4a3eb02SAdrian Chadd start, end, count, flags); 754f4a3eb02SAdrian Chadd return (rv); 755f4a3eb02SAdrian Chadd } 756f4a3eb02SAdrian Chadd 757f4a3eb02SAdrian Chadd /* Populate defaults */ 758f4a3eb02SAdrian Chadd if (!passthrough && isdefault) { 759f4a3eb02SAdrian Chadd /* Fetch the resource list entry. */ 760f4a3eb02SAdrian Chadd rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), 761f4a3eb02SAdrian Chadd type, *rid); 762f4a3eb02SAdrian Chadd if (rle == NULL) { 763f4a3eb02SAdrian Chadd device_printf(dev, 764f4a3eb02SAdrian Chadd "default resource %#x type %d for child %s " 765f4a3eb02SAdrian Chadd "not found\n", *rid, type, 766f4a3eb02SAdrian Chadd device_get_nameunit(child)); 767f4a3eb02SAdrian Chadd return (NULL); 768f4a3eb02SAdrian Chadd } 769f4a3eb02SAdrian Chadd 770f4a3eb02SAdrian Chadd if (rle->res != NULL) { 771f4a3eb02SAdrian Chadd device_printf(dev, 7722b693a88SLandon J. Fuller "resource entry %#x type %d for child %s is busy " 7732b693a88SLandon J. Fuller "[%d]\n", 7742b693a88SLandon J. Fuller *rid, type, device_get_nameunit(child), 7752b693a88SLandon J. Fuller rman_get_flags(rle->res)); 776f4a3eb02SAdrian Chadd 777f4a3eb02SAdrian Chadd return (NULL); 778f4a3eb02SAdrian Chadd } 779f4a3eb02SAdrian Chadd 780f4a3eb02SAdrian Chadd start = rle->start; 781f4a3eb02SAdrian Chadd end = rle->end; 782f4a3eb02SAdrian Chadd count = ulmax(count, rle->count); 783f4a3eb02SAdrian Chadd } 784f4a3eb02SAdrian Chadd 785f4a3eb02SAdrian Chadd /* Locate a mapping region */ 786f4a3eb02SAdrian Chadd if ((cr = chipc_find_region(sc, start, end)) == NULL) { 787f4a3eb02SAdrian Chadd /* Resource requests outside our shared port regions can be 788f4a3eb02SAdrian Chadd * delegated to our parent. */ 789f4a3eb02SAdrian Chadd rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 790f4a3eb02SAdrian Chadd start, end, count, flags); 791f4a3eb02SAdrian Chadd return (rv); 792f4a3eb02SAdrian Chadd } 793f4a3eb02SAdrian Chadd 794f4a3eb02SAdrian Chadd /* Try to retain a region reference */ 7957d1fb1aaSLandon J. Fuller if ((error = chipc_retain_region(sc, cr, RF_ALLOCATED))) 796f4a3eb02SAdrian Chadd return (NULL); 797f4a3eb02SAdrian Chadd 798f4a3eb02SAdrian Chadd /* Make our rman reservation */ 799f4a3eb02SAdrian Chadd rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE, 800f4a3eb02SAdrian Chadd child); 801f4a3eb02SAdrian Chadd if (rv == NULL) { 802f4a3eb02SAdrian Chadd chipc_release_region(sc, cr, RF_ALLOCATED); 803f4a3eb02SAdrian Chadd return (NULL); 804f4a3eb02SAdrian Chadd } 805f4a3eb02SAdrian Chadd 806f4a3eb02SAdrian Chadd rman_set_rid(rv, *rid); 807f4a3eb02SAdrian Chadd 808f4a3eb02SAdrian Chadd /* Activate */ 809f4a3eb02SAdrian Chadd if (flags & RF_ACTIVE) { 810f4a3eb02SAdrian Chadd error = bus_activate_resource(child, type, *rid, rv); 811f4a3eb02SAdrian Chadd if (error) { 812f4a3eb02SAdrian Chadd device_printf(dev, 813f4a3eb02SAdrian Chadd "failed to activate entry %#x type %d for " 814f4a3eb02SAdrian Chadd "child %s: %d\n", 815f4a3eb02SAdrian Chadd *rid, type, device_get_nameunit(child), error); 816f4a3eb02SAdrian Chadd 817f4a3eb02SAdrian Chadd chipc_release_region(sc, cr, RF_ALLOCATED); 818f4a3eb02SAdrian Chadd rman_release_resource(rv); 819f4a3eb02SAdrian Chadd 820f4a3eb02SAdrian Chadd return (NULL); 821f4a3eb02SAdrian Chadd } 822f4a3eb02SAdrian Chadd } 823f4a3eb02SAdrian Chadd 824f4a3eb02SAdrian Chadd /* Update child's resource list entry */ 825f4a3eb02SAdrian Chadd if (rle != NULL) { 826f4a3eb02SAdrian Chadd rle->res = rv; 827f4a3eb02SAdrian Chadd rle->start = rman_get_start(rv); 828f4a3eb02SAdrian Chadd rle->end = rman_get_end(rv); 829f4a3eb02SAdrian Chadd rle->count = rman_get_size(rv); 830f4a3eb02SAdrian Chadd } 831f4a3eb02SAdrian Chadd 832f4a3eb02SAdrian Chadd return (rv); 833f4a3eb02SAdrian Chadd } 834f4a3eb02SAdrian Chadd 835f4a3eb02SAdrian Chadd static int 836f4a3eb02SAdrian Chadd chipc_release_resource(device_t dev, device_t child, int type, int rid, 837f4a3eb02SAdrian Chadd struct resource *r) 838f4a3eb02SAdrian Chadd { 839f4a3eb02SAdrian Chadd struct chipc_softc *sc; 840f4a3eb02SAdrian Chadd struct chipc_region *cr; 841f4a3eb02SAdrian Chadd struct rman *rm; 8422b693a88SLandon J. Fuller struct resource_list_entry *rle; 843f4a3eb02SAdrian Chadd int error; 844f4a3eb02SAdrian Chadd 845f4a3eb02SAdrian Chadd sc = device_get_softc(dev); 846f4a3eb02SAdrian Chadd 847f4a3eb02SAdrian Chadd /* Handled by parent bus? */ 848f4a3eb02SAdrian Chadd rm = chipc_get_rman(sc, type); 849f4a3eb02SAdrian Chadd if (rm == NULL || !rman_is_region_manager(r, rm)) { 850f4a3eb02SAdrian Chadd return (bus_generic_rl_release_resource(dev, child, type, rid, 851f4a3eb02SAdrian Chadd r)); 852f4a3eb02SAdrian Chadd } 853f4a3eb02SAdrian Chadd 854f4a3eb02SAdrian Chadd /* Locate the mapping region */ 855f4a3eb02SAdrian Chadd cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 856f4a3eb02SAdrian Chadd if (cr == NULL) 857f4a3eb02SAdrian Chadd return (EINVAL); 858f4a3eb02SAdrian Chadd 859f4a3eb02SAdrian Chadd /* Deactivate resources */ 860f4a3eb02SAdrian Chadd if (rman_get_flags(r) & RF_ACTIVE) { 861f4a3eb02SAdrian Chadd error = BUS_DEACTIVATE_RESOURCE(dev, child, type, rid, r); 862f4a3eb02SAdrian Chadd if (error) 863f4a3eb02SAdrian Chadd return (error); 864f4a3eb02SAdrian Chadd } 865f4a3eb02SAdrian Chadd 866f4a3eb02SAdrian Chadd if ((error = rman_release_resource(r))) 867f4a3eb02SAdrian Chadd return (error); 868f4a3eb02SAdrian Chadd 869f4a3eb02SAdrian Chadd /* Drop allocation reference */ 870f4a3eb02SAdrian Chadd chipc_release_region(sc, cr, RF_ALLOCATED); 871f4a3eb02SAdrian Chadd 8722b693a88SLandon J. Fuller /* Clear reference from the resource list entry if exists */ 8732b693a88SLandon J. Fuller rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), type, rid); 8742b693a88SLandon J. Fuller if (rle != NULL) 8752b693a88SLandon J. Fuller rle->res = NULL; 8762b693a88SLandon J. Fuller 877f4a3eb02SAdrian Chadd return (0); 878f4a3eb02SAdrian Chadd } 879f4a3eb02SAdrian Chadd 880f4a3eb02SAdrian Chadd static int 881f4a3eb02SAdrian Chadd chipc_adjust_resource(device_t dev, device_t child, int type, 882f4a3eb02SAdrian Chadd struct resource *r, rman_res_t start, rman_res_t end) 883f4a3eb02SAdrian Chadd { 884f4a3eb02SAdrian Chadd struct chipc_softc *sc; 885f4a3eb02SAdrian Chadd struct chipc_region *cr; 886f4a3eb02SAdrian Chadd struct rman *rm; 887f4a3eb02SAdrian Chadd 888f4a3eb02SAdrian Chadd sc = device_get_softc(dev); 889f4a3eb02SAdrian Chadd 890f4a3eb02SAdrian Chadd /* Handled by parent bus? */ 891f4a3eb02SAdrian Chadd rm = chipc_get_rman(sc, type); 892f4a3eb02SAdrian Chadd if (rm == NULL || !rman_is_region_manager(r, rm)) { 893f4a3eb02SAdrian Chadd return (bus_generic_adjust_resource(dev, child, type, r, start, 894f4a3eb02SAdrian Chadd end)); 895f4a3eb02SAdrian Chadd } 896f4a3eb02SAdrian Chadd 897f4a3eb02SAdrian Chadd /* The range is limited to the existing region mapping */ 898f4a3eb02SAdrian Chadd cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 899f4a3eb02SAdrian Chadd if (cr == NULL) 900f4a3eb02SAdrian Chadd return (EINVAL); 901f4a3eb02SAdrian Chadd 902f4a3eb02SAdrian Chadd if (end <= start) 903f4a3eb02SAdrian Chadd return (EINVAL); 904f4a3eb02SAdrian Chadd 905f4a3eb02SAdrian Chadd if (start < cr->cr_addr || end > cr->cr_end) 906f4a3eb02SAdrian Chadd return (EINVAL); 907f4a3eb02SAdrian Chadd 908f4a3eb02SAdrian Chadd /* Range falls within the existing region */ 909f4a3eb02SAdrian Chadd return (rman_adjust_resource(r, start, end)); 910f4a3eb02SAdrian Chadd } 911f4a3eb02SAdrian Chadd 912f4a3eb02SAdrian Chadd /** 913f4a3eb02SAdrian Chadd * Retain an RF_ACTIVE reference to the region mapping @p r, and 914f4a3eb02SAdrian Chadd * configure @p r with its subregion values. 915f4a3eb02SAdrian Chadd * 916f4a3eb02SAdrian Chadd * @param sc Driver instance state. 917f4a3eb02SAdrian Chadd * @param child Requesting child device. 918f4a3eb02SAdrian Chadd * @param type resource type of @p r. 919f4a3eb02SAdrian Chadd * @param rid resource id of @p r 920f4a3eb02SAdrian Chadd * @param r resource to be activated. 921f4a3eb02SAdrian Chadd * @param req_direct If true, failure to allocate a direct bhnd resource 922f4a3eb02SAdrian Chadd * will be treated as an error. If false, the resource will not be marked 923f4a3eb02SAdrian Chadd * as RF_ACTIVE if bhnd direct resource allocation fails. 924f4a3eb02SAdrian Chadd */ 925f4a3eb02SAdrian Chadd static int 926f4a3eb02SAdrian Chadd chipc_try_activate_resource(struct chipc_softc *sc, device_t child, int type, 927f4a3eb02SAdrian Chadd int rid, struct resource *r, bool req_direct) 928f4a3eb02SAdrian Chadd { 929f4a3eb02SAdrian Chadd struct rman *rm; 930f4a3eb02SAdrian Chadd struct chipc_region *cr; 931f4a3eb02SAdrian Chadd bhnd_size_t cr_offset; 932f4a3eb02SAdrian Chadd rman_res_t r_start, r_end, r_size; 933f4a3eb02SAdrian Chadd int error; 934f4a3eb02SAdrian Chadd 935f4a3eb02SAdrian Chadd rm = chipc_get_rman(sc, type); 936f4a3eb02SAdrian Chadd if (rm == NULL || !rman_is_region_manager(r, rm)) 937f4a3eb02SAdrian Chadd return (EINVAL); 938f4a3eb02SAdrian Chadd 939f4a3eb02SAdrian Chadd r_start = rman_get_start(r); 940f4a3eb02SAdrian Chadd r_end = rman_get_end(r); 941f4a3eb02SAdrian Chadd r_size = rman_get_size(r); 942f4a3eb02SAdrian Chadd 943f4a3eb02SAdrian Chadd /* Find the corresponding chipc region */ 944f4a3eb02SAdrian Chadd cr = chipc_find_region(sc, r_start, r_end); 945f4a3eb02SAdrian Chadd if (cr == NULL) 946f4a3eb02SAdrian Chadd return (EINVAL); 947f4a3eb02SAdrian Chadd 948f4a3eb02SAdrian Chadd /* Calculate subregion offset within the chipc region */ 949f4a3eb02SAdrian Chadd cr_offset = r_start - cr->cr_addr; 950f4a3eb02SAdrian Chadd 951f4a3eb02SAdrian Chadd /* Retain (and activate, if necessary) the chipc region */ 952f4a3eb02SAdrian Chadd if ((error = chipc_retain_region(sc, cr, RF_ACTIVE))) 953f4a3eb02SAdrian Chadd return (error); 954f4a3eb02SAdrian Chadd 955f4a3eb02SAdrian Chadd /* Configure child resource with its subregion values. */ 956f4a3eb02SAdrian Chadd if (cr->cr_res->direct) { 957f4a3eb02SAdrian Chadd error = chipc_init_child_resource(r, cr->cr_res->res, 958f4a3eb02SAdrian Chadd cr_offset, r_size); 959f4a3eb02SAdrian Chadd if (error) 960f4a3eb02SAdrian Chadd goto cleanup; 961f4a3eb02SAdrian Chadd 962f4a3eb02SAdrian Chadd /* Mark active */ 963f4a3eb02SAdrian Chadd if ((error = rman_activate_resource(r))) 964f4a3eb02SAdrian Chadd goto cleanup; 965f4a3eb02SAdrian Chadd } else if (req_direct) { 966f4a3eb02SAdrian Chadd error = ENOMEM; 967f4a3eb02SAdrian Chadd goto cleanup; 968f4a3eb02SAdrian Chadd } 969f4a3eb02SAdrian Chadd 970f4a3eb02SAdrian Chadd return (0); 971f4a3eb02SAdrian Chadd 972f4a3eb02SAdrian Chadd cleanup: 973f4a3eb02SAdrian Chadd chipc_release_region(sc, cr, RF_ACTIVE); 974f4a3eb02SAdrian Chadd return (error); 975f4a3eb02SAdrian Chadd } 976f4a3eb02SAdrian Chadd 977f4a3eb02SAdrian Chadd static int 978f4a3eb02SAdrian Chadd chipc_activate_bhnd_resource(device_t dev, device_t child, int type, 979f4a3eb02SAdrian Chadd int rid, struct bhnd_resource *r) 980f4a3eb02SAdrian Chadd { 981f4a3eb02SAdrian Chadd struct chipc_softc *sc; 982f4a3eb02SAdrian Chadd struct rman *rm; 983f4a3eb02SAdrian Chadd int error; 984f4a3eb02SAdrian Chadd 985f4a3eb02SAdrian Chadd sc = device_get_softc(dev); 986f4a3eb02SAdrian Chadd 987f4a3eb02SAdrian Chadd /* Delegate non-locally managed resources to parent */ 988f4a3eb02SAdrian Chadd rm = chipc_get_rman(sc, type); 989f4a3eb02SAdrian Chadd if (rm == NULL || !rman_is_region_manager(r->res, rm)) { 990f4a3eb02SAdrian Chadd return (bhnd_bus_generic_activate_resource(dev, child, type, 991f4a3eb02SAdrian Chadd rid, r)); 992f4a3eb02SAdrian Chadd } 993f4a3eb02SAdrian Chadd 994f4a3eb02SAdrian Chadd /* Try activating the chipc region resource */ 995f4a3eb02SAdrian Chadd error = chipc_try_activate_resource(sc, child, type, rid, r->res, 996f4a3eb02SAdrian Chadd false); 997f4a3eb02SAdrian Chadd if (error) 998f4a3eb02SAdrian Chadd return (error); 999f4a3eb02SAdrian Chadd 1000f4a3eb02SAdrian Chadd /* Mark the child resource as direct according to the returned resource 1001f4a3eb02SAdrian Chadd * state */ 1002f4a3eb02SAdrian Chadd if (rman_get_flags(r->res) & RF_ACTIVE) 1003f4a3eb02SAdrian Chadd r->direct = true; 1004f4a3eb02SAdrian Chadd 1005f4a3eb02SAdrian Chadd return (0); 1006f4a3eb02SAdrian Chadd } 1007f4a3eb02SAdrian Chadd 1008f4a3eb02SAdrian Chadd static int 1009f4a3eb02SAdrian Chadd chipc_activate_resource(device_t dev, device_t child, int type, int rid, 1010f4a3eb02SAdrian Chadd struct resource *r) 1011f4a3eb02SAdrian Chadd { 1012f4a3eb02SAdrian Chadd struct chipc_softc *sc; 1013f4a3eb02SAdrian Chadd struct rman *rm; 1014f4a3eb02SAdrian Chadd 1015f4a3eb02SAdrian Chadd sc = device_get_softc(dev); 1016f4a3eb02SAdrian Chadd 1017f4a3eb02SAdrian Chadd /* Delegate non-locally managed resources to parent */ 1018f4a3eb02SAdrian Chadd rm = chipc_get_rman(sc, type); 1019f4a3eb02SAdrian Chadd if (rm == NULL || !rman_is_region_manager(r, rm)) { 1020f4a3eb02SAdrian Chadd return (bus_generic_activate_resource(dev, child, type, rid, 1021f4a3eb02SAdrian Chadd r)); 1022f4a3eb02SAdrian Chadd } 1023f4a3eb02SAdrian Chadd 1024f4a3eb02SAdrian Chadd /* Try activating the chipc region-based resource */ 1025f4a3eb02SAdrian Chadd return (chipc_try_activate_resource(sc, child, type, rid, r, true)); 1026f4a3eb02SAdrian Chadd } 1027f4a3eb02SAdrian Chadd 1028f4a3eb02SAdrian Chadd /** 1029f4a3eb02SAdrian Chadd * Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE(). 1030f4a3eb02SAdrian Chadd */ 1031f4a3eb02SAdrian Chadd static int 1032f4a3eb02SAdrian Chadd chipc_deactivate_resource(device_t dev, device_t child, int type, 1033f4a3eb02SAdrian Chadd int rid, struct resource *r) 1034f4a3eb02SAdrian Chadd { 1035f4a3eb02SAdrian Chadd struct chipc_softc *sc; 1036f4a3eb02SAdrian Chadd struct chipc_region *cr; 1037f4a3eb02SAdrian Chadd struct rman *rm; 1038f4a3eb02SAdrian Chadd int error; 1039f4a3eb02SAdrian Chadd 1040f4a3eb02SAdrian Chadd sc = device_get_softc(dev); 1041f4a3eb02SAdrian Chadd 1042f4a3eb02SAdrian Chadd /* Handled by parent bus? */ 1043f4a3eb02SAdrian Chadd rm = chipc_get_rman(sc, type); 1044f4a3eb02SAdrian Chadd if (rm == NULL || !rman_is_region_manager(r, rm)) { 1045f4a3eb02SAdrian Chadd return (bus_generic_deactivate_resource(dev, child, type, rid, 1046f4a3eb02SAdrian Chadd r)); 1047f4a3eb02SAdrian Chadd } 1048f4a3eb02SAdrian Chadd 1049f4a3eb02SAdrian Chadd /* Find the corresponding chipc region */ 1050f4a3eb02SAdrian Chadd cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 1051f4a3eb02SAdrian Chadd if (cr == NULL) 1052f4a3eb02SAdrian Chadd return (EINVAL); 1053f4a3eb02SAdrian Chadd 1054f4a3eb02SAdrian Chadd /* Mark inactive */ 1055f4a3eb02SAdrian Chadd if ((error = rman_deactivate_resource(r))) 1056f4a3eb02SAdrian Chadd return (error); 1057f4a3eb02SAdrian Chadd 1058f4a3eb02SAdrian Chadd /* Drop associated RF_ACTIVE reference */ 1059f4a3eb02SAdrian Chadd chipc_release_region(sc, cr, RF_ACTIVE); 1060f4a3eb02SAdrian Chadd 1061f4a3eb02SAdrian Chadd return (0); 1062f4a3eb02SAdrian Chadd } 1063f4a3eb02SAdrian Chadd 1064f4a3eb02SAdrian Chadd /** 1065f4a3eb02SAdrian Chadd * Examine bus state and make a best effort determination of whether it's 1066f4a3eb02SAdrian Chadd * likely safe to enable the muxed SPROM pins. 1067f4a3eb02SAdrian Chadd * 1068f4a3eb02SAdrian Chadd * On devices that do not use SPROM pin muxing, always returns true. 1069f4a3eb02SAdrian Chadd * 1070f4a3eb02SAdrian Chadd * @param sc chipc driver state. 1071f4a3eb02SAdrian Chadd */ 1072f4a3eb02SAdrian Chadd static bool 1073f90f4b65SLandon J. Fuller chipc_should_enable_muxed_sprom(struct chipc_softc *sc) 1074f4a3eb02SAdrian Chadd { 1075f4a3eb02SAdrian Chadd device_t *devs; 1076f4a3eb02SAdrian Chadd device_t hostb; 1077f4a3eb02SAdrian Chadd device_t parent; 1078f4a3eb02SAdrian Chadd int devcount; 1079f4a3eb02SAdrian Chadd int error; 1080f4a3eb02SAdrian Chadd bool result; 1081f4a3eb02SAdrian Chadd 1082f4a3eb02SAdrian Chadd /* Nothing to do? */ 1083f4a3eb02SAdrian Chadd if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1084f4a3eb02SAdrian Chadd return (true); 1085f4a3eb02SAdrian Chadd 1086f90f4b65SLandon J. Fuller mtx_lock(&Giant); /* for newbus */ 1087f90f4b65SLandon J. Fuller 1088f4a3eb02SAdrian Chadd parent = device_get_parent(sc->dev); 1089f4a3eb02SAdrian Chadd hostb = bhnd_find_hostb_device(parent); 1090f4a3eb02SAdrian Chadd 1091f90f4b65SLandon J. Fuller if ((error = device_get_children(parent, &devs, &devcount))) { 1092f90f4b65SLandon J. Fuller mtx_unlock(&Giant); 1093f4a3eb02SAdrian Chadd return (false); 1094f90f4b65SLandon J. Fuller } 1095f4a3eb02SAdrian Chadd 1096f4a3eb02SAdrian Chadd /* Reject any active devices other than ChipCommon, or the 1097f4a3eb02SAdrian Chadd * host bridge (if any). */ 1098f4a3eb02SAdrian Chadd result = true; 1099f4a3eb02SAdrian Chadd for (int i = 0; i < devcount; i++) { 1100f4a3eb02SAdrian Chadd if (devs[i] == hostb || devs[i] == sc->dev) 1101f4a3eb02SAdrian Chadd continue; 1102f4a3eb02SAdrian Chadd 1103f4a3eb02SAdrian Chadd if (!device_is_attached(devs[i])) 1104f4a3eb02SAdrian Chadd continue; 1105f4a3eb02SAdrian Chadd 1106f4a3eb02SAdrian Chadd if (device_is_suspended(devs[i])) 1107f4a3eb02SAdrian Chadd continue; 1108f4a3eb02SAdrian Chadd 1109f4a3eb02SAdrian Chadd /* Active device; assume SPROM is busy */ 1110f4a3eb02SAdrian Chadd result = false; 1111f4a3eb02SAdrian Chadd break; 1112f4a3eb02SAdrian Chadd } 1113f4a3eb02SAdrian Chadd 1114f4a3eb02SAdrian Chadd free(devs, M_TEMP); 1115f90f4b65SLandon J. Fuller mtx_unlock(&Giant); 1116f4a3eb02SAdrian Chadd return (result); 1117f4a3eb02SAdrian Chadd } 1118e83ce340SAdrian Chadd 1119f90f4b65SLandon J. Fuller static int 1120f90f4b65SLandon J. Fuller chipc_enable_sprom(device_t dev) 1121f90f4b65SLandon J. Fuller { 1122f90f4b65SLandon J. Fuller struct chipc_softc *sc; 1123f90f4b65SLandon J. Fuller int error; 1124f90f4b65SLandon J. Fuller 1125f90f4b65SLandon J. Fuller sc = device_get_softc(dev); 1126f90f4b65SLandon J. Fuller CHIPC_LOCK(sc); 1127f90f4b65SLandon J. Fuller 1128f90f4b65SLandon J. Fuller /* Already enabled? */ 1129f90f4b65SLandon J. Fuller if (sc->sprom_refcnt >= 1) { 1130f90f4b65SLandon J. Fuller sc->sprom_refcnt++; 1131f90f4b65SLandon J. Fuller CHIPC_UNLOCK(sc); 1132f90f4b65SLandon J. Fuller 1133f90f4b65SLandon J. Fuller return (0); 1134f90f4b65SLandon J. Fuller } 1135f90f4b65SLandon J. Fuller 1136f90f4b65SLandon J. Fuller switch (sc->caps.nvram_src) { 1137f90f4b65SLandon J. Fuller case BHND_NVRAM_SRC_SPROM: 1138f90f4b65SLandon J. Fuller error = chipc_enable_sprom_pins(sc); 1139f90f4b65SLandon J. Fuller break; 1140f90f4b65SLandon J. Fuller case BHND_NVRAM_SRC_OTP: 1141f90f4b65SLandon J. Fuller error = chipc_enable_otp_power(sc); 1142f90f4b65SLandon J. Fuller break; 1143f90f4b65SLandon J. Fuller default: 1144f90f4b65SLandon J. Fuller error = 0; 1145f90f4b65SLandon J. Fuller break; 1146f90f4b65SLandon J. Fuller } 1147f90f4b65SLandon J. Fuller 1148f90f4b65SLandon J. Fuller /* Bump the reference count */ 1149f90f4b65SLandon J. Fuller if (error == 0) 1150f90f4b65SLandon J. Fuller sc->sprom_refcnt++; 1151f90f4b65SLandon J. Fuller 1152f90f4b65SLandon J. Fuller CHIPC_UNLOCK(sc); 1153f90f4b65SLandon J. Fuller return (error); 1154f90f4b65SLandon J. Fuller } 1155f90f4b65SLandon J. Fuller 1156f90f4b65SLandon J. Fuller static void 1157f90f4b65SLandon J. Fuller chipc_disable_sprom(device_t dev) 1158f90f4b65SLandon J. Fuller { 1159f90f4b65SLandon J. Fuller struct chipc_softc *sc; 1160f90f4b65SLandon J. Fuller 1161f90f4b65SLandon J. Fuller sc = device_get_softc(dev); 1162f90f4b65SLandon J. Fuller CHIPC_LOCK(sc); 1163f90f4b65SLandon J. Fuller 1164f90f4b65SLandon J. Fuller /* Check reference count, skip disable if in-use. */ 1165f90f4b65SLandon J. Fuller KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease")); 1166f90f4b65SLandon J. Fuller sc->sprom_refcnt--; 1167f90f4b65SLandon J. Fuller if (sc->sprom_refcnt > 0) { 1168f90f4b65SLandon J. Fuller CHIPC_UNLOCK(sc); 1169f90f4b65SLandon J. Fuller return; 1170f90f4b65SLandon J. Fuller } 1171f90f4b65SLandon J. Fuller 1172f90f4b65SLandon J. Fuller switch (sc->caps.nvram_src) { 1173f90f4b65SLandon J. Fuller case BHND_NVRAM_SRC_SPROM: 1174f90f4b65SLandon J. Fuller chipc_disable_sprom_pins(sc); 1175f90f4b65SLandon J. Fuller break; 1176f90f4b65SLandon J. Fuller case BHND_NVRAM_SRC_OTP: 1177f90f4b65SLandon J. Fuller chipc_disable_otp_power(sc); 1178f90f4b65SLandon J. Fuller break; 1179f90f4b65SLandon J. Fuller default: 1180f90f4b65SLandon J. Fuller break; 1181f90f4b65SLandon J. Fuller } 1182f90f4b65SLandon J. Fuller 1183f90f4b65SLandon J. Fuller 1184f90f4b65SLandon J. Fuller CHIPC_UNLOCK(sc); 1185f90f4b65SLandon J. Fuller } 1186f90f4b65SLandon J. Fuller 1187f90f4b65SLandon J. Fuller static int 1188f90f4b65SLandon J. Fuller chipc_enable_otp_power(struct chipc_softc *sc) 1189f90f4b65SLandon J. Fuller { 1190f90f4b65SLandon J. Fuller // TODO: Enable OTP resource via PMU, and wait up to 100 usec for 1191f90f4b65SLandon J. Fuller // OTPS_READY to be set in `optstatus`. 1192f90f4b65SLandon J. Fuller return (0); 1193f90f4b65SLandon J. Fuller } 1194f90f4b65SLandon J. Fuller 1195f90f4b65SLandon J. Fuller static void 1196f90f4b65SLandon J. Fuller chipc_disable_otp_power(struct chipc_softc *sc) 1197f90f4b65SLandon J. Fuller { 1198f90f4b65SLandon J. Fuller // TODO: Disable OTP resource via PMU 1199f90f4b65SLandon J. Fuller } 1200f90f4b65SLandon J. Fuller 1201e83ce340SAdrian Chadd /** 1202e83ce340SAdrian Chadd * If required by this device, enable access to the SPROM. 1203e83ce340SAdrian Chadd * 1204e83ce340SAdrian Chadd * @param sc chipc driver state. 1205e83ce340SAdrian Chadd */ 1206e83ce340SAdrian Chadd static int 1207f90f4b65SLandon J. Fuller chipc_enable_sprom_pins(struct chipc_softc *sc) 1208e83ce340SAdrian Chadd { 1209e83ce340SAdrian Chadd uint32_t cctrl; 1210e83ce340SAdrian Chadd 1211f90f4b65SLandon J. Fuller CHIPC_LOCK_ASSERT(sc, MA_OWNED); 1212f90f4b65SLandon J. Fuller KASSERT(sc->sprom_refcnt == 0, ("sprom pins already enabled")); 1213e83ce340SAdrian Chadd 1214e83ce340SAdrian Chadd /* Nothing to do? */ 1215e83ce340SAdrian Chadd if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1216e83ce340SAdrian Chadd return (0); 1217e83ce340SAdrian Chadd 1218f4a3eb02SAdrian Chadd /* Check whether bus is busy */ 1219f90f4b65SLandon J. Fuller if (!chipc_should_enable_muxed_sprom(sc)) 1220f90f4b65SLandon J. Fuller return (EBUSY); 1221f4a3eb02SAdrian Chadd 1222e83ce340SAdrian Chadd cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1223e83ce340SAdrian Chadd 1224e83ce340SAdrian Chadd /* 4331 devices */ 1225e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1226e83ce340SAdrian Chadd cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN; 1227e83ce340SAdrian Chadd 1228e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1229e83ce340SAdrian Chadd cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1230e83ce340SAdrian Chadd 1231e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1232e83ce340SAdrian Chadd cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2; 1233e83ce340SAdrian Chadd 1234e83ce340SAdrian Chadd bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1235f90f4b65SLandon J. Fuller return (0); 1236e83ce340SAdrian Chadd } 1237e83ce340SAdrian Chadd 1238e83ce340SAdrian Chadd /* 4360 devices */ 1239e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1240e83ce340SAdrian Chadd /* Unimplemented */ 1241e83ce340SAdrian Chadd } 1242e83ce340SAdrian Chadd 1243e83ce340SAdrian Chadd /* Refuse to proceed on unsupported devices with muxed SPROM pins */ 1244e83ce340SAdrian Chadd device_printf(sc->dev, "muxed sprom lines on unrecognized device\n"); 1245f90f4b65SLandon J. Fuller return (ENXIO); 1246e83ce340SAdrian Chadd } 1247e83ce340SAdrian Chadd 1248e83ce340SAdrian Chadd /** 1249e83ce340SAdrian Chadd * If required by this device, revert any GPIO/pin configuration applied 1250e83ce340SAdrian Chadd * to allow SPROM access. 1251e83ce340SAdrian Chadd * 1252e83ce340SAdrian Chadd * @param sc chipc driver state. 1253e83ce340SAdrian Chadd */ 1254f4a3eb02SAdrian Chadd static void 1255f90f4b65SLandon J. Fuller chipc_disable_sprom_pins(struct chipc_softc *sc) 1256e83ce340SAdrian Chadd { 1257e83ce340SAdrian Chadd uint32_t cctrl; 1258e83ce340SAdrian Chadd 1259e83ce340SAdrian Chadd /* Nothing to do? */ 1260e83ce340SAdrian Chadd if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1261f4a3eb02SAdrian Chadd return; 1262f4a3eb02SAdrian Chadd 1263f90f4b65SLandon J. Fuller CHIPC_LOCK_ASSERT(sc, MA_OWNED); 1264f90f4b65SLandon J. Fuller KASSERT(sc->sprom_refcnt != 0, ("sprom pins already disabled")); 1265f90f4b65SLandon J. Fuller KASSERT(sc->sprom_refcnt == 1, ("sprom pins in use")); 1266e83ce340SAdrian Chadd 1267e83ce340SAdrian Chadd cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1268e83ce340SAdrian Chadd 1269e83ce340SAdrian Chadd /* 4331 devices */ 1270e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1271e83ce340SAdrian Chadd cctrl |= CHIPC_CCTRL4331_EXTPA_EN; 1272e83ce340SAdrian Chadd 1273e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1274e83ce340SAdrian Chadd cctrl |= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1275e83ce340SAdrian Chadd 1276e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1277e83ce340SAdrian Chadd cctrl |= CHIPC_CCTRL4331_EXTPA_EN2; 1278e83ce340SAdrian Chadd 1279e83ce340SAdrian Chadd bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1280f90f4b65SLandon J. Fuller return; 1281e83ce340SAdrian Chadd } 1282e83ce340SAdrian Chadd 1283e83ce340SAdrian Chadd /* 4360 devices */ 1284e83ce340SAdrian Chadd if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1285e83ce340SAdrian Chadd /* Unimplemented */ 1286e83ce340SAdrian Chadd } 1287f90f4b65SLandon J. Fuller } 1288e83ce340SAdrian Chadd 1289f90f4b65SLandon J. Fuller static uint32_t 1290f90f4b65SLandon J. Fuller chipc_read_chipst(device_t dev) 1291f90f4b65SLandon J. Fuller { 1292f90f4b65SLandon J. Fuller struct chipc_softc *sc = device_get_softc(dev); 1293f90f4b65SLandon J. Fuller return (bhnd_bus_read_4(sc->core, CHIPC_CHIPST)); 1294e83ce340SAdrian Chadd } 1295e83ce340SAdrian Chadd 12968ef24a0dSAdrian Chadd static void 12978ef24a0dSAdrian Chadd chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask) 12988ef24a0dSAdrian Chadd { 12998ef24a0dSAdrian Chadd struct chipc_softc *sc; 13008ef24a0dSAdrian Chadd uint32_t cctrl; 13018ef24a0dSAdrian Chadd 13028ef24a0dSAdrian Chadd sc = device_get_softc(dev); 13038ef24a0dSAdrian Chadd 13048ef24a0dSAdrian Chadd CHIPC_LOCK(sc); 13058ef24a0dSAdrian Chadd 13068ef24a0dSAdrian Chadd cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 13078ef24a0dSAdrian Chadd cctrl = (cctrl & ~mask) | (value | mask); 13088ef24a0dSAdrian Chadd bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 13098ef24a0dSAdrian Chadd 13108ef24a0dSAdrian Chadd CHIPC_UNLOCK(sc); 13118ef24a0dSAdrian Chadd } 13128ef24a0dSAdrian Chadd 13132b693a88SLandon J. Fuller static struct chipc_caps * 13142b693a88SLandon J. Fuller chipc_get_caps(device_t dev) 13152b693a88SLandon J. Fuller { 13162b693a88SLandon J. Fuller struct chipc_softc *sc; 13172b693a88SLandon J. Fuller 13182b693a88SLandon J. Fuller sc = device_get_softc(dev); 13192b693a88SLandon J. Fuller return (&sc->caps); 13202b693a88SLandon J. Fuller } 13212b693a88SLandon J. Fuller 13224ad7e9b0SAdrian Chadd static device_method_t chipc_methods[] = { 13234ad7e9b0SAdrian Chadd /* Device interface */ 13244ad7e9b0SAdrian Chadd DEVMETHOD(device_probe, chipc_probe), 13254ad7e9b0SAdrian Chadd DEVMETHOD(device_attach, chipc_attach), 13264ad7e9b0SAdrian Chadd DEVMETHOD(device_detach, chipc_detach), 13274ad7e9b0SAdrian Chadd DEVMETHOD(device_suspend, chipc_suspend), 13284ad7e9b0SAdrian Chadd DEVMETHOD(device_resume, chipc_resume), 13294ad7e9b0SAdrian Chadd 1330f4a3eb02SAdrian Chadd /* Bus interface */ 1331f4a3eb02SAdrian Chadd DEVMETHOD(bus_probe_nomatch, chipc_probe_nomatch), 1332f4a3eb02SAdrian Chadd DEVMETHOD(bus_print_child, chipc_print_child), 1333f4a3eb02SAdrian Chadd DEVMETHOD(bus_child_pnpinfo_str, chipc_child_pnpinfo_str), 1334f4a3eb02SAdrian Chadd DEVMETHOD(bus_child_location_str, chipc_child_location_str), 1335f4a3eb02SAdrian Chadd 1336f4a3eb02SAdrian Chadd DEVMETHOD(bus_add_child, chipc_add_child), 1337f4a3eb02SAdrian Chadd DEVMETHOD(bus_child_deleted, chipc_child_deleted), 1338f4a3eb02SAdrian Chadd 1339f4a3eb02SAdrian Chadd DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 1340f4a3eb02SAdrian Chadd DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 1341f4a3eb02SAdrian Chadd DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource), 1342f4a3eb02SAdrian Chadd DEVMETHOD(bus_alloc_resource, chipc_alloc_resource), 1343f4a3eb02SAdrian Chadd DEVMETHOD(bus_release_resource, chipc_release_resource), 1344f4a3eb02SAdrian Chadd DEVMETHOD(bus_adjust_resource, chipc_adjust_resource), 1345f4a3eb02SAdrian Chadd DEVMETHOD(bus_activate_resource, chipc_activate_resource), 1346f4a3eb02SAdrian Chadd DEVMETHOD(bus_deactivate_resource, chipc_deactivate_resource), 1347f4a3eb02SAdrian Chadd DEVMETHOD(bus_get_resource_list, chipc_get_resource_list), 1348f4a3eb02SAdrian Chadd 1349f4a3eb02SAdrian Chadd DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1350f4a3eb02SAdrian Chadd DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1351f4a3eb02SAdrian Chadd DEVMETHOD(bus_config_intr, bus_generic_config_intr), 1352f4a3eb02SAdrian Chadd DEVMETHOD(bus_bind_intr, bus_generic_bind_intr), 1353f4a3eb02SAdrian Chadd DEVMETHOD(bus_describe_intr, bus_generic_describe_intr), 1354f4a3eb02SAdrian Chadd 1355f4a3eb02SAdrian Chadd /* BHND bus inteface */ 1356f4a3eb02SAdrian Chadd DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource), 1357f4a3eb02SAdrian Chadd 13584ad7e9b0SAdrian Chadd /* ChipCommon interface */ 1359f90f4b65SLandon J. Fuller DEVMETHOD(bhnd_chipc_read_chipst, chipc_read_chipst), 13608ef24a0dSAdrian Chadd DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl), 1361f90f4b65SLandon J. Fuller DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom), 1362f90f4b65SLandon J. Fuller DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom), 13632b693a88SLandon J. Fuller DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps), 1364e83ce340SAdrian Chadd 13654ad7e9b0SAdrian Chadd DEVMETHOD_END 13664ad7e9b0SAdrian Chadd }; 13674ad7e9b0SAdrian Chadd 1368f90f4b65SLandon J. Fuller DEFINE_CLASS_0(bhnd_chipc, bhnd_chipc_driver, chipc_methods, sizeof(struct chipc_softc)); 1369f90f4b65SLandon J. Fuller EARLY_DRIVER_MODULE(bhnd_chipc, bhnd, bhnd_chipc_driver, bhnd_chipc_devclass, 0, 0, 1370e129bcd6SLandon J. Fuller BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 137196546b75SAdrian Chadd MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1); 13724ad7e9b0SAdrian Chadd MODULE_VERSION(bhnd_chipc, 1); 1373