1 /*- 2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 3 * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 13 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 14 * redistribution must be conditioned upon including a substantially 15 * similar Disclaimer requirement for further binary redistribution. 16 * 17 * NO WARRANTY 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 21 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 23 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 26 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGES. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * Broadcom ChipCommon driver. 36 * 37 * With the exception of some very early chipsets, the ChipCommon core 38 * has been included in all HND SoCs and chipsets based on the siba(4) 39 * and bcma(4) interconnects, providing a common interface to chipset 40 * identification, bus enumeration, UARTs, clocks, watchdog interrupts, 41 * GPIO, flash, etc. 42 */ 43 44 #include <sys/param.h> 45 #include <sys/kernel.h> 46 #include <sys/lock.h> 47 #include <sys/bus.h> 48 #include <sys/rman.h> 49 #include <sys/malloc.h> 50 #include <sys/module.h> 51 #include <sys/mutex.h> 52 #include <sys/systm.h> 53 54 #include <machine/bus.h> 55 #include <machine/resource.h> 56 57 #include <dev/bhnd/bhnd.h> 58 #include <dev/bhnd/bhndvar.h> 59 60 #include "chipcreg.h" 61 #include "chipcvar.h" 62 63 #include "chipc_private.h" 64 65 devclass_t bhnd_chipc_devclass; /**< bhnd(4) chipcommon device class */ 66 67 static struct bhnd_device_quirk chipc_quirks[]; 68 69 /* Supported device identifiers */ 70 static const struct bhnd_device chipc_devices[] = { 71 BHND_DEVICE(BCM, CC, NULL, chipc_quirks), 72 BHND_DEVICE_END 73 }; 74 75 76 /* Device quirks table */ 77 static struct bhnd_device_quirk chipc_quirks[] = { 78 /* HND OTP controller revisions */ 79 BHND_CORE_QUIRK (HWREV_EQ (12), CHIPC_QUIRK_OTP_HND), /* (?) */ 80 BHND_CORE_QUIRK (HWREV_EQ (17), CHIPC_QUIRK_OTP_HND), /* BCM4311 */ 81 BHND_CORE_QUIRK (HWREV_EQ (22), CHIPC_QUIRK_OTP_HND), /* BCM4312 */ 82 83 /* IPX OTP controller revisions */ 84 BHND_CORE_QUIRK (HWREV_EQ (21), CHIPC_QUIRK_OTP_IPX), 85 BHND_CORE_QUIRK (HWREV_GTE(23), CHIPC_QUIRK_OTP_IPX), 86 87 BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM), 88 BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT), 89 BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPL_SIZE), 90 91 /* 4706 variant quirks */ 92 BHND_CORE_QUIRK (HWREV_EQ (38), CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */ 93 BHND_CHIP_QUIRK (4706, HWREV_ANY, CHIPC_QUIRK_4706_NFLASH), 94 95 /* 4331 quirks*/ 96 BHND_CHIP_QUIRK (4331, HWREV_ANY, CHIPC_QUIRK_4331_EXTPA_MUX_SPROM), 97 BHND_PKG_QUIRK (4331, TN, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 98 BHND_PKG_QUIRK (4331, TNA0, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 99 BHND_PKG_QUIRK (4331, TT, CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM), 100 101 /* 4360 quirks */ 102 BHND_CHIP_QUIRK (4352, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 103 BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 104 BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 105 BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 106 107 BHND_DEVICE_QUIRK_END 108 }; 109 110 // FIXME: IRQ shouldn't be hard-coded 111 #define CHIPC_MIPS_IRQ 2 112 113 static int chipc_add_children(struct chipc_softc *sc); 114 115 static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc, 116 struct chipc_caps *caps); 117 static int chipc_read_caps(struct chipc_softc *sc, 118 struct chipc_caps *caps); 119 120 static bool chipc_should_enable_sprom( 121 struct chipc_softc *sc); 122 123 static int chipc_try_activate_resource( 124 struct chipc_softc *sc, device_t child, 125 int type, int rid, struct resource *r, 126 bool req_direct); 127 128 static int chipc_init_rman(struct chipc_softc *sc); 129 static void chipc_free_rman(struct chipc_softc *sc); 130 static struct rman *chipc_get_rman(struct chipc_softc *sc, 131 int type); 132 133 /* quirk and capability flag convenience macros */ 134 #define CHIPC_QUIRK(_sc, _name) \ 135 ((_sc)->quirks & CHIPC_QUIRK_ ## _name) 136 137 #define CHIPC_CAP(_sc, _name) \ 138 ((_sc)->caps._name) 139 140 #define CHIPC_ASSERT_QUIRK(_sc, name) \ 141 KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set")) 142 143 #define CHIPC_ASSERT_CAP(_sc, name) \ 144 KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set")) 145 146 static int 147 chipc_probe(device_t dev) 148 { 149 const struct bhnd_device *id; 150 151 id = bhnd_device_lookup(dev, chipc_devices, sizeof(chipc_devices[0])); 152 if (id == NULL) 153 return (ENXIO); 154 155 bhnd_set_default_core_desc(dev); 156 return (BUS_PROBE_DEFAULT); 157 } 158 159 static int 160 chipc_attach(device_t dev) 161 { 162 struct chipc_softc *sc; 163 int error; 164 165 sc = device_get_softc(dev); 166 sc->dev = dev; 167 sc->quirks = bhnd_device_quirks(dev, chipc_devices, 168 sizeof(chipc_devices[0])); 169 sc->sprom_refcnt = 0; 170 171 CHIPC_LOCK_INIT(sc); 172 STAILQ_INIT(&sc->mem_regions); 173 174 /* Set up resource management */ 175 if ((error = chipc_init_rman(sc))) { 176 device_printf(sc->dev, 177 "failed to initialize chipc resource state: %d\n", error); 178 goto failed; 179 } 180 181 /* Allocate the region containing the chipc register block */ 182 if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) { 183 error = ENXIO; 184 goto failed; 185 } 186 187 error = chipc_retain_region(sc, sc->core_region, 188 RF_ALLOCATED|RF_ACTIVE); 189 if (error) { 190 sc->core_region = NULL; 191 goto failed; 192 } 193 194 /* Save a direct reference to our chipc registers */ 195 sc->core = sc->core_region->cr_res; 196 197 /* Fetch and parse capability register(s) */ 198 if ((error = chipc_read_caps(sc, &sc->caps))) 199 goto failed; 200 201 if (bootverbose) 202 chipc_print_caps(sc->dev, &sc->caps); 203 204 /* Attach all supported child devices */ 205 if ((error = chipc_add_children(sc))) 206 goto failed; 207 208 if ((error = bus_generic_attach(dev))) 209 goto failed; 210 211 return (0); 212 213 failed: 214 device_delete_children(sc->dev); 215 216 if (sc->core_region != NULL) { 217 chipc_release_region(sc, sc->core_region, 218 RF_ALLOCATED|RF_ACTIVE); 219 } 220 221 chipc_free_rman(sc); 222 CHIPC_LOCK_DESTROY(sc); 223 return (error); 224 } 225 226 static int 227 chipc_detach(device_t dev) 228 { 229 struct chipc_softc *sc; 230 int error; 231 232 sc = device_get_softc(dev); 233 234 if ((error = bus_generic_detach(dev))) 235 return (error); 236 237 chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE); 238 chipc_free_rman(sc); 239 240 CHIPC_LOCK_DESTROY(sc); 241 242 return (0); 243 } 244 245 static int 246 chipc_add_children(struct chipc_softc *sc) 247 { 248 device_t child; 249 const char *flash_bus; 250 int error; 251 252 /* SPROM/OTP */ 253 if (sc->caps.nvram_src == BHND_NVRAM_SRC_SPROM || 254 sc->caps.nvram_src == BHND_NVRAM_SRC_OTP) 255 { 256 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_nvram", -1); 257 if (child == NULL) { 258 device_printf(sc->dev, "failed to add nvram device\n"); 259 return (ENXIO); 260 } 261 262 /* Both OTP and external SPROM are mapped at CHIPC_SPROM_OTP */ 263 error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, 264 CHIPC_SPROM_OTP, CHIPC_SPROM_OTP_SIZE, 0, 0); 265 if (error) 266 return (error); 267 } 268 269 #ifdef notyet 270 /* 271 * PMU/SLOWCLK/INSTACLK 272 * 273 * On AOB ("Always on Bus") devices, a PMU core (if it exists) is 274 * enumerated directly by the bhnd(4) bus -- not chipc. 275 * 276 * Otherwise, we always add a PMU child device, and let the 277 * chipc bhnd_pmu drivers probe for it. If the core supports an 278 * earlier non-PMU clock/power register interface, one of the instaclk, 279 * powerctl, or null bhnd_pmu drivers will claim the device. 280 */ 281 if (!sc->caps.aob || (sc->caps.aob && !sc->caps.pmu)) { 282 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pmu", -1); 283 if (child == NULL) { 284 device_printf(sc->dev, "failed to add pmu\n"); 285 return (ENXIO); 286 } 287 288 /* Associate the applicable register block */ 289 error = 0; 290 if (sc->caps.pmu) { 291 error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, 292 CHIPC_PMU, CHIPC_PMU_SIZE, 0, 0); 293 } else if (sc->caps.power_control) { 294 error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, 295 CHIPC_PWRCTL, CHIPC_PWRCTL_SIZE, 0, 0); 296 } 297 298 if (error) 299 return (error); 300 301 } 302 #endif /* notyet */ 303 304 /* All remaining devices are SoC-only */ 305 if (bhnd_get_attach_type(sc->dev) != BHND_ATTACH_NATIVE) 306 return (0); 307 308 /* UARTs */ 309 for (u_int i = 0; i < min(sc->caps.num_uarts, CHIPC_UART_MAX); i++) { 310 child = BUS_ADD_CHILD(sc->dev, 0, "uart", -1); 311 if (child == NULL) { 312 device_printf(sc->dev, "failed to add uart%u\n", i); 313 return (ENXIO); 314 } 315 316 /* Shared IRQ */ 317 error = bus_set_resource(child, SYS_RES_IRQ, 0, CHIPC_MIPS_IRQ, 318 1); 319 if (error) { 320 device_printf(sc->dev, "failed to set uart%u irq %u\n", 321 i, CHIPC_MIPS_IRQ); 322 return (error); 323 } 324 325 /* UART registers are mapped sequentially */ 326 error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, 327 CHIPC_UART(i), CHIPC_UART_SIZE, 0, 0); 328 if (error) 329 return (error); 330 } 331 332 /* Flash */ 333 flash_bus = chipc_flash_bus_name(sc->caps.flash_type); 334 if (flash_bus != NULL) { 335 child = BUS_ADD_CHILD(sc->dev, 0, flash_bus, -1); 336 if (child == NULL) { 337 device_printf(sc->dev, "failed to add %s device\n", 338 flash_bus); 339 return (ENXIO); 340 } 341 342 /* flash memory mapping */ 343 error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, 344 0, RM_MAX_END, 1, 1); 345 if (error) 346 return (error); 347 348 /* flashctrl registers */ 349 error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 1, 350 CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0, 0); 351 if (error) 352 return (error); 353 } 354 355 return (0); 356 } 357 358 /** 359 * Determine the NVRAM data source for this device. 360 * 361 * The SPROM, OTP, and flash capability flags must be fully populated in 362 * @p caps. 363 * 364 * @param sc chipc driver state. 365 * @param caps capability flags to be used to derive NVRAM configuration. 366 */ 367 static bhnd_nvram_src 368 chipc_find_nvram_src(struct chipc_softc *sc, struct chipc_caps *caps) 369 { 370 uint32_t otp_st, srom_ctrl; 371 372 /* 373 * We check for hardware presence in order of precedence. For example, 374 * SPROM is is always used in preference to internal OTP if found. 375 */ 376 if (CHIPC_QUIRK(sc, SUPPORTS_SPROM) && caps->sprom) { 377 srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL); 378 if (srom_ctrl & CHIPC_SRC_PRESENT) 379 return (BHND_NVRAM_SRC_SPROM); 380 } 381 382 /* Check for programmed OTP H/W subregion (contains SROM data) */ 383 if (CHIPC_QUIRK(sc, SUPPORTS_OTP) && caps->otp_size > 0) { 384 /* TODO: need access to HND-OTP device */ 385 if (!CHIPC_QUIRK(sc, OTP_HND)) { 386 device_printf(sc->dev, 387 "NVRAM unavailable: unsupported OTP controller.\n"); 388 return (BHND_NVRAM_SRC_UNKNOWN); 389 } 390 391 otp_st = bhnd_bus_read_4(sc->core, CHIPC_OTPST); 392 if (otp_st & CHIPC_OTPS_GUP_HW) 393 return (BHND_NVRAM_SRC_OTP); 394 } 395 396 /* Check for flash */ 397 if (caps->flash_type != CHIPC_FLASH_NONE) 398 return (BHND_NVRAM_SRC_FLASH); 399 400 /* No NVRAM hardware capability declared */ 401 return (BHND_NVRAM_SRC_UNKNOWN); 402 } 403 404 /* Read and parse chipc capabilities */ 405 static int 406 chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps) 407 { 408 uint32_t cap_reg; 409 uint32_t cap_ext_reg; 410 uint32_t regval; 411 412 /* Fetch cap registers */ 413 cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES); 414 cap_ext_reg = 0; 415 if (CHIPC_QUIRK(sc, SUPPORTS_CAP_EXT)) 416 cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT); 417 418 /* Extract values */ 419 caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART); 420 caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB); 421 caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO); 422 caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL); 423 424 caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS); 425 caps->power_control = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL); 426 caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP); 427 428 caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL); 429 caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64); 430 caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM); 431 caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU); 432 caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI); 433 caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM); 434 caps->otp_size = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_OTP_SIZE); 435 436 caps->seci = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_SECI); 437 caps->gsio = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_GSIO); 438 caps->aob = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_AOB); 439 440 /* Fetch OTP size for later IPX controller revisions */ 441 if (CHIPC_QUIRK(sc, IPX_OTPL_SIZE)) { 442 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 443 caps->otp_size = CHIPC_GET_BITS(regval, CHIPC_OTPL_SIZE); 444 } 445 446 /* Determine flash type and parameters */ 447 caps->cfi_width = 0; 448 switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) { 449 case CHIPC_CAP_SFLASH_ST: 450 caps->flash_type = CHIPC_SFLASH_ST; 451 break; 452 case CHIPC_CAP_SFLASH_AT: 453 caps->flash_type = CHIPC_SFLASH_AT; 454 break; 455 case CHIPC_CAP_NFLASH: 456 /* unimplemented */ 457 caps->flash_type = CHIPC_NFLASH; 458 break; 459 case CHIPC_CAP_PFLASH: 460 caps->flash_type = CHIPC_PFLASH_CFI; 461 462 /* determine cfi width */ 463 regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG); 464 if (CHIPC_GET_FLAG(regval, CHIPC_FLASH_CFG_DS)) 465 caps->cfi_width = 2; 466 else 467 caps->cfi_width = 1; 468 469 break; 470 case CHIPC_CAP_FLASH_NONE: 471 caps->flash_type = CHIPC_FLASH_NONE; 472 break; 473 474 } 475 476 /* Handle 4706_NFLASH fallback */ 477 if (CHIPC_QUIRK(sc, 4706_NFLASH) && 478 CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_4706_NFLASH)) 479 { 480 caps->flash_type = CHIPC_NFLASH_4706; 481 } 482 483 484 /* Determine NVRAM source. Must occur after the SPROM/OTP/flash 485 * capability flags have been populated. */ 486 caps->nvram_src = chipc_find_nvram_src(sc, caps); 487 488 /* Determine the SPROM offset within OTP (if any). SPROM-formatted 489 * data is placed within the OTP general use region. */ 490 caps->sprom_offset = 0; 491 if (caps->nvram_src == BHND_NVRAM_SRC_OTP) { 492 CHIPC_ASSERT_QUIRK(sc, OTP_IPX); 493 494 /* Bit offset to GUP HW subregion containing SPROM data */ 495 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 496 caps->sprom_offset = CHIPC_GET_BITS(regval, CHIPC_OTPL_GUP); 497 498 /* Convert to bytes */ 499 caps->sprom_offset /= 8; 500 } 501 502 return (0); 503 } 504 505 static int 506 chipc_suspend(device_t dev) 507 { 508 return (bus_generic_suspend(dev)); 509 } 510 511 static int 512 chipc_resume(device_t dev) 513 { 514 return (bus_generic_resume(dev)); 515 } 516 517 static void 518 chipc_probe_nomatch(device_t dev, device_t child) 519 { 520 struct resource_list *rl; 521 const char *name; 522 523 name = device_get_name(child); 524 if (name == NULL) 525 name = "unknown device"; 526 527 device_printf(dev, "<%s> at", name); 528 529 rl = BUS_GET_RESOURCE_LIST(dev, child); 530 if (rl != NULL) { 531 resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 532 resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 533 } 534 535 printf(" (no driver attached)\n"); 536 } 537 538 static int 539 chipc_print_child(device_t dev, device_t child) 540 { 541 struct resource_list *rl; 542 int retval = 0; 543 544 retval += bus_print_child_header(dev, child); 545 546 rl = BUS_GET_RESOURCE_LIST(dev, child); 547 if (rl != NULL) { 548 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, 549 "%#jx"); 550 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, 551 "%jd"); 552 } 553 554 retval += bus_print_child_domain(dev, child); 555 retval += bus_print_child_footer(dev, child); 556 557 return (retval); 558 } 559 560 static int 561 chipc_child_pnpinfo_str(device_t dev, device_t child, char *buf, 562 size_t buflen) 563 { 564 if (buflen == 0) 565 return (EOVERFLOW); 566 567 *buf = '\0'; 568 return (0); 569 } 570 571 static int 572 chipc_child_location_str(device_t dev, device_t child, char *buf, 573 size_t buflen) 574 { 575 if (buflen == 0) 576 return (EOVERFLOW); 577 578 *buf = '\0'; 579 return (ENXIO); 580 } 581 582 static device_t 583 chipc_add_child(device_t dev, u_int order, const char *name, int unit) 584 { 585 struct chipc_softc *sc; 586 struct chipc_devinfo *dinfo; 587 device_t child; 588 589 sc = device_get_softc(dev); 590 591 child = device_add_child_ordered(dev, order, name, unit); 592 if (child == NULL) 593 return (NULL); 594 595 dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT); 596 if (dinfo == NULL) { 597 device_delete_child(dev, child); 598 return (NULL); 599 } 600 601 resource_list_init(&dinfo->resources); 602 device_set_ivars(child, dinfo); 603 604 return (child); 605 } 606 607 static void 608 chipc_child_deleted(device_t dev, device_t child) 609 { 610 struct chipc_devinfo *dinfo = device_get_ivars(child); 611 612 if (dinfo != NULL) { 613 resource_list_free(&dinfo->resources); 614 free(dinfo, M_BHND); 615 } 616 617 device_set_ivars(child, NULL); 618 } 619 620 static struct resource_list * 621 chipc_get_resource_list(device_t dev, device_t child) 622 { 623 struct chipc_devinfo *dinfo = device_get_ivars(child); 624 return (&dinfo->resources); 625 } 626 627 628 /* Allocate region records for the given port, and add the port's memory 629 * range to the mem_rman */ 630 static int 631 chipc_rman_init_regions (struct chipc_softc *sc, bhnd_port_type type, 632 u_int port) 633 { 634 struct chipc_region *cr; 635 rman_res_t start, end; 636 u_int num_regions; 637 int error; 638 639 num_regions = bhnd_get_region_count(sc->dev, type, port); 640 for (u_int region = 0; region < num_regions; region++) { 641 /* Allocate new region record */ 642 cr = chipc_alloc_region(sc, type, port, region); 643 if (cr == NULL) 644 return (ENODEV); 645 646 /* Can't manage regions that cannot be allocated */ 647 if (cr->cr_rid < 0) { 648 BHND_DEBUG_DEV(sc->dev, "no rid for chipc region " 649 "%s%u.%u", bhnd_port_type_name(type), port, region); 650 chipc_free_region(sc, cr); 651 continue; 652 } 653 654 /* Add to rman's managed range */ 655 start = cr->cr_addr; 656 end = cr->cr_end; 657 if ((error = rman_manage_region(&sc->mem_rman, start, end))) { 658 chipc_free_region(sc, cr); 659 return (error); 660 } 661 662 /* Add to region list */ 663 STAILQ_INSERT_TAIL(&sc->mem_regions, cr, cr_link); 664 } 665 666 return (0); 667 } 668 669 /* Initialize memory state for all chipc port regions */ 670 static int 671 chipc_init_rman(struct chipc_softc *sc) 672 { 673 u_int num_ports; 674 int error; 675 676 /* Port types for which we'll register chipc_region mappings */ 677 bhnd_port_type types[] = { 678 BHND_PORT_DEVICE 679 }; 680 681 /* Initialize resource manager */ 682 sc->mem_rman.rm_start = 0; 683 sc->mem_rman.rm_end = BUS_SPACE_MAXADDR; 684 sc->mem_rman.rm_type = RMAN_ARRAY; 685 sc->mem_rman.rm_descr = "ChipCommon Device Memory"; 686 if ((error = rman_init(&sc->mem_rman))) { 687 device_printf(sc->dev, "could not initialize mem_rman: %d\n", 688 error); 689 return (error); 690 } 691 692 /* Populate per-port-region state */ 693 for (u_int i = 0; i < nitems(types); i++) { 694 num_ports = bhnd_get_port_count(sc->dev, types[i]); 695 for (u_int port = 0; port < num_ports; port++) { 696 error = chipc_rman_init_regions(sc, types[i], port); 697 if (error) { 698 device_printf(sc->dev, 699 "region init failed for %s%u: %d\n", 700 bhnd_port_type_name(types[i]), port, 701 error); 702 703 goto failed; 704 } 705 } 706 } 707 708 return (0); 709 710 failed: 711 chipc_free_rman(sc); 712 return (error); 713 } 714 715 /* Free memory management state */ 716 static void 717 chipc_free_rman(struct chipc_softc *sc) 718 { 719 struct chipc_region *cr, *cr_next; 720 721 STAILQ_FOREACH_SAFE(cr, &sc->mem_regions, cr_link, cr_next) 722 chipc_free_region(sc, cr); 723 724 rman_fini(&sc->mem_rman); 725 } 726 727 /** 728 * Return the rman instance for a given resource @p type, if any. 729 * 730 * @param sc The chipc device state. 731 * @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...) 732 */ 733 static struct rman * 734 chipc_get_rman(struct chipc_softc *sc, int type) 735 { 736 switch (type) { 737 case SYS_RES_MEMORY: 738 return (&sc->mem_rman); 739 740 case SYS_RES_IRQ: 741 /* IRQs can be used with RF_SHAREABLE, so we don't perform 742 * any local proxying of resource requests. */ 743 return (NULL); 744 745 default: 746 return (NULL); 747 }; 748 } 749 750 static struct resource * 751 chipc_alloc_resource(device_t dev, device_t child, int type, 752 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 753 { 754 struct chipc_softc *sc; 755 struct chipc_region *cr; 756 struct resource_list_entry *rle; 757 struct resource *rv; 758 struct rman *rm; 759 int error; 760 bool passthrough, isdefault; 761 762 sc = device_get_softc(dev); 763 passthrough = (device_get_parent(child) != dev); 764 isdefault = RMAN_IS_DEFAULT_RANGE(start, end); 765 rle = NULL; 766 767 /* Fetch the resource manager, delegate request if necessary */ 768 rm = chipc_get_rman(sc, type); 769 if (rm == NULL) { 770 /* Requested resource type is delegated to our parent */ 771 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 772 start, end, count, flags); 773 return (rv); 774 } 775 776 /* Populate defaults */ 777 if (!passthrough && isdefault) { 778 /* Fetch the resource list entry. */ 779 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), 780 type, *rid); 781 if (rle == NULL) { 782 device_printf(dev, 783 "default resource %#x type %d for child %s " 784 "not found\n", *rid, type, 785 device_get_nameunit(child)); 786 return (NULL); 787 } 788 789 if (rle->res != NULL) { 790 device_printf(dev, 791 "resource entry %#x type %d for child %s is busy " 792 "[%d]\n", 793 *rid, type, device_get_nameunit(child), 794 rman_get_flags(rle->res)); 795 796 return (NULL); 797 } 798 799 start = rle->start; 800 end = rle->end; 801 count = ulmax(count, rle->count); 802 } 803 804 /* Locate a mapping region */ 805 if ((cr = chipc_find_region(sc, start, end)) == NULL) { 806 /* Resource requests outside our shared port regions can be 807 * delegated to our parent. */ 808 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 809 start, end, count, flags); 810 return (rv); 811 } 812 813 /* Try to retain a region reference */ 814 if ((error = chipc_retain_region(sc, cr, RF_ALLOCATED))) 815 return (NULL); 816 817 /* Make our rman reservation */ 818 rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE, 819 child); 820 if (rv == NULL) { 821 chipc_release_region(sc, cr, RF_ALLOCATED); 822 return (NULL); 823 } 824 825 rman_set_rid(rv, *rid); 826 827 /* Activate */ 828 if (flags & RF_ACTIVE) { 829 error = bus_activate_resource(child, type, *rid, rv); 830 if (error) { 831 device_printf(dev, 832 "failed to activate entry %#x type %d for " 833 "child %s: %d\n", 834 *rid, type, device_get_nameunit(child), error); 835 836 chipc_release_region(sc, cr, RF_ALLOCATED); 837 rman_release_resource(rv); 838 839 return (NULL); 840 } 841 } 842 843 /* Update child's resource list entry */ 844 if (rle != NULL) { 845 rle->res = rv; 846 rle->start = rman_get_start(rv); 847 rle->end = rman_get_end(rv); 848 rle->count = rman_get_size(rv); 849 } 850 851 return (rv); 852 } 853 854 static int 855 chipc_release_resource(device_t dev, device_t child, int type, int rid, 856 struct resource *r) 857 { 858 struct chipc_softc *sc; 859 struct chipc_region *cr; 860 struct rman *rm; 861 struct resource_list_entry *rle; 862 int error; 863 864 sc = device_get_softc(dev); 865 866 /* Handled by parent bus? */ 867 rm = chipc_get_rman(sc, type); 868 if (rm == NULL || !rman_is_region_manager(r, rm)) { 869 return (bus_generic_rl_release_resource(dev, child, type, rid, 870 r)); 871 } 872 873 /* Locate the mapping region */ 874 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 875 if (cr == NULL) 876 return (EINVAL); 877 878 /* Deactivate resources */ 879 if (rman_get_flags(r) & RF_ACTIVE) { 880 error = BUS_DEACTIVATE_RESOURCE(dev, child, type, rid, r); 881 if (error) 882 return (error); 883 } 884 885 if ((error = rman_release_resource(r))) 886 return (error); 887 888 /* Drop allocation reference */ 889 chipc_release_region(sc, cr, RF_ALLOCATED); 890 891 /* Clear reference from the resource list entry if exists */ 892 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), type, rid); 893 if (rle != NULL) 894 rle->res = NULL; 895 896 return (0); 897 } 898 899 static int 900 chipc_adjust_resource(device_t dev, device_t child, int type, 901 struct resource *r, rman_res_t start, rman_res_t end) 902 { 903 struct chipc_softc *sc; 904 struct chipc_region *cr; 905 struct rman *rm; 906 907 sc = device_get_softc(dev); 908 909 /* Handled by parent bus? */ 910 rm = chipc_get_rman(sc, type); 911 if (rm == NULL || !rman_is_region_manager(r, rm)) { 912 return (bus_generic_adjust_resource(dev, child, type, r, start, 913 end)); 914 } 915 916 /* The range is limited to the existing region mapping */ 917 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 918 if (cr == NULL) 919 return (EINVAL); 920 921 if (end <= start) 922 return (EINVAL); 923 924 if (start < cr->cr_addr || end > cr->cr_end) 925 return (EINVAL); 926 927 /* Range falls within the existing region */ 928 return (rman_adjust_resource(r, start, end)); 929 } 930 931 /** 932 * Retain an RF_ACTIVE reference to the region mapping @p r, and 933 * configure @p r with its subregion values. 934 * 935 * @param sc Driver instance state. 936 * @param child Requesting child device. 937 * @param type resource type of @p r. 938 * @param rid resource id of @p r 939 * @param r resource to be activated. 940 * @param req_direct If true, failure to allocate a direct bhnd resource 941 * will be treated as an error. If false, the resource will not be marked 942 * as RF_ACTIVE if bhnd direct resource allocation fails. 943 */ 944 static int 945 chipc_try_activate_resource(struct chipc_softc *sc, device_t child, int type, 946 int rid, struct resource *r, bool req_direct) 947 { 948 struct rman *rm; 949 struct chipc_region *cr; 950 bhnd_size_t cr_offset; 951 rman_res_t r_start, r_end, r_size; 952 int error; 953 954 rm = chipc_get_rman(sc, type); 955 if (rm == NULL || !rman_is_region_manager(r, rm)) 956 return (EINVAL); 957 958 r_start = rman_get_start(r); 959 r_end = rman_get_end(r); 960 r_size = rman_get_size(r); 961 962 /* Find the corresponding chipc region */ 963 cr = chipc_find_region(sc, r_start, r_end); 964 if (cr == NULL) 965 return (EINVAL); 966 967 /* Calculate subregion offset within the chipc region */ 968 cr_offset = r_start - cr->cr_addr; 969 970 /* Retain (and activate, if necessary) the chipc region */ 971 if ((error = chipc_retain_region(sc, cr, RF_ACTIVE))) 972 return (error); 973 974 /* Configure child resource with its subregion values. */ 975 if (cr->cr_res->direct) { 976 error = chipc_init_child_resource(r, cr->cr_res->res, 977 cr_offset, r_size); 978 if (error) 979 goto cleanup; 980 981 /* Mark active */ 982 if ((error = rman_activate_resource(r))) 983 goto cleanup; 984 } else if (req_direct) { 985 error = ENOMEM; 986 goto cleanup; 987 } 988 989 return (0); 990 991 cleanup: 992 chipc_release_region(sc, cr, RF_ACTIVE); 993 return (error); 994 } 995 996 static int 997 chipc_activate_bhnd_resource(device_t dev, device_t child, int type, 998 int rid, struct bhnd_resource *r) 999 { 1000 struct chipc_softc *sc; 1001 struct rman *rm; 1002 int error; 1003 1004 sc = device_get_softc(dev); 1005 1006 /* Delegate non-locally managed resources to parent */ 1007 rm = chipc_get_rman(sc, type); 1008 if (rm == NULL || !rman_is_region_manager(r->res, rm)) { 1009 return (bhnd_bus_generic_activate_resource(dev, child, type, 1010 rid, r)); 1011 } 1012 1013 /* Try activating the chipc region resource */ 1014 error = chipc_try_activate_resource(sc, child, type, rid, r->res, 1015 false); 1016 if (error) 1017 return (error); 1018 1019 /* Mark the child resource as direct according to the returned resource 1020 * state */ 1021 if (rman_get_flags(r->res) & RF_ACTIVE) 1022 r->direct = true; 1023 1024 return (0); 1025 } 1026 1027 static int 1028 chipc_activate_resource(device_t dev, device_t child, int type, int rid, 1029 struct resource *r) 1030 { 1031 struct chipc_softc *sc; 1032 struct rman *rm; 1033 1034 sc = device_get_softc(dev); 1035 1036 /* Delegate non-locally managed resources to parent */ 1037 rm = chipc_get_rman(sc, type); 1038 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1039 return (bus_generic_activate_resource(dev, child, type, rid, 1040 r)); 1041 } 1042 1043 /* Try activating the chipc region-based resource */ 1044 return (chipc_try_activate_resource(sc, child, type, rid, r, true)); 1045 } 1046 1047 /** 1048 * Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE(). 1049 */ 1050 static int 1051 chipc_deactivate_resource(device_t dev, device_t child, int type, 1052 int rid, struct resource *r) 1053 { 1054 struct chipc_softc *sc; 1055 struct chipc_region *cr; 1056 struct rman *rm; 1057 int error; 1058 1059 sc = device_get_softc(dev); 1060 1061 /* Handled by parent bus? */ 1062 rm = chipc_get_rman(sc, type); 1063 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1064 return (bus_generic_deactivate_resource(dev, child, type, rid, 1065 r)); 1066 } 1067 1068 /* Find the corresponding chipc region */ 1069 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 1070 if (cr == NULL) 1071 return (EINVAL); 1072 1073 /* Mark inactive */ 1074 if ((error = rman_deactivate_resource(r))) 1075 return (error); 1076 1077 /* Drop associated RF_ACTIVE reference */ 1078 chipc_release_region(sc, cr, RF_ACTIVE); 1079 1080 return (0); 1081 } 1082 1083 /** 1084 * Examine bus state and make a best effort determination of whether it's 1085 * likely safe to enable the muxed SPROM pins. 1086 * 1087 * On devices that do not use SPROM pin muxing, always returns true. 1088 * 1089 * @param sc chipc driver state. 1090 */ 1091 static bool 1092 chipc_should_enable_sprom(struct chipc_softc *sc) 1093 { 1094 device_t *devs; 1095 device_t hostb; 1096 device_t parent; 1097 int devcount; 1098 int error; 1099 bool result; 1100 1101 mtx_assert(&Giant, MA_OWNED); /* for newbus */ 1102 1103 /* Nothing to do? */ 1104 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1105 return (true); 1106 1107 parent = device_get_parent(sc->dev); 1108 hostb = bhnd_find_hostb_device(parent); 1109 1110 if ((error = device_get_children(parent, &devs, &devcount))) 1111 return (false); 1112 1113 /* Reject any active devices other than ChipCommon, or the 1114 * host bridge (if any). */ 1115 result = true; 1116 for (int i = 0; i < devcount; i++) { 1117 if (devs[i] == hostb || devs[i] == sc->dev) 1118 continue; 1119 1120 if (!device_is_attached(devs[i])) 1121 continue; 1122 1123 if (device_is_suspended(devs[i])) 1124 continue; 1125 1126 /* Active device; assume SPROM is busy */ 1127 result = false; 1128 break; 1129 } 1130 1131 free(devs, M_TEMP); 1132 return (result); 1133 } 1134 1135 /** 1136 * If required by this device, enable access to the SPROM. 1137 * 1138 * @param sc chipc driver state. 1139 */ 1140 static int 1141 chipc_enable_sprom_pins(device_t dev) 1142 { 1143 struct chipc_softc *sc; 1144 uint32_t cctrl; 1145 int error; 1146 1147 sc = device_get_softc(dev); 1148 1149 /* Nothing to do? */ 1150 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1151 return (0); 1152 1153 /* Make sure we're holding Giant for newbus */ 1154 mtx_lock(&Giant); 1155 CHIPC_LOCK(sc); 1156 1157 /* Already enabled? */ 1158 if (sc->sprom_refcnt >= 1) { 1159 error = 0; 1160 goto finished; 1161 } 1162 1163 /* Check whether bus is busy */ 1164 if (!chipc_should_enable_sprom(sc)) { 1165 error = EBUSY; 1166 goto finished; 1167 } 1168 1169 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1170 1171 /* 4331 devices */ 1172 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1173 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN; 1174 1175 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1176 cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1177 1178 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1179 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2; 1180 1181 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1182 error = 0; 1183 goto finished; 1184 } 1185 1186 /* 4360 devices */ 1187 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1188 /* Unimplemented */ 1189 } 1190 1191 /* Refuse to proceed on unsupported devices with muxed SPROM pins */ 1192 device_printf(sc->dev, "muxed sprom lines on unrecognized device\n"); 1193 error = ENXIO; 1194 1195 finished: 1196 /* Bump the reference count */ 1197 if (error == 0) 1198 sc->sprom_refcnt++; 1199 1200 CHIPC_UNLOCK(sc); 1201 mtx_unlock(&Giant); 1202 1203 return (error); 1204 } 1205 1206 /** 1207 * If required by this device, revert any GPIO/pin configuration applied 1208 * to allow SPROM access. 1209 * 1210 * @param sc chipc driver state. 1211 */ 1212 static void 1213 chipc_disable_sprom_pins(device_t dev) 1214 { 1215 struct chipc_softc *sc; 1216 uint32_t cctrl; 1217 1218 sc = device_get_softc(dev); 1219 1220 /* Nothing to do? */ 1221 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1222 return; 1223 1224 CHIPC_LOCK(sc); 1225 1226 /* Check reference count, skip disable if in-use. */ 1227 KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease")); 1228 sc->sprom_refcnt--; 1229 if (sc->sprom_refcnt > 0) 1230 goto finished; 1231 1232 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1233 1234 /* 4331 devices */ 1235 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1236 cctrl |= CHIPC_CCTRL4331_EXTPA_EN; 1237 1238 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1239 cctrl |= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1240 1241 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1242 cctrl |= CHIPC_CCTRL4331_EXTPA_EN2; 1243 1244 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1245 goto finished; 1246 } 1247 1248 /* 4360 devices */ 1249 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1250 /* Unimplemented */ 1251 } 1252 1253 finished: 1254 CHIPC_UNLOCK(sc); 1255 } 1256 1257 static void 1258 chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask) 1259 { 1260 struct chipc_softc *sc; 1261 uint32_t cctrl; 1262 1263 sc = device_get_softc(dev); 1264 1265 CHIPC_LOCK(sc); 1266 1267 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1268 cctrl = (cctrl & ~mask) | (value | mask); 1269 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1270 1271 CHIPC_UNLOCK(sc); 1272 } 1273 1274 static struct chipc_caps * 1275 chipc_get_caps(device_t dev) 1276 { 1277 struct chipc_softc *sc; 1278 1279 sc = device_get_softc(dev); 1280 return (&sc->caps); 1281 } 1282 1283 static device_method_t chipc_methods[] = { 1284 /* Device interface */ 1285 DEVMETHOD(device_probe, chipc_probe), 1286 DEVMETHOD(device_attach, chipc_attach), 1287 DEVMETHOD(device_detach, chipc_detach), 1288 DEVMETHOD(device_suspend, chipc_suspend), 1289 DEVMETHOD(device_resume, chipc_resume), 1290 1291 /* Bus interface */ 1292 DEVMETHOD(bus_probe_nomatch, chipc_probe_nomatch), 1293 DEVMETHOD(bus_print_child, chipc_print_child), 1294 DEVMETHOD(bus_child_pnpinfo_str, chipc_child_pnpinfo_str), 1295 DEVMETHOD(bus_child_location_str, chipc_child_location_str), 1296 1297 DEVMETHOD(bus_add_child, chipc_add_child), 1298 DEVMETHOD(bus_child_deleted, chipc_child_deleted), 1299 1300 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 1301 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 1302 DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource), 1303 DEVMETHOD(bus_alloc_resource, chipc_alloc_resource), 1304 DEVMETHOD(bus_release_resource, chipc_release_resource), 1305 DEVMETHOD(bus_adjust_resource, chipc_adjust_resource), 1306 DEVMETHOD(bus_activate_resource, chipc_activate_resource), 1307 DEVMETHOD(bus_deactivate_resource, chipc_deactivate_resource), 1308 DEVMETHOD(bus_get_resource_list, chipc_get_resource_list), 1309 1310 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1311 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1312 DEVMETHOD(bus_config_intr, bus_generic_config_intr), 1313 DEVMETHOD(bus_bind_intr, bus_generic_bind_intr), 1314 DEVMETHOD(bus_describe_intr, bus_generic_describe_intr), 1315 1316 /* BHND bus inteface */ 1317 DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource), 1318 1319 /* ChipCommon interface */ 1320 DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl), 1321 DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom_pins), 1322 DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom_pins), 1323 DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps), 1324 1325 DEVMETHOD_END 1326 }; 1327 1328 DEFINE_CLASS_0(bhnd_chipc, chipc_driver, chipc_methods, sizeof(struct chipc_softc)); 1329 EARLY_DRIVER_MODULE(bhnd_chipc, bhnd, chipc_driver, bhnd_chipc_devclass, 0, 0, 1330 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 1331 MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1); 1332 MODULE_VERSION(bhnd_chipc, 1); 1333