1 /*- 2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 3 * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com> 4 * Copyright (c) 2017 The FreeBSD Foundation 5 * All rights reserved. 6 * 7 * Portions of this software were developed by Landon Fuller 8 * under sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 18 * redistribution must be conditioned upon including a substantially 19 * similar Disclaimer requirement for further binary redistribution. 20 * 21 * NO WARRANTY 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 25 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 26 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 27 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 30 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGES. 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 /* 39 * Broadcom ChipCommon driver. 40 * 41 * With the exception of some very early chipsets, the ChipCommon core 42 * has been included in all HND SoCs and chipsets based on the siba(4) 43 * and bcma(4) interconnects, providing a common interface to chipset 44 * identification, bus enumeration, UARTs, clocks, watchdog interrupts, 45 * GPIO, flash, etc. 46 */ 47 48 #include <sys/param.h> 49 #include <sys/kernel.h> 50 #include <sys/lock.h> 51 #include <sys/bus.h> 52 #include <sys/rman.h> 53 #include <sys/malloc.h> 54 #include <sys/module.h> 55 #include <sys/mutex.h> 56 #include <sys/systm.h> 57 58 #include <machine/bus.h> 59 #include <machine/resource.h> 60 61 #include <dev/bhnd/bhnd.h> 62 #include <dev/bhnd/bhndvar.h> 63 64 #include "chipcreg.h" 65 #include "chipcvar.h" 66 67 #include "chipc_private.h" 68 69 devclass_t bhnd_chipc_devclass; /**< bhnd(4) chipcommon device class */ 70 71 static struct bhnd_device_quirk chipc_quirks[]; 72 73 /* Supported device identifiers */ 74 static const struct bhnd_device chipc_devices[] = { 75 BHND_DEVICE(BCM, CC, NULL, chipc_quirks), 76 BHND_DEVICE(BCM, 4706_CC, NULL, chipc_quirks), 77 BHND_DEVICE_END 78 }; 79 80 81 /* Device quirks table */ 82 static struct bhnd_device_quirk chipc_quirks[] = { 83 /* HND OTP controller revisions */ 84 BHND_CORE_QUIRK (HWREV_EQ (12), CHIPC_QUIRK_OTP_HND), /* (?) */ 85 BHND_CORE_QUIRK (HWREV_EQ (17), CHIPC_QUIRK_OTP_HND), /* BCM4311 */ 86 BHND_CORE_QUIRK (HWREV_EQ (22), CHIPC_QUIRK_OTP_HND), /* BCM4312 */ 87 88 /* IPX OTP controller revisions */ 89 BHND_CORE_QUIRK (HWREV_EQ (21), CHIPC_QUIRK_OTP_IPX), 90 BHND_CORE_QUIRK (HWREV_GTE(23), CHIPC_QUIRK_OTP_IPX), 91 92 BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM), 93 BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT), 94 BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPL_SIZE), 95 96 /* 4706 variant quirks */ 97 BHND_CORE_QUIRK (HWREV_EQ (38), CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */ 98 BHND_CHIP_QUIRK (4706, HWREV_ANY, CHIPC_QUIRK_4706_NFLASH), 99 100 /* 4331 quirks*/ 101 BHND_CHIP_QUIRK (4331, HWREV_ANY, CHIPC_QUIRK_4331_EXTPA_MUX_SPROM), 102 BHND_PKG_QUIRK (4331, TN, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 103 BHND_PKG_QUIRK (4331, TNA0, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 104 BHND_PKG_QUIRK (4331, TT, CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM), 105 106 /* 4360 quirks */ 107 BHND_CHIP_QUIRK (4352, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 108 BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 109 BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 110 BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 111 112 BHND_DEVICE_QUIRK_END 113 }; 114 115 static int chipc_add_children(struct chipc_softc *sc); 116 117 static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc, 118 struct chipc_caps *caps); 119 static int chipc_read_caps(struct chipc_softc *sc, 120 struct chipc_caps *caps); 121 122 static bool chipc_should_enable_muxed_sprom( 123 struct chipc_softc *sc); 124 static int chipc_enable_otp_power(struct chipc_softc *sc); 125 static void chipc_disable_otp_power(struct chipc_softc *sc); 126 static int chipc_enable_sprom_pins(struct chipc_softc *sc); 127 static void chipc_disable_sprom_pins(struct chipc_softc *sc); 128 129 static int chipc_try_activate_resource(struct chipc_softc *sc, 130 device_t child, int type, int rid, 131 struct resource *r, bool req_direct); 132 133 static int chipc_init_rman(struct chipc_softc *sc); 134 static void chipc_free_rman(struct chipc_softc *sc); 135 static struct rman *chipc_get_rman(struct chipc_softc *sc, int type); 136 137 /* quirk and capability flag convenience macros */ 138 #define CHIPC_QUIRK(_sc, _name) \ 139 ((_sc)->quirks & CHIPC_QUIRK_ ## _name) 140 141 #define CHIPC_CAP(_sc, _name) \ 142 ((_sc)->caps._name) 143 144 #define CHIPC_ASSERT_QUIRK(_sc, name) \ 145 KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set")) 146 147 #define CHIPC_ASSERT_CAP(_sc, name) \ 148 KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set")) 149 150 static int 151 chipc_probe(device_t dev) 152 { 153 const struct bhnd_device *id; 154 155 id = bhnd_device_lookup(dev, chipc_devices, sizeof(chipc_devices[0])); 156 if (id == NULL) 157 return (ENXIO); 158 159 bhnd_set_default_core_desc(dev); 160 return (BUS_PROBE_DEFAULT); 161 } 162 163 static int 164 chipc_attach(device_t dev) 165 { 166 struct chipc_softc *sc; 167 int error; 168 169 sc = device_get_softc(dev); 170 sc->dev = dev; 171 sc->quirks = bhnd_device_quirks(dev, chipc_devices, 172 sizeof(chipc_devices[0])); 173 sc->sprom_refcnt = 0; 174 175 CHIPC_LOCK_INIT(sc); 176 STAILQ_INIT(&sc->mem_regions); 177 178 /* Set up resource management */ 179 if ((error = chipc_init_rman(sc))) { 180 device_printf(sc->dev, 181 "failed to initialize chipc resource state: %d\n", error); 182 goto failed; 183 } 184 185 /* Allocate the region containing the chipc register block */ 186 if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) { 187 error = ENXIO; 188 goto failed; 189 } 190 191 error = chipc_retain_region(sc, sc->core_region, 192 RF_ALLOCATED|RF_ACTIVE); 193 if (error) { 194 sc->core_region = NULL; 195 goto failed; 196 } 197 198 /* Save a direct reference to our chipc registers */ 199 sc->core = sc->core_region->cr_res; 200 201 /* Fetch and parse capability register(s) */ 202 if ((error = chipc_read_caps(sc, &sc->caps))) 203 goto failed; 204 205 if (bootverbose) 206 chipc_print_caps(sc->dev, &sc->caps); 207 208 /* Attach all supported child devices */ 209 if ((error = chipc_add_children(sc))) 210 goto failed; 211 212 /* 213 * Register ourselves with the bus; we're fully initialized and can 214 * response to ChipCommin API requests. 215 * 216 * Since our children may need access to ChipCommon, this must be done 217 * before attaching our children below (via bus_generic_attach). 218 */ 219 if ((error = bhnd_register_provider(dev, BHND_SERVICE_CHIPC))) 220 goto failed; 221 222 if ((error = bus_generic_attach(dev))) 223 goto failed; 224 225 return (0); 226 227 failed: 228 device_delete_children(sc->dev); 229 230 if (sc->core_region != NULL) { 231 chipc_release_region(sc, sc->core_region, 232 RF_ALLOCATED|RF_ACTIVE); 233 } 234 235 chipc_free_rman(sc); 236 CHIPC_LOCK_DESTROY(sc); 237 return (error); 238 } 239 240 static int 241 chipc_detach(device_t dev) 242 { 243 struct chipc_softc *sc; 244 int error; 245 246 sc = device_get_softc(dev); 247 248 if ((error = bus_generic_detach(dev))) 249 return (error); 250 251 if ((error = bhnd_deregister_provider(dev, BHND_SERVICE_ANY))) 252 return (error); 253 254 chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE); 255 chipc_free_rman(sc); 256 257 CHIPC_LOCK_DESTROY(sc); 258 259 return (0); 260 } 261 262 static int 263 chipc_add_children(struct chipc_softc *sc) 264 { 265 device_t child; 266 const char *flash_bus; 267 int error; 268 269 /* SPROM/OTP */ 270 if (sc->caps.nvram_src == BHND_NVRAM_SRC_SPROM || 271 sc->caps.nvram_src == BHND_NVRAM_SRC_OTP) 272 { 273 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_nvram", -1); 274 if (child == NULL) { 275 device_printf(sc->dev, "failed to add nvram device\n"); 276 return (ENXIO); 277 } 278 279 /* Both OTP and external SPROM are mapped at CHIPC_SPROM_OTP */ 280 error = chipc_set_mem_resource(sc, child, 0, CHIPC_SPROM_OTP, 281 CHIPC_SPROM_OTP_SIZE, 0, 0); 282 if (error) { 283 device_printf(sc->dev, "failed to set OTP memory " 284 "resource: %d\n", error); 285 return (error); 286 } 287 } 288 289 /* 290 * PMU/PWR_CTRL 291 * 292 * On AOB ("Always on Bus") devices, the PMU core (if it exists) is 293 * attached directly to the bhnd(4) bus -- not chipc. 294 */ 295 if (sc->caps.pmu && !sc->caps.aob) { 296 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pmu", 0); 297 if (child == NULL) { 298 device_printf(sc->dev, "failed to add pmu\n"); 299 return (ENXIO); 300 } 301 } else if (sc->caps.pwr_ctrl) { 302 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pwrctl", 0); 303 if (child == NULL) { 304 device_printf(sc->dev, "failed to add pwrctl\n"); 305 return (ENXIO); 306 } 307 } 308 309 /* GPIO */ 310 child = BUS_ADD_CHILD(sc->dev, 0, "gpio", 0); 311 if (child == NULL) { 312 device_printf(sc->dev, "failed to add gpio\n"); 313 return (ENXIO); 314 } 315 316 error = chipc_set_mem_resource(sc, child, 0, 0, RM_MAX_END, 0, 0); 317 if (error) { 318 device_printf(sc->dev, "failed to set gpio memory resource: " 319 "%d\n", error); 320 return (error); 321 } 322 323 /* All remaining devices are SoC-only */ 324 if (bhnd_get_attach_type(sc->dev) != BHND_ATTACH_NATIVE) 325 return (0); 326 327 /* UARTs */ 328 for (u_int i = 0; i < min(sc->caps.num_uarts, CHIPC_UART_MAX); i++) { 329 int irq_rid, mem_rid; 330 331 irq_rid = 0; 332 mem_rid = 0; 333 334 child = BUS_ADD_CHILD(sc->dev, 0, "uart", -1); 335 if (child == NULL) { 336 device_printf(sc->dev, "failed to add uart%u\n", i); 337 return (ENXIO); 338 } 339 340 /* Shared IRQ */ 341 error = chipc_set_irq_resource(sc, child, irq_rid, 0); 342 if (error) { 343 device_printf(sc->dev, "failed to set uart%u irq %u\n", 344 i, 0); 345 return (error); 346 } 347 348 /* UART registers are mapped sequentially */ 349 error = chipc_set_mem_resource(sc, child, mem_rid, 350 CHIPC_UART(i), CHIPC_UART_SIZE, 0, 0); 351 if (error) { 352 device_printf(sc->dev, "failed to set uart%u memory " 353 "resource: %d\n", i, error); 354 return (error); 355 } 356 } 357 358 /* Flash */ 359 flash_bus = chipc_flash_bus_name(sc->caps.flash_type); 360 if (flash_bus != NULL) { 361 int rid; 362 363 child = BUS_ADD_CHILD(sc->dev, 0, flash_bus, -1); 364 if (child == NULL) { 365 device_printf(sc->dev, "failed to add %s device\n", 366 flash_bus); 367 return (ENXIO); 368 } 369 370 /* flash memory mapping */ 371 rid = 0; 372 error = chipc_set_mem_resource(sc, child, rid, 0, RM_MAX_END, 1, 373 1); 374 if (error) { 375 device_printf(sc->dev, "failed to set flash memory " 376 "resource %d: %d\n", rid, error); 377 return (error); 378 } 379 380 /* flashctrl registers */ 381 rid++; 382 error = chipc_set_mem_resource(sc, child, rid, 383 CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0, 0); 384 if (error) { 385 device_printf(sc->dev, "failed to set flash memory " 386 "resource %d: %d\n", rid, error); 387 return (error); 388 } 389 } 390 391 return (0); 392 } 393 394 /** 395 * Determine the NVRAM data source for this device. 396 * 397 * The SPROM, OTP, and flash capability flags must be fully populated in 398 * @p caps. 399 * 400 * @param sc chipc driver state. 401 * @param caps capability flags to be used to derive NVRAM configuration. 402 */ 403 static bhnd_nvram_src 404 chipc_find_nvram_src(struct chipc_softc *sc, struct chipc_caps *caps) 405 { 406 uint32_t otp_st, srom_ctrl; 407 408 /* 409 * We check for hardware presence in order of precedence. For example, 410 * SPROM is is always used in preference to internal OTP if found. 411 */ 412 if (CHIPC_QUIRK(sc, SUPPORTS_SPROM) && caps->sprom) { 413 srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL); 414 if (srom_ctrl & CHIPC_SRC_PRESENT) 415 return (BHND_NVRAM_SRC_SPROM); 416 } 417 418 /* Check for programmed OTP H/W subregion (contains SROM data) */ 419 if (CHIPC_QUIRK(sc, SUPPORTS_OTP) && caps->otp_size > 0) { 420 /* TODO: need access to HND-OTP device */ 421 if (!CHIPC_QUIRK(sc, OTP_HND)) { 422 device_printf(sc->dev, 423 "NVRAM unavailable: unsupported OTP controller.\n"); 424 return (BHND_NVRAM_SRC_UNKNOWN); 425 } 426 427 otp_st = bhnd_bus_read_4(sc->core, CHIPC_OTPST); 428 if (otp_st & CHIPC_OTPS_GUP_HW) 429 return (BHND_NVRAM_SRC_OTP); 430 } 431 432 /* Check for flash */ 433 if (caps->flash_type != CHIPC_FLASH_NONE) 434 return (BHND_NVRAM_SRC_FLASH); 435 436 /* No NVRAM hardware capability declared */ 437 return (BHND_NVRAM_SRC_UNKNOWN); 438 } 439 440 /* Read and parse chipc capabilities */ 441 static int 442 chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps) 443 { 444 uint32_t cap_reg; 445 uint32_t cap_ext_reg; 446 uint32_t regval; 447 448 /* Fetch cap registers */ 449 cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES); 450 cap_ext_reg = 0; 451 if (CHIPC_QUIRK(sc, SUPPORTS_CAP_EXT)) 452 cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT); 453 454 /* Extract values */ 455 caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART); 456 caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB); 457 caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO); 458 caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL); 459 460 caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS); 461 caps->pwr_ctrl = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL); 462 caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP); 463 464 caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL); 465 caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64); 466 caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM); 467 caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU); 468 caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI); 469 caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM); 470 caps->otp_size = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_OTP_SIZE); 471 472 caps->seci = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_SECI); 473 caps->gsio = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_GSIO); 474 caps->aob = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_AOB); 475 476 /* Fetch OTP size for later IPX controller revisions */ 477 if (CHIPC_QUIRK(sc, IPX_OTPL_SIZE)) { 478 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 479 caps->otp_size = CHIPC_GET_BITS(regval, CHIPC_OTPL_SIZE); 480 } 481 482 /* Determine flash type and parameters */ 483 caps->cfi_width = 0; 484 switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) { 485 case CHIPC_CAP_SFLASH_ST: 486 caps->flash_type = CHIPC_SFLASH_ST; 487 break; 488 case CHIPC_CAP_SFLASH_AT: 489 caps->flash_type = CHIPC_SFLASH_AT; 490 break; 491 case CHIPC_CAP_NFLASH: 492 /* unimplemented */ 493 caps->flash_type = CHIPC_NFLASH; 494 break; 495 case CHIPC_CAP_PFLASH: 496 caps->flash_type = CHIPC_PFLASH_CFI; 497 498 /* determine cfi width */ 499 regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG); 500 if (CHIPC_GET_FLAG(regval, CHIPC_FLASH_CFG_DS)) 501 caps->cfi_width = 2; 502 else 503 caps->cfi_width = 1; 504 505 break; 506 case CHIPC_CAP_FLASH_NONE: 507 caps->flash_type = CHIPC_FLASH_NONE; 508 break; 509 510 } 511 512 /* Handle 4706_NFLASH fallback */ 513 if (CHIPC_QUIRK(sc, 4706_NFLASH) && 514 CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_4706_NFLASH)) 515 { 516 caps->flash_type = CHIPC_NFLASH_4706; 517 } 518 519 520 /* Determine NVRAM source. Must occur after the SPROM/OTP/flash 521 * capability flags have been populated. */ 522 caps->nvram_src = chipc_find_nvram_src(sc, caps); 523 524 /* Determine the SPROM offset within OTP (if any). SPROM-formatted 525 * data is placed within the OTP general use region. */ 526 caps->sprom_offset = 0; 527 if (caps->nvram_src == BHND_NVRAM_SRC_OTP) { 528 CHIPC_ASSERT_QUIRK(sc, OTP_IPX); 529 530 /* Bit offset to GUP HW subregion containing SPROM data */ 531 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 532 caps->sprom_offset = CHIPC_GET_BITS(regval, CHIPC_OTPL_GUP); 533 534 /* Convert to bytes */ 535 caps->sprom_offset /= 8; 536 } 537 538 return (0); 539 } 540 541 static int 542 chipc_suspend(device_t dev) 543 { 544 return (bus_generic_suspend(dev)); 545 } 546 547 static int 548 chipc_resume(device_t dev) 549 { 550 return (bus_generic_resume(dev)); 551 } 552 553 static void 554 chipc_probe_nomatch(device_t dev, device_t child) 555 { 556 struct resource_list *rl; 557 const char *name; 558 559 name = device_get_name(child); 560 if (name == NULL) 561 name = "unknown device"; 562 563 device_printf(dev, "<%s> at", name); 564 565 rl = BUS_GET_RESOURCE_LIST(dev, child); 566 if (rl != NULL) { 567 resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 568 resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 569 } 570 571 printf(" (no driver attached)\n"); 572 } 573 574 static int 575 chipc_print_child(device_t dev, device_t child) 576 { 577 struct resource_list *rl; 578 int retval = 0; 579 580 retval += bus_print_child_header(dev, child); 581 582 rl = BUS_GET_RESOURCE_LIST(dev, child); 583 if (rl != NULL) { 584 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, 585 "%#jx"); 586 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, 587 "%jd"); 588 } 589 590 retval += bus_print_child_domain(dev, child); 591 retval += bus_print_child_footer(dev, child); 592 593 return (retval); 594 } 595 596 static int 597 chipc_child_pnpinfo_str(device_t dev, device_t child, char *buf, 598 size_t buflen) 599 { 600 if (buflen == 0) 601 return (EOVERFLOW); 602 603 *buf = '\0'; 604 return (0); 605 } 606 607 static int 608 chipc_child_location_str(device_t dev, device_t child, char *buf, 609 size_t buflen) 610 { 611 if (buflen == 0) 612 return (EOVERFLOW); 613 614 *buf = '\0'; 615 return (ENXIO); 616 } 617 618 static device_t 619 chipc_add_child(device_t dev, u_int order, const char *name, int unit) 620 { 621 struct chipc_softc *sc; 622 struct chipc_devinfo *dinfo; 623 device_t child; 624 625 sc = device_get_softc(dev); 626 627 child = device_add_child_ordered(dev, order, name, unit); 628 if (child == NULL) 629 return (NULL); 630 631 dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT); 632 if (dinfo == NULL) { 633 device_delete_child(dev, child); 634 return (NULL); 635 } 636 637 resource_list_init(&dinfo->resources); 638 dinfo->irq_mapped = false; 639 device_set_ivars(child, dinfo); 640 641 return (child); 642 } 643 644 static void 645 chipc_child_deleted(device_t dev, device_t child) 646 { 647 struct chipc_devinfo *dinfo = device_get_ivars(child); 648 649 if (dinfo != NULL) { 650 /* Free the child's resource list */ 651 resource_list_free(&dinfo->resources); 652 653 /* Unmap the child's IRQ */ 654 if (dinfo->irq_mapped) { 655 bhnd_unmap_intr(dev, dinfo->irq); 656 dinfo->irq_mapped = false; 657 } 658 659 free(dinfo, M_BHND); 660 } 661 662 device_set_ivars(child, NULL); 663 } 664 665 static struct resource_list * 666 chipc_get_resource_list(device_t dev, device_t child) 667 { 668 struct chipc_devinfo *dinfo = device_get_ivars(child); 669 return (&dinfo->resources); 670 } 671 672 673 /* Allocate region records for the given port, and add the port's memory 674 * range to the mem_rman */ 675 static int 676 chipc_rman_init_regions (struct chipc_softc *sc, bhnd_port_type type, 677 u_int port) 678 { 679 struct chipc_region *cr; 680 rman_res_t start, end; 681 u_int num_regions; 682 int error; 683 684 num_regions = bhnd_get_region_count(sc->dev, type, port); 685 for (u_int region = 0; region < num_regions; region++) { 686 /* Allocate new region record */ 687 cr = chipc_alloc_region(sc, type, port, region); 688 if (cr == NULL) 689 return (ENODEV); 690 691 /* Can't manage regions that cannot be allocated */ 692 if (cr->cr_rid < 0) { 693 BHND_DEBUG_DEV(sc->dev, "no rid for chipc region " 694 "%s%u.%u", bhnd_port_type_name(type), port, region); 695 chipc_free_region(sc, cr); 696 continue; 697 } 698 699 /* Add to rman's managed range */ 700 start = cr->cr_addr; 701 end = cr->cr_end; 702 if ((error = rman_manage_region(&sc->mem_rman, start, end))) { 703 chipc_free_region(sc, cr); 704 return (error); 705 } 706 707 /* Add to region list */ 708 STAILQ_INSERT_TAIL(&sc->mem_regions, cr, cr_link); 709 } 710 711 return (0); 712 } 713 714 /* Initialize memory state for all chipc port regions */ 715 static int 716 chipc_init_rman(struct chipc_softc *sc) 717 { 718 u_int num_ports; 719 int error; 720 721 /* Port types for which we'll register chipc_region mappings */ 722 bhnd_port_type types[] = { 723 BHND_PORT_DEVICE 724 }; 725 726 /* Initialize resource manager */ 727 sc->mem_rman.rm_start = 0; 728 sc->mem_rman.rm_end = BUS_SPACE_MAXADDR; 729 sc->mem_rman.rm_type = RMAN_ARRAY; 730 sc->mem_rman.rm_descr = "ChipCommon Device Memory"; 731 if ((error = rman_init(&sc->mem_rman))) { 732 device_printf(sc->dev, "could not initialize mem_rman: %d\n", 733 error); 734 return (error); 735 } 736 737 /* Populate per-port-region state */ 738 for (u_int i = 0; i < nitems(types); i++) { 739 num_ports = bhnd_get_port_count(sc->dev, types[i]); 740 for (u_int port = 0; port < num_ports; port++) { 741 error = chipc_rman_init_regions(sc, types[i], port); 742 if (error) { 743 device_printf(sc->dev, 744 "region init failed for %s%u: %d\n", 745 bhnd_port_type_name(types[i]), port, 746 error); 747 748 goto failed; 749 } 750 } 751 } 752 753 return (0); 754 755 failed: 756 chipc_free_rman(sc); 757 return (error); 758 } 759 760 /* Free memory management state */ 761 static void 762 chipc_free_rman(struct chipc_softc *sc) 763 { 764 struct chipc_region *cr, *cr_next; 765 766 STAILQ_FOREACH_SAFE(cr, &sc->mem_regions, cr_link, cr_next) 767 chipc_free_region(sc, cr); 768 769 rman_fini(&sc->mem_rman); 770 } 771 772 /** 773 * Return the rman instance for a given resource @p type, if any. 774 * 775 * @param sc The chipc device state. 776 * @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...) 777 */ 778 static struct rman * 779 chipc_get_rman(struct chipc_softc *sc, int type) 780 { 781 switch (type) { 782 case SYS_RES_MEMORY: 783 return (&sc->mem_rman); 784 785 case SYS_RES_IRQ: 786 /* We delegate IRQ resource management to the parent bus */ 787 return (NULL); 788 789 default: 790 return (NULL); 791 }; 792 } 793 794 static struct resource * 795 chipc_alloc_resource(device_t dev, device_t child, int type, 796 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 797 { 798 struct chipc_softc *sc; 799 struct chipc_region *cr; 800 struct resource_list_entry *rle; 801 struct resource *rv; 802 struct rman *rm; 803 int error; 804 bool passthrough, isdefault; 805 806 sc = device_get_softc(dev); 807 passthrough = (device_get_parent(child) != dev); 808 isdefault = RMAN_IS_DEFAULT_RANGE(start, end); 809 rle = NULL; 810 811 /* Fetch the resource manager, delegate request if necessary */ 812 rm = chipc_get_rman(sc, type); 813 if (rm == NULL) { 814 /* Requested resource type is delegated to our parent */ 815 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 816 start, end, count, flags); 817 return (rv); 818 } 819 820 /* Populate defaults */ 821 if (!passthrough && isdefault) { 822 /* Fetch the resource list entry. */ 823 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), 824 type, *rid); 825 if (rle == NULL) { 826 device_printf(dev, 827 "default resource %#x type %d for child %s " 828 "not found\n", *rid, type, 829 device_get_nameunit(child)); 830 return (NULL); 831 } 832 833 if (rle->res != NULL) { 834 device_printf(dev, 835 "resource entry %#x type %d for child %s is busy " 836 "[%d]\n", 837 *rid, type, device_get_nameunit(child), 838 rman_get_flags(rle->res)); 839 840 return (NULL); 841 } 842 843 start = rle->start; 844 end = rle->end; 845 count = ulmax(count, rle->count); 846 } 847 848 /* Locate a mapping region */ 849 if ((cr = chipc_find_region(sc, start, end)) == NULL) { 850 /* Resource requests outside our shared port regions can be 851 * delegated to our parent. */ 852 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 853 start, end, count, flags); 854 return (rv); 855 } 856 857 /* 858 * As a special case, children that map the complete ChipCommon register 859 * block are delegated to our parent. 860 * 861 * The rman API does not support sharing resources that are not 862 * identical in size; since we allocate subregions to various children, 863 * any children that need to map the entire register block (e.g. because 864 * they require access to discontiguous register ranges) must make the 865 * allocation through our parent, where we hold a compatible 866 * RF_SHAREABLE allocation. 867 */ 868 if (cr == sc->core_region && cr->cr_addr == start && 869 cr->cr_end == end && cr->cr_count == count) 870 { 871 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 872 start, end, count, flags); 873 return (rv); 874 } 875 876 /* Try to retain a region reference */ 877 if ((error = chipc_retain_region(sc, cr, RF_ALLOCATED))) 878 return (NULL); 879 880 /* Make our rman reservation */ 881 rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE, 882 child); 883 if (rv == NULL) { 884 chipc_release_region(sc, cr, RF_ALLOCATED); 885 return (NULL); 886 } 887 888 rman_set_rid(rv, *rid); 889 890 /* Activate */ 891 if (flags & RF_ACTIVE) { 892 error = bus_activate_resource(child, type, *rid, rv); 893 if (error) { 894 device_printf(dev, 895 "failed to activate entry %#x type %d for " 896 "child %s: %d\n", 897 *rid, type, device_get_nameunit(child), error); 898 899 chipc_release_region(sc, cr, RF_ALLOCATED); 900 rman_release_resource(rv); 901 902 return (NULL); 903 } 904 } 905 906 /* Update child's resource list entry */ 907 if (rle != NULL) { 908 rle->res = rv; 909 rle->start = rman_get_start(rv); 910 rle->end = rman_get_end(rv); 911 rle->count = rman_get_size(rv); 912 } 913 914 return (rv); 915 } 916 917 static int 918 chipc_release_resource(device_t dev, device_t child, int type, int rid, 919 struct resource *r) 920 { 921 struct chipc_softc *sc; 922 struct chipc_region *cr; 923 struct rman *rm; 924 struct resource_list_entry *rle; 925 int error; 926 927 sc = device_get_softc(dev); 928 929 /* Handled by parent bus? */ 930 rm = chipc_get_rman(sc, type); 931 if (rm == NULL || !rman_is_region_manager(r, rm)) { 932 return (bus_generic_rl_release_resource(dev, child, type, rid, 933 r)); 934 } 935 936 /* Locate the mapping region */ 937 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 938 if (cr == NULL) 939 return (EINVAL); 940 941 /* Deactivate resources */ 942 if (rman_get_flags(r) & RF_ACTIVE) { 943 error = BUS_DEACTIVATE_RESOURCE(dev, child, type, rid, r); 944 if (error) 945 return (error); 946 } 947 948 if ((error = rman_release_resource(r))) 949 return (error); 950 951 /* Drop allocation reference */ 952 chipc_release_region(sc, cr, RF_ALLOCATED); 953 954 /* Clear reference from the resource list entry if exists */ 955 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), type, rid); 956 if (rle != NULL) 957 rle->res = NULL; 958 959 return (0); 960 } 961 962 static int 963 chipc_adjust_resource(device_t dev, device_t child, int type, 964 struct resource *r, rman_res_t start, rman_res_t end) 965 { 966 struct chipc_softc *sc; 967 struct chipc_region *cr; 968 struct rman *rm; 969 970 sc = device_get_softc(dev); 971 972 /* Handled by parent bus? */ 973 rm = chipc_get_rman(sc, type); 974 if (rm == NULL || !rman_is_region_manager(r, rm)) { 975 return (bus_generic_adjust_resource(dev, child, type, r, start, 976 end)); 977 } 978 979 /* The range is limited to the existing region mapping */ 980 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 981 if (cr == NULL) 982 return (EINVAL); 983 984 if (end <= start) 985 return (EINVAL); 986 987 if (start < cr->cr_addr || end > cr->cr_end) 988 return (EINVAL); 989 990 /* Range falls within the existing region */ 991 return (rman_adjust_resource(r, start, end)); 992 } 993 994 /** 995 * Retain an RF_ACTIVE reference to the region mapping @p r, and 996 * configure @p r with its subregion values. 997 * 998 * @param sc Driver instance state. 999 * @param child Requesting child device. 1000 * @param type resource type of @p r. 1001 * @param rid resource id of @p r 1002 * @param r resource to be activated. 1003 * @param req_direct If true, failure to allocate a direct bhnd resource 1004 * will be treated as an error. If false, the resource will not be marked 1005 * as RF_ACTIVE if bhnd direct resource allocation fails. 1006 */ 1007 static int 1008 chipc_try_activate_resource(struct chipc_softc *sc, device_t child, int type, 1009 int rid, struct resource *r, bool req_direct) 1010 { 1011 struct rman *rm; 1012 struct chipc_region *cr; 1013 bhnd_size_t cr_offset; 1014 rman_res_t r_start, r_end, r_size; 1015 int error; 1016 1017 rm = chipc_get_rman(sc, type); 1018 if (rm == NULL || !rman_is_region_manager(r, rm)) 1019 return (EINVAL); 1020 1021 r_start = rman_get_start(r); 1022 r_end = rman_get_end(r); 1023 r_size = rman_get_size(r); 1024 1025 /* Find the corresponding chipc region */ 1026 cr = chipc_find_region(sc, r_start, r_end); 1027 if (cr == NULL) 1028 return (EINVAL); 1029 1030 /* Calculate subregion offset within the chipc region */ 1031 cr_offset = r_start - cr->cr_addr; 1032 1033 /* Retain (and activate, if necessary) the chipc region */ 1034 if ((error = chipc_retain_region(sc, cr, RF_ACTIVE))) 1035 return (error); 1036 1037 /* Configure child resource with its subregion values. */ 1038 if (cr->cr_res->direct) { 1039 error = chipc_init_child_resource(r, cr->cr_res->res, 1040 cr_offset, r_size); 1041 if (error) 1042 goto cleanup; 1043 1044 /* Mark active */ 1045 if ((error = rman_activate_resource(r))) 1046 goto cleanup; 1047 } else if (req_direct) { 1048 error = ENOMEM; 1049 goto cleanup; 1050 } 1051 1052 return (0); 1053 1054 cleanup: 1055 chipc_release_region(sc, cr, RF_ACTIVE); 1056 return (error); 1057 } 1058 1059 static int 1060 chipc_activate_bhnd_resource(device_t dev, device_t child, int type, 1061 int rid, struct bhnd_resource *r) 1062 { 1063 struct chipc_softc *sc; 1064 struct rman *rm; 1065 int error; 1066 1067 sc = device_get_softc(dev); 1068 1069 /* Delegate non-locally managed resources to parent */ 1070 rm = chipc_get_rman(sc, type); 1071 if (rm == NULL || !rman_is_region_manager(r->res, rm)) { 1072 return (bhnd_bus_generic_activate_resource(dev, child, type, 1073 rid, r)); 1074 } 1075 1076 /* Try activating the chipc region resource */ 1077 error = chipc_try_activate_resource(sc, child, type, rid, r->res, 1078 false); 1079 if (error) 1080 return (error); 1081 1082 /* Mark the child resource as direct according to the returned resource 1083 * state */ 1084 if (rman_get_flags(r->res) & RF_ACTIVE) 1085 r->direct = true; 1086 1087 return (0); 1088 } 1089 1090 static int 1091 chipc_activate_resource(device_t dev, device_t child, int type, int rid, 1092 struct resource *r) 1093 { 1094 struct chipc_softc *sc; 1095 struct rman *rm; 1096 1097 sc = device_get_softc(dev); 1098 1099 /* Delegate non-locally managed resources to parent */ 1100 rm = chipc_get_rman(sc, type); 1101 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1102 return (bus_generic_activate_resource(dev, child, type, rid, 1103 r)); 1104 } 1105 1106 /* Try activating the chipc region-based resource */ 1107 return (chipc_try_activate_resource(sc, child, type, rid, r, true)); 1108 } 1109 1110 /** 1111 * Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE(). 1112 */ 1113 static int 1114 chipc_deactivate_resource(device_t dev, device_t child, int type, 1115 int rid, struct resource *r) 1116 { 1117 struct chipc_softc *sc; 1118 struct chipc_region *cr; 1119 struct rman *rm; 1120 int error; 1121 1122 sc = device_get_softc(dev); 1123 1124 /* Handled by parent bus? */ 1125 rm = chipc_get_rman(sc, type); 1126 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1127 return (bus_generic_deactivate_resource(dev, child, type, rid, 1128 r)); 1129 } 1130 1131 /* Find the corresponding chipc region */ 1132 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 1133 if (cr == NULL) 1134 return (EINVAL); 1135 1136 /* Mark inactive */ 1137 if ((error = rman_deactivate_resource(r))) 1138 return (error); 1139 1140 /* Drop associated RF_ACTIVE reference */ 1141 chipc_release_region(sc, cr, RF_ACTIVE); 1142 1143 return (0); 1144 } 1145 1146 /** 1147 * Examine bus state and make a best effort determination of whether it's 1148 * likely safe to enable the muxed SPROM pins. 1149 * 1150 * On devices that do not use SPROM pin muxing, always returns true. 1151 * 1152 * @param sc chipc driver state. 1153 */ 1154 static bool 1155 chipc_should_enable_muxed_sprom(struct chipc_softc *sc) 1156 { 1157 device_t *devs; 1158 device_t hostb; 1159 device_t parent; 1160 int devcount; 1161 int error; 1162 bool result; 1163 1164 /* Nothing to do? */ 1165 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1166 return (true); 1167 1168 mtx_lock(&Giant); /* for newbus */ 1169 1170 parent = device_get_parent(sc->dev); 1171 hostb = bhnd_bus_find_hostb_device(parent); 1172 1173 if ((error = device_get_children(parent, &devs, &devcount))) { 1174 mtx_unlock(&Giant); 1175 return (false); 1176 } 1177 1178 /* Reject any active devices other than ChipCommon, or the 1179 * host bridge (if any). */ 1180 result = true; 1181 for (int i = 0; i < devcount; i++) { 1182 if (devs[i] == hostb || devs[i] == sc->dev) 1183 continue; 1184 1185 if (!device_is_attached(devs[i])) 1186 continue; 1187 1188 if (device_is_suspended(devs[i])) 1189 continue; 1190 1191 /* Active device; assume SPROM is busy */ 1192 result = false; 1193 break; 1194 } 1195 1196 free(devs, M_TEMP); 1197 mtx_unlock(&Giant); 1198 return (result); 1199 } 1200 1201 static int 1202 chipc_enable_sprom(device_t dev) 1203 { 1204 struct chipc_softc *sc; 1205 int error; 1206 1207 sc = device_get_softc(dev); 1208 CHIPC_LOCK(sc); 1209 1210 /* Already enabled? */ 1211 if (sc->sprom_refcnt >= 1) { 1212 sc->sprom_refcnt++; 1213 CHIPC_UNLOCK(sc); 1214 1215 return (0); 1216 } 1217 1218 switch (sc->caps.nvram_src) { 1219 case BHND_NVRAM_SRC_SPROM: 1220 error = chipc_enable_sprom_pins(sc); 1221 break; 1222 case BHND_NVRAM_SRC_OTP: 1223 error = chipc_enable_otp_power(sc); 1224 break; 1225 default: 1226 error = 0; 1227 break; 1228 } 1229 1230 /* Bump the reference count */ 1231 if (error == 0) 1232 sc->sprom_refcnt++; 1233 1234 CHIPC_UNLOCK(sc); 1235 return (error); 1236 } 1237 1238 static void 1239 chipc_disable_sprom(device_t dev) 1240 { 1241 struct chipc_softc *sc; 1242 1243 sc = device_get_softc(dev); 1244 CHIPC_LOCK(sc); 1245 1246 /* Check reference count, skip disable if in-use. */ 1247 KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease")); 1248 sc->sprom_refcnt--; 1249 if (sc->sprom_refcnt > 0) { 1250 CHIPC_UNLOCK(sc); 1251 return; 1252 } 1253 1254 switch (sc->caps.nvram_src) { 1255 case BHND_NVRAM_SRC_SPROM: 1256 chipc_disable_sprom_pins(sc); 1257 break; 1258 case BHND_NVRAM_SRC_OTP: 1259 chipc_disable_otp_power(sc); 1260 break; 1261 default: 1262 break; 1263 } 1264 1265 1266 CHIPC_UNLOCK(sc); 1267 } 1268 1269 static int 1270 chipc_enable_otp_power(struct chipc_softc *sc) 1271 { 1272 // TODO: Enable OTP resource via PMU, and wait up to 100 usec for 1273 // OTPS_READY to be set in `optstatus`. 1274 return (0); 1275 } 1276 1277 static void 1278 chipc_disable_otp_power(struct chipc_softc *sc) 1279 { 1280 // TODO: Disable OTP resource via PMU 1281 } 1282 1283 /** 1284 * If required by this device, enable access to the SPROM. 1285 * 1286 * @param sc chipc driver state. 1287 */ 1288 static int 1289 chipc_enable_sprom_pins(struct chipc_softc *sc) 1290 { 1291 uint32_t cctrl; 1292 1293 CHIPC_LOCK_ASSERT(sc, MA_OWNED); 1294 KASSERT(sc->sprom_refcnt == 0, ("sprom pins already enabled")); 1295 1296 /* Nothing to do? */ 1297 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1298 return (0); 1299 1300 /* Check whether bus is busy */ 1301 if (!chipc_should_enable_muxed_sprom(sc)) 1302 return (EBUSY); 1303 1304 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1305 1306 /* 4331 devices */ 1307 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1308 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN; 1309 1310 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1311 cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1312 1313 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1314 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2; 1315 1316 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1317 return (0); 1318 } 1319 1320 /* 4360 devices */ 1321 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1322 /* Unimplemented */ 1323 } 1324 1325 /* Refuse to proceed on unsupported devices with muxed SPROM pins */ 1326 device_printf(sc->dev, "muxed sprom lines on unrecognized device\n"); 1327 return (ENXIO); 1328 } 1329 1330 /** 1331 * If required by this device, revert any GPIO/pin configuration applied 1332 * to allow SPROM access. 1333 * 1334 * @param sc chipc driver state. 1335 */ 1336 static void 1337 chipc_disable_sprom_pins(struct chipc_softc *sc) 1338 { 1339 uint32_t cctrl; 1340 1341 /* Nothing to do? */ 1342 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1343 return; 1344 1345 CHIPC_LOCK_ASSERT(sc, MA_OWNED); 1346 KASSERT(sc->sprom_refcnt == 0, ("sprom pins in use")); 1347 1348 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1349 1350 /* 4331 devices */ 1351 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1352 cctrl |= CHIPC_CCTRL4331_EXTPA_EN; 1353 1354 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1355 cctrl |= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1356 1357 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1358 cctrl |= CHIPC_CCTRL4331_EXTPA_EN2; 1359 1360 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1361 return; 1362 } 1363 1364 /* 4360 devices */ 1365 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1366 /* Unimplemented */ 1367 } 1368 } 1369 1370 static uint32_t 1371 chipc_read_chipst(device_t dev) 1372 { 1373 struct chipc_softc *sc = device_get_softc(dev); 1374 return (bhnd_bus_read_4(sc->core, CHIPC_CHIPST)); 1375 } 1376 1377 static void 1378 chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask) 1379 { 1380 struct chipc_softc *sc; 1381 uint32_t cctrl; 1382 1383 sc = device_get_softc(dev); 1384 1385 CHIPC_LOCK(sc); 1386 1387 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1388 cctrl = (cctrl & ~mask) | (value | mask); 1389 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1390 1391 CHIPC_UNLOCK(sc); 1392 } 1393 1394 static struct chipc_caps * 1395 chipc_get_caps(device_t dev) 1396 { 1397 struct chipc_softc *sc; 1398 1399 sc = device_get_softc(dev); 1400 return (&sc->caps); 1401 } 1402 1403 static device_method_t chipc_methods[] = { 1404 /* Device interface */ 1405 DEVMETHOD(device_probe, chipc_probe), 1406 DEVMETHOD(device_attach, chipc_attach), 1407 DEVMETHOD(device_detach, chipc_detach), 1408 DEVMETHOD(device_suspend, chipc_suspend), 1409 DEVMETHOD(device_resume, chipc_resume), 1410 1411 /* Bus interface */ 1412 DEVMETHOD(bus_probe_nomatch, chipc_probe_nomatch), 1413 DEVMETHOD(bus_print_child, chipc_print_child), 1414 DEVMETHOD(bus_child_pnpinfo_str, chipc_child_pnpinfo_str), 1415 DEVMETHOD(bus_child_location_str, chipc_child_location_str), 1416 1417 DEVMETHOD(bus_add_child, chipc_add_child), 1418 DEVMETHOD(bus_child_deleted, chipc_child_deleted), 1419 1420 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 1421 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 1422 DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource), 1423 DEVMETHOD(bus_alloc_resource, chipc_alloc_resource), 1424 DEVMETHOD(bus_release_resource, chipc_release_resource), 1425 DEVMETHOD(bus_adjust_resource, chipc_adjust_resource), 1426 DEVMETHOD(bus_activate_resource, chipc_activate_resource), 1427 DEVMETHOD(bus_deactivate_resource, chipc_deactivate_resource), 1428 DEVMETHOD(bus_get_resource_list, chipc_get_resource_list), 1429 1430 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1431 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1432 DEVMETHOD(bus_config_intr, bus_generic_config_intr), 1433 DEVMETHOD(bus_bind_intr, bus_generic_bind_intr), 1434 DEVMETHOD(bus_describe_intr, bus_generic_describe_intr), 1435 1436 /* BHND bus inteface */ 1437 DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource), 1438 1439 /* ChipCommon interface */ 1440 DEVMETHOD(bhnd_chipc_read_chipst, chipc_read_chipst), 1441 DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl), 1442 DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom), 1443 DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom), 1444 DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps), 1445 1446 DEVMETHOD_END 1447 }; 1448 1449 DEFINE_CLASS_0(bhnd_chipc, bhnd_chipc_driver, chipc_methods, sizeof(struct chipc_softc)); 1450 EARLY_DRIVER_MODULE(bhnd_chipc, bhnd, bhnd_chipc_driver, bhnd_chipc_devclass, 0, 0, 1451 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 1452 MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1); 1453 MODULE_VERSION(bhnd_chipc, 1); 1454