1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 5 * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com> 6 * Copyright (c) 2017 The FreeBSD Foundation 7 * All rights reserved. 8 * 9 * Portions of this software were developed by Landon Fuller 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer, 17 * without modification. 18 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 19 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 20 * redistribution must be conditioned upon including a substantially 21 * similar Disclaimer requirement for further binary redistribution. 22 * 23 * NO WARRANTY 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGES. 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 /* 41 * Broadcom ChipCommon driver. 42 * 43 * With the exception of some very early chipsets, the ChipCommon core 44 * has been included in all HND SoCs and chipsets based on the siba(4) 45 * and bcma(4) interconnects, providing a common interface to chipset 46 * identification, bus enumeration, UARTs, clocks, watchdog interrupts, 47 * GPIO, flash, etc. 48 */ 49 50 #include <sys/param.h> 51 #include <sys/kernel.h> 52 #include <sys/lock.h> 53 #include <sys/bus.h> 54 #include <sys/rman.h> 55 #include <sys/malloc.h> 56 #include <sys/module.h> 57 #include <sys/mutex.h> 58 #include <sys/systm.h> 59 60 #include <machine/bus.h> 61 #include <machine/resource.h> 62 63 #include <dev/bhnd/bhnd.h> 64 #include <dev/bhnd/bhndvar.h> 65 66 #include "chipcreg.h" 67 #include "chipcvar.h" 68 69 #include "chipc_private.h" 70 71 devclass_t bhnd_chipc_devclass; /**< bhnd(4) chipcommon device class */ 72 73 static struct bhnd_device_quirk chipc_quirks[]; 74 75 /* Supported device identifiers */ 76 static const struct bhnd_device chipc_devices[] = { 77 BHND_DEVICE(BCM, CC, NULL, chipc_quirks), 78 BHND_DEVICE(BCM, 4706_CC, NULL, chipc_quirks), 79 BHND_DEVICE_END 80 }; 81 82 /* Device quirks table */ 83 static struct bhnd_device_quirk chipc_quirks[] = { 84 /* HND OTP controller revisions */ 85 BHND_CORE_QUIRK (HWREV_EQ (12), CHIPC_QUIRK_OTP_HND), /* (?) */ 86 BHND_CORE_QUIRK (HWREV_EQ (17), CHIPC_QUIRK_OTP_HND), /* BCM4311 */ 87 BHND_CORE_QUIRK (HWREV_EQ (22), CHIPC_QUIRK_OTP_HND), /* BCM4312 */ 88 89 /* IPX OTP controller revisions */ 90 BHND_CORE_QUIRK (HWREV_EQ (21), CHIPC_QUIRK_OTP_IPX), 91 BHND_CORE_QUIRK (HWREV_GTE(23), CHIPC_QUIRK_OTP_IPX), 92 93 BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM), 94 BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT), 95 BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPL_SIZE), 96 97 /* 4706 variant quirks */ 98 BHND_CORE_QUIRK (HWREV_EQ (38), CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */ 99 BHND_CHIP_QUIRK (4706, HWREV_ANY, CHIPC_QUIRK_4706_NFLASH), 100 101 /* 4331 quirks*/ 102 BHND_CHIP_QUIRK (4331, HWREV_ANY, CHIPC_QUIRK_4331_EXTPA_MUX_SPROM), 103 BHND_PKG_QUIRK (4331, TN, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 104 BHND_PKG_QUIRK (4331, TNA0, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 105 BHND_PKG_QUIRK (4331, TT, CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM), 106 107 /* 4360 quirks */ 108 BHND_CHIP_QUIRK (4352, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 109 BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 110 BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 111 BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 112 113 BHND_DEVICE_QUIRK_END 114 }; 115 116 static int chipc_add_children(struct chipc_softc *sc); 117 118 static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc, 119 struct chipc_caps *caps); 120 static int chipc_read_caps(struct chipc_softc *sc, 121 struct chipc_caps *caps); 122 123 static bool chipc_should_enable_muxed_sprom( 124 struct chipc_softc *sc); 125 static int chipc_enable_otp_power(struct chipc_softc *sc); 126 static void chipc_disable_otp_power(struct chipc_softc *sc); 127 static int chipc_enable_sprom_pins(struct chipc_softc *sc); 128 static void chipc_disable_sprom_pins(struct chipc_softc *sc); 129 130 static int chipc_try_activate_resource(struct chipc_softc *sc, 131 device_t child, int type, int rid, 132 struct resource *r, bool req_direct); 133 134 static int chipc_init_rman(struct chipc_softc *sc); 135 static void chipc_free_rman(struct chipc_softc *sc); 136 static struct rman *chipc_get_rman(struct chipc_softc *sc, int type); 137 138 /* quirk and capability flag convenience macros */ 139 #define CHIPC_QUIRK(_sc, _name) \ 140 ((_sc)->quirks & CHIPC_QUIRK_ ## _name) 141 142 #define CHIPC_CAP(_sc, _name) \ 143 ((_sc)->caps._name) 144 145 #define CHIPC_ASSERT_QUIRK(_sc, name) \ 146 KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set")) 147 148 #define CHIPC_ASSERT_CAP(_sc, name) \ 149 KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set")) 150 151 static int 152 chipc_probe(device_t dev) 153 { 154 const struct bhnd_device *id; 155 156 id = bhnd_device_lookup(dev, chipc_devices, sizeof(chipc_devices[0])); 157 if (id == NULL) 158 return (ENXIO); 159 160 bhnd_set_default_core_desc(dev); 161 return (BUS_PROBE_DEFAULT); 162 } 163 164 static int 165 chipc_attach(device_t dev) 166 { 167 struct chipc_softc *sc; 168 int error; 169 170 sc = device_get_softc(dev); 171 sc->dev = dev; 172 sc->quirks = bhnd_device_quirks(dev, chipc_devices, 173 sizeof(chipc_devices[0])); 174 sc->sprom_refcnt = 0; 175 176 CHIPC_LOCK_INIT(sc); 177 STAILQ_INIT(&sc->mem_regions); 178 179 /* Set up resource management */ 180 if ((error = chipc_init_rman(sc))) { 181 device_printf(sc->dev, 182 "failed to initialize chipc resource state: %d\n", error); 183 goto failed; 184 } 185 186 /* Allocate the region containing the chipc register block */ 187 if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) { 188 error = ENXIO; 189 goto failed; 190 } 191 192 error = chipc_retain_region(sc, sc->core_region, 193 RF_ALLOCATED|RF_ACTIVE); 194 if (error) { 195 sc->core_region = NULL; 196 goto failed; 197 } 198 199 /* Save a direct reference to our chipc registers */ 200 sc->core = sc->core_region->cr_res; 201 202 /* Fetch and parse capability register(s) */ 203 if ((error = chipc_read_caps(sc, &sc->caps))) 204 goto failed; 205 206 if (bootverbose) 207 chipc_print_caps(sc->dev, &sc->caps); 208 209 /* Attach all supported child devices */ 210 if ((error = chipc_add_children(sc))) 211 goto failed; 212 213 /* 214 * Register ourselves with the bus; we're fully initialized and can 215 * response to ChipCommin API requests. 216 * 217 * Since our children may need access to ChipCommon, this must be done 218 * before attaching our children below (via bus_generic_attach). 219 */ 220 if ((error = bhnd_register_provider(dev, BHND_SERVICE_CHIPC))) 221 goto failed; 222 223 if ((error = bus_generic_attach(dev))) 224 goto failed; 225 226 return (0); 227 228 failed: 229 device_delete_children(sc->dev); 230 231 if (sc->core_region != NULL) { 232 chipc_release_region(sc, sc->core_region, 233 RF_ALLOCATED|RF_ACTIVE); 234 } 235 236 chipc_free_rman(sc); 237 CHIPC_LOCK_DESTROY(sc); 238 return (error); 239 } 240 241 static int 242 chipc_detach(device_t dev) 243 { 244 struct chipc_softc *sc; 245 int error; 246 247 sc = device_get_softc(dev); 248 249 if ((error = bus_generic_detach(dev))) 250 return (error); 251 252 if ((error = device_delete_children(dev))) 253 return (error); 254 255 if ((error = bhnd_deregister_provider(dev, BHND_SERVICE_ANY))) 256 return (error); 257 258 chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE); 259 chipc_free_rman(sc); 260 261 CHIPC_LOCK_DESTROY(sc); 262 263 return (0); 264 } 265 266 static int 267 chipc_add_children(struct chipc_softc *sc) 268 { 269 device_t child; 270 const char *flash_bus; 271 int error; 272 273 /* SPROM/OTP */ 274 if (sc->caps.nvram_src == BHND_NVRAM_SRC_SPROM || 275 sc->caps.nvram_src == BHND_NVRAM_SRC_OTP) 276 { 277 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_nvram", -1); 278 if (child == NULL) { 279 device_printf(sc->dev, "failed to add nvram device\n"); 280 return (ENXIO); 281 } 282 283 /* Both OTP and external SPROM are mapped at CHIPC_SPROM_OTP */ 284 error = chipc_set_mem_resource(sc, child, 0, CHIPC_SPROM_OTP, 285 CHIPC_SPROM_OTP_SIZE, 0, 0); 286 if (error) { 287 device_printf(sc->dev, "failed to set OTP memory " 288 "resource: %d\n", error); 289 return (error); 290 } 291 } 292 293 /* 294 * PMU/PWR_CTRL 295 * 296 * On AOB ("Always on Bus") devices, the PMU core (if it exists) is 297 * attached directly to the bhnd(4) bus -- not chipc. 298 */ 299 if (sc->caps.pmu && !sc->caps.aob) { 300 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pmu", -1); 301 if (child == NULL) { 302 device_printf(sc->dev, "failed to add pmu\n"); 303 return (ENXIO); 304 } 305 } else if (sc->caps.pwr_ctrl) { 306 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pwrctl", -1); 307 if (child == NULL) { 308 device_printf(sc->dev, "failed to add pwrctl\n"); 309 return (ENXIO); 310 } 311 } 312 313 /* GPIO */ 314 child = BUS_ADD_CHILD(sc->dev, 0, "gpio", -1); 315 if (child == NULL) { 316 device_printf(sc->dev, "failed to add gpio\n"); 317 return (ENXIO); 318 } 319 320 error = chipc_set_mem_resource(sc, child, 0, 0, RM_MAX_END, 0, 0); 321 if (error) { 322 device_printf(sc->dev, "failed to set gpio memory resource: " 323 "%d\n", error); 324 return (error); 325 } 326 327 /* All remaining devices are SoC-only */ 328 if (bhnd_get_attach_type(sc->dev) != BHND_ATTACH_NATIVE) 329 return (0); 330 331 /* UARTs */ 332 for (u_int i = 0; i < min(sc->caps.num_uarts, CHIPC_UART_MAX); i++) { 333 int irq_rid, mem_rid; 334 335 irq_rid = 0; 336 mem_rid = 0; 337 338 child = BUS_ADD_CHILD(sc->dev, 0, "uart", -1); 339 if (child == NULL) { 340 device_printf(sc->dev, "failed to add uart%u\n", i); 341 return (ENXIO); 342 } 343 344 /* Shared IRQ */ 345 error = chipc_set_irq_resource(sc, child, irq_rid, 0); 346 if (error) { 347 device_printf(sc->dev, "failed to set uart%u irq %u\n", 348 i, 0); 349 return (error); 350 } 351 352 /* UART registers are mapped sequentially */ 353 error = chipc_set_mem_resource(sc, child, mem_rid, 354 CHIPC_UART(i), CHIPC_UART_SIZE, 0, 0); 355 if (error) { 356 device_printf(sc->dev, "failed to set uart%u memory " 357 "resource: %d\n", i, error); 358 return (error); 359 } 360 } 361 362 /* Flash */ 363 flash_bus = chipc_flash_bus_name(sc->caps.flash_type); 364 if (flash_bus != NULL) { 365 int rid; 366 367 child = BUS_ADD_CHILD(sc->dev, 0, flash_bus, -1); 368 if (child == NULL) { 369 device_printf(sc->dev, "failed to add %s device\n", 370 flash_bus); 371 return (ENXIO); 372 } 373 374 /* flash memory mapping */ 375 rid = 0; 376 error = chipc_set_mem_resource(sc, child, rid, 0, RM_MAX_END, 1, 377 1); 378 if (error) { 379 device_printf(sc->dev, "failed to set flash memory " 380 "resource %d: %d\n", rid, error); 381 return (error); 382 } 383 384 /* flashctrl registers */ 385 rid++; 386 error = chipc_set_mem_resource(sc, child, rid, 387 CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0, 0); 388 if (error) { 389 device_printf(sc->dev, "failed to set flash memory " 390 "resource %d: %d\n", rid, error); 391 return (error); 392 } 393 } 394 395 return (0); 396 } 397 398 /** 399 * Determine the NVRAM data source for this device. 400 * 401 * The SPROM, OTP, and flash capability flags must be fully populated in 402 * @p caps. 403 * 404 * @param sc chipc driver state. 405 * @param caps capability flags to be used to derive NVRAM configuration. 406 */ 407 static bhnd_nvram_src 408 chipc_find_nvram_src(struct chipc_softc *sc, struct chipc_caps *caps) 409 { 410 uint32_t otp_st, srom_ctrl; 411 412 /* 413 * We check for hardware presence in order of precedence. For example, 414 * SPROM is is always used in preference to internal OTP if found. 415 */ 416 if (CHIPC_QUIRK(sc, SUPPORTS_SPROM) && caps->sprom) { 417 srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL); 418 if (srom_ctrl & CHIPC_SRC_PRESENT) 419 return (BHND_NVRAM_SRC_SPROM); 420 } 421 422 /* Check for programmed OTP H/W subregion (contains SROM data) */ 423 if (CHIPC_QUIRK(sc, SUPPORTS_OTP) && caps->otp_size > 0) { 424 /* TODO: need access to HND-OTP device */ 425 if (!CHIPC_QUIRK(sc, OTP_HND)) { 426 device_printf(sc->dev, 427 "NVRAM unavailable: unsupported OTP controller.\n"); 428 return (BHND_NVRAM_SRC_UNKNOWN); 429 } 430 431 otp_st = bhnd_bus_read_4(sc->core, CHIPC_OTPST); 432 if (otp_st & CHIPC_OTPS_GUP_HW) 433 return (BHND_NVRAM_SRC_OTP); 434 } 435 436 /* Check for flash */ 437 if (caps->flash_type != CHIPC_FLASH_NONE) 438 return (BHND_NVRAM_SRC_FLASH); 439 440 /* No NVRAM hardware capability declared */ 441 return (BHND_NVRAM_SRC_UNKNOWN); 442 } 443 444 /* Read and parse chipc capabilities */ 445 static int 446 chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps) 447 { 448 uint32_t cap_reg; 449 uint32_t cap_ext_reg; 450 uint32_t regval; 451 452 /* Fetch cap registers */ 453 cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES); 454 cap_ext_reg = 0; 455 if (CHIPC_QUIRK(sc, SUPPORTS_CAP_EXT)) 456 cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT); 457 458 /* Extract values */ 459 caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART); 460 caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB); 461 caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO); 462 caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL); 463 464 caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS); 465 caps->pwr_ctrl = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL); 466 caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP); 467 468 caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL); 469 caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64); 470 caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM); 471 caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU); 472 caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI); 473 caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM); 474 caps->otp_size = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_OTP_SIZE); 475 476 caps->seci = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_SECI); 477 caps->gsio = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_GSIO); 478 caps->aob = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_AOB); 479 480 /* Fetch OTP size for later IPX controller revisions */ 481 if (CHIPC_QUIRK(sc, IPX_OTPL_SIZE)) { 482 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 483 caps->otp_size = CHIPC_GET_BITS(regval, CHIPC_OTPL_SIZE); 484 } 485 486 /* Determine flash type and parameters */ 487 caps->cfi_width = 0; 488 switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) { 489 case CHIPC_CAP_SFLASH_ST: 490 caps->flash_type = CHIPC_SFLASH_ST; 491 break; 492 case CHIPC_CAP_SFLASH_AT: 493 caps->flash_type = CHIPC_SFLASH_AT; 494 break; 495 case CHIPC_CAP_NFLASH: 496 /* unimplemented */ 497 caps->flash_type = CHIPC_NFLASH; 498 break; 499 case CHIPC_CAP_PFLASH: 500 caps->flash_type = CHIPC_PFLASH_CFI; 501 502 /* determine cfi width */ 503 regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG); 504 if (CHIPC_GET_FLAG(regval, CHIPC_FLASH_CFG_DS)) 505 caps->cfi_width = 2; 506 else 507 caps->cfi_width = 1; 508 509 break; 510 case CHIPC_CAP_FLASH_NONE: 511 caps->flash_type = CHIPC_FLASH_NONE; 512 break; 513 514 } 515 516 /* Handle 4706_NFLASH fallback */ 517 if (CHIPC_QUIRK(sc, 4706_NFLASH) && 518 CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_4706_NFLASH)) 519 { 520 caps->flash_type = CHIPC_NFLASH_4706; 521 } 522 523 /* Determine NVRAM source. Must occur after the SPROM/OTP/flash 524 * capability flags have been populated. */ 525 caps->nvram_src = chipc_find_nvram_src(sc, caps); 526 527 /* Determine the SPROM offset within OTP (if any). SPROM-formatted 528 * data is placed within the OTP general use region. */ 529 caps->sprom_offset = 0; 530 if (caps->nvram_src == BHND_NVRAM_SRC_OTP) { 531 CHIPC_ASSERT_QUIRK(sc, OTP_IPX); 532 533 /* Bit offset to GUP HW subregion containing SPROM data */ 534 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 535 caps->sprom_offset = CHIPC_GET_BITS(regval, CHIPC_OTPL_GUP); 536 537 /* Convert to bytes */ 538 caps->sprom_offset /= 8; 539 } 540 541 return (0); 542 } 543 544 static int 545 chipc_suspend(device_t dev) 546 { 547 return (bus_generic_suspend(dev)); 548 } 549 550 static int 551 chipc_resume(device_t dev) 552 { 553 return (bus_generic_resume(dev)); 554 } 555 556 static void 557 chipc_probe_nomatch(device_t dev, device_t child) 558 { 559 struct resource_list *rl; 560 const char *name; 561 562 name = device_get_name(child); 563 if (name == NULL) 564 name = "unknown device"; 565 566 device_printf(dev, "<%s> at", name); 567 568 rl = BUS_GET_RESOURCE_LIST(dev, child); 569 if (rl != NULL) { 570 resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 571 resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 572 } 573 574 printf(" (no driver attached)\n"); 575 } 576 577 static int 578 chipc_print_child(device_t dev, device_t child) 579 { 580 struct resource_list *rl; 581 int retval = 0; 582 583 retval += bus_print_child_header(dev, child); 584 585 rl = BUS_GET_RESOURCE_LIST(dev, child); 586 if (rl != NULL) { 587 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, 588 "%#jx"); 589 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, 590 "%jd"); 591 } 592 593 retval += bus_print_child_domain(dev, child); 594 retval += bus_print_child_footer(dev, child); 595 596 return (retval); 597 } 598 599 static device_t 600 chipc_add_child(device_t dev, u_int order, const char *name, int unit) 601 { 602 struct chipc_devinfo *dinfo; 603 device_t child; 604 605 child = device_add_child_ordered(dev, order, name, unit); 606 if (child == NULL) 607 return (NULL); 608 609 dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT); 610 if (dinfo == NULL) { 611 device_delete_child(dev, child); 612 return (NULL); 613 } 614 615 resource_list_init(&dinfo->resources); 616 dinfo->irq_mapped = false; 617 device_set_ivars(child, dinfo); 618 619 return (child); 620 } 621 622 static void 623 chipc_child_deleted(device_t dev, device_t child) 624 { 625 struct chipc_devinfo *dinfo = device_get_ivars(child); 626 627 if (dinfo != NULL) { 628 /* Free the child's resource list */ 629 resource_list_free(&dinfo->resources); 630 631 /* Unmap the child's IRQ */ 632 if (dinfo->irq_mapped) { 633 bhnd_unmap_intr(dev, dinfo->irq); 634 dinfo->irq_mapped = false; 635 } 636 637 free(dinfo, M_BHND); 638 } 639 640 device_set_ivars(child, NULL); 641 } 642 643 static struct resource_list * 644 chipc_get_resource_list(device_t dev, device_t child) 645 { 646 struct chipc_devinfo *dinfo = device_get_ivars(child); 647 return (&dinfo->resources); 648 } 649 650 /* Allocate region records for the given port, and add the port's memory 651 * range to the mem_rman */ 652 static int 653 chipc_rman_init_regions (struct chipc_softc *sc, bhnd_port_type type, 654 u_int port) 655 { 656 struct chipc_region *cr; 657 rman_res_t start, end; 658 u_int num_regions; 659 int error; 660 661 num_regions = bhnd_get_region_count(sc->dev, type, port); 662 for (u_int region = 0; region < num_regions; region++) { 663 /* Allocate new region record */ 664 cr = chipc_alloc_region(sc, type, port, region); 665 if (cr == NULL) 666 return (ENODEV); 667 668 /* Can't manage regions that cannot be allocated */ 669 if (cr->cr_rid < 0) { 670 BHND_DEBUG_DEV(sc->dev, "no rid for chipc region " 671 "%s%u.%u", bhnd_port_type_name(type), port, region); 672 chipc_free_region(sc, cr); 673 continue; 674 } 675 676 /* Add to rman's managed range */ 677 start = cr->cr_addr; 678 end = cr->cr_end; 679 if ((error = rman_manage_region(&sc->mem_rman, start, end))) { 680 chipc_free_region(sc, cr); 681 return (error); 682 } 683 684 /* Add to region list */ 685 STAILQ_INSERT_TAIL(&sc->mem_regions, cr, cr_link); 686 } 687 688 return (0); 689 } 690 691 /* Initialize memory state for all chipc port regions */ 692 static int 693 chipc_init_rman(struct chipc_softc *sc) 694 { 695 u_int num_ports; 696 int error; 697 698 /* Port types for which we'll register chipc_region mappings */ 699 bhnd_port_type types[] = { 700 BHND_PORT_DEVICE 701 }; 702 703 /* Initialize resource manager */ 704 sc->mem_rman.rm_start = 0; 705 sc->mem_rman.rm_end = BUS_SPACE_MAXADDR; 706 sc->mem_rman.rm_type = RMAN_ARRAY; 707 sc->mem_rman.rm_descr = "ChipCommon Device Memory"; 708 if ((error = rman_init(&sc->mem_rman))) { 709 device_printf(sc->dev, "could not initialize mem_rman: %d\n", 710 error); 711 return (error); 712 } 713 714 /* Populate per-port-region state */ 715 for (u_int i = 0; i < nitems(types); i++) { 716 num_ports = bhnd_get_port_count(sc->dev, types[i]); 717 for (u_int port = 0; port < num_ports; port++) { 718 error = chipc_rman_init_regions(sc, types[i], port); 719 if (error) { 720 device_printf(sc->dev, 721 "region init failed for %s%u: %d\n", 722 bhnd_port_type_name(types[i]), port, 723 error); 724 725 goto failed; 726 } 727 } 728 } 729 730 return (0); 731 732 failed: 733 chipc_free_rman(sc); 734 return (error); 735 } 736 737 /* Free memory management state */ 738 static void 739 chipc_free_rman(struct chipc_softc *sc) 740 { 741 struct chipc_region *cr, *cr_next; 742 743 STAILQ_FOREACH_SAFE(cr, &sc->mem_regions, cr_link, cr_next) 744 chipc_free_region(sc, cr); 745 746 rman_fini(&sc->mem_rman); 747 } 748 749 /** 750 * Return the rman instance for a given resource @p type, if any. 751 * 752 * @param sc The chipc device state. 753 * @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...) 754 */ 755 static struct rman * 756 chipc_get_rman(struct chipc_softc *sc, int type) 757 { 758 switch (type) { 759 case SYS_RES_MEMORY: 760 return (&sc->mem_rman); 761 762 case SYS_RES_IRQ: 763 /* We delegate IRQ resource management to the parent bus */ 764 return (NULL); 765 766 default: 767 return (NULL); 768 }; 769 } 770 771 static struct resource * 772 chipc_alloc_resource(device_t dev, device_t child, int type, 773 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 774 { 775 struct chipc_softc *sc; 776 struct chipc_region *cr; 777 struct resource_list_entry *rle; 778 struct resource *rv; 779 struct rman *rm; 780 int error; 781 bool passthrough, isdefault; 782 783 sc = device_get_softc(dev); 784 passthrough = (device_get_parent(child) != dev); 785 isdefault = RMAN_IS_DEFAULT_RANGE(start, end); 786 rle = NULL; 787 788 /* Fetch the resource manager, delegate request if necessary */ 789 rm = chipc_get_rman(sc, type); 790 if (rm == NULL) { 791 /* Requested resource type is delegated to our parent */ 792 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 793 start, end, count, flags); 794 return (rv); 795 } 796 797 /* Populate defaults */ 798 if (!passthrough && isdefault) { 799 /* Fetch the resource list entry. */ 800 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), 801 type, *rid); 802 if (rle == NULL) { 803 device_printf(dev, 804 "default resource %#x type %d for child %s " 805 "not found\n", *rid, type, 806 device_get_nameunit(child)); 807 return (NULL); 808 } 809 810 if (rle->res != NULL) { 811 device_printf(dev, 812 "resource entry %#x type %d for child %s is busy " 813 "[%d]\n", 814 *rid, type, device_get_nameunit(child), 815 rman_get_flags(rle->res)); 816 817 return (NULL); 818 } 819 820 start = rle->start; 821 end = rle->end; 822 count = ulmax(count, rle->count); 823 } 824 825 /* Locate a mapping region */ 826 if ((cr = chipc_find_region(sc, start, end)) == NULL) { 827 /* Resource requests outside our shared port regions can be 828 * delegated to our parent. */ 829 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 830 start, end, count, flags); 831 return (rv); 832 } 833 834 /* 835 * As a special case, children that map the complete ChipCommon register 836 * block are delegated to our parent. 837 * 838 * The rman API does not support sharing resources that are not 839 * identical in size; since we allocate subregions to various children, 840 * any children that need to map the entire register block (e.g. because 841 * they require access to discontiguous register ranges) must make the 842 * allocation through our parent, where we hold a compatible 843 * RF_SHAREABLE allocation. 844 */ 845 if (cr == sc->core_region && cr->cr_addr == start && 846 cr->cr_end == end && cr->cr_count == count) 847 { 848 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 849 start, end, count, flags); 850 return (rv); 851 } 852 853 /* Try to retain a region reference */ 854 if ((error = chipc_retain_region(sc, cr, RF_ALLOCATED))) 855 return (NULL); 856 857 /* Make our rman reservation */ 858 rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE, 859 child); 860 if (rv == NULL) { 861 chipc_release_region(sc, cr, RF_ALLOCATED); 862 return (NULL); 863 } 864 865 rman_set_rid(rv, *rid); 866 867 /* Activate */ 868 if (flags & RF_ACTIVE) { 869 error = bus_activate_resource(child, type, *rid, rv); 870 if (error) { 871 device_printf(dev, 872 "failed to activate entry %#x type %d for " 873 "child %s: %d\n", 874 *rid, type, device_get_nameunit(child), error); 875 876 chipc_release_region(sc, cr, RF_ALLOCATED); 877 rman_release_resource(rv); 878 879 return (NULL); 880 } 881 } 882 883 /* Update child's resource list entry */ 884 if (rle != NULL) { 885 rle->res = rv; 886 rle->start = rman_get_start(rv); 887 rle->end = rman_get_end(rv); 888 rle->count = rman_get_size(rv); 889 } 890 891 return (rv); 892 } 893 894 static int 895 chipc_release_resource(device_t dev, device_t child, int type, int rid, 896 struct resource *r) 897 { 898 struct chipc_softc *sc; 899 struct chipc_region *cr; 900 struct rman *rm; 901 struct resource_list_entry *rle; 902 int error; 903 904 sc = device_get_softc(dev); 905 906 /* Handled by parent bus? */ 907 rm = chipc_get_rman(sc, type); 908 if (rm == NULL || !rman_is_region_manager(r, rm)) { 909 return (bus_generic_rl_release_resource(dev, child, type, rid, 910 r)); 911 } 912 913 /* Locate the mapping region */ 914 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 915 if (cr == NULL) 916 return (EINVAL); 917 918 /* Deactivate resources */ 919 if (rman_get_flags(r) & RF_ACTIVE) { 920 error = BUS_DEACTIVATE_RESOURCE(dev, child, type, rid, r); 921 if (error) 922 return (error); 923 } 924 925 if ((error = rman_release_resource(r))) 926 return (error); 927 928 /* Drop allocation reference */ 929 chipc_release_region(sc, cr, RF_ALLOCATED); 930 931 /* Clear reference from the resource list entry if exists */ 932 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), type, rid); 933 if (rle != NULL) 934 rle->res = NULL; 935 936 return (0); 937 } 938 939 static int 940 chipc_adjust_resource(device_t dev, device_t child, int type, 941 struct resource *r, rman_res_t start, rman_res_t end) 942 { 943 struct chipc_softc *sc; 944 struct chipc_region *cr; 945 struct rman *rm; 946 947 sc = device_get_softc(dev); 948 949 /* Handled by parent bus? */ 950 rm = chipc_get_rman(sc, type); 951 if (rm == NULL || !rman_is_region_manager(r, rm)) { 952 return (bus_generic_adjust_resource(dev, child, type, r, start, 953 end)); 954 } 955 956 /* The range is limited to the existing region mapping */ 957 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 958 if (cr == NULL) 959 return (EINVAL); 960 961 if (end <= start) 962 return (EINVAL); 963 964 if (start < cr->cr_addr || end > cr->cr_end) 965 return (EINVAL); 966 967 /* Range falls within the existing region */ 968 return (rman_adjust_resource(r, start, end)); 969 } 970 971 /** 972 * Retain an RF_ACTIVE reference to the region mapping @p r, and 973 * configure @p r with its subregion values. 974 * 975 * @param sc Driver instance state. 976 * @param child Requesting child device. 977 * @param type resource type of @p r. 978 * @param rid resource id of @p r 979 * @param r resource to be activated. 980 * @param req_direct If true, failure to allocate a direct bhnd resource 981 * will be treated as an error. If false, the resource will not be marked 982 * as RF_ACTIVE if bhnd direct resource allocation fails. 983 */ 984 static int 985 chipc_try_activate_resource(struct chipc_softc *sc, device_t child, int type, 986 int rid, struct resource *r, bool req_direct) 987 { 988 struct rman *rm; 989 struct chipc_region *cr; 990 bhnd_size_t cr_offset; 991 rman_res_t r_start, r_end, r_size; 992 int error; 993 994 rm = chipc_get_rman(sc, type); 995 if (rm == NULL || !rman_is_region_manager(r, rm)) 996 return (EINVAL); 997 998 r_start = rman_get_start(r); 999 r_end = rman_get_end(r); 1000 r_size = rman_get_size(r); 1001 1002 /* Find the corresponding chipc region */ 1003 cr = chipc_find_region(sc, r_start, r_end); 1004 if (cr == NULL) 1005 return (EINVAL); 1006 1007 /* Calculate subregion offset within the chipc region */ 1008 cr_offset = r_start - cr->cr_addr; 1009 1010 /* Retain (and activate, if necessary) the chipc region */ 1011 if ((error = chipc_retain_region(sc, cr, RF_ACTIVE))) 1012 return (error); 1013 1014 /* Configure child resource with its subregion values. */ 1015 if (cr->cr_res->direct) { 1016 error = chipc_init_child_resource(r, cr->cr_res->res, 1017 cr_offset, r_size); 1018 if (error) 1019 goto cleanup; 1020 1021 /* Mark active */ 1022 if ((error = rman_activate_resource(r))) 1023 goto cleanup; 1024 } else if (req_direct) { 1025 error = ENOMEM; 1026 goto cleanup; 1027 } 1028 1029 return (0); 1030 1031 cleanup: 1032 chipc_release_region(sc, cr, RF_ACTIVE); 1033 return (error); 1034 } 1035 1036 static int 1037 chipc_activate_bhnd_resource(device_t dev, device_t child, int type, 1038 int rid, struct bhnd_resource *r) 1039 { 1040 struct chipc_softc *sc; 1041 struct rman *rm; 1042 int error; 1043 1044 sc = device_get_softc(dev); 1045 1046 /* Delegate non-locally managed resources to parent */ 1047 rm = chipc_get_rman(sc, type); 1048 if (rm == NULL || !rman_is_region_manager(r->res, rm)) { 1049 return (bhnd_bus_generic_activate_resource(dev, child, type, 1050 rid, r)); 1051 } 1052 1053 /* Try activating the chipc region resource */ 1054 error = chipc_try_activate_resource(sc, child, type, rid, r->res, 1055 false); 1056 if (error) 1057 return (error); 1058 1059 /* Mark the child resource as direct according to the returned resource 1060 * state */ 1061 if (rman_get_flags(r->res) & RF_ACTIVE) 1062 r->direct = true; 1063 1064 return (0); 1065 } 1066 1067 static int 1068 chipc_activate_resource(device_t dev, device_t child, int type, int rid, 1069 struct resource *r) 1070 { 1071 struct chipc_softc *sc; 1072 struct rman *rm; 1073 1074 sc = device_get_softc(dev); 1075 1076 /* Delegate non-locally managed resources to parent */ 1077 rm = chipc_get_rman(sc, type); 1078 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1079 return (bus_generic_activate_resource(dev, child, type, rid, 1080 r)); 1081 } 1082 1083 /* Try activating the chipc region-based resource */ 1084 return (chipc_try_activate_resource(sc, child, type, rid, r, true)); 1085 } 1086 1087 /** 1088 * Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE(). 1089 */ 1090 static int 1091 chipc_deactivate_resource(device_t dev, device_t child, int type, 1092 int rid, struct resource *r) 1093 { 1094 struct chipc_softc *sc; 1095 struct chipc_region *cr; 1096 struct rman *rm; 1097 int error; 1098 1099 sc = device_get_softc(dev); 1100 1101 /* Handled by parent bus? */ 1102 rm = chipc_get_rman(sc, type); 1103 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1104 return (bus_generic_deactivate_resource(dev, child, type, rid, 1105 r)); 1106 } 1107 1108 /* Find the corresponding chipc region */ 1109 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 1110 if (cr == NULL) 1111 return (EINVAL); 1112 1113 /* Mark inactive */ 1114 if ((error = rman_deactivate_resource(r))) 1115 return (error); 1116 1117 /* Drop associated RF_ACTIVE reference */ 1118 chipc_release_region(sc, cr, RF_ACTIVE); 1119 1120 return (0); 1121 } 1122 1123 /** 1124 * Examine bus state and make a best effort determination of whether it's 1125 * likely safe to enable the muxed SPROM pins. 1126 * 1127 * On devices that do not use SPROM pin muxing, always returns true. 1128 * 1129 * @param sc chipc driver state. 1130 */ 1131 static bool 1132 chipc_should_enable_muxed_sprom(struct chipc_softc *sc) 1133 { 1134 device_t *devs; 1135 device_t hostb; 1136 device_t parent; 1137 int devcount; 1138 int error; 1139 bool result; 1140 1141 /* Nothing to do? */ 1142 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1143 return (true); 1144 1145 bus_topo_lock(); 1146 1147 parent = device_get_parent(sc->dev); 1148 hostb = bhnd_bus_find_hostb_device(parent); 1149 1150 if ((error = device_get_children(parent, &devs, &devcount))) { 1151 bus_topo_unlock(); 1152 return (false); 1153 } 1154 1155 /* Reject any active devices other than ChipCommon, or the 1156 * host bridge (if any). */ 1157 result = true; 1158 for (int i = 0; i < devcount; i++) { 1159 if (devs[i] == hostb || devs[i] == sc->dev) 1160 continue; 1161 1162 if (!device_is_attached(devs[i])) 1163 continue; 1164 1165 if (device_is_suspended(devs[i])) 1166 continue; 1167 1168 /* Active device; assume SPROM is busy */ 1169 result = false; 1170 break; 1171 } 1172 1173 free(devs, M_TEMP); 1174 bus_topo_unlock(); 1175 return (result); 1176 } 1177 1178 static int 1179 chipc_enable_sprom(device_t dev) 1180 { 1181 struct chipc_softc *sc; 1182 int error; 1183 1184 sc = device_get_softc(dev); 1185 CHIPC_LOCK(sc); 1186 1187 /* Already enabled? */ 1188 if (sc->sprom_refcnt >= 1) { 1189 sc->sprom_refcnt++; 1190 CHIPC_UNLOCK(sc); 1191 1192 return (0); 1193 } 1194 1195 switch (sc->caps.nvram_src) { 1196 case BHND_NVRAM_SRC_SPROM: 1197 error = chipc_enable_sprom_pins(sc); 1198 break; 1199 case BHND_NVRAM_SRC_OTP: 1200 error = chipc_enable_otp_power(sc); 1201 break; 1202 default: 1203 error = 0; 1204 break; 1205 } 1206 1207 /* Bump the reference count */ 1208 if (error == 0) 1209 sc->sprom_refcnt++; 1210 1211 CHIPC_UNLOCK(sc); 1212 return (error); 1213 } 1214 1215 static void 1216 chipc_disable_sprom(device_t dev) 1217 { 1218 struct chipc_softc *sc; 1219 1220 sc = device_get_softc(dev); 1221 CHIPC_LOCK(sc); 1222 1223 /* Check reference count, skip disable if in-use. */ 1224 KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease")); 1225 sc->sprom_refcnt--; 1226 if (sc->sprom_refcnt > 0) { 1227 CHIPC_UNLOCK(sc); 1228 return; 1229 } 1230 1231 switch (sc->caps.nvram_src) { 1232 case BHND_NVRAM_SRC_SPROM: 1233 chipc_disable_sprom_pins(sc); 1234 break; 1235 case BHND_NVRAM_SRC_OTP: 1236 chipc_disable_otp_power(sc); 1237 break; 1238 default: 1239 break; 1240 } 1241 1242 CHIPC_UNLOCK(sc); 1243 } 1244 1245 static int 1246 chipc_enable_otp_power(struct chipc_softc *sc) 1247 { 1248 // TODO: Enable OTP resource via PMU, and wait up to 100 usec for 1249 // OTPS_READY to be set in `optstatus`. 1250 return (0); 1251 } 1252 1253 static void 1254 chipc_disable_otp_power(struct chipc_softc *sc) 1255 { 1256 // TODO: Disable OTP resource via PMU 1257 } 1258 1259 /** 1260 * If required by this device, enable access to the SPROM. 1261 * 1262 * @param sc chipc driver state. 1263 */ 1264 static int 1265 chipc_enable_sprom_pins(struct chipc_softc *sc) 1266 { 1267 uint32_t cctrl; 1268 1269 CHIPC_LOCK_ASSERT(sc, MA_OWNED); 1270 KASSERT(sc->sprom_refcnt == 0, ("sprom pins already enabled")); 1271 1272 /* Nothing to do? */ 1273 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1274 return (0); 1275 1276 /* Check whether bus is busy */ 1277 if (!chipc_should_enable_muxed_sprom(sc)) 1278 return (EBUSY); 1279 1280 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1281 1282 /* 4331 devices */ 1283 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1284 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN; 1285 1286 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1287 cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1288 1289 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1290 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2; 1291 1292 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1293 return (0); 1294 } 1295 1296 /* 4360 devices */ 1297 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1298 /* Unimplemented */ 1299 } 1300 1301 /* Refuse to proceed on unsupported devices with muxed SPROM pins */ 1302 device_printf(sc->dev, "muxed sprom lines on unrecognized device\n"); 1303 return (ENXIO); 1304 } 1305 1306 /** 1307 * If required by this device, revert any GPIO/pin configuration applied 1308 * to allow SPROM access. 1309 * 1310 * @param sc chipc driver state. 1311 */ 1312 static void 1313 chipc_disable_sprom_pins(struct chipc_softc *sc) 1314 { 1315 uint32_t cctrl; 1316 1317 /* Nothing to do? */ 1318 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1319 return; 1320 1321 CHIPC_LOCK_ASSERT(sc, MA_OWNED); 1322 KASSERT(sc->sprom_refcnt == 0, ("sprom pins in use")); 1323 1324 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1325 1326 /* 4331 devices */ 1327 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1328 cctrl |= CHIPC_CCTRL4331_EXTPA_EN; 1329 1330 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1331 cctrl |= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1332 1333 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1334 cctrl |= CHIPC_CCTRL4331_EXTPA_EN2; 1335 1336 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1337 return; 1338 } 1339 1340 /* 4360 devices */ 1341 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1342 /* Unimplemented */ 1343 } 1344 } 1345 1346 static uint32_t 1347 chipc_read_chipst(device_t dev) 1348 { 1349 struct chipc_softc *sc = device_get_softc(dev); 1350 return (bhnd_bus_read_4(sc->core, CHIPC_CHIPST)); 1351 } 1352 1353 static void 1354 chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask) 1355 { 1356 struct chipc_softc *sc; 1357 uint32_t cctrl; 1358 1359 sc = device_get_softc(dev); 1360 1361 CHIPC_LOCK(sc); 1362 1363 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1364 cctrl = (cctrl & ~mask) | (value | mask); 1365 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1366 1367 CHIPC_UNLOCK(sc); 1368 } 1369 1370 static struct chipc_caps * 1371 chipc_get_caps(device_t dev) 1372 { 1373 struct chipc_softc *sc; 1374 1375 sc = device_get_softc(dev); 1376 return (&sc->caps); 1377 } 1378 1379 static device_method_t chipc_methods[] = { 1380 /* Device interface */ 1381 DEVMETHOD(device_probe, chipc_probe), 1382 DEVMETHOD(device_attach, chipc_attach), 1383 DEVMETHOD(device_detach, chipc_detach), 1384 DEVMETHOD(device_suspend, chipc_suspend), 1385 DEVMETHOD(device_resume, chipc_resume), 1386 1387 /* Bus interface */ 1388 DEVMETHOD(bus_probe_nomatch, chipc_probe_nomatch), 1389 DEVMETHOD(bus_print_child, chipc_print_child), 1390 1391 DEVMETHOD(bus_add_child, chipc_add_child), 1392 DEVMETHOD(bus_child_deleted, chipc_child_deleted), 1393 1394 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 1395 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 1396 DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource), 1397 DEVMETHOD(bus_alloc_resource, chipc_alloc_resource), 1398 DEVMETHOD(bus_release_resource, chipc_release_resource), 1399 DEVMETHOD(bus_adjust_resource, chipc_adjust_resource), 1400 DEVMETHOD(bus_activate_resource, chipc_activate_resource), 1401 DEVMETHOD(bus_deactivate_resource, chipc_deactivate_resource), 1402 DEVMETHOD(bus_get_resource_list, chipc_get_resource_list), 1403 1404 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1405 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1406 DEVMETHOD(bus_config_intr, bus_generic_config_intr), 1407 DEVMETHOD(bus_bind_intr, bus_generic_bind_intr), 1408 DEVMETHOD(bus_describe_intr, bus_generic_describe_intr), 1409 1410 /* BHND bus inteface */ 1411 DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource), 1412 1413 /* ChipCommon interface */ 1414 DEVMETHOD(bhnd_chipc_read_chipst, chipc_read_chipst), 1415 DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl), 1416 DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom), 1417 DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom), 1418 DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps), 1419 1420 DEVMETHOD_END 1421 }; 1422 1423 DEFINE_CLASS_0(bhnd_chipc, bhnd_chipc_driver, chipc_methods, sizeof(struct chipc_softc)); 1424 EARLY_DRIVER_MODULE(bhnd_chipc, bhnd, bhnd_chipc_driver, bhnd_chipc_devclass, 0, 0, 1425 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 1426 MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1); 1427 MODULE_VERSION(bhnd_chipc, 1); 1428