1 /*- 2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 3 * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com> 4 * Copyright (c) 2017 The FreeBSD Foundation 5 * All rights reserved. 6 * 7 * Portions of this software were developed by Landon Fuller 8 * under sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 18 * redistribution must be conditioned upon including a substantially 19 * similar Disclaimer requirement for further binary redistribution. 20 * 21 * NO WARRANTY 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 25 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 26 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 27 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 30 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGES. 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 /* 39 * Broadcom ChipCommon driver. 40 * 41 * With the exception of some very early chipsets, the ChipCommon core 42 * has been included in all HND SoCs and chipsets based on the siba(4) 43 * and bcma(4) interconnects, providing a common interface to chipset 44 * identification, bus enumeration, UARTs, clocks, watchdog interrupts, 45 * GPIO, flash, etc. 46 */ 47 48 #include <sys/param.h> 49 #include <sys/kernel.h> 50 #include <sys/lock.h> 51 #include <sys/bus.h> 52 #include <sys/rman.h> 53 #include <sys/malloc.h> 54 #include <sys/module.h> 55 #include <sys/mutex.h> 56 #include <sys/systm.h> 57 58 #include <machine/bus.h> 59 #include <machine/resource.h> 60 61 #include <dev/bhnd/bhnd.h> 62 #include <dev/bhnd/bhndvar.h> 63 64 #include "chipcreg.h" 65 #include "chipcvar.h" 66 67 #include "chipc_private.h" 68 69 devclass_t bhnd_chipc_devclass; /**< bhnd(4) chipcommon device class */ 70 71 static struct bhnd_device_quirk chipc_quirks[]; 72 73 /* Supported device identifiers */ 74 static const struct bhnd_device chipc_devices[] = { 75 BHND_DEVICE(BCM, CC, NULL, chipc_quirks), 76 BHND_DEVICE(BCM, 4706_CC, NULL, chipc_quirks), 77 BHND_DEVICE_END 78 }; 79 80 81 /* Device quirks table */ 82 static struct bhnd_device_quirk chipc_quirks[] = { 83 /* HND OTP controller revisions */ 84 BHND_CORE_QUIRK (HWREV_EQ (12), CHIPC_QUIRK_OTP_HND), /* (?) */ 85 BHND_CORE_QUIRK (HWREV_EQ (17), CHIPC_QUIRK_OTP_HND), /* BCM4311 */ 86 BHND_CORE_QUIRK (HWREV_EQ (22), CHIPC_QUIRK_OTP_HND), /* BCM4312 */ 87 88 /* IPX OTP controller revisions */ 89 BHND_CORE_QUIRK (HWREV_EQ (21), CHIPC_QUIRK_OTP_IPX), 90 BHND_CORE_QUIRK (HWREV_GTE(23), CHIPC_QUIRK_OTP_IPX), 91 92 BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM), 93 BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT), 94 BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPL_SIZE), 95 96 /* 4706 variant quirks */ 97 BHND_CORE_QUIRK (HWREV_EQ (38), CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */ 98 BHND_CHIP_QUIRK (4706, HWREV_ANY, CHIPC_QUIRK_4706_NFLASH), 99 100 /* 4331 quirks*/ 101 BHND_CHIP_QUIRK (4331, HWREV_ANY, CHIPC_QUIRK_4331_EXTPA_MUX_SPROM), 102 BHND_PKG_QUIRK (4331, TN, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 103 BHND_PKG_QUIRK (4331, TNA0, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 104 BHND_PKG_QUIRK (4331, TT, CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM), 105 106 /* 4360 quirks */ 107 BHND_CHIP_QUIRK (4352, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 108 BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 109 BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 110 BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 111 112 BHND_DEVICE_QUIRK_END 113 }; 114 115 static int chipc_add_children(struct chipc_softc *sc); 116 117 static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc, 118 struct chipc_caps *caps); 119 static int chipc_read_caps(struct chipc_softc *sc, 120 struct chipc_caps *caps); 121 122 static bool chipc_should_enable_muxed_sprom( 123 struct chipc_softc *sc); 124 static int chipc_enable_otp_power(struct chipc_softc *sc); 125 static void chipc_disable_otp_power(struct chipc_softc *sc); 126 static int chipc_enable_sprom_pins(struct chipc_softc *sc); 127 static void chipc_disable_sprom_pins(struct chipc_softc *sc); 128 129 static int chipc_try_activate_resource(struct chipc_softc *sc, 130 device_t child, int type, int rid, 131 struct resource *r, bool req_direct); 132 133 static int chipc_init_rman(struct chipc_softc *sc); 134 static void chipc_free_rman(struct chipc_softc *sc); 135 static struct rman *chipc_get_rman(struct chipc_softc *sc, int type); 136 137 /* quirk and capability flag convenience macros */ 138 #define CHIPC_QUIRK(_sc, _name) \ 139 ((_sc)->quirks & CHIPC_QUIRK_ ## _name) 140 141 #define CHIPC_CAP(_sc, _name) \ 142 ((_sc)->caps._name) 143 144 #define CHIPC_ASSERT_QUIRK(_sc, name) \ 145 KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set")) 146 147 #define CHIPC_ASSERT_CAP(_sc, name) \ 148 KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set")) 149 150 static int 151 chipc_probe(device_t dev) 152 { 153 const struct bhnd_device *id; 154 155 id = bhnd_device_lookup(dev, chipc_devices, sizeof(chipc_devices[0])); 156 if (id == NULL) 157 return (ENXIO); 158 159 bhnd_set_default_core_desc(dev); 160 return (BUS_PROBE_DEFAULT); 161 } 162 163 static int 164 chipc_attach(device_t dev) 165 { 166 struct chipc_softc *sc; 167 int error; 168 169 sc = device_get_softc(dev); 170 sc->dev = dev; 171 sc->quirks = bhnd_device_quirks(dev, chipc_devices, 172 sizeof(chipc_devices[0])); 173 sc->sprom_refcnt = 0; 174 175 CHIPC_LOCK_INIT(sc); 176 STAILQ_INIT(&sc->mem_regions); 177 178 /* Set up resource management */ 179 if ((error = chipc_init_rman(sc))) { 180 device_printf(sc->dev, 181 "failed to initialize chipc resource state: %d\n", error); 182 goto failed; 183 } 184 185 /* Allocate the region containing the chipc register block */ 186 if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) { 187 error = ENXIO; 188 goto failed; 189 } 190 191 error = chipc_retain_region(sc, sc->core_region, 192 RF_ALLOCATED|RF_ACTIVE); 193 if (error) { 194 sc->core_region = NULL; 195 goto failed; 196 } 197 198 /* Save a direct reference to our chipc registers */ 199 sc->core = sc->core_region->cr_res; 200 201 /* Fetch and parse capability register(s) */ 202 if ((error = chipc_read_caps(sc, &sc->caps))) 203 goto failed; 204 205 if (bootverbose) 206 chipc_print_caps(sc->dev, &sc->caps); 207 208 /* Attach all supported child devices */ 209 if ((error = chipc_add_children(sc))) 210 goto failed; 211 212 /* 213 * Register ourselves with the bus; we're fully initialized and can 214 * response to ChipCommin API requests. 215 * 216 * Since our children may need access to ChipCommon, this must be done 217 * before attaching our children below (via bus_generic_attach). 218 */ 219 if ((error = bhnd_register_provider(dev, BHND_SERVICE_CHIPC))) 220 goto failed; 221 222 if ((error = bus_generic_attach(dev))) 223 goto failed; 224 225 return (0); 226 227 failed: 228 device_delete_children(sc->dev); 229 230 if (sc->core_region != NULL) { 231 chipc_release_region(sc, sc->core_region, 232 RF_ALLOCATED|RF_ACTIVE); 233 } 234 235 chipc_free_rman(sc); 236 CHIPC_LOCK_DESTROY(sc); 237 return (error); 238 } 239 240 static int 241 chipc_detach(device_t dev) 242 { 243 struct chipc_softc *sc; 244 int error; 245 246 sc = device_get_softc(dev); 247 248 if ((error = bhnd_deregister_provider(dev, BHND_SERVICE_ANY))) 249 return (error); 250 251 if ((error = bus_generic_detach(dev))) 252 return (error); 253 254 chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE); 255 chipc_free_rman(sc); 256 257 CHIPC_LOCK_DESTROY(sc); 258 259 return (0); 260 } 261 262 static int 263 chipc_add_children(struct chipc_softc *sc) 264 { 265 device_t child; 266 const char *flash_bus; 267 int error; 268 269 /* SPROM/OTP */ 270 if (sc->caps.nvram_src == BHND_NVRAM_SRC_SPROM || 271 sc->caps.nvram_src == BHND_NVRAM_SRC_OTP) 272 { 273 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_nvram", -1); 274 if (child == NULL) { 275 device_printf(sc->dev, "failed to add nvram device\n"); 276 return (ENXIO); 277 } 278 279 /* Both OTP and external SPROM are mapped at CHIPC_SPROM_OTP */ 280 error = chipc_set_mem_resource(sc, child, 0, CHIPC_SPROM_OTP, 281 CHIPC_SPROM_OTP_SIZE, 0, 0); 282 if (error) { 283 device_printf(sc->dev, "failed to set OTP memory " 284 "resource: %d\n", error); 285 return (error); 286 } 287 } 288 289 /* 290 * PMU/PWR_CTRL 291 * 292 * On AOB ("Always on Bus") devices, the PMU core (if it exists) is 293 * attached directly to the bhnd(4) bus -- not chipc. 294 */ 295 if (sc->caps.pmu && !sc->caps.aob) { 296 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pmu", 0); 297 if (child == NULL) { 298 device_printf(sc->dev, "failed to add pmu\n"); 299 return (ENXIO); 300 } 301 } else if (sc->caps.pwr_ctrl) { 302 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pwrctl", 0); 303 if (child == NULL) { 304 device_printf(sc->dev, "failed to add pwrctl\n"); 305 return (ENXIO); 306 } 307 } 308 309 /* All remaining devices are SoC-only */ 310 if (bhnd_get_attach_type(sc->dev) != BHND_ATTACH_NATIVE) 311 return (0); 312 313 /* UARTs */ 314 for (u_int i = 0; i < min(sc->caps.num_uarts, CHIPC_UART_MAX); i++) { 315 int irq_rid, mem_rid; 316 317 irq_rid = 0; 318 mem_rid = 0; 319 320 child = BUS_ADD_CHILD(sc->dev, 0, "uart", -1); 321 if (child == NULL) { 322 device_printf(sc->dev, "failed to add uart%u\n", i); 323 return (ENXIO); 324 } 325 326 /* Shared IRQ */ 327 error = chipc_set_irq_resource(sc, child, irq_rid, 0); 328 if (error) { 329 device_printf(sc->dev, "failed to set uart%u irq %u\n", 330 i, 0); 331 return (error); 332 } 333 334 /* UART registers are mapped sequentially */ 335 error = chipc_set_mem_resource(sc, child, mem_rid, 336 CHIPC_UART(i), CHIPC_UART_SIZE, 0, 0); 337 if (error) { 338 device_printf(sc->dev, "failed to set uart%u memory " 339 "resource: %d\n", i, error); 340 return (error); 341 } 342 } 343 344 /* Flash */ 345 flash_bus = chipc_flash_bus_name(sc->caps.flash_type); 346 if (flash_bus != NULL) { 347 int rid; 348 349 child = BUS_ADD_CHILD(sc->dev, 0, flash_bus, -1); 350 if (child == NULL) { 351 device_printf(sc->dev, "failed to add %s device\n", 352 flash_bus); 353 return (ENXIO); 354 } 355 356 /* flash memory mapping */ 357 rid = 0; 358 error = chipc_set_mem_resource(sc, child, rid, 0, RM_MAX_END, 1, 359 1); 360 if (error) { 361 device_printf(sc->dev, "failed to set flash memory " 362 "resource %d: %d\n", rid, error); 363 return (error); 364 } 365 366 /* flashctrl registers */ 367 rid++; 368 error = chipc_set_mem_resource(sc, child, rid, 369 CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0, 0); 370 if (error) { 371 device_printf(sc->dev, "failed to set flash memory " 372 "resource %d: %d\n", rid, error); 373 return (error); 374 } 375 } 376 377 return (0); 378 } 379 380 /** 381 * Determine the NVRAM data source for this device. 382 * 383 * The SPROM, OTP, and flash capability flags must be fully populated in 384 * @p caps. 385 * 386 * @param sc chipc driver state. 387 * @param caps capability flags to be used to derive NVRAM configuration. 388 */ 389 static bhnd_nvram_src 390 chipc_find_nvram_src(struct chipc_softc *sc, struct chipc_caps *caps) 391 { 392 uint32_t otp_st, srom_ctrl; 393 394 /* 395 * We check for hardware presence in order of precedence. For example, 396 * SPROM is is always used in preference to internal OTP if found. 397 */ 398 if (CHIPC_QUIRK(sc, SUPPORTS_SPROM) && caps->sprom) { 399 srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL); 400 if (srom_ctrl & CHIPC_SRC_PRESENT) 401 return (BHND_NVRAM_SRC_SPROM); 402 } 403 404 /* Check for programmed OTP H/W subregion (contains SROM data) */ 405 if (CHIPC_QUIRK(sc, SUPPORTS_OTP) && caps->otp_size > 0) { 406 /* TODO: need access to HND-OTP device */ 407 if (!CHIPC_QUIRK(sc, OTP_HND)) { 408 device_printf(sc->dev, 409 "NVRAM unavailable: unsupported OTP controller.\n"); 410 return (BHND_NVRAM_SRC_UNKNOWN); 411 } 412 413 otp_st = bhnd_bus_read_4(sc->core, CHIPC_OTPST); 414 if (otp_st & CHIPC_OTPS_GUP_HW) 415 return (BHND_NVRAM_SRC_OTP); 416 } 417 418 /* Check for flash */ 419 if (caps->flash_type != CHIPC_FLASH_NONE) 420 return (BHND_NVRAM_SRC_FLASH); 421 422 /* No NVRAM hardware capability declared */ 423 return (BHND_NVRAM_SRC_UNKNOWN); 424 } 425 426 /* Read and parse chipc capabilities */ 427 static int 428 chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps) 429 { 430 uint32_t cap_reg; 431 uint32_t cap_ext_reg; 432 uint32_t regval; 433 434 /* Fetch cap registers */ 435 cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES); 436 cap_ext_reg = 0; 437 if (CHIPC_QUIRK(sc, SUPPORTS_CAP_EXT)) 438 cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT); 439 440 /* Extract values */ 441 caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART); 442 caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB); 443 caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO); 444 caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL); 445 446 caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS); 447 caps->pwr_ctrl = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL); 448 caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP); 449 450 caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL); 451 caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64); 452 caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM); 453 caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU); 454 caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI); 455 caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM); 456 caps->otp_size = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_OTP_SIZE); 457 458 caps->seci = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_SECI); 459 caps->gsio = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_GSIO); 460 caps->aob = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_AOB); 461 462 /* Fetch OTP size for later IPX controller revisions */ 463 if (CHIPC_QUIRK(sc, IPX_OTPL_SIZE)) { 464 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 465 caps->otp_size = CHIPC_GET_BITS(regval, CHIPC_OTPL_SIZE); 466 } 467 468 /* Determine flash type and parameters */ 469 caps->cfi_width = 0; 470 switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) { 471 case CHIPC_CAP_SFLASH_ST: 472 caps->flash_type = CHIPC_SFLASH_ST; 473 break; 474 case CHIPC_CAP_SFLASH_AT: 475 caps->flash_type = CHIPC_SFLASH_AT; 476 break; 477 case CHIPC_CAP_NFLASH: 478 /* unimplemented */ 479 caps->flash_type = CHIPC_NFLASH; 480 break; 481 case CHIPC_CAP_PFLASH: 482 caps->flash_type = CHIPC_PFLASH_CFI; 483 484 /* determine cfi width */ 485 regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG); 486 if (CHIPC_GET_FLAG(regval, CHIPC_FLASH_CFG_DS)) 487 caps->cfi_width = 2; 488 else 489 caps->cfi_width = 1; 490 491 break; 492 case CHIPC_CAP_FLASH_NONE: 493 caps->flash_type = CHIPC_FLASH_NONE; 494 break; 495 496 } 497 498 /* Handle 4706_NFLASH fallback */ 499 if (CHIPC_QUIRK(sc, 4706_NFLASH) && 500 CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_4706_NFLASH)) 501 { 502 caps->flash_type = CHIPC_NFLASH_4706; 503 } 504 505 506 /* Determine NVRAM source. Must occur after the SPROM/OTP/flash 507 * capability flags have been populated. */ 508 caps->nvram_src = chipc_find_nvram_src(sc, caps); 509 510 /* Determine the SPROM offset within OTP (if any). SPROM-formatted 511 * data is placed within the OTP general use region. */ 512 caps->sprom_offset = 0; 513 if (caps->nvram_src == BHND_NVRAM_SRC_OTP) { 514 CHIPC_ASSERT_QUIRK(sc, OTP_IPX); 515 516 /* Bit offset to GUP HW subregion containing SPROM data */ 517 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 518 caps->sprom_offset = CHIPC_GET_BITS(regval, CHIPC_OTPL_GUP); 519 520 /* Convert to bytes */ 521 caps->sprom_offset /= 8; 522 } 523 524 return (0); 525 } 526 527 static int 528 chipc_suspend(device_t dev) 529 { 530 return (bus_generic_suspend(dev)); 531 } 532 533 static int 534 chipc_resume(device_t dev) 535 { 536 return (bus_generic_resume(dev)); 537 } 538 539 static void 540 chipc_probe_nomatch(device_t dev, device_t child) 541 { 542 struct resource_list *rl; 543 const char *name; 544 545 name = device_get_name(child); 546 if (name == NULL) 547 name = "unknown device"; 548 549 device_printf(dev, "<%s> at", name); 550 551 rl = BUS_GET_RESOURCE_LIST(dev, child); 552 if (rl != NULL) { 553 resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 554 resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 555 } 556 557 printf(" (no driver attached)\n"); 558 } 559 560 static int 561 chipc_print_child(device_t dev, device_t child) 562 { 563 struct resource_list *rl; 564 int retval = 0; 565 566 retval += bus_print_child_header(dev, child); 567 568 rl = BUS_GET_RESOURCE_LIST(dev, child); 569 if (rl != NULL) { 570 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, 571 "%#jx"); 572 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, 573 "%jd"); 574 } 575 576 retval += bus_print_child_domain(dev, child); 577 retval += bus_print_child_footer(dev, child); 578 579 return (retval); 580 } 581 582 static int 583 chipc_child_pnpinfo_str(device_t dev, device_t child, char *buf, 584 size_t buflen) 585 { 586 if (buflen == 0) 587 return (EOVERFLOW); 588 589 *buf = '\0'; 590 return (0); 591 } 592 593 static int 594 chipc_child_location_str(device_t dev, device_t child, char *buf, 595 size_t buflen) 596 { 597 if (buflen == 0) 598 return (EOVERFLOW); 599 600 *buf = '\0'; 601 return (ENXIO); 602 } 603 604 static device_t 605 chipc_add_child(device_t dev, u_int order, const char *name, int unit) 606 { 607 struct chipc_softc *sc; 608 struct chipc_devinfo *dinfo; 609 device_t child; 610 611 sc = device_get_softc(dev); 612 613 child = device_add_child_ordered(dev, order, name, unit); 614 if (child == NULL) 615 return (NULL); 616 617 dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT); 618 if (dinfo == NULL) { 619 device_delete_child(dev, child); 620 return (NULL); 621 } 622 623 resource_list_init(&dinfo->resources); 624 dinfo->irq_mapped = false; 625 device_set_ivars(child, dinfo); 626 627 return (child); 628 } 629 630 static void 631 chipc_child_deleted(device_t dev, device_t child) 632 { 633 struct chipc_devinfo *dinfo = device_get_ivars(child); 634 635 if (dinfo != NULL) { 636 /* Free the child's resource list */ 637 resource_list_free(&dinfo->resources); 638 639 /* Unmap the child's IRQ */ 640 if (dinfo->irq_mapped) { 641 bhnd_unmap_intr(dev, dinfo->irq); 642 dinfo->irq_mapped = false; 643 } 644 645 free(dinfo, M_BHND); 646 } 647 648 device_set_ivars(child, NULL); 649 } 650 651 static struct resource_list * 652 chipc_get_resource_list(device_t dev, device_t child) 653 { 654 struct chipc_devinfo *dinfo = device_get_ivars(child); 655 return (&dinfo->resources); 656 } 657 658 659 /* Allocate region records for the given port, and add the port's memory 660 * range to the mem_rman */ 661 static int 662 chipc_rman_init_regions (struct chipc_softc *sc, bhnd_port_type type, 663 u_int port) 664 { 665 struct chipc_region *cr; 666 rman_res_t start, end; 667 u_int num_regions; 668 int error; 669 670 num_regions = bhnd_get_region_count(sc->dev, type, port); 671 for (u_int region = 0; region < num_regions; region++) { 672 /* Allocate new region record */ 673 cr = chipc_alloc_region(sc, type, port, region); 674 if (cr == NULL) 675 return (ENODEV); 676 677 /* Can't manage regions that cannot be allocated */ 678 if (cr->cr_rid < 0) { 679 BHND_DEBUG_DEV(sc->dev, "no rid for chipc region " 680 "%s%u.%u", bhnd_port_type_name(type), port, region); 681 chipc_free_region(sc, cr); 682 continue; 683 } 684 685 /* Add to rman's managed range */ 686 start = cr->cr_addr; 687 end = cr->cr_end; 688 if ((error = rman_manage_region(&sc->mem_rman, start, end))) { 689 chipc_free_region(sc, cr); 690 return (error); 691 } 692 693 /* Add to region list */ 694 STAILQ_INSERT_TAIL(&sc->mem_regions, cr, cr_link); 695 } 696 697 return (0); 698 } 699 700 /* Initialize memory state for all chipc port regions */ 701 static int 702 chipc_init_rman(struct chipc_softc *sc) 703 { 704 u_int num_ports; 705 int error; 706 707 /* Port types for which we'll register chipc_region mappings */ 708 bhnd_port_type types[] = { 709 BHND_PORT_DEVICE 710 }; 711 712 /* Initialize resource manager */ 713 sc->mem_rman.rm_start = 0; 714 sc->mem_rman.rm_end = BUS_SPACE_MAXADDR; 715 sc->mem_rman.rm_type = RMAN_ARRAY; 716 sc->mem_rman.rm_descr = "ChipCommon Device Memory"; 717 if ((error = rman_init(&sc->mem_rman))) { 718 device_printf(sc->dev, "could not initialize mem_rman: %d\n", 719 error); 720 return (error); 721 } 722 723 /* Populate per-port-region state */ 724 for (u_int i = 0; i < nitems(types); i++) { 725 num_ports = bhnd_get_port_count(sc->dev, types[i]); 726 for (u_int port = 0; port < num_ports; port++) { 727 error = chipc_rman_init_regions(sc, types[i], port); 728 if (error) { 729 device_printf(sc->dev, 730 "region init failed for %s%u: %d\n", 731 bhnd_port_type_name(types[i]), port, 732 error); 733 734 goto failed; 735 } 736 } 737 } 738 739 return (0); 740 741 failed: 742 chipc_free_rman(sc); 743 return (error); 744 } 745 746 /* Free memory management state */ 747 static void 748 chipc_free_rman(struct chipc_softc *sc) 749 { 750 struct chipc_region *cr, *cr_next; 751 752 STAILQ_FOREACH_SAFE(cr, &sc->mem_regions, cr_link, cr_next) 753 chipc_free_region(sc, cr); 754 755 rman_fini(&sc->mem_rman); 756 } 757 758 /** 759 * Return the rman instance for a given resource @p type, if any. 760 * 761 * @param sc The chipc device state. 762 * @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...) 763 */ 764 static struct rman * 765 chipc_get_rman(struct chipc_softc *sc, int type) 766 { 767 switch (type) { 768 case SYS_RES_MEMORY: 769 return (&sc->mem_rman); 770 771 case SYS_RES_IRQ: 772 /* We delegate IRQ resource management to the parent bus */ 773 return (NULL); 774 775 default: 776 return (NULL); 777 }; 778 } 779 780 static struct resource * 781 chipc_alloc_resource(device_t dev, device_t child, int type, 782 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 783 { 784 struct chipc_softc *sc; 785 struct chipc_region *cr; 786 struct resource_list_entry *rle; 787 struct resource *rv; 788 struct rman *rm; 789 int error; 790 bool passthrough, isdefault; 791 792 sc = device_get_softc(dev); 793 passthrough = (device_get_parent(child) != dev); 794 isdefault = RMAN_IS_DEFAULT_RANGE(start, end); 795 rle = NULL; 796 797 /* Fetch the resource manager, delegate request if necessary */ 798 rm = chipc_get_rman(sc, type); 799 if (rm == NULL) { 800 /* Requested resource type is delegated to our parent */ 801 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 802 start, end, count, flags); 803 return (rv); 804 } 805 806 /* Populate defaults */ 807 if (!passthrough && isdefault) { 808 /* Fetch the resource list entry. */ 809 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), 810 type, *rid); 811 if (rle == NULL) { 812 device_printf(dev, 813 "default resource %#x type %d for child %s " 814 "not found\n", *rid, type, 815 device_get_nameunit(child)); 816 return (NULL); 817 } 818 819 if (rle->res != NULL) { 820 device_printf(dev, 821 "resource entry %#x type %d for child %s is busy " 822 "[%d]\n", 823 *rid, type, device_get_nameunit(child), 824 rman_get_flags(rle->res)); 825 826 return (NULL); 827 } 828 829 start = rle->start; 830 end = rle->end; 831 count = ulmax(count, rle->count); 832 } 833 834 /* Locate a mapping region */ 835 if ((cr = chipc_find_region(sc, start, end)) == NULL) { 836 /* Resource requests outside our shared port regions can be 837 * delegated to our parent. */ 838 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 839 start, end, count, flags); 840 return (rv); 841 } 842 843 /* Try to retain a region reference */ 844 if ((error = chipc_retain_region(sc, cr, RF_ALLOCATED))) 845 return (NULL); 846 847 /* Make our rman reservation */ 848 rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE, 849 child); 850 if (rv == NULL) { 851 chipc_release_region(sc, cr, RF_ALLOCATED); 852 return (NULL); 853 } 854 855 rman_set_rid(rv, *rid); 856 857 /* Activate */ 858 if (flags & RF_ACTIVE) { 859 error = bus_activate_resource(child, type, *rid, rv); 860 if (error) { 861 device_printf(dev, 862 "failed to activate entry %#x type %d for " 863 "child %s: %d\n", 864 *rid, type, device_get_nameunit(child), error); 865 866 chipc_release_region(sc, cr, RF_ALLOCATED); 867 rman_release_resource(rv); 868 869 return (NULL); 870 } 871 } 872 873 /* Update child's resource list entry */ 874 if (rle != NULL) { 875 rle->res = rv; 876 rle->start = rman_get_start(rv); 877 rle->end = rman_get_end(rv); 878 rle->count = rman_get_size(rv); 879 } 880 881 return (rv); 882 } 883 884 static int 885 chipc_release_resource(device_t dev, device_t child, int type, int rid, 886 struct resource *r) 887 { 888 struct chipc_softc *sc; 889 struct chipc_region *cr; 890 struct rman *rm; 891 struct resource_list_entry *rle; 892 int error; 893 894 sc = device_get_softc(dev); 895 896 /* Handled by parent bus? */ 897 rm = chipc_get_rman(sc, type); 898 if (rm == NULL || !rman_is_region_manager(r, rm)) { 899 return (bus_generic_rl_release_resource(dev, child, type, rid, 900 r)); 901 } 902 903 /* Locate the mapping region */ 904 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 905 if (cr == NULL) 906 return (EINVAL); 907 908 /* Deactivate resources */ 909 if (rman_get_flags(r) & RF_ACTIVE) { 910 error = BUS_DEACTIVATE_RESOURCE(dev, child, type, rid, r); 911 if (error) 912 return (error); 913 } 914 915 if ((error = rman_release_resource(r))) 916 return (error); 917 918 /* Drop allocation reference */ 919 chipc_release_region(sc, cr, RF_ALLOCATED); 920 921 /* Clear reference from the resource list entry if exists */ 922 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), type, rid); 923 if (rle != NULL) 924 rle->res = NULL; 925 926 return (0); 927 } 928 929 static int 930 chipc_adjust_resource(device_t dev, device_t child, int type, 931 struct resource *r, rman_res_t start, rman_res_t end) 932 { 933 struct chipc_softc *sc; 934 struct chipc_region *cr; 935 struct rman *rm; 936 937 sc = device_get_softc(dev); 938 939 /* Handled by parent bus? */ 940 rm = chipc_get_rman(sc, type); 941 if (rm == NULL || !rman_is_region_manager(r, rm)) { 942 return (bus_generic_adjust_resource(dev, child, type, r, start, 943 end)); 944 } 945 946 /* The range is limited to the existing region mapping */ 947 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 948 if (cr == NULL) 949 return (EINVAL); 950 951 if (end <= start) 952 return (EINVAL); 953 954 if (start < cr->cr_addr || end > cr->cr_end) 955 return (EINVAL); 956 957 /* Range falls within the existing region */ 958 return (rman_adjust_resource(r, start, end)); 959 } 960 961 /** 962 * Retain an RF_ACTIVE reference to the region mapping @p r, and 963 * configure @p r with its subregion values. 964 * 965 * @param sc Driver instance state. 966 * @param child Requesting child device. 967 * @param type resource type of @p r. 968 * @param rid resource id of @p r 969 * @param r resource to be activated. 970 * @param req_direct If true, failure to allocate a direct bhnd resource 971 * will be treated as an error. If false, the resource will not be marked 972 * as RF_ACTIVE if bhnd direct resource allocation fails. 973 */ 974 static int 975 chipc_try_activate_resource(struct chipc_softc *sc, device_t child, int type, 976 int rid, struct resource *r, bool req_direct) 977 { 978 struct rman *rm; 979 struct chipc_region *cr; 980 bhnd_size_t cr_offset; 981 rman_res_t r_start, r_end, r_size; 982 int error; 983 984 rm = chipc_get_rman(sc, type); 985 if (rm == NULL || !rman_is_region_manager(r, rm)) 986 return (EINVAL); 987 988 r_start = rman_get_start(r); 989 r_end = rman_get_end(r); 990 r_size = rman_get_size(r); 991 992 /* Find the corresponding chipc region */ 993 cr = chipc_find_region(sc, r_start, r_end); 994 if (cr == NULL) 995 return (EINVAL); 996 997 /* Calculate subregion offset within the chipc region */ 998 cr_offset = r_start - cr->cr_addr; 999 1000 /* Retain (and activate, if necessary) the chipc region */ 1001 if ((error = chipc_retain_region(sc, cr, RF_ACTIVE))) 1002 return (error); 1003 1004 /* Configure child resource with its subregion values. */ 1005 if (cr->cr_res->direct) { 1006 error = chipc_init_child_resource(r, cr->cr_res->res, 1007 cr_offset, r_size); 1008 if (error) 1009 goto cleanup; 1010 1011 /* Mark active */ 1012 if ((error = rman_activate_resource(r))) 1013 goto cleanup; 1014 } else if (req_direct) { 1015 error = ENOMEM; 1016 goto cleanup; 1017 } 1018 1019 return (0); 1020 1021 cleanup: 1022 chipc_release_region(sc, cr, RF_ACTIVE); 1023 return (error); 1024 } 1025 1026 static int 1027 chipc_activate_bhnd_resource(device_t dev, device_t child, int type, 1028 int rid, struct bhnd_resource *r) 1029 { 1030 struct chipc_softc *sc; 1031 struct rman *rm; 1032 int error; 1033 1034 sc = device_get_softc(dev); 1035 1036 /* Delegate non-locally managed resources to parent */ 1037 rm = chipc_get_rman(sc, type); 1038 if (rm == NULL || !rman_is_region_manager(r->res, rm)) { 1039 return (bhnd_bus_generic_activate_resource(dev, child, type, 1040 rid, r)); 1041 } 1042 1043 /* Try activating the chipc region resource */ 1044 error = chipc_try_activate_resource(sc, child, type, rid, r->res, 1045 false); 1046 if (error) 1047 return (error); 1048 1049 /* Mark the child resource as direct according to the returned resource 1050 * state */ 1051 if (rman_get_flags(r->res) & RF_ACTIVE) 1052 r->direct = true; 1053 1054 return (0); 1055 } 1056 1057 static int 1058 chipc_activate_resource(device_t dev, device_t child, int type, int rid, 1059 struct resource *r) 1060 { 1061 struct chipc_softc *sc; 1062 struct rman *rm; 1063 1064 sc = device_get_softc(dev); 1065 1066 /* Delegate non-locally managed resources to parent */ 1067 rm = chipc_get_rman(sc, type); 1068 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1069 return (bus_generic_activate_resource(dev, child, type, rid, 1070 r)); 1071 } 1072 1073 /* Try activating the chipc region-based resource */ 1074 return (chipc_try_activate_resource(sc, child, type, rid, r, true)); 1075 } 1076 1077 /** 1078 * Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE(). 1079 */ 1080 static int 1081 chipc_deactivate_resource(device_t dev, device_t child, int type, 1082 int rid, struct resource *r) 1083 { 1084 struct chipc_softc *sc; 1085 struct chipc_region *cr; 1086 struct rman *rm; 1087 int error; 1088 1089 sc = device_get_softc(dev); 1090 1091 /* Handled by parent bus? */ 1092 rm = chipc_get_rman(sc, type); 1093 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1094 return (bus_generic_deactivate_resource(dev, child, type, rid, 1095 r)); 1096 } 1097 1098 /* Find the corresponding chipc region */ 1099 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 1100 if (cr == NULL) 1101 return (EINVAL); 1102 1103 /* Mark inactive */ 1104 if ((error = rman_deactivate_resource(r))) 1105 return (error); 1106 1107 /* Drop associated RF_ACTIVE reference */ 1108 chipc_release_region(sc, cr, RF_ACTIVE); 1109 1110 return (0); 1111 } 1112 1113 /** 1114 * Examine bus state and make a best effort determination of whether it's 1115 * likely safe to enable the muxed SPROM pins. 1116 * 1117 * On devices that do not use SPROM pin muxing, always returns true. 1118 * 1119 * @param sc chipc driver state. 1120 */ 1121 static bool 1122 chipc_should_enable_muxed_sprom(struct chipc_softc *sc) 1123 { 1124 device_t *devs; 1125 device_t hostb; 1126 device_t parent; 1127 int devcount; 1128 int error; 1129 bool result; 1130 1131 /* Nothing to do? */ 1132 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1133 return (true); 1134 1135 mtx_lock(&Giant); /* for newbus */ 1136 1137 parent = device_get_parent(sc->dev); 1138 hostb = bhnd_bus_find_hostb_device(parent); 1139 1140 if ((error = device_get_children(parent, &devs, &devcount))) { 1141 mtx_unlock(&Giant); 1142 return (false); 1143 } 1144 1145 /* Reject any active devices other than ChipCommon, or the 1146 * host bridge (if any). */ 1147 result = true; 1148 for (int i = 0; i < devcount; i++) { 1149 if (devs[i] == hostb || devs[i] == sc->dev) 1150 continue; 1151 1152 if (!device_is_attached(devs[i])) 1153 continue; 1154 1155 if (device_is_suspended(devs[i])) 1156 continue; 1157 1158 /* Active device; assume SPROM is busy */ 1159 result = false; 1160 break; 1161 } 1162 1163 free(devs, M_TEMP); 1164 mtx_unlock(&Giant); 1165 return (result); 1166 } 1167 1168 static int 1169 chipc_enable_sprom(device_t dev) 1170 { 1171 struct chipc_softc *sc; 1172 int error; 1173 1174 sc = device_get_softc(dev); 1175 CHIPC_LOCK(sc); 1176 1177 /* Already enabled? */ 1178 if (sc->sprom_refcnt >= 1) { 1179 sc->sprom_refcnt++; 1180 CHIPC_UNLOCK(sc); 1181 1182 return (0); 1183 } 1184 1185 switch (sc->caps.nvram_src) { 1186 case BHND_NVRAM_SRC_SPROM: 1187 error = chipc_enable_sprom_pins(sc); 1188 break; 1189 case BHND_NVRAM_SRC_OTP: 1190 error = chipc_enable_otp_power(sc); 1191 break; 1192 default: 1193 error = 0; 1194 break; 1195 } 1196 1197 /* Bump the reference count */ 1198 if (error == 0) 1199 sc->sprom_refcnt++; 1200 1201 CHIPC_UNLOCK(sc); 1202 return (error); 1203 } 1204 1205 static void 1206 chipc_disable_sprom(device_t dev) 1207 { 1208 struct chipc_softc *sc; 1209 1210 sc = device_get_softc(dev); 1211 CHIPC_LOCK(sc); 1212 1213 /* Check reference count, skip disable if in-use. */ 1214 KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease")); 1215 sc->sprom_refcnt--; 1216 if (sc->sprom_refcnt > 0) { 1217 CHIPC_UNLOCK(sc); 1218 return; 1219 } 1220 1221 switch (sc->caps.nvram_src) { 1222 case BHND_NVRAM_SRC_SPROM: 1223 chipc_disable_sprom_pins(sc); 1224 break; 1225 case BHND_NVRAM_SRC_OTP: 1226 chipc_disable_otp_power(sc); 1227 break; 1228 default: 1229 break; 1230 } 1231 1232 1233 CHIPC_UNLOCK(sc); 1234 } 1235 1236 static int 1237 chipc_enable_otp_power(struct chipc_softc *sc) 1238 { 1239 // TODO: Enable OTP resource via PMU, and wait up to 100 usec for 1240 // OTPS_READY to be set in `optstatus`. 1241 return (0); 1242 } 1243 1244 static void 1245 chipc_disable_otp_power(struct chipc_softc *sc) 1246 { 1247 // TODO: Disable OTP resource via PMU 1248 } 1249 1250 /** 1251 * If required by this device, enable access to the SPROM. 1252 * 1253 * @param sc chipc driver state. 1254 */ 1255 static int 1256 chipc_enable_sprom_pins(struct chipc_softc *sc) 1257 { 1258 uint32_t cctrl; 1259 1260 CHIPC_LOCK_ASSERT(sc, MA_OWNED); 1261 KASSERT(sc->sprom_refcnt == 0, ("sprom pins already enabled")); 1262 1263 /* Nothing to do? */ 1264 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1265 return (0); 1266 1267 /* Check whether bus is busy */ 1268 if (!chipc_should_enable_muxed_sprom(sc)) 1269 return (EBUSY); 1270 1271 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1272 1273 /* 4331 devices */ 1274 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1275 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN; 1276 1277 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1278 cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1279 1280 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1281 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2; 1282 1283 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1284 return (0); 1285 } 1286 1287 /* 4360 devices */ 1288 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1289 /* Unimplemented */ 1290 } 1291 1292 /* Refuse to proceed on unsupported devices with muxed SPROM pins */ 1293 device_printf(sc->dev, "muxed sprom lines on unrecognized device\n"); 1294 return (ENXIO); 1295 } 1296 1297 /** 1298 * If required by this device, revert any GPIO/pin configuration applied 1299 * to allow SPROM access. 1300 * 1301 * @param sc chipc driver state. 1302 */ 1303 static void 1304 chipc_disable_sprom_pins(struct chipc_softc *sc) 1305 { 1306 uint32_t cctrl; 1307 1308 /* Nothing to do? */ 1309 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1310 return; 1311 1312 CHIPC_LOCK_ASSERT(sc, MA_OWNED); 1313 KASSERT(sc->sprom_refcnt == 0, ("sprom pins in use")); 1314 1315 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1316 1317 /* 4331 devices */ 1318 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1319 cctrl |= CHIPC_CCTRL4331_EXTPA_EN; 1320 1321 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1322 cctrl |= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1323 1324 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1325 cctrl |= CHIPC_CCTRL4331_EXTPA_EN2; 1326 1327 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1328 return; 1329 } 1330 1331 /* 4360 devices */ 1332 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1333 /* Unimplemented */ 1334 } 1335 } 1336 1337 static uint32_t 1338 chipc_read_chipst(device_t dev) 1339 { 1340 struct chipc_softc *sc = device_get_softc(dev); 1341 return (bhnd_bus_read_4(sc->core, CHIPC_CHIPST)); 1342 } 1343 1344 static void 1345 chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask) 1346 { 1347 struct chipc_softc *sc; 1348 uint32_t cctrl; 1349 1350 sc = device_get_softc(dev); 1351 1352 CHIPC_LOCK(sc); 1353 1354 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1355 cctrl = (cctrl & ~mask) | (value | mask); 1356 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1357 1358 CHIPC_UNLOCK(sc); 1359 } 1360 1361 static struct chipc_caps * 1362 chipc_get_caps(device_t dev) 1363 { 1364 struct chipc_softc *sc; 1365 1366 sc = device_get_softc(dev); 1367 return (&sc->caps); 1368 } 1369 1370 static device_method_t chipc_methods[] = { 1371 /* Device interface */ 1372 DEVMETHOD(device_probe, chipc_probe), 1373 DEVMETHOD(device_attach, chipc_attach), 1374 DEVMETHOD(device_detach, chipc_detach), 1375 DEVMETHOD(device_suspend, chipc_suspend), 1376 DEVMETHOD(device_resume, chipc_resume), 1377 1378 /* Bus interface */ 1379 DEVMETHOD(bus_probe_nomatch, chipc_probe_nomatch), 1380 DEVMETHOD(bus_print_child, chipc_print_child), 1381 DEVMETHOD(bus_child_pnpinfo_str, chipc_child_pnpinfo_str), 1382 DEVMETHOD(bus_child_location_str, chipc_child_location_str), 1383 1384 DEVMETHOD(bus_add_child, chipc_add_child), 1385 DEVMETHOD(bus_child_deleted, chipc_child_deleted), 1386 1387 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 1388 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 1389 DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource), 1390 DEVMETHOD(bus_alloc_resource, chipc_alloc_resource), 1391 DEVMETHOD(bus_release_resource, chipc_release_resource), 1392 DEVMETHOD(bus_adjust_resource, chipc_adjust_resource), 1393 DEVMETHOD(bus_activate_resource, chipc_activate_resource), 1394 DEVMETHOD(bus_deactivate_resource, chipc_deactivate_resource), 1395 DEVMETHOD(bus_get_resource_list, chipc_get_resource_list), 1396 1397 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1398 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1399 DEVMETHOD(bus_config_intr, bus_generic_config_intr), 1400 DEVMETHOD(bus_bind_intr, bus_generic_bind_intr), 1401 DEVMETHOD(bus_describe_intr, bus_generic_describe_intr), 1402 1403 /* BHND bus inteface */ 1404 DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource), 1405 1406 /* ChipCommon interface */ 1407 DEVMETHOD(bhnd_chipc_read_chipst, chipc_read_chipst), 1408 DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl), 1409 DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom), 1410 DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom), 1411 DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps), 1412 1413 DEVMETHOD_END 1414 }; 1415 1416 DEFINE_CLASS_0(bhnd_chipc, bhnd_chipc_driver, chipc_methods, sizeof(struct chipc_softc)); 1417 EARLY_DRIVER_MODULE(bhnd_chipc, bhnd, bhnd_chipc_driver, bhnd_chipc_devclass, 0, 0, 1418 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 1419 MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1); 1420 MODULE_VERSION(bhnd_chipc, 1); 1421