1 /*- 2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 3 * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com> 4 * Copyright (c) 2017 The FreeBSD Foundation 5 * All rights reserved. 6 * 7 * This software was developed by Landon Fuller under sponsorship from 8 * the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 18 * redistribution must be conditioned upon including a substantially 19 * similar Disclaimer requirement for further binary redistribution. 20 * 21 * NO WARRANTY 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 25 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 26 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 27 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 30 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGES. 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 /* 39 * Broadcom ChipCommon driver. 40 * 41 * With the exception of some very early chipsets, the ChipCommon core 42 * has been included in all HND SoCs and chipsets based on the siba(4) 43 * and bcma(4) interconnects, providing a common interface to chipset 44 * identification, bus enumeration, UARTs, clocks, watchdog interrupts, 45 * GPIO, flash, etc. 46 */ 47 48 #include <sys/param.h> 49 #include <sys/kernel.h> 50 #include <sys/lock.h> 51 #include <sys/bus.h> 52 #include <sys/rman.h> 53 #include <sys/malloc.h> 54 #include <sys/module.h> 55 #include <sys/mutex.h> 56 #include <sys/systm.h> 57 58 #include <machine/bus.h> 59 #include <machine/resource.h> 60 61 #include <dev/bhnd/bhnd.h> 62 #include <dev/bhnd/bhndvar.h> 63 64 #include "chipcreg.h" 65 #include "chipcvar.h" 66 67 #include "chipc_private.h" 68 69 devclass_t bhnd_chipc_devclass; /**< bhnd(4) chipcommon device class */ 70 71 static struct bhnd_device_quirk chipc_quirks[]; 72 73 /* Supported device identifiers */ 74 static const struct bhnd_device chipc_devices[] = { 75 BHND_DEVICE(BCM, CC, NULL, chipc_quirks), 76 BHND_DEVICE(BCM, 4706_CC, NULL, chipc_quirks), 77 BHND_DEVICE_END 78 }; 79 80 81 /* Device quirks table */ 82 static struct bhnd_device_quirk chipc_quirks[] = { 83 /* HND OTP controller revisions */ 84 BHND_CORE_QUIRK (HWREV_EQ (12), CHIPC_QUIRK_OTP_HND), /* (?) */ 85 BHND_CORE_QUIRK (HWREV_EQ (17), CHIPC_QUIRK_OTP_HND), /* BCM4311 */ 86 BHND_CORE_QUIRK (HWREV_EQ (22), CHIPC_QUIRK_OTP_HND), /* BCM4312 */ 87 88 /* IPX OTP controller revisions */ 89 BHND_CORE_QUIRK (HWREV_EQ (21), CHIPC_QUIRK_OTP_IPX), 90 BHND_CORE_QUIRK (HWREV_GTE(23), CHIPC_QUIRK_OTP_IPX), 91 92 BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM), 93 BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT), 94 BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPL_SIZE), 95 96 /* 4706 variant quirks */ 97 BHND_CORE_QUIRK (HWREV_EQ (38), CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */ 98 BHND_CHIP_QUIRK (4706, HWREV_ANY, CHIPC_QUIRK_4706_NFLASH), 99 100 /* 4331 quirks*/ 101 BHND_CHIP_QUIRK (4331, HWREV_ANY, CHIPC_QUIRK_4331_EXTPA_MUX_SPROM), 102 BHND_PKG_QUIRK (4331, TN, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 103 BHND_PKG_QUIRK (4331, TNA0, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 104 BHND_PKG_QUIRK (4331, TT, CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM), 105 106 /* 4360 quirks */ 107 BHND_CHIP_QUIRK (4352, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 108 BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 109 BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 110 BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 111 112 BHND_DEVICE_QUIRK_END 113 }; 114 115 static int chipc_add_children(struct chipc_softc *sc); 116 117 static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc, 118 struct chipc_caps *caps); 119 static int chipc_read_caps(struct chipc_softc *sc, 120 struct chipc_caps *caps); 121 122 static bool chipc_should_enable_muxed_sprom( 123 struct chipc_softc *sc); 124 static int chipc_enable_otp_power(struct chipc_softc *sc); 125 static void chipc_disable_otp_power(struct chipc_softc *sc); 126 static int chipc_enable_sprom_pins(struct chipc_softc *sc); 127 static void chipc_disable_sprom_pins(struct chipc_softc *sc); 128 129 static int chipc_try_activate_resource(struct chipc_softc *sc, 130 device_t child, int type, int rid, 131 struct resource *r, bool req_direct); 132 133 static int chipc_init_rman(struct chipc_softc *sc); 134 static void chipc_free_rman(struct chipc_softc *sc); 135 static struct rman *chipc_get_rman(struct chipc_softc *sc, int type); 136 137 /* quirk and capability flag convenience macros */ 138 #define CHIPC_QUIRK(_sc, _name) \ 139 ((_sc)->quirks & CHIPC_QUIRK_ ## _name) 140 141 #define CHIPC_CAP(_sc, _name) \ 142 ((_sc)->caps._name) 143 144 #define CHIPC_ASSERT_QUIRK(_sc, name) \ 145 KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set")) 146 147 #define CHIPC_ASSERT_CAP(_sc, name) \ 148 KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set")) 149 150 static int 151 chipc_probe(device_t dev) 152 { 153 const struct bhnd_device *id; 154 155 id = bhnd_device_lookup(dev, chipc_devices, sizeof(chipc_devices[0])); 156 if (id == NULL) 157 return (ENXIO); 158 159 bhnd_set_default_core_desc(dev); 160 return (BUS_PROBE_DEFAULT); 161 } 162 163 static int 164 chipc_attach(device_t dev) 165 { 166 struct chipc_softc *sc; 167 int error; 168 169 sc = device_get_softc(dev); 170 sc->dev = dev; 171 sc->quirks = bhnd_device_quirks(dev, chipc_devices, 172 sizeof(chipc_devices[0])); 173 sc->sprom_refcnt = 0; 174 175 CHIPC_LOCK_INIT(sc); 176 STAILQ_INIT(&sc->mem_regions); 177 178 /* Set up resource management */ 179 if ((error = chipc_init_rman(sc))) { 180 device_printf(sc->dev, 181 "failed to initialize chipc resource state: %d\n", error); 182 goto failed; 183 } 184 185 /* Allocate the region containing the chipc register block */ 186 if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) { 187 error = ENXIO; 188 goto failed; 189 } 190 191 error = chipc_retain_region(sc, sc->core_region, 192 RF_ALLOCATED|RF_ACTIVE); 193 if (error) { 194 sc->core_region = NULL; 195 goto failed; 196 } 197 198 /* Save a direct reference to our chipc registers */ 199 sc->core = sc->core_region->cr_res; 200 201 /* Fetch and parse capability register(s) */ 202 if ((error = chipc_read_caps(sc, &sc->caps))) 203 goto failed; 204 205 if (bootverbose) 206 chipc_print_caps(sc->dev, &sc->caps); 207 208 /* Attach all supported child devices */ 209 if ((error = chipc_add_children(sc))) 210 goto failed; 211 212 if ((error = bus_generic_attach(dev))) 213 goto failed; 214 215 /* Register ourselves with the bus */ 216 if ((error = bhnd_register_provider(dev, BHND_SERVICE_CHIPC))) 217 goto failed; 218 219 return (0); 220 221 failed: 222 device_delete_children(sc->dev); 223 224 if (sc->core_region != NULL) { 225 chipc_release_region(sc, sc->core_region, 226 RF_ALLOCATED|RF_ACTIVE); 227 } 228 229 chipc_free_rman(sc); 230 CHIPC_LOCK_DESTROY(sc); 231 return (error); 232 } 233 234 static int 235 chipc_detach(device_t dev) 236 { 237 struct chipc_softc *sc; 238 int error; 239 240 sc = device_get_softc(dev); 241 242 if ((error = bhnd_deregister_provider(dev, BHND_SERVICE_ANY))) 243 return (error); 244 245 if ((error = bus_generic_detach(dev))) 246 return (error); 247 248 chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE); 249 chipc_free_rman(sc); 250 251 CHIPC_LOCK_DESTROY(sc); 252 253 return (0); 254 } 255 256 static int 257 chipc_add_children(struct chipc_softc *sc) 258 { 259 device_t child; 260 const char *flash_bus; 261 int error; 262 263 /* SPROM/OTP */ 264 if (sc->caps.nvram_src == BHND_NVRAM_SRC_SPROM || 265 sc->caps.nvram_src == BHND_NVRAM_SRC_OTP) 266 { 267 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_nvram", -1); 268 if (child == NULL) { 269 device_printf(sc->dev, "failed to add nvram device\n"); 270 return (ENXIO); 271 } 272 273 /* Both OTP and external SPROM are mapped at CHIPC_SPROM_OTP */ 274 error = chipc_set_mem_resource(sc, child, 0, CHIPC_SPROM_OTP, 275 CHIPC_SPROM_OTP_SIZE, 0, 0); 276 if (error) { 277 device_printf(sc->dev, "failed to set OTP memory " 278 "resource: %d\n", error); 279 return (error); 280 } 281 } 282 283 /* 284 * PMU/PWR_CTRL 285 * 286 * On AOB ("Always on Bus") devices, the PMU core (if it exists) is 287 * attached directly to the bhnd(4) bus -- not chipc. 288 */ 289 if (sc->caps.pwr_ctrl || (sc->caps.pmu && !sc->caps.aob)) { 290 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pmu", -1); 291 if (child == NULL) { 292 device_printf(sc->dev, "failed to add pmu\n"); 293 return (ENXIO); 294 } 295 } 296 297 /* All remaining devices are SoC-only */ 298 if (bhnd_get_attach_type(sc->dev) != BHND_ATTACH_NATIVE) 299 return (0); 300 301 /* UARTs */ 302 for (u_int i = 0; i < min(sc->caps.num_uarts, CHIPC_UART_MAX); i++) { 303 int irq_rid, mem_rid; 304 305 irq_rid = 0; 306 mem_rid = 0; 307 308 child = BUS_ADD_CHILD(sc->dev, 0, "uart", -1); 309 if (child == NULL) { 310 device_printf(sc->dev, "failed to add uart%u\n", i); 311 return (ENXIO); 312 } 313 314 /* Shared IRQ */ 315 error = chipc_set_irq_resource(sc, child, irq_rid, 0); 316 if (error) { 317 device_printf(sc->dev, "failed to set uart%u irq %u\n", 318 i, 0); 319 return (error); 320 } 321 322 /* UART registers are mapped sequentially */ 323 error = chipc_set_mem_resource(sc, child, mem_rid, 324 CHIPC_UART(i), CHIPC_UART_SIZE, 0, 0); 325 if (error) { 326 device_printf(sc->dev, "failed to set uart%u memory " 327 "resource: %d\n", i, error); 328 return (error); 329 } 330 } 331 332 /* Flash */ 333 flash_bus = chipc_flash_bus_name(sc->caps.flash_type); 334 if (flash_bus != NULL) { 335 int rid; 336 337 child = BUS_ADD_CHILD(sc->dev, 0, flash_bus, -1); 338 if (child == NULL) { 339 device_printf(sc->dev, "failed to add %s device\n", 340 flash_bus); 341 return (ENXIO); 342 } 343 344 /* flash memory mapping */ 345 rid = 0; 346 error = chipc_set_mem_resource(sc, child, rid, 0, RM_MAX_END, 1, 347 1); 348 if (error) { 349 device_printf(sc->dev, "failed to set flash memory " 350 "resource %d: %d\n", rid, error); 351 return (error); 352 } 353 354 /* flashctrl registers */ 355 rid++; 356 error = chipc_set_mem_resource(sc, child, rid, 357 CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0, 0); 358 if (error) { 359 device_printf(sc->dev, "failed to set flash memory " 360 "resource %d: %d\n", rid, error); 361 return (error); 362 } 363 } 364 365 return (0); 366 } 367 368 /** 369 * Determine the NVRAM data source for this device. 370 * 371 * The SPROM, OTP, and flash capability flags must be fully populated in 372 * @p caps. 373 * 374 * @param sc chipc driver state. 375 * @param caps capability flags to be used to derive NVRAM configuration. 376 */ 377 static bhnd_nvram_src 378 chipc_find_nvram_src(struct chipc_softc *sc, struct chipc_caps *caps) 379 { 380 uint32_t otp_st, srom_ctrl; 381 382 /* 383 * We check for hardware presence in order of precedence. For example, 384 * SPROM is is always used in preference to internal OTP if found. 385 */ 386 if (CHIPC_QUIRK(sc, SUPPORTS_SPROM) && caps->sprom) { 387 srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL); 388 if (srom_ctrl & CHIPC_SRC_PRESENT) 389 return (BHND_NVRAM_SRC_SPROM); 390 } 391 392 /* Check for programmed OTP H/W subregion (contains SROM data) */ 393 if (CHIPC_QUIRK(sc, SUPPORTS_OTP) && caps->otp_size > 0) { 394 /* TODO: need access to HND-OTP device */ 395 if (!CHIPC_QUIRK(sc, OTP_HND)) { 396 device_printf(sc->dev, 397 "NVRAM unavailable: unsupported OTP controller.\n"); 398 return (BHND_NVRAM_SRC_UNKNOWN); 399 } 400 401 otp_st = bhnd_bus_read_4(sc->core, CHIPC_OTPST); 402 if (otp_st & CHIPC_OTPS_GUP_HW) 403 return (BHND_NVRAM_SRC_OTP); 404 } 405 406 /* Check for flash */ 407 if (caps->flash_type != CHIPC_FLASH_NONE) 408 return (BHND_NVRAM_SRC_FLASH); 409 410 /* No NVRAM hardware capability declared */ 411 return (BHND_NVRAM_SRC_UNKNOWN); 412 } 413 414 /* Read and parse chipc capabilities */ 415 static int 416 chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps) 417 { 418 uint32_t cap_reg; 419 uint32_t cap_ext_reg; 420 uint32_t regval; 421 422 /* Fetch cap registers */ 423 cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES); 424 cap_ext_reg = 0; 425 if (CHIPC_QUIRK(sc, SUPPORTS_CAP_EXT)) 426 cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT); 427 428 /* Extract values */ 429 caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART); 430 caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB); 431 caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO); 432 caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL); 433 434 caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS); 435 caps->pwr_ctrl = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL); 436 caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP); 437 438 caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL); 439 caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64); 440 caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM); 441 caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU); 442 caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI); 443 caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM); 444 caps->otp_size = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_OTP_SIZE); 445 446 caps->seci = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_SECI); 447 caps->gsio = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_GSIO); 448 caps->aob = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_AOB); 449 450 /* Fetch OTP size for later IPX controller revisions */ 451 if (CHIPC_QUIRK(sc, IPX_OTPL_SIZE)) { 452 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 453 caps->otp_size = CHIPC_GET_BITS(regval, CHIPC_OTPL_SIZE); 454 } 455 456 /* Determine flash type and parameters */ 457 caps->cfi_width = 0; 458 switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) { 459 case CHIPC_CAP_SFLASH_ST: 460 caps->flash_type = CHIPC_SFLASH_ST; 461 break; 462 case CHIPC_CAP_SFLASH_AT: 463 caps->flash_type = CHIPC_SFLASH_AT; 464 break; 465 case CHIPC_CAP_NFLASH: 466 /* unimplemented */ 467 caps->flash_type = CHIPC_NFLASH; 468 break; 469 case CHIPC_CAP_PFLASH: 470 caps->flash_type = CHIPC_PFLASH_CFI; 471 472 /* determine cfi width */ 473 regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG); 474 if (CHIPC_GET_FLAG(regval, CHIPC_FLASH_CFG_DS)) 475 caps->cfi_width = 2; 476 else 477 caps->cfi_width = 1; 478 479 break; 480 case CHIPC_CAP_FLASH_NONE: 481 caps->flash_type = CHIPC_FLASH_NONE; 482 break; 483 484 } 485 486 /* Handle 4706_NFLASH fallback */ 487 if (CHIPC_QUIRK(sc, 4706_NFLASH) && 488 CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_4706_NFLASH)) 489 { 490 caps->flash_type = CHIPC_NFLASH_4706; 491 } 492 493 494 /* Determine NVRAM source. Must occur after the SPROM/OTP/flash 495 * capability flags have been populated. */ 496 caps->nvram_src = chipc_find_nvram_src(sc, caps); 497 498 /* Determine the SPROM offset within OTP (if any). SPROM-formatted 499 * data is placed within the OTP general use region. */ 500 caps->sprom_offset = 0; 501 if (caps->nvram_src == BHND_NVRAM_SRC_OTP) { 502 CHIPC_ASSERT_QUIRK(sc, OTP_IPX); 503 504 /* Bit offset to GUP HW subregion containing SPROM data */ 505 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 506 caps->sprom_offset = CHIPC_GET_BITS(regval, CHIPC_OTPL_GUP); 507 508 /* Convert to bytes */ 509 caps->sprom_offset /= 8; 510 } 511 512 return (0); 513 } 514 515 static int 516 chipc_suspend(device_t dev) 517 { 518 return (bus_generic_suspend(dev)); 519 } 520 521 static int 522 chipc_resume(device_t dev) 523 { 524 return (bus_generic_resume(dev)); 525 } 526 527 static void 528 chipc_probe_nomatch(device_t dev, device_t child) 529 { 530 struct resource_list *rl; 531 const char *name; 532 533 name = device_get_name(child); 534 if (name == NULL) 535 name = "unknown device"; 536 537 device_printf(dev, "<%s> at", name); 538 539 rl = BUS_GET_RESOURCE_LIST(dev, child); 540 if (rl != NULL) { 541 resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 542 resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 543 } 544 545 printf(" (no driver attached)\n"); 546 } 547 548 static int 549 chipc_print_child(device_t dev, device_t child) 550 { 551 struct resource_list *rl; 552 int retval = 0; 553 554 retval += bus_print_child_header(dev, child); 555 556 rl = BUS_GET_RESOURCE_LIST(dev, child); 557 if (rl != NULL) { 558 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, 559 "%#jx"); 560 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, 561 "%jd"); 562 } 563 564 retval += bus_print_child_domain(dev, child); 565 retval += bus_print_child_footer(dev, child); 566 567 return (retval); 568 } 569 570 static int 571 chipc_child_pnpinfo_str(device_t dev, device_t child, char *buf, 572 size_t buflen) 573 { 574 if (buflen == 0) 575 return (EOVERFLOW); 576 577 *buf = '\0'; 578 return (0); 579 } 580 581 static int 582 chipc_child_location_str(device_t dev, device_t child, char *buf, 583 size_t buflen) 584 { 585 if (buflen == 0) 586 return (EOVERFLOW); 587 588 *buf = '\0'; 589 return (ENXIO); 590 } 591 592 static device_t 593 chipc_add_child(device_t dev, u_int order, const char *name, int unit) 594 { 595 struct chipc_softc *sc; 596 struct chipc_devinfo *dinfo; 597 device_t child; 598 599 sc = device_get_softc(dev); 600 601 child = device_add_child_ordered(dev, order, name, unit); 602 if (child == NULL) 603 return (NULL); 604 605 dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT); 606 if (dinfo == NULL) { 607 device_delete_child(dev, child); 608 return (NULL); 609 } 610 611 resource_list_init(&dinfo->resources); 612 dinfo->irq_mapped = false; 613 device_set_ivars(child, dinfo); 614 615 return (child); 616 } 617 618 static void 619 chipc_child_deleted(device_t dev, device_t child) 620 { 621 struct chipc_devinfo *dinfo = device_get_ivars(child); 622 623 if (dinfo != NULL) { 624 /* Free the child's resource list */ 625 resource_list_free(&dinfo->resources); 626 627 /* Unmap the child's IRQ */ 628 if (dinfo->irq_mapped) { 629 bhnd_unmap_intr(dev, dinfo->irq); 630 dinfo->irq_mapped = false; 631 } 632 633 free(dinfo, M_BHND); 634 } 635 636 device_set_ivars(child, NULL); 637 } 638 639 static struct resource_list * 640 chipc_get_resource_list(device_t dev, device_t child) 641 { 642 struct chipc_devinfo *dinfo = device_get_ivars(child); 643 return (&dinfo->resources); 644 } 645 646 647 /* Allocate region records for the given port, and add the port's memory 648 * range to the mem_rman */ 649 static int 650 chipc_rman_init_regions (struct chipc_softc *sc, bhnd_port_type type, 651 u_int port) 652 { 653 struct chipc_region *cr; 654 rman_res_t start, end; 655 u_int num_regions; 656 int error; 657 658 num_regions = bhnd_get_region_count(sc->dev, type, port); 659 for (u_int region = 0; region < num_regions; region++) { 660 /* Allocate new region record */ 661 cr = chipc_alloc_region(sc, type, port, region); 662 if (cr == NULL) 663 return (ENODEV); 664 665 /* Can't manage regions that cannot be allocated */ 666 if (cr->cr_rid < 0) { 667 BHND_DEBUG_DEV(sc->dev, "no rid for chipc region " 668 "%s%u.%u", bhnd_port_type_name(type), port, region); 669 chipc_free_region(sc, cr); 670 continue; 671 } 672 673 /* Add to rman's managed range */ 674 start = cr->cr_addr; 675 end = cr->cr_end; 676 if ((error = rman_manage_region(&sc->mem_rman, start, end))) { 677 chipc_free_region(sc, cr); 678 return (error); 679 } 680 681 /* Add to region list */ 682 STAILQ_INSERT_TAIL(&sc->mem_regions, cr, cr_link); 683 } 684 685 return (0); 686 } 687 688 /* Initialize memory state for all chipc port regions */ 689 static int 690 chipc_init_rman(struct chipc_softc *sc) 691 { 692 u_int num_ports; 693 int error; 694 695 /* Port types for which we'll register chipc_region mappings */ 696 bhnd_port_type types[] = { 697 BHND_PORT_DEVICE 698 }; 699 700 /* Initialize resource manager */ 701 sc->mem_rman.rm_start = 0; 702 sc->mem_rman.rm_end = BUS_SPACE_MAXADDR; 703 sc->mem_rman.rm_type = RMAN_ARRAY; 704 sc->mem_rman.rm_descr = "ChipCommon Device Memory"; 705 if ((error = rman_init(&sc->mem_rman))) { 706 device_printf(sc->dev, "could not initialize mem_rman: %d\n", 707 error); 708 return (error); 709 } 710 711 /* Populate per-port-region state */ 712 for (u_int i = 0; i < nitems(types); i++) { 713 num_ports = bhnd_get_port_count(sc->dev, types[i]); 714 for (u_int port = 0; port < num_ports; port++) { 715 error = chipc_rman_init_regions(sc, types[i], port); 716 if (error) { 717 device_printf(sc->dev, 718 "region init failed for %s%u: %d\n", 719 bhnd_port_type_name(types[i]), port, 720 error); 721 722 goto failed; 723 } 724 } 725 } 726 727 return (0); 728 729 failed: 730 chipc_free_rman(sc); 731 return (error); 732 } 733 734 /* Free memory management state */ 735 static void 736 chipc_free_rman(struct chipc_softc *sc) 737 { 738 struct chipc_region *cr, *cr_next; 739 740 STAILQ_FOREACH_SAFE(cr, &sc->mem_regions, cr_link, cr_next) 741 chipc_free_region(sc, cr); 742 743 rman_fini(&sc->mem_rman); 744 } 745 746 /** 747 * Return the rman instance for a given resource @p type, if any. 748 * 749 * @param sc The chipc device state. 750 * @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...) 751 */ 752 static struct rman * 753 chipc_get_rman(struct chipc_softc *sc, int type) 754 { 755 switch (type) { 756 case SYS_RES_MEMORY: 757 return (&sc->mem_rman); 758 759 case SYS_RES_IRQ: 760 /* We delegate IRQ resource management to the parent bus */ 761 return (NULL); 762 763 default: 764 return (NULL); 765 }; 766 } 767 768 static struct resource * 769 chipc_alloc_resource(device_t dev, device_t child, int type, 770 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 771 { 772 struct chipc_softc *sc; 773 struct chipc_region *cr; 774 struct resource_list_entry *rle; 775 struct resource *rv; 776 struct rman *rm; 777 int error; 778 bool passthrough, isdefault; 779 780 sc = device_get_softc(dev); 781 passthrough = (device_get_parent(child) != dev); 782 isdefault = RMAN_IS_DEFAULT_RANGE(start, end); 783 rle = NULL; 784 785 /* Fetch the resource manager, delegate request if necessary */ 786 rm = chipc_get_rman(sc, type); 787 if (rm == NULL) { 788 /* Requested resource type is delegated to our parent */ 789 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 790 start, end, count, flags); 791 return (rv); 792 } 793 794 /* Populate defaults */ 795 if (!passthrough && isdefault) { 796 /* Fetch the resource list entry. */ 797 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), 798 type, *rid); 799 if (rle == NULL) { 800 device_printf(dev, 801 "default resource %#x type %d for child %s " 802 "not found\n", *rid, type, 803 device_get_nameunit(child)); 804 return (NULL); 805 } 806 807 if (rle->res != NULL) { 808 device_printf(dev, 809 "resource entry %#x type %d for child %s is busy " 810 "[%d]\n", 811 *rid, type, device_get_nameunit(child), 812 rman_get_flags(rle->res)); 813 814 return (NULL); 815 } 816 817 start = rle->start; 818 end = rle->end; 819 count = ulmax(count, rle->count); 820 } 821 822 /* Locate a mapping region */ 823 if ((cr = chipc_find_region(sc, start, end)) == NULL) { 824 /* Resource requests outside our shared port regions can be 825 * delegated to our parent. */ 826 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 827 start, end, count, flags); 828 return (rv); 829 } 830 831 /* Try to retain a region reference */ 832 if ((error = chipc_retain_region(sc, cr, RF_ALLOCATED))) 833 return (NULL); 834 835 /* Make our rman reservation */ 836 rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE, 837 child); 838 if (rv == NULL) { 839 chipc_release_region(sc, cr, RF_ALLOCATED); 840 return (NULL); 841 } 842 843 rman_set_rid(rv, *rid); 844 845 /* Activate */ 846 if (flags & RF_ACTIVE) { 847 error = bus_activate_resource(child, type, *rid, rv); 848 if (error) { 849 device_printf(dev, 850 "failed to activate entry %#x type %d for " 851 "child %s: %d\n", 852 *rid, type, device_get_nameunit(child), error); 853 854 chipc_release_region(sc, cr, RF_ALLOCATED); 855 rman_release_resource(rv); 856 857 return (NULL); 858 } 859 } 860 861 /* Update child's resource list entry */ 862 if (rle != NULL) { 863 rle->res = rv; 864 rle->start = rman_get_start(rv); 865 rle->end = rman_get_end(rv); 866 rle->count = rman_get_size(rv); 867 } 868 869 return (rv); 870 } 871 872 static int 873 chipc_release_resource(device_t dev, device_t child, int type, int rid, 874 struct resource *r) 875 { 876 struct chipc_softc *sc; 877 struct chipc_region *cr; 878 struct rman *rm; 879 struct resource_list_entry *rle; 880 int error; 881 882 sc = device_get_softc(dev); 883 884 /* Handled by parent bus? */ 885 rm = chipc_get_rman(sc, type); 886 if (rm == NULL || !rman_is_region_manager(r, rm)) { 887 return (bus_generic_rl_release_resource(dev, child, type, rid, 888 r)); 889 } 890 891 /* Locate the mapping region */ 892 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 893 if (cr == NULL) 894 return (EINVAL); 895 896 /* Deactivate resources */ 897 if (rman_get_flags(r) & RF_ACTIVE) { 898 error = BUS_DEACTIVATE_RESOURCE(dev, child, type, rid, r); 899 if (error) 900 return (error); 901 } 902 903 if ((error = rman_release_resource(r))) 904 return (error); 905 906 /* Drop allocation reference */ 907 chipc_release_region(sc, cr, RF_ALLOCATED); 908 909 /* Clear reference from the resource list entry if exists */ 910 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), type, rid); 911 if (rle != NULL) 912 rle->res = NULL; 913 914 return (0); 915 } 916 917 static int 918 chipc_adjust_resource(device_t dev, device_t child, int type, 919 struct resource *r, rman_res_t start, rman_res_t end) 920 { 921 struct chipc_softc *sc; 922 struct chipc_region *cr; 923 struct rman *rm; 924 925 sc = device_get_softc(dev); 926 927 /* Handled by parent bus? */ 928 rm = chipc_get_rman(sc, type); 929 if (rm == NULL || !rman_is_region_manager(r, rm)) { 930 return (bus_generic_adjust_resource(dev, child, type, r, start, 931 end)); 932 } 933 934 /* The range is limited to the existing region mapping */ 935 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 936 if (cr == NULL) 937 return (EINVAL); 938 939 if (end <= start) 940 return (EINVAL); 941 942 if (start < cr->cr_addr || end > cr->cr_end) 943 return (EINVAL); 944 945 /* Range falls within the existing region */ 946 return (rman_adjust_resource(r, start, end)); 947 } 948 949 /** 950 * Retain an RF_ACTIVE reference to the region mapping @p r, and 951 * configure @p r with its subregion values. 952 * 953 * @param sc Driver instance state. 954 * @param child Requesting child device. 955 * @param type resource type of @p r. 956 * @param rid resource id of @p r 957 * @param r resource to be activated. 958 * @param req_direct If true, failure to allocate a direct bhnd resource 959 * will be treated as an error. If false, the resource will not be marked 960 * as RF_ACTIVE if bhnd direct resource allocation fails. 961 */ 962 static int 963 chipc_try_activate_resource(struct chipc_softc *sc, device_t child, int type, 964 int rid, struct resource *r, bool req_direct) 965 { 966 struct rman *rm; 967 struct chipc_region *cr; 968 bhnd_size_t cr_offset; 969 rman_res_t r_start, r_end, r_size; 970 int error; 971 972 rm = chipc_get_rman(sc, type); 973 if (rm == NULL || !rman_is_region_manager(r, rm)) 974 return (EINVAL); 975 976 r_start = rman_get_start(r); 977 r_end = rman_get_end(r); 978 r_size = rman_get_size(r); 979 980 /* Find the corresponding chipc region */ 981 cr = chipc_find_region(sc, r_start, r_end); 982 if (cr == NULL) 983 return (EINVAL); 984 985 /* Calculate subregion offset within the chipc region */ 986 cr_offset = r_start - cr->cr_addr; 987 988 /* Retain (and activate, if necessary) the chipc region */ 989 if ((error = chipc_retain_region(sc, cr, RF_ACTIVE))) 990 return (error); 991 992 /* Configure child resource with its subregion values. */ 993 if (cr->cr_res->direct) { 994 error = chipc_init_child_resource(r, cr->cr_res->res, 995 cr_offset, r_size); 996 if (error) 997 goto cleanup; 998 999 /* Mark active */ 1000 if ((error = rman_activate_resource(r))) 1001 goto cleanup; 1002 } else if (req_direct) { 1003 error = ENOMEM; 1004 goto cleanup; 1005 } 1006 1007 return (0); 1008 1009 cleanup: 1010 chipc_release_region(sc, cr, RF_ACTIVE); 1011 return (error); 1012 } 1013 1014 static int 1015 chipc_activate_bhnd_resource(device_t dev, device_t child, int type, 1016 int rid, struct bhnd_resource *r) 1017 { 1018 struct chipc_softc *sc; 1019 struct rman *rm; 1020 int error; 1021 1022 sc = device_get_softc(dev); 1023 1024 /* Delegate non-locally managed resources to parent */ 1025 rm = chipc_get_rman(sc, type); 1026 if (rm == NULL || !rman_is_region_manager(r->res, rm)) { 1027 return (bhnd_bus_generic_activate_resource(dev, child, type, 1028 rid, r)); 1029 } 1030 1031 /* Try activating the chipc region resource */ 1032 error = chipc_try_activate_resource(sc, child, type, rid, r->res, 1033 false); 1034 if (error) 1035 return (error); 1036 1037 /* Mark the child resource as direct according to the returned resource 1038 * state */ 1039 if (rman_get_flags(r->res) & RF_ACTIVE) 1040 r->direct = true; 1041 1042 return (0); 1043 } 1044 1045 static int 1046 chipc_activate_resource(device_t dev, device_t child, int type, int rid, 1047 struct resource *r) 1048 { 1049 struct chipc_softc *sc; 1050 struct rman *rm; 1051 1052 sc = device_get_softc(dev); 1053 1054 /* Delegate non-locally managed resources to parent */ 1055 rm = chipc_get_rman(sc, type); 1056 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1057 return (bus_generic_activate_resource(dev, child, type, rid, 1058 r)); 1059 } 1060 1061 /* Try activating the chipc region-based resource */ 1062 return (chipc_try_activate_resource(sc, child, type, rid, r, true)); 1063 } 1064 1065 /** 1066 * Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE(). 1067 */ 1068 static int 1069 chipc_deactivate_resource(device_t dev, device_t child, int type, 1070 int rid, struct resource *r) 1071 { 1072 struct chipc_softc *sc; 1073 struct chipc_region *cr; 1074 struct rman *rm; 1075 int error; 1076 1077 sc = device_get_softc(dev); 1078 1079 /* Handled by parent bus? */ 1080 rm = chipc_get_rman(sc, type); 1081 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1082 return (bus_generic_deactivate_resource(dev, child, type, rid, 1083 r)); 1084 } 1085 1086 /* Find the corresponding chipc region */ 1087 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 1088 if (cr == NULL) 1089 return (EINVAL); 1090 1091 /* Mark inactive */ 1092 if ((error = rman_deactivate_resource(r))) 1093 return (error); 1094 1095 /* Drop associated RF_ACTIVE reference */ 1096 chipc_release_region(sc, cr, RF_ACTIVE); 1097 1098 return (0); 1099 } 1100 1101 /** 1102 * Examine bus state and make a best effort determination of whether it's 1103 * likely safe to enable the muxed SPROM pins. 1104 * 1105 * On devices that do not use SPROM pin muxing, always returns true. 1106 * 1107 * @param sc chipc driver state. 1108 */ 1109 static bool 1110 chipc_should_enable_muxed_sprom(struct chipc_softc *sc) 1111 { 1112 device_t *devs; 1113 device_t hostb; 1114 device_t parent; 1115 int devcount; 1116 int error; 1117 bool result; 1118 1119 /* Nothing to do? */ 1120 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1121 return (true); 1122 1123 mtx_lock(&Giant); /* for newbus */ 1124 1125 parent = device_get_parent(sc->dev); 1126 hostb = bhnd_bus_find_hostb_device(parent); 1127 1128 if ((error = device_get_children(parent, &devs, &devcount))) { 1129 mtx_unlock(&Giant); 1130 return (false); 1131 } 1132 1133 /* Reject any active devices other than ChipCommon, or the 1134 * host bridge (if any). */ 1135 result = true; 1136 for (int i = 0; i < devcount; i++) { 1137 if (devs[i] == hostb || devs[i] == sc->dev) 1138 continue; 1139 1140 if (!device_is_attached(devs[i])) 1141 continue; 1142 1143 if (device_is_suspended(devs[i])) 1144 continue; 1145 1146 /* Active device; assume SPROM is busy */ 1147 result = false; 1148 break; 1149 } 1150 1151 free(devs, M_TEMP); 1152 mtx_unlock(&Giant); 1153 return (result); 1154 } 1155 1156 static int 1157 chipc_enable_sprom(device_t dev) 1158 { 1159 struct chipc_softc *sc; 1160 int error; 1161 1162 sc = device_get_softc(dev); 1163 CHIPC_LOCK(sc); 1164 1165 /* Already enabled? */ 1166 if (sc->sprom_refcnt >= 1) { 1167 sc->sprom_refcnt++; 1168 CHIPC_UNLOCK(sc); 1169 1170 return (0); 1171 } 1172 1173 switch (sc->caps.nvram_src) { 1174 case BHND_NVRAM_SRC_SPROM: 1175 error = chipc_enable_sprom_pins(sc); 1176 break; 1177 case BHND_NVRAM_SRC_OTP: 1178 error = chipc_enable_otp_power(sc); 1179 break; 1180 default: 1181 error = 0; 1182 break; 1183 } 1184 1185 /* Bump the reference count */ 1186 if (error == 0) 1187 sc->sprom_refcnt++; 1188 1189 CHIPC_UNLOCK(sc); 1190 return (error); 1191 } 1192 1193 static void 1194 chipc_disable_sprom(device_t dev) 1195 { 1196 struct chipc_softc *sc; 1197 1198 sc = device_get_softc(dev); 1199 CHIPC_LOCK(sc); 1200 1201 /* Check reference count, skip disable if in-use. */ 1202 KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease")); 1203 sc->sprom_refcnt--; 1204 if (sc->sprom_refcnt > 0) { 1205 CHIPC_UNLOCK(sc); 1206 return; 1207 } 1208 1209 switch (sc->caps.nvram_src) { 1210 case BHND_NVRAM_SRC_SPROM: 1211 chipc_disable_sprom_pins(sc); 1212 break; 1213 case BHND_NVRAM_SRC_OTP: 1214 chipc_disable_otp_power(sc); 1215 break; 1216 default: 1217 break; 1218 } 1219 1220 1221 CHIPC_UNLOCK(sc); 1222 } 1223 1224 static int 1225 chipc_enable_otp_power(struct chipc_softc *sc) 1226 { 1227 // TODO: Enable OTP resource via PMU, and wait up to 100 usec for 1228 // OTPS_READY to be set in `optstatus`. 1229 return (0); 1230 } 1231 1232 static void 1233 chipc_disable_otp_power(struct chipc_softc *sc) 1234 { 1235 // TODO: Disable OTP resource via PMU 1236 } 1237 1238 /** 1239 * If required by this device, enable access to the SPROM. 1240 * 1241 * @param sc chipc driver state. 1242 */ 1243 static int 1244 chipc_enable_sprom_pins(struct chipc_softc *sc) 1245 { 1246 uint32_t cctrl; 1247 1248 CHIPC_LOCK_ASSERT(sc, MA_OWNED); 1249 KASSERT(sc->sprom_refcnt == 0, ("sprom pins already enabled")); 1250 1251 /* Nothing to do? */ 1252 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1253 return (0); 1254 1255 /* Check whether bus is busy */ 1256 if (!chipc_should_enable_muxed_sprom(sc)) 1257 return (EBUSY); 1258 1259 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1260 1261 /* 4331 devices */ 1262 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1263 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN; 1264 1265 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1266 cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1267 1268 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1269 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2; 1270 1271 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1272 return (0); 1273 } 1274 1275 /* 4360 devices */ 1276 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1277 /* Unimplemented */ 1278 } 1279 1280 /* Refuse to proceed on unsupported devices with muxed SPROM pins */ 1281 device_printf(sc->dev, "muxed sprom lines on unrecognized device\n"); 1282 return (ENXIO); 1283 } 1284 1285 /** 1286 * If required by this device, revert any GPIO/pin configuration applied 1287 * to allow SPROM access. 1288 * 1289 * @param sc chipc driver state. 1290 */ 1291 static void 1292 chipc_disable_sprom_pins(struct chipc_softc *sc) 1293 { 1294 uint32_t cctrl; 1295 1296 /* Nothing to do? */ 1297 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1298 return; 1299 1300 CHIPC_LOCK_ASSERT(sc, MA_OWNED); 1301 KASSERT(sc->sprom_refcnt == 0, ("sprom pins in use")); 1302 1303 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1304 1305 /* 4331 devices */ 1306 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1307 cctrl |= CHIPC_CCTRL4331_EXTPA_EN; 1308 1309 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1310 cctrl |= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1311 1312 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1313 cctrl |= CHIPC_CCTRL4331_EXTPA_EN2; 1314 1315 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1316 return; 1317 } 1318 1319 /* 4360 devices */ 1320 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1321 /* Unimplemented */ 1322 } 1323 } 1324 1325 static uint32_t 1326 chipc_read_chipst(device_t dev) 1327 { 1328 struct chipc_softc *sc = device_get_softc(dev); 1329 return (bhnd_bus_read_4(sc->core, CHIPC_CHIPST)); 1330 } 1331 1332 static void 1333 chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask) 1334 { 1335 struct chipc_softc *sc; 1336 uint32_t cctrl; 1337 1338 sc = device_get_softc(dev); 1339 1340 CHIPC_LOCK(sc); 1341 1342 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1343 cctrl = (cctrl & ~mask) | (value | mask); 1344 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1345 1346 CHIPC_UNLOCK(sc); 1347 } 1348 1349 static struct chipc_caps * 1350 chipc_get_caps(device_t dev) 1351 { 1352 struct chipc_softc *sc; 1353 1354 sc = device_get_softc(dev); 1355 return (&sc->caps); 1356 } 1357 1358 static device_method_t chipc_methods[] = { 1359 /* Device interface */ 1360 DEVMETHOD(device_probe, chipc_probe), 1361 DEVMETHOD(device_attach, chipc_attach), 1362 DEVMETHOD(device_detach, chipc_detach), 1363 DEVMETHOD(device_suspend, chipc_suspend), 1364 DEVMETHOD(device_resume, chipc_resume), 1365 1366 /* Bus interface */ 1367 DEVMETHOD(bus_probe_nomatch, chipc_probe_nomatch), 1368 DEVMETHOD(bus_print_child, chipc_print_child), 1369 DEVMETHOD(bus_child_pnpinfo_str, chipc_child_pnpinfo_str), 1370 DEVMETHOD(bus_child_location_str, chipc_child_location_str), 1371 1372 DEVMETHOD(bus_add_child, chipc_add_child), 1373 DEVMETHOD(bus_child_deleted, chipc_child_deleted), 1374 1375 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 1376 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 1377 DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource), 1378 DEVMETHOD(bus_alloc_resource, chipc_alloc_resource), 1379 DEVMETHOD(bus_release_resource, chipc_release_resource), 1380 DEVMETHOD(bus_adjust_resource, chipc_adjust_resource), 1381 DEVMETHOD(bus_activate_resource, chipc_activate_resource), 1382 DEVMETHOD(bus_deactivate_resource, chipc_deactivate_resource), 1383 DEVMETHOD(bus_get_resource_list, chipc_get_resource_list), 1384 1385 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1386 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1387 DEVMETHOD(bus_config_intr, bus_generic_config_intr), 1388 DEVMETHOD(bus_bind_intr, bus_generic_bind_intr), 1389 DEVMETHOD(bus_describe_intr, bus_generic_describe_intr), 1390 1391 /* BHND bus inteface */ 1392 DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource), 1393 1394 /* ChipCommon interface */ 1395 DEVMETHOD(bhnd_chipc_read_chipst, chipc_read_chipst), 1396 DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl), 1397 DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom), 1398 DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom), 1399 DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps), 1400 1401 DEVMETHOD_END 1402 }; 1403 1404 DEFINE_CLASS_0(bhnd_chipc, bhnd_chipc_driver, chipc_methods, sizeof(struct chipc_softc)); 1405 EARLY_DRIVER_MODULE(bhnd_chipc, bhnd, bhnd_chipc_driver, bhnd_chipc_devclass, 0, 0, 1406 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 1407 MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1); 1408 MODULE_VERSION(bhnd_chipc, 1); 1409