1 /*- 2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 3 * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 13 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 14 * redistribution must be conditioned upon including a substantially 15 * similar Disclaimer requirement for further binary redistribution. 16 * 17 * NO WARRANTY 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 21 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 23 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 26 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGES. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * Broadcom ChipCommon driver. 36 * 37 * With the exception of some very early chipsets, the ChipCommon core 38 * has been included in all HND SoCs and chipsets based on the siba(4) 39 * and bcma(4) interconnects, providing a common interface to chipset 40 * identification, bus enumeration, UARTs, clocks, watchdog interrupts, 41 * GPIO, flash, etc. 42 */ 43 44 #include <sys/param.h> 45 #include <sys/kernel.h> 46 #include <sys/lock.h> 47 #include <sys/bus.h> 48 #include <sys/rman.h> 49 #include <sys/malloc.h> 50 #include <sys/module.h> 51 #include <sys/mutex.h> 52 #include <sys/systm.h> 53 54 #include <machine/bus.h> 55 #include <machine/resource.h> 56 57 #include <dev/bhnd/bhnd.h> 58 #include <dev/bhnd/bhndvar.h> 59 60 #include "chipcreg.h" 61 #include "chipcvar.h" 62 63 #include "chipc_private.h" 64 65 devclass_t bhnd_chipc_devclass; /**< bhnd(4) chipcommon device class */ 66 67 static struct bhnd_device_quirk chipc_quirks[]; 68 69 /* Supported device identifiers */ 70 static const struct bhnd_device chipc_devices[] = { 71 BHND_DEVICE(BCM, CC, NULL, chipc_quirks), 72 BHND_DEVICE_END 73 }; 74 75 76 /* Device quirks table */ 77 static struct bhnd_device_quirk chipc_quirks[] = { 78 /* HND OTP controller revisions */ 79 BHND_CORE_QUIRK (HWREV_EQ (12), CHIPC_QUIRK_OTP_HND), /* (?) */ 80 BHND_CORE_QUIRK (HWREV_EQ (17), CHIPC_QUIRK_OTP_HND), /* BCM4311 */ 81 BHND_CORE_QUIRK (HWREV_EQ (22), CHIPC_QUIRK_OTP_HND), /* BCM4312 */ 82 83 /* IPX OTP controller revisions */ 84 BHND_CORE_QUIRK (HWREV_EQ (21), CHIPC_QUIRK_OTP_IPX), 85 BHND_CORE_QUIRK (HWREV_GTE(23), CHIPC_QUIRK_OTP_IPX), 86 87 BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM), 88 BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT), 89 BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPL_SIZE), 90 91 /* 4706 variant quirks */ 92 BHND_CORE_QUIRK (HWREV_EQ (38), CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */ 93 BHND_CHIP_QUIRK (4706, HWREV_ANY, CHIPC_QUIRK_4706_NFLASH), 94 95 /* 4331 quirks*/ 96 BHND_CHIP_QUIRK (4331, HWREV_ANY, CHIPC_QUIRK_4331_EXTPA_MUX_SPROM), 97 BHND_PKG_QUIRK (4331, TN, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 98 BHND_PKG_QUIRK (4331, TNA0, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 99 BHND_PKG_QUIRK (4331, TT, CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM), 100 101 /* 4360 quirks */ 102 BHND_CHIP_QUIRK (4352, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 103 BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 104 BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 105 BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 106 107 BHND_DEVICE_QUIRK_END 108 }; 109 110 // FIXME: IRQ shouldn't be hard-coded 111 #define CHIPC_MIPS_IRQ 2 112 113 static int chipc_add_children(struct chipc_softc *sc); 114 115 static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc, 116 struct chipc_caps *caps); 117 static int chipc_read_caps(struct chipc_softc *sc, 118 struct chipc_caps *caps); 119 120 static bool chipc_should_enable_muxed_sprom( 121 struct chipc_softc *sc); 122 static int chipc_enable_otp_power(struct chipc_softc *sc); 123 static void chipc_disable_otp_power(struct chipc_softc *sc); 124 static int chipc_enable_sprom_pins(struct chipc_softc *sc); 125 static void chipc_disable_sprom_pins(struct chipc_softc *sc); 126 127 static int chipc_try_activate_resource(struct chipc_softc *sc, 128 device_t child, int type, int rid, 129 struct resource *r, bool req_direct); 130 131 static int chipc_init_rman(struct chipc_softc *sc); 132 static void chipc_free_rman(struct chipc_softc *sc); 133 static struct rman *chipc_get_rman(struct chipc_softc *sc, int type); 134 135 /* quirk and capability flag convenience macros */ 136 #define CHIPC_QUIRK(_sc, _name) \ 137 ((_sc)->quirks & CHIPC_QUIRK_ ## _name) 138 139 #define CHIPC_CAP(_sc, _name) \ 140 ((_sc)->caps._name) 141 142 #define CHIPC_ASSERT_QUIRK(_sc, name) \ 143 KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set")) 144 145 #define CHIPC_ASSERT_CAP(_sc, name) \ 146 KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set")) 147 148 static int 149 chipc_probe(device_t dev) 150 { 151 const struct bhnd_device *id; 152 153 id = bhnd_device_lookup(dev, chipc_devices, sizeof(chipc_devices[0])); 154 if (id == NULL) 155 return (ENXIO); 156 157 bhnd_set_default_core_desc(dev); 158 return (BUS_PROBE_DEFAULT); 159 } 160 161 static int 162 chipc_attach(device_t dev) 163 { 164 struct chipc_softc *sc; 165 int error; 166 167 sc = device_get_softc(dev); 168 sc->dev = dev; 169 sc->quirks = bhnd_device_quirks(dev, chipc_devices, 170 sizeof(chipc_devices[0])); 171 sc->sprom_refcnt = 0; 172 173 CHIPC_LOCK_INIT(sc); 174 STAILQ_INIT(&sc->mem_regions); 175 176 /* Set up resource management */ 177 if ((error = chipc_init_rman(sc))) { 178 device_printf(sc->dev, 179 "failed to initialize chipc resource state: %d\n", error); 180 goto failed; 181 } 182 183 /* Allocate the region containing the chipc register block */ 184 if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) { 185 error = ENXIO; 186 goto failed; 187 } 188 189 error = chipc_retain_region(sc, sc->core_region, 190 RF_ALLOCATED|RF_ACTIVE); 191 if (error) { 192 sc->core_region = NULL; 193 goto failed; 194 } 195 196 /* Save a direct reference to our chipc registers */ 197 sc->core = sc->core_region->cr_res; 198 199 /* Fetch and parse capability register(s) */ 200 if ((error = chipc_read_caps(sc, &sc->caps))) 201 goto failed; 202 203 if (bootverbose) 204 chipc_print_caps(sc->dev, &sc->caps); 205 206 /* Attach all supported child devices */ 207 if ((error = chipc_add_children(sc))) 208 goto failed; 209 210 if ((error = bus_generic_attach(dev))) 211 goto failed; 212 213 return (0); 214 215 failed: 216 device_delete_children(sc->dev); 217 218 if (sc->core_region != NULL) { 219 chipc_release_region(sc, sc->core_region, 220 RF_ALLOCATED|RF_ACTIVE); 221 } 222 223 chipc_free_rman(sc); 224 CHIPC_LOCK_DESTROY(sc); 225 return (error); 226 } 227 228 static int 229 chipc_detach(device_t dev) 230 { 231 struct chipc_softc *sc; 232 int error; 233 234 sc = device_get_softc(dev); 235 236 if ((error = bus_generic_detach(dev))) 237 return (error); 238 239 chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE); 240 chipc_free_rman(sc); 241 242 CHIPC_LOCK_DESTROY(sc); 243 244 return (0); 245 } 246 247 static int 248 chipc_add_children(struct chipc_softc *sc) 249 { 250 device_t child; 251 const char *flash_bus; 252 int error; 253 254 /* SPROM/OTP */ 255 if (sc->caps.nvram_src == BHND_NVRAM_SRC_SPROM || 256 sc->caps.nvram_src == BHND_NVRAM_SRC_OTP) 257 { 258 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_nvram", -1); 259 if (child == NULL) { 260 device_printf(sc->dev, "failed to add nvram device\n"); 261 return (ENXIO); 262 } 263 264 /* Both OTP and external SPROM are mapped at CHIPC_SPROM_OTP */ 265 error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, 266 CHIPC_SPROM_OTP, CHIPC_SPROM_OTP_SIZE, 0, 0); 267 if (error) 268 return (error); 269 } 270 271 /* 272 * PMU/PWR_CTRL 273 * 274 * On AOB ("Always on Bus") devices, the PMU core (if it exists) is 275 * attached directly to the bhnd(4) bus -- not chipc. 276 */ 277 if (sc->caps.pwr_ctrl || (sc->caps.pmu && !sc->caps.aob)) { 278 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pmu", -1); 279 if (child == NULL) { 280 device_printf(sc->dev, "failed to add pmu\n"); 281 return (ENXIO); 282 } 283 } 284 285 /* All remaining devices are SoC-only */ 286 if (bhnd_get_attach_type(sc->dev) != BHND_ATTACH_NATIVE) 287 return (0); 288 289 /* UARTs */ 290 for (u_int i = 0; i < min(sc->caps.num_uarts, CHIPC_UART_MAX); i++) { 291 child = BUS_ADD_CHILD(sc->dev, 0, "uart", -1); 292 if (child == NULL) { 293 device_printf(sc->dev, "failed to add uart%u\n", i); 294 return (ENXIO); 295 } 296 297 /* Shared IRQ */ 298 error = bus_set_resource(child, SYS_RES_IRQ, 0, CHIPC_MIPS_IRQ, 299 1); 300 if (error) { 301 device_printf(sc->dev, "failed to set uart%u irq %u\n", 302 i, CHIPC_MIPS_IRQ); 303 return (error); 304 } 305 306 /* UART registers are mapped sequentially */ 307 error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, 308 CHIPC_UART(i), CHIPC_UART_SIZE, 0, 0); 309 if (error) 310 return (error); 311 } 312 313 /* Flash */ 314 flash_bus = chipc_flash_bus_name(sc->caps.flash_type); 315 if (flash_bus != NULL) { 316 child = BUS_ADD_CHILD(sc->dev, 0, flash_bus, -1); 317 if (child == NULL) { 318 device_printf(sc->dev, "failed to add %s device\n", 319 flash_bus); 320 return (ENXIO); 321 } 322 323 /* flash memory mapping */ 324 error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, 325 0, RM_MAX_END, 1, 1); 326 if (error) 327 return (error); 328 329 /* flashctrl registers */ 330 error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 1, 331 CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0, 0); 332 if (error) 333 return (error); 334 } 335 336 return (0); 337 } 338 339 /** 340 * Determine the NVRAM data source for this device. 341 * 342 * The SPROM, OTP, and flash capability flags must be fully populated in 343 * @p caps. 344 * 345 * @param sc chipc driver state. 346 * @param caps capability flags to be used to derive NVRAM configuration. 347 */ 348 static bhnd_nvram_src 349 chipc_find_nvram_src(struct chipc_softc *sc, struct chipc_caps *caps) 350 { 351 uint32_t otp_st, srom_ctrl; 352 353 /* 354 * We check for hardware presence in order of precedence. For example, 355 * SPROM is is always used in preference to internal OTP if found. 356 */ 357 if (CHIPC_QUIRK(sc, SUPPORTS_SPROM) && caps->sprom) { 358 srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL); 359 if (srom_ctrl & CHIPC_SRC_PRESENT) 360 return (BHND_NVRAM_SRC_SPROM); 361 } 362 363 /* Check for programmed OTP H/W subregion (contains SROM data) */ 364 if (CHIPC_QUIRK(sc, SUPPORTS_OTP) && caps->otp_size > 0) { 365 /* TODO: need access to HND-OTP device */ 366 if (!CHIPC_QUIRK(sc, OTP_HND)) { 367 device_printf(sc->dev, 368 "NVRAM unavailable: unsupported OTP controller.\n"); 369 return (BHND_NVRAM_SRC_UNKNOWN); 370 } 371 372 otp_st = bhnd_bus_read_4(sc->core, CHIPC_OTPST); 373 if (otp_st & CHIPC_OTPS_GUP_HW) 374 return (BHND_NVRAM_SRC_OTP); 375 } 376 377 /* Check for flash */ 378 if (caps->flash_type != CHIPC_FLASH_NONE) 379 return (BHND_NVRAM_SRC_FLASH); 380 381 /* No NVRAM hardware capability declared */ 382 return (BHND_NVRAM_SRC_UNKNOWN); 383 } 384 385 /* Read and parse chipc capabilities */ 386 static int 387 chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps) 388 { 389 uint32_t cap_reg; 390 uint32_t cap_ext_reg; 391 uint32_t regval; 392 393 /* Fetch cap registers */ 394 cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES); 395 cap_ext_reg = 0; 396 if (CHIPC_QUIRK(sc, SUPPORTS_CAP_EXT)) 397 cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT); 398 399 /* Extract values */ 400 caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART); 401 caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB); 402 caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO); 403 caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL); 404 405 caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS); 406 caps->pwr_ctrl = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL); 407 caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP); 408 409 caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL); 410 caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64); 411 caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM); 412 caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU); 413 caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI); 414 caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM); 415 caps->otp_size = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_OTP_SIZE); 416 417 caps->seci = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_SECI); 418 caps->gsio = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_GSIO); 419 caps->aob = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_AOB); 420 421 /* Fetch OTP size for later IPX controller revisions */ 422 if (CHIPC_QUIRK(sc, IPX_OTPL_SIZE)) { 423 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 424 caps->otp_size = CHIPC_GET_BITS(regval, CHIPC_OTPL_SIZE); 425 } 426 427 /* Determine flash type and parameters */ 428 caps->cfi_width = 0; 429 switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) { 430 case CHIPC_CAP_SFLASH_ST: 431 caps->flash_type = CHIPC_SFLASH_ST; 432 break; 433 case CHIPC_CAP_SFLASH_AT: 434 caps->flash_type = CHIPC_SFLASH_AT; 435 break; 436 case CHIPC_CAP_NFLASH: 437 /* unimplemented */ 438 caps->flash_type = CHIPC_NFLASH; 439 break; 440 case CHIPC_CAP_PFLASH: 441 caps->flash_type = CHIPC_PFLASH_CFI; 442 443 /* determine cfi width */ 444 regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG); 445 if (CHIPC_GET_FLAG(regval, CHIPC_FLASH_CFG_DS)) 446 caps->cfi_width = 2; 447 else 448 caps->cfi_width = 1; 449 450 break; 451 case CHIPC_CAP_FLASH_NONE: 452 caps->flash_type = CHIPC_FLASH_NONE; 453 break; 454 455 } 456 457 /* Handle 4706_NFLASH fallback */ 458 if (CHIPC_QUIRK(sc, 4706_NFLASH) && 459 CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_4706_NFLASH)) 460 { 461 caps->flash_type = CHIPC_NFLASH_4706; 462 } 463 464 465 /* Determine NVRAM source. Must occur after the SPROM/OTP/flash 466 * capability flags have been populated. */ 467 caps->nvram_src = chipc_find_nvram_src(sc, caps); 468 469 /* Determine the SPROM offset within OTP (if any). SPROM-formatted 470 * data is placed within the OTP general use region. */ 471 caps->sprom_offset = 0; 472 if (caps->nvram_src == BHND_NVRAM_SRC_OTP) { 473 CHIPC_ASSERT_QUIRK(sc, OTP_IPX); 474 475 /* Bit offset to GUP HW subregion containing SPROM data */ 476 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 477 caps->sprom_offset = CHIPC_GET_BITS(regval, CHIPC_OTPL_GUP); 478 479 /* Convert to bytes */ 480 caps->sprom_offset /= 8; 481 } 482 483 return (0); 484 } 485 486 static int 487 chipc_suspend(device_t dev) 488 { 489 return (bus_generic_suspend(dev)); 490 } 491 492 static int 493 chipc_resume(device_t dev) 494 { 495 return (bus_generic_resume(dev)); 496 } 497 498 static void 499 chipc_probe_nomatch(device_t dev, device_t child) 500 { 501 struct resource_list *rl; 502 const char *name; 503 504 name = device_get_name(child); 505 if (name == NULL) 506 name = "unknown device"; 507 508 device_printf(dev, "<%s> at", name); 509 510 rl = BUS_GET_RESOURCE_LIST(dev, child); 511 if (rl != NULL) { 512 resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 513 resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 514 } 515 516 printf(" (no driver attached)\n"); 517 } 518 519 static int 520 chipc_print_child(device_t dev, device_t child) 521 { 522 struct resource_list *rl; 523 int retval = 0; 524 525 retval += bus_print_child_header(dev, child); 526 527 rl = BUS_GET_RESOURCE_LIST(dev, child); 528 if (rl != NULL) { 529 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, 530 "%#jx"); 531 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, 532 "%jd"); 533 } 534 535 retval += bus_print_child_domain(dev, child); 536 retval += bus_print_child_footer(dev, child); 537 538 return (retval); 539 } 540 541 static int 542 chipc_child_pnpinfo_str(device_t dev, device_t child, char *buf, 543 size_t buflen) 544 { 545 if (buflen == 0) 546 return (EOVERFLOW); 547 548 *buf = '\0'; 549 return (0); 550 } 551 552 static int 553 chipc_child_location_str(device_t dev, device_t child, char *buf, 554 size_t buflen) 555 { 556 if (buflen == 0) 557 return (EOVERFLOW); 558 559 *buf = '\0'; 560 return (ENXIO); 561 } 562 563 static device_t 564 chipc_add_child(device_t dev, u_int order, const char *name, int unit) 565 { 566 struct chipc_softc *sc; 567 struct chipc_devinfo *dinfo; 568 device_t child; 569 570 sc = device_get_softc(dev); 571 572 child = device_add_child_ordered(dev, order, name, unit); 573 if (child == NULL) 574 return (NULL); 575 576 dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT); 577 if (dinfo == NULL) { 578 device_delete_child(dev, child); 579 return (NULL); 580 } 581 582 resource_list_init(&dinfo->resources); 583 device_set_ivars(child, dinfo); 584 585 return (child); 586 } 587 588 static void 589 chipc_child_deleted(device_t dev, device_t child) 590 { 591 struct chipc_devinfo *dinfo = device_get_ivars(child); 592 593 if (dinfo != NULL) { 594 resource_list_free(&dinfo->resources); 595 free(dinfo, M_BHND); 596 } 597 598 device_set_ivars(child, NULL); 599 } 600 601 static struct resource_list * 602 chipc_get_resource_list(device_t dev, device_t child) 603 { 604 struct chipc_devinfo *dinfo = device_get_ivars(child); 605 return (&dinfo->resources); 606 } 607 608 609 /* Allocate region records for the given port, and add the port's memory 610 * range to the mem_rman */ 611 static int 612 chipc_rman_init_regions (struct chipc_softc *sc, bhnd_port_type type, 613 u_int port) 614 { 615 struct chipc_region *cr; 616 rman_res_t start, end; 617 u_int num_regions; 618 int error; 619 620 num_regions = bhnd_get_region_count(sc->dev, type, port); 621 for (u_int region = 0; region < num_regions; region++) { 622 /* Allocate new region record */ 623 cr = chipc_alloc_region(sc, type, port, region); 624 if (cr == NULL) 625 return (ENODEV); 626 627 /* Can't manage regions that cannot be allocated */ 628 if (cr->cr_rid < 0) { 629 BHND_DEBUG_DEV(sc->dev, "no rid for chipc region " 630 "%s%u.%u", bhnd_port_type_name(type), port, region); 631 chipc_free_region(sc, cr); 632 continue; 633 } 634 635 /* Add to rman's managed range */ 636 start = cr->cr_addr; 637 end = cr->cr_end; 638 if ((error = rman_manage_region(&sc->mem_rman, start, end))) { 639 chipc_free_region(sc, cr); 640 return (error); 641 } 642 643 /* Add to region list */ 644 STAILQ_INSERT_TAIL(&sc->mem_regions, cr, cr_link); 645 } 646 647 return (0); 648 } 649 650 /* Initialize memory state for all chipc port regions */ 651 static int 652 chipc_init_rman(struct chipc_softc *sc) 653 { 654 u_int num_ports; 655 int error; 656 657 /* Port types for which we'll register chipc_region mappings */ 658 bhnd_port_type types[] = { 659 BHND_PORT_DEVICE 660 }; 661 662 /* Initialize resource manager */ 663 sc->mem_rman.rm_start = 0; 664 sc->mem_rman.rm_end = BUS_SPACE_MAXADDR; 665 sc->mem_rman.rm_type = RMAN_ARRAY; 666 sc->mem_rman.rm_descr = "ChipCommon Device Memory"; 667 if ((error = rman_init(&sc->mem_rman))) { 668 device_printf(sc->dev, "could not initialize mem_rman: %d\n", 669 error); 670 return (error); 671 } 672 673 /* Populate per-port-region state */ 674 for (u_int i = 0; i < nitems(types); i++) { 675 num_ports = bhnd_get_port_count(sc->dev, types[i]); 676 for (u_int port = 0; port < num_ports; port++) { 677 error = chipc_rman_init_regions(sc, types[i], port); 678 if (error) { 679 device_printf(sc->dev, 680 "region init failed for %s%u: %d\n", 681 bhnd_port_type_name(types[i]), port, 682 error); 683 684 goto failed; 685 } 686 } 687 } 688 689 return (0); 690 691 failed: 692 chipc_free_rman(sc); 693 return (error); 694 } 695 696 /* Free memory management state */ 697 static void 698 chipc_free_rman(struct chipc_softc *sc) 699 { 700 struct chipc_region *cr, *cr_next; 701 702 STAILQ_FOREACH_SAFE(cr, &sc->mem_regions, cr_link, cr_next) 703 chipc_free_region(sc, cr); 704 705 rman_fini(&sc->mem_rman); 706 } 707 708 /** 709 * Return the rman instance for a given resource @p type, if any. 710 * 711 * @param sc The chipc device state. 712 * @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...) 713 */ 714 static struct rman * 715 chipc_get_rman(struct chipc_softc *sc, int type) 716 { 717 switch (type) { 718 case SYS_RES_MEMORY: 719 return (&sc->mem_rman); 720 721 case SYS_RES_IRQ: 722 /* IRQs can be used with RF_SHAREABLE, so we don't perform 723 * any local proxying of resource requests. */ 724 return (NULL); 725 726 default: 727 return (NULL); 728 }; 729 } 730 731 static struct resource * 732 chipc_alloc_resource(device_t dev, device_t child, int type, 733 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 734 { 735 struct chipc_softc *sc; 736 struct chipc_region *cr; 737 struct resource_list_entry *rle; 738 struct resource *rv; 739 struct rman *rm; 740 int error; 741 bool passthrough, isdefault; 742 743 sc = device_get_softc(dev); 744 passthrough = (device_get_parent(child) != dev); 745 isdefault = RMAN_IS_DEFAULT_RANGE(start, end); 746 rle = NULL; 747 748 /* Fetch the resource manager, delegate request if necessary */ 749 rm = chipc_get_rman(sc, type); 750 if (rm == NULL) { 751 /* Requested resource type is delegated to our parent */ 752 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 753 start, end, count, flags); 754 return (rv); 755 } 756 757 /* Populate defaults */ 758 if (!passthrough && isdefault) { 759 /* Fetch the resource list entry. */ 760 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), 761 type, *rid); 762 if (rle == NULL) { 763 device_printf(dev, 764 "default resource %#x type %d for child %s " 765 "not found\n", *rid, type, 766 device_get_nameunit(child)); 767 return (NULL); 768 } 769 770 if (rle->res != NULL) { 771 device_printf(dev, 772 "resource entry %#x type %d for child %s is busy " 773 "[%d]\n", 774 *rid, type, device_get_nameunit(child), 775 rman_get_flags(rle->res)); 776 777 return (NULL); 778 } 779 780 start = rle->start; 781 end = rle->end; 782 count = ulmax(count, rle->count); 783 } 784 785 /* Locate a mapping region */ 786 if ((cr = chipc_find_region(sc, start, end)) == NULL) { 787 /* Resource requests outside our shared port regions can be 788 * delegated to our parent. */ 789 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 790 start, end, count, flags); 791 return (rv); 792 } 793 794 /* Try to retain a region reference */ 795 if ((error = chipc_retain_region(sc, cr, RF_ALLOCATED))) 796 return (NULL); 797 798 /* Make our rman reservation */ 799 rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE, 800 child); 801 if (rv == NULL) { 802 chipc_release_region(sc, cr, RF_ALLOCATED); 803 return (NULL); 804 } 805 806 rman_set_rid(rv, *rid); 807 808 /* Activate */ 809 if (flags & RF_ACTIVE) { 810 error = bus_activate_resource(child, type, *rid, rv); 811 if (error) { 812 device_printf(dev, 813 "failed to activate entry %#x type %d for " 814 "child %s: %d\n", 815 *rid, type, device_get_nameunit(child), error); 816 817 chipc_release_region(sc, cr, RF_ALLOCATED); 818 rman_release_resource(rv); 819 820 return (NULL); 821 } 822 } 823 824 /* Update child's resource list entry */ 825 if (rle != NULL) { 826 rle->res = rv; 827 rle->start = rman_get_start(rv); 828 rle->end = rman_get_end(rv); 829 rle->count = rman_get_size(rv); 830 } 831 832 return (rv); 833 } 834 835 static int 836 chipc_release_resource(device_t dev, device_t child, int type, int rid, 837 struct resource *r) 838 { 839 struct chipc_softc *sc; 840 struct chipc_region *cr; 841 struct rman *rm; 842 struct resource_list_entry *rle; 843 int error; 844 845 sc = device_get_softc(dev); 846 847 /* Handled by parent bus? */ 848 rm = chipc_get_rman(sc, type); 849 if (rm == NULL || !rman_is_region_manager(r, rm)) { 850 return (bus_generic_rl_release_resource(dev, child, type, rid, 851 r)); 852 } 853 854 /* Locate the mapping region */ 855 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 856 if (cr == NULL) 857 return (EINVAL); 858 859 /* Deactivate resources */ 860 if (rman_get_flags(r) & RF_ACTIVE) { 861 error = BUS_DEACTIVATE_RESOURCE(dev, child, type, rid, r); 862 if (error) 863 return (error); 864 } 865 866 if ((error = rman_release_resource(r))) 867 return (error); 868 869 /* Drop allocation reference */ 870 chipc_release_region(sc, cr, RF_ALLOCATED); 871 872 /* Clear reference from the resource list entry if exists */ 873 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), type, rid); 874 if (rle != NULL) 875 rle->res = NULL; 876 877 return (0); 878 } 879 880 static int 881 chipc_adjust_resource(device_t dev, device_t child, int type, 882 struct resource *r, rman_res_t start, rman_res_t end) 883 { 884 struct chipc_softc *sc; 885 struct chipc_region *cr; 886 struct rman *rm; 887 888 sc = device_get_softc(dev); 889 890 /* Handled by parent bus? */ 891 rm = chipc_get_rman(sc, type); 892 if (rm == NULL || !rman_is_region_manager(r, rm)) { 893 return (bus_generic_adjust_resource(dev, child, type, r, start, 894 end)); 895 } 896 897 /* The range is limited to the existing region mapping */ 898 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 899 if (cr == NULL) 900 return (EINVAL); 901 902 if (end <= start) 903 return (EINVAL); 904 905 if (start < cr->cr_addr || end > cr->cr_end) 906 return (EINVAL); 907 908 /* Range falls within the existing region */ 909 return (rman_adjust_resource(r, start, end)); 910 } 911 912 /** 913 * Retain an RF_ACTIVE reference to the region mapping @p r, and 914 * configure @p r with its subregion values. 915 * 916 * @param sc Driver instance state. 917 * @param child Requesting child device. 918 * @param type resource type of @p r. 919 * @param rid resource id of @p r 920 * @param r resource to be activated. 921 * @param req_direct If true, failure to allocate a direct bhnd resource 922 * will be treated as an error. If false, the resource will not be marked 923 * as RF_ACTIVE if bhnd direct resource allocation fails. 924 */ 925 static int 926 chipc_try_activate_resource(struct chipc_softc *sc, device_t child, int type, 927 int rid, struct resource *r, bool req_direct) 928 { 929 struct rman *rm; 930 struct chipc_region *cr; 931 bhnd_size_t cr_offset; 932 rman_res_t r_start, r_end, r_size; 933 int error; 934 935 rm = chipc_get_rman(sc, type); 936 if (rm == NULL || !rman_is_region_manager(r, rm)) 937 return (EINVAL); 938 939 r_start = rman_get_start(r); 940 r_end = rman_get_end(r); 941 r_size = rman_get_size(r); 942 943 /* Find the corresponding chipc region */ 944 cr = chipc_find_region(sc, r_start, r_end); 945 if (cr == NULL) 946 return (EINVAL); 947 948 /* Calculate subregion offset within the chipc region */ 949 cr_offset = r_start - cr->cr_addr; 950 951 /* Retain (and activate, if necessary) the chipc region */ 952 if ((error = chipc_retain_region(sc, cr, RF_ACTIVE))) 953 return (error); 954 955 /* Configure child resource with its subregion values. */ 956 if (cr->cr_res->direct) { 957 error = chipc_init_child_resource(r, cr->cr_res->res, 958 cr_offset, r_size); 959 if (error) 960 goto cleanup; 961 962 /* Mark active */ 963 if ((error = rman_activate_resource(r))) 964 goto cleanup; 965 } else if (req_direct) { 966 error = ENOMEM; 967 goto cleanup; 968 } 969 970 return (0); 971 972 cleanup: 973 chipc_release_region(sc, cr, RF_ACTIVE); 974 return (error); 975 } 976 977 static int 978 chipc_activate_bhnd_resource(device_t dev, device_t child, int type, 979 int rid, struct bhnd_resource *r) 980 { 981 struct chipc_softc *sc; 982 struct rman *rm; 983 int error; 984 985 sc = device_get_softc(dev); 986 987 /* Delegate non-locally managed resources to parent */ 988 rm = chipc_get_rman(sc, type); 989 if (rm == NULL || !rman_is_region_manager(r->res, rm)) { 990 return (bhnd_bus_generic_activate_resource(dev, child, type, 991 rid, r)); 992 } 993 994 /* Try activating the chipc region resource */ 995 error = chipc_try_activate_resource(sc, child, type, rid, r->res, 996 false); 997 if (error) 998 return (error); 999 1000 /* Mark the child resource as direct according to the returned resource 1001 * state */ 1002 if (rman_get_flags(r->res) & RF_ACTIVE) 1003 r->direct = true; 1004 1005 return (0); 1006 } 1007 1008 static int 1009 chipc_activate_resource(device_t dev, device_t child, int type, int rid, 1010 struct resource *r) 1011 { 1012 struct chipc_softc *sc; 1013 struct rman *rm; 1014 1015 sc = device_get_softc(dev); 1016 1017 /* Delegate non-locally managed resources to parent */ 1018 rm = chipc_get_rman(sc, type); 1019 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1020 return (bus_generic_activate_resource(dev, child, type, rid, 1021 r)); 1022 } 1023 1024 /* Try activating the chipc region-based resource */ 1025 return (chipc_try_activate_resource(sc, child, type, rid, r, true)); 1026 } 1027 1028 /** 1029 * Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE(). 1030 */ 1031 static int 1032 chipc_deactivate_resource(device_t dev, device_t child, int type, 1033 int rid, struct resource *r) 1034 { 1035 struct chipc_softc *sc; 1036 struct chipc_region *cr; 1037 struct rman *rm; 1038 int error; 1039 1040 sc = device_get_softc(dev); 1041 1042 /* Handled by parent bus? */ 1043 rm = chipc_get_rman(sc, type); 1044 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1045 return (bus_generic_deactivate_resource(dev, child, type, rid, 1046 r)); 1047 } 1048 1049 /* Find the corresponding chipc region */ 1050 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 1051 if (cr == NULL) 1052 return (EINVAL); 1053 1054 /* Mark inactive */ 1055 if ((error = rman_deactivate_resource(r))) 1056 return (error); 1057 1058 /* Drop associated RF_ACTIVE reference */ 1059 chipc_release_region(sc, cr, RF_ACTIVE); 1060 1061 return (0); 1062 } 1063 1064 /** 1065 * Examine bus state and make a best effort determination of whether it's 1066 * likely safe to enable the muxed SPROM pins. 1067 * 1068 * On devices that do not use SPROM pin muxing, always returns true. 1069 * 1070 * @param sc chipc driver state. 1071 */ 1072 static bool 1073 chipc_should_enable_muxed_sprom(struct chipc_softc *sc) 1074 { 1075 device_t *devs; 1076 device_t hostb; 1077 device_t parent; 1078 int devcount; 1079 int error; 1080 bool result; 1081 1082 /* Nothing to do? */ 1083 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1084 return (true); 1085 1086 mtx_lock(&Giant); /* for newbus */ 1087 1088 parent = device_get_parent(sc->dev); 1089 hostb = bhnd_find_hostb_device(parent); 1090 1091 if ((error = device_get_children(parent, &devs, &devcount))) { 1092 mtx_unlock(&Giant); 1093 return (false); 1094 } 1095 1096 /* Reject any active devices other than ChipCommon, or the 1097 * host bridge (if any). */ 1098 result = true; 1099 for (int i = 0; i < devcount; i++) { 1100 if (devs[i] == hostb || devs[i] == sc->dev) 1101 continue; 1102 1103 if (!device_is_attached(devs[i])) 1104 continue; 1105 1106 if (device_is_suspended(devs[i])) 1107 continue; 1108 1109 /* Active device; assume SPROM is busy */ 1110 result = false; 1111 break; 1112 } 1113 1114 free(devs, M_TEMP); 1115 mtx_unlock(&Giant); 1116 return (result); 1117 } 1118 1119 static int 1120 chipc_enable_sprom(device_t dev) 1121 { 1122 struct chipc_softc *sc; 1123 int error; 1124 1125 sc = device_get_softc(dev); 1126 CHIPC_LOCK(sc); 1127 1128 /* Already enabled? */ 1129 if (sc->sprom_refcnt >= 1) { 1130 sc->sprom_refcnt++; 1131 CHIPC_UNLOCK(sc); 1132 1133 return (0); 1134 } 1135 1136 switch (sc->caps.nvram_src) { 1137 case BHND_NVRAM_SRC_SPROM: 1138 error = chipc_enable_sprom_pins(sc); 1139 break; 1140 case BHND_NVRAM_SRC_OTP: 1141 error = chipc_enable_otp_power(sc); 1142 break; 1143 default: 1144 error = 0; 1145 break; 1146 } 1147 1148 /* Bump the reference count */ 1149 if (error == 0) 1150 sc->sprom_refcnt++; 1151 1152 CHIPC_UNLOCK(sc); 1153 return (error); 1154 } 1155 1156 static void 1157 chipc_disable_sprom(device_t dev) 1158 { 1159 struct chipc_softc *sc; 1160 1161 sc = device_get_softc(dev); 1162 CHIPC_LOCK(sc); 1163 1164 /* Check reference count, skip disable if in-use. */ 1165 KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease")); 1166 sc->sprom_refcnt--; 1167 if (sc->sprom_refcnt > 0) { 1168 CHIPC_UNLOCK(sc); 1169 return; 1170 } 1171 1172 switch (sc->caps.nvram_src) { 1173 case BHND_NVRAM_SRC_SPROM: 1174 chipc_disable_sprom_pins(sc); 1175 break; 1176 case BHND_NVRAM_SRC_OTP: 1177 chipc_disable_otp_power(sc); 1178 break; 1179 default: 1180 break; 1181 } 1182 1183 1184 CHIPC_UNLOCK(sc); 1185 } 1186 1187 static int 1188 chipc_enable_otp_power(struct chipc_softc *sc) 1189 { 1190 // TODO: Enable OTP resource via PMU, and wait up to 100 usec for 1191 // OTPS_READY to be set in `optstatus`. 1192 return (0); 1193 } 1194 1195 static void 1196 chipc_disable_otp_power(struct chipc_softc *sc) 1197 { 1198 // TODO: Disable OTP resource via PMU 1199 } 1200 1201 /** 1202 * If required by this device, enable access to the SPROM. 1203 * 1204 * @param sc chipc driver state. 1205 */ 1206 static int 1207 chipc_enable_sprom_pins(struct chipc_softc *sc) 1208 { 1209 uint32_t cctrl; 1210 1211 CHIPC_LOCK_ASSERT(sc, MA_OWNED); 1212 KASSERT(sc->sprom_refcnt == 0, ("sprom pins already enabled")); 1213 1214 /* Nothing to do? */ 1215 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1216 return (0); 1217 1218 /* Check whether bus is busy */ 1219 if (!chipc_should_enable_muxed_sprom(sc)) 1220 return (EBUSY); 1221 1222 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1223 1224 /* 4331 devices */ 1225 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1226 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN; 1227 1228 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1229 cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1230 1231 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1232 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2; 1233 1234 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1235 return (0); 1236 } 1237 1238 /* 4360 devices */ 1239 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1240 /* Unimplemented */ 1241 } 1242 1243 /* Refuse to proceed on unsupported devices with muxed SPROM pins */ 1244 device_printf(sc->dev, "muxed sprom lines on unrecognized device\n"); 1245 return (ENXIO); 1246 } 1247 1248 /** 1249 * If required by this device, revert any GPIO/pin configuration applied 1250 * to allow SPROM access. 1251 * 1252 * @param sc chipc driver state. 1253 */ 1254 static void 1255 chipc_disable_sprom_pins(struct chipc_softc *sc) 1256 { 1257 uint32_t cctrl; 1258 1259 /* Nothing to do? */ 1260 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1261 return; 1262 1263 CHIPC_LOCK_ASSERT(sc, MA_OWNED); 1264 KASSERT(sc->sprom_refcnt != 0, ("sprom pins already disabled")); 1265 KASSERT(sc->sprom_refcnt == 1, ("sprom pins in use")); 1266 1267 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1268 1269 /* 4331 devices */ 1270 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1271 cctrl |= CHIPC_CCTRL4331_EXTPA_EN; 1272 1273 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1274 cctrl |= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1275 1276 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1277 cctrl |= CHIPC_CCTRL4331_EXTPA_EN2; 1278 1279 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1280 return; 1281 } 1282 1283 /* 4360 devices */ 1284 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1285 /* Unimplemented */ 1286 } 1287 } 1288 1289 static uint32_t 1290 chipc_read_chipst(device_t dev) 1291 { 1292 struct chipc_softc *sc = device_get_softc(dev); 1293 return (bhnd_bus_read_4(sc->core, CHIPC_CHIPST)); 1294 } 1295 1296 static void 1297 chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask) 1298 { 1299 struct chipc_softc *sc; 1300 uint32_t cctrl; 1301 1302 sc = device_get_softc(dev); 1303 1304 CHIPC_LOCK(sc); 1305 1306 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1307 cctrl = (cctrl & ~mask) | (value | mask); 1308 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1309 1310 CHIPC_UNLOCK(sc); 1311 } 1312 1313 static struct chipc_caps * 1314 chipc_get_caps(device_t dev) 1315 { 1316 struct chipc_softc *sc; 1317 1318 sc = device_get_softc(dev); 1319 return (&sc->caps); 1320 } 1321 1322 static device_method_t chipc_methods[] = { 1323 /* Device interface */ 1324 DEVMETHOD(device_probe, chipc_probe), 1325 DEVMETHOD(device_attach, chipc_attach), 1326 DEVMETHOD(device_detach, chipc_detach), 1327 DEVMETHOD(device_suspend, chipc_suspend), 1328 DEVMETHOD(device_resume, chipc_resume), 1329 1330 /* Bus interface */ 1331 DEVMETHOD(bus_probe_nomatch, chipc_probe_nomatch), 1332 DEVMETHOD(bus_print_child, chipc_print_child), 1333 DEVMETHOD(bus_child_pnpinfo_str, chipc_child_pnpinfo_str), 1334 DEVMETHOD(bus_child_location_str, chipc_child_location_str), 1335 1336 DEVMETHOD(bus_add_child, chipc_add_child), 1337 DEVMETHOD(bus_child_deleted, chipc_child_deleted), 1338 1339 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 1340 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 1341 DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource), 1342 DEVMETHOD(bus_alloc_resource, chipc_alloc_resource), 1343 DEVMETHOD(bus_release_resource, chipc_release_resource), 1344 DEVMETHOD(bus_adjust_resource, chipc_adjust_resource), 1345 DEVMETHOD(bus_activate_resource, chipc_activate_resource), 1346 DEVMETHOD(bus_deactivate_resource, chipc_deactivate_resource), 1347 DEVMETHOD(bus_get_resource_list, chipc_get_resource_list), 1348 1349 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1350 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1351 DEVMETHOD(bus_config_intr, bus_generic_config_intr), 1352 DEVMETHOD(bus_bind_intr, bus_generic_bind_intr), 1353 DEVMETHOD(bus_describe_intr, bus_generic_describe_intr), 1354 1355 /* BHND bus inteface */ 1356 DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource), 1357 1358 /* ChipCommon interface */ 1359 DEVMETHOD(bhnd_chipc_read_chipst, chipc_read_chipst), 1360 DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl), 1361 DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom), 1362 DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom), 1363 DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps), 1364 1365 DEVMETHOD_END 1366 }; 1367 1368 DEFINE_CLASS_0(bhnd_chipc, bhnd_chipc_driver, chipc_methods, sizeof(struct chipc_softc)); 1369 EARLY_DRIVER_MODULE(bhnd_chipc, bhnd, bhnd_chipc_driver, bhnd_chipc_devclass, 0, 0, 1370 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 1371 MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1); 1372 MODULE_VERSION(bhnd_chipc, 1); 1373