1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2017 The FreeBSD Foundation 5 * 6 * This software was developed by Landon Fuller under sponsorship from 7 * the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/kernel.h> 33 #include <sys/bus.h> 34 #include <sys/gpio.h> 35 #include <sys/limits.h> 36 #include <sys/module.h> 37 38 #include <machine/_inttypes.h> 39 #include <machine/bus.h> 40 #include <sys/rman.h> 41 #include <machine/resource.h> 42 43 #include <dev/bhnd/bhnd.h> 44 #include <dev/gpio/gpiobusvar.h> 45 46 #include "gpio_if.h" 47 48 #include "bhnd_nvram_map.h" 49 50 #include "chipcreg.h" 51 #include "chipc_gpiovar.h" 52 53 /* 54 * ChipCommon GPIO driver 55 */ 56 57 static int chipc_gpio_check_flags( 58 struct chipc_gpio_softc *sc, 59 uint32_t pin_num, uint32_t flags, 60 chipc_gpio_pin_mode *mode); 61 static int chipc_gpio_pin_update( 62 struct chipc_gpio_softc *sc, 63 struct chipc_gpio_update *update, 64 uint32_t pin_num, uint32_t flags); 65 static int chipc_gpio_commit_update( 66 struct chipc_gpio_softc *sc, 67 struct chipc_gpio_update *update); 68 static chipc_gpio_pin_mode chipc_gpio_pin_get_mode( 69 struct chipc_gpio_softc *sc, 70 uint32_t pin_num); 71 72 /* Debugging flags */ 73 static u_long chipc_gpio_debug = 0; 74 TUNABLE_ULONG("hw.bhnd_chipc.gpio_debug", &chipc_gpio_debug); 75 76 enum { 77 /** Allow userspace GPIO access on bridged network (e.g. wi-fi) 78 * adapters */ 79 CC_GPIO_DEBUG_ADAPTER_GPIOC = 1 << 0, 80 }; 81 82 #define CC_GPIO_DEBUG(_type) (CC_GPIO_DEBUG_ ## _type & chipc_gpio_debug) 83 84 static struct bhnd_device_quirk chipc_gpio_quirks[]; 85 86 /* Supported parent core device identifiers */ 87 static const struct bhnd_device chipc_gpio_devices[] = { 88 BHND_DEVICE(BCM, CC, "Broadcom ChipCommon GPIO", chipc_gpio_quirks), 89 BHND_DEVICE_END 90 }; 91 92 /* Device quirks table */ 93 static struct bhnd_device_quirk chipc_gpio_quirks[] = { 94 BHND_CORE_QUIRK (HWREV_LTE(10), CC_GPIO_QUIRK_NO_EVENTS), 95 BHND_CORE_QUIRK (HWREV_LTE(15), CC_GPIO_QUIRK_NO_DCTIMER), 96 BHND_CORE_QUIRK (HWREV_LTE(19), CC_GPIO_QUIRK_NO_PULLUPDOWN), 97 98 BHND_DEVICE_QUIRK_END 99 }; 100 101 static int 102 chipc_gpio_probe(device_t dev) 103 { 104 const struct bhnd_device *id; 105 device_t chipc; 106 107 /* Look for compatible chipc parent */ 108 chipc = device_get_parent(dev); 109 id = bhnd_device_lookup(chipc, chipc_gpio_devices, 110 sizeof(chipc_gpio_devices[0])); 111 if (id == NULL) 112 return (ENXIO); 113 114 device_set_desc(dev, id->desc); 115 return (BUS_PROBE_NOWILDCARD); 116 } 117 118 static int 119 chipc_gpio_attach(device_t dev) 120 { 121 struct chipc_gpio_softc *sc; 122 device_t chipc; 123 int error; 124 125 chipc = device_get_parent(dev); 126 127 sc = device_get_softc(dev); 128 sc->dev = dev; 129 sc->quirks = bhnd_device_quirks(chipc, chipc_gpio_devices, 130 sizeof(chipc_gpio_devices[0])); 131 132 /* If this is a bridged wi-fi adapter, we don't want to support 133 * userspace requests via gpioc(4) */ 134 if (bhnd_get_attach_type(chipc) == BHND_ATTACH_ADAPTER) { 135 if (!CC_GPIO_DEBUG(ADAPTER_GPIOC)) 136 sc->quirks |= CC_GPIO_QUIRK_NO_GPIOC; 137 } 138 139 CC_GPIO_LOCK_INIT(sc); 140 141 sc->mem_rid = 0; 142 sc->mem_res = bhnd_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 143 RF_ACTIVE|RF_SHAREABLE); 144 if (sc->mem_res == NULL) { 145 device_printf(dev, "failed to allocate chipcommon registers\n"); 146 error = ENXIO; 147 goto failed; 148 } 149 150 /* 151 * If hardware 'pulsate' support is available, set the timer duty-cycle 152 * to either the NVRAM 'leddc' value if available, or the default duty 153 * cycle. 154 */ 155 if (!CC_GPIO_QUIRK(sc, NO_DCTIMER)) { 156 uint32_t dctimerval; 157 158 error = bhnd_nvram_getvar_uint32(chipc, BHND_NVAR_LEDDC, 159 &dctimerval); 160 if (error == ENOENT) { 161 /* Fall back on default duty cycle */ 162 dctimerval = CHIPC_GPIOTIMERVAL_DEFAULT; 163 } else if (error) { 164 device_printf(dev, "error reading %s from NVRAM: %d\n", 165 BHND_NVAR_LEDDC, error); 166 goto failed; 167 } 168 169 CC_GPIO_WR4(sc, CHIPC_GPIOTIMERVAL, dctimerval); 170 } 171 172 /* Attach gpioc/gpiobus */ 173 if (CC_GPIO_QUIRK(sc, NO_GPIOC)) { 174 sc->gpiobus = NULL; 175 } else { 176 if ((sc->gpiobus = gpiobus_attach_bus(dev)) == NULL) { 177 device_printf(dev, "failed to attach gpiobus\n"); 178 error = ENXIO; 179 goto failed; 180 } 181 } 182 183 /* Register as the bus GPIO provider */ 184 if ((error = bhnd_register_provider(dev, BHND_SERVICE_GPIO))) { 185 device_printf(dev, "failed to register gpio with bus: %d\n", 186 error); 187 goto failed; 188 } 189 190 return (0); 191 192 failed: 193 device_delete_children(dev); 194 195 if (sc->mem_res != NULL) { 196 bhnd_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, 197 sc->mem_res); 198 } 199 200 CC_GPIO_LOCK_DESTROY(sc); 201 202 return (error); 203 } 204 205 static int 206 chipc_gpio_detach(device_t dev) 207 { 208 struct chipc_gpio_softc *sc; 209 int error; 210 211 sc = device_get_softc(dev); 212 213 if ((error = bus_generic_detach(dev))) 214 return (error); 215 216 if ((error = bhnd_deregister_provider(dev, BHND_SERVICE_ANY))) 217 return (error); 218 219 bhnd_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res); 220 CC_GPIO_LOCK_DESTROY(sc); 221 222 return (0); 223 } 224 225 static device_t 226 chipc_gpio_get_bus(device_t dev) 227 { 228 struct chipc_gpio_softc *sc = device_get_softc(dev); 229 230 return (sc->gpiobus); 231 } 232 233 static int 234 chipc_gpio_pin_max(device_t dev, int *maxpin) 235 { 236 *maxpin = CC_GPIO_NPINS-1; 237 return (0); 238 } 239 240 static int 241 chipc_gpio_pin_set(device_t dev, uint32_t pin_num, uint32_t pin_value) 242 { 243 struct chipc_gpio_softc *sc; 244 bool pin_high; 245 int error; 246 247 sc = device_get_softc(dev); 248 error = 0; 249 250 if (!CC_GPIO_VALID_PIN(pin_num)) 251 return (EINVAL); 252 253 switch (pin_value) { 254 case GPIO_PIN_HIGH: 255 pin_high = true; 256 break; 257 case GPIO_PIN_LOW: 258 pin_high = false; 259 break; 260 default: 261 return (EINVAL); 262 } 263 264 CC_GPIO_LOCK(sc); 265 266 switch (chipc_gpio_pin_get_mode(sc, pin_num)) { 267 case CC_GPIO_PIN_INPUT: 268 case CC_GPIO_PIN_TRISTATE: 269 error = ENODEV; 270 break; 271 272 case CC_GPIO_PIN_OUTPUT: 273 CC_GPIO_WRFLAG(sc, pin_num, GPIOOUT, pin_high); 274 break; 275 } 276 277 CC_GPIO_UNLOCK(sc); 278 279 return (error); 280 } 281 282 static int 283 chipc_gpio_pin_get(device_t dev, uint32_t pin_num, uint32_t *pin_value) 284 { 285 struct chipc_gpio_softc *sc; 286 bool pin_high; 287 288 if (!CC_GPIO_VALID_PIN(pin_num)) 289 return (EINVAL); 290 291 sc = device_get_softc(dev); 292 pin_high = false; 293 294 CC_GPIO_LOCK(sc); 295 296 switch (chipc_gpio_pin_get_mode(sc, pin_num)) { 297 case CC_GPIO_PIN_INPUT: 298 pin_high = CC_GPIO_RDFLAG(sc, pin_num, GPIOIN); 299 break; 300 301 case CC_GPIO_PIN_OUTPUT: 302 pin_high = CC_GPIO_RDFLAG(sc, pin_num, GPIOOUT); 303 break; 304 305 case CC_GPIO_PIN_TRISTATE: 306 pin_high = false; 307 break; 308 } 309 310 CC_GPIO_UNLOCK(sc); 311 312 *pin_value = pin_high ? GPIO_PIN_HIGH : GPIO_PIN_LOW; 313 314 return (0); 315 } 316 317 static int 318 chipc_gpio_pin_toggle(device_t dev, uint32_t pin_num) 319 { 320 struct chipc_gpio_softc *sc; 321 bool pin_high; 322 int error; 323 324 if (!CC_GPIO_VALID_PIN(pin_num)) 325 return (EINVAL); 326 327 sc = device_get_softc(dev); 328 error = 0; 329 330 CC_GPIO_LOCK(sc); 331 332 switch (chipc_gpio_pin_get_mode(sc, pin_num)) { 333 case CC_GPIO_PIN_INPUT: 334 case CC_GPIO_PIN_TRISTATE: 335 error = ENODEV; 336 break; 337 338 case CC_GPIO_PIN_OUTPUT: 339 pin_high = CC_GPIO_RDFLAG(sc, pin_num, GPIOOUT); 340 CC_GPIO_WRFLAG(sc, pin_num, GPIOOUT, !pin_high); 341 break; 342 } 343 344 CC_GPIO_UNLOCK(sc); 345 346 return (error); 347 } 348 349 static int 350 chipc_gpio_pin_getcaps(device_t dev, uint32_t pin_num, uint32_t *caps) 351 { 352 struct chipc_gpio_softc *sc = device_get_softc(dev); 353 354 if (!CC_GPIO_VALID_PIN(pin_num)) 355 return (EINVAL); 356 357 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE); 358 359 if (!CC_GPIO_QUIRK(sc, NO_PULLUPDOWN)) 360 *caps |= (GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN); 361 362 if (!CC_GPIO_QUIRK(sc, NO_DCTIMER)) 363 *caps |= GPIO_PIN_PULSATE; 364 365 return (0); 366 } 367 368 static int 369 chipc_gpio_pin_getflags(device_t dev, uint32_t pin_num, uint32_t *flags) 370 { 371 struct chipc_gpio_softc *sc = device_get_softc(dev); 372 373 if (!CC_GPIO_VALID_PIN(pin_num)) 374 return (EINVAL); 375 376 CC_GPIO_LOCK(sc); 377 378 switch (chipc_gpio_pin_get_mode(sc, pin_num)) { 379 case CC_GPIO_PIN_INPUT: 380 *flags = GPIO_PIN_INPUT; 381 382 if (!CC_GPIO_QUIRK(sc, NO_PULLUPDOWN)) { 383 if (CC_GPIO_RDFLAG(sc, pin_num, GPIOPU)) { 384 *flags |= GPIO_PIN_PULLUP; 385 } else if (CC_GPIO_RDFLAG(sc, pin_num, GPIOPD)) { 386 *flags |= GPIO_PIN_PULLDOWN; 387 } 388 } 389 break; 390 391 case CC_GPIO_PIN_OUTPUT: 392 *flags = GPIO_PIN_OUTPUT; 393 394 if (!CC_GPIO_QUIRK(sc, NO_DCTIMER)) { 395 if (CC_GPIO_RDFLAG(sc, pin_num, GPIOTIMEROUTMASK)) 396 *flags |= GPIO_PIN_PULSATE; 397 } 398 399 break; 400 401 case CC_GPIO_PIN_TRISTATE: 402 *flags = GPIO_PIN_TRISTATE|GPIO_PIN_OUTPUT; 403 break; 404 } 405 406 CC_GPIO_UNLOCK(sc); 407 408 return (0); 409 } 410 411 static int 412 chipc_gpio_pin_getname(device_t dev, uint32_t pin_num, char *name) 413 { 414 int ret; 415 416 if (!CC_GPIO_VALID_PIN(pin_num)) 417 return (EINVAL); 418 419 ret = snprintf(name, GPIOMAXNAME, "bhnd_gpio%02" PRIu32, pin_num); 420 421 if (ret < 0) 422 return (ENXIO); 423 424 if (ret >= GPIOMAXNAME) 425 return (ENOMEM); 426 427 return (0); 428 } 429 430 static int 431 chipc_gpio_pin_setflags(device_t dev, uint32_t pin_num, uint32_t flags) 432 { 433 struct chipc_gpio_softc *sc; 434 struct chipc_gpio_update upd; 435 int error; 436 437 sc = device_get_softc(dev); 438 439 if (!CC_GPIO_VALID_PIN(pin_num)) 440 return (EINVAL); 441 442 /* Produce an update descriptor */ 443 memset(&upd, 0, sizeof(upd)); 444 if ((error = chipc_gpio_pin_update(sc, &upd, pin_num, flags))) 445 return (error); 446 447 /* Commit the update */ 448 CC_GPIO_LOCK(sc); 449 error = chipc_gpio_commit_update(sc, &upd); 450 CC_GPIO_UNLOCK(sc); 451 452 return (error); 453 } 454 455 static int 456 chipc_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins, 457 uint32_t change_pins, uint32_t *orig_pins) 458 { 459 struct chipc_gpio_softc *sc; 460 struct chipc_gpio_update upd; 461 uint32_t out, outen, ctrl; 462 uint32_t num_pins; 463 int error; 464 465 sc = device_get_softc(dev); 466 467 if (first_pin >= CC_GPIO_NPINS) 468 return (EINVAL); 469 470 /* Determine the actual number of referenced pins */ 471 if (clear_pins == 0 && change_pins == 0) { 472 num_pins = CC_GPIO_NPINS - first_pin; 473 } else { 474 int num_clear_pins, num_change_pins; 475 476 num_clear_pins = flsl((u_long)clear_pins); 477 num_change_pins = flsl((u_long)change_pins); 478 num_pins = MAX(num_clear_pins, num_change_pins); 479 } 480 481 /* Validate the full pin range */ 482 if (!CC_GPIO_VALID_PINS(first_pin, num_pins)) 483 return (EINVAL); 484 485 /* Produce an update descriptor for all pins, relative to the current 486 * pin state */ 487 CC_GPIO_LOCK(sc); 488 memset(&upd, 0, sizeof(upd)); 489 490 out = CC_GPIO_RD4(sc, CHIPC_GPIOOUT); 491 outen = CC_GPIO_RD4(sc, CHIPC_GPIOOUTEN); 492 ctrl = CC_GPIO_RD4(sc, CHIPC_GPIOCTRL); 493 494 for (uint32_t i = 0; i < num_pins; i++) { 495 uint32_t pin; 496 bool pin_high; 497 498 pin = first_pin + i; 499 500 /* The pin must be configured for output */ 501 if ((outen & (1 << pin)) == 0) { 502 CC_GPIO_UNLOCK(sc); 503 return (EINVAL); 504 } 505 506 /* The pin must not tristated */ 507 if ((ctrl & (1 << pin)) != 0) { 508 CC_GPIO_UNLOCK(sc); 509 return (EINVAL); 510 } 511 512 /* Fetch current state */ 513 if (out & (1 << pin)) { 514 pin_high = true; 515 } else { 516 pin_high = false; 517 } 518 519 /* Apply clear/toggle request */ 520 if (clear_pins & (1 << pin)) 521 pin_high = false; 522 523 if (change_pins & (1 << pin)) 524 pin_high = !pin_high; 525 526 /* Add to our update descriptor */ 527 CC_GPIO_UPDATE(&upd, pin, out, pin_high); 528 } 529 530 /* Commit the update */ 531 error = chipc_gpio_commit_update(sc, &upd); 532 CC_GPIO_UNLOCK(sc); 533 534 return (error); 535 } 536 537 static int 538 chipc_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins, 539 uint32_t *pin_flags) 540 { 541 struct chipc_gpio_softc *sc; 542 struct chipc_gpio_update upd; 543 int error; 544 545 sc = device_get_softc(dev); 546 547 if (!CC_GPIO_VALID_PINS(first_pin, num_pins)) 548 return (EINVAL); 549 550 /* Produce an update descriptor */ 551 memset(&upd, 0, sizeof(upd)); 552 for (uint32_t i = 0; i < num_pins; i++) { 553 uint32_t pin, flags; 554 555 pin = first_pin + i; 556 flags = pin_flags[i]; 557 558 /* As per the gpio_config_32 API documentation, any pins for 559 * which neither GPIO_PIN_OUTPUT or GPIO_PIN_INPUT are set 560 * should be ignored and left unmodified */ 561 if ((flags & (GPIO_PIN_OUTPUT|GPIO_PIN_INPUT)) == 0) 562 continue; 563 564 if ((error = chipc_gpio_pin_update(sc, &upd, pin, flags))) 565 return (error); 566 } 567 568 /* Commit the update */ 569 CC_GPIO_LOCK(sc); 570 error = chipc_gpio_commit_update(sc, &upd); 571 CC_GPIO_UNLOCK(sc); 572 573 return (error); 574 } 575 576 /** 577 * Commit a single @p reg register update. 578 */ 579 static void 580 chipc_gpio_commit_reg(struct chipc_gpio_softc *sc, bus_size_t offset, 581 struct chipc_gpio_reg *reg) 582 { 583 uint32_t value; 584 585 CC_GPIO_LOCK_ASSERT(sc, MA_OWNED); 586 587 if (reg->mask == 0) 588 return; 589 590 value = bhnd_bus_read_4(sc->mem_res, offset); 591 value &= ~reg->mask; 592 value |= reg->value; 593 594 bhnd_bus_write_4(sc->mem_res, offset, value); 595 } 596 597 /** 598 * Commit the set of GPIO register updates described by @p update. 599 */ 600 static int 601 chipc_gpio_commit_update(struct chipc_gpio_softc *sc, 602 struct chipc_gpio_update *update) 603 { 604 CC_GPIO_LOCK_ASSERT(sc, MA_OWNED); 605 606 /* Commit pulldown/pullup before potentially disabling an output pin */ 607 chipc_gpio_commit_reg(sc, CHIPC_GPIOPD, &update->pulldown); 608 chipc_gpio_commit_reg(sc, CHIPC_GPIOPU, &update->pullup); 609 610 /* Commit output settings before potentially enabling an output pin */ 611 chipc_gpio_commit_reg(sc, CHIPC_GPIOTIMEROUTMASK, 612 &update->timeroutmask); 613 chipc_gpio_commit_reg(sc, CHIPC_GPIOOUT, &update->out); 614 615 /* Commit input/output/tristate modes */ 616 chipc_gpio_commit_reg(sc, CHIPC_GPIOOUTEN, &update->outen); 617 chipc_gpio_commit_reg(sc, CHIPC_GPIOCTRL, &update->ctrl); 618 619 return (0); 620 } 621 622 /** 623 * Apply the changes described by @p flags for @p pin_num to the given @p update 624 * descriptor. 625 */ 626 static int 627 chipc_gpio_pin_update(struct chipc_gpio_softc *sc, 628 struct chipc_gpio_update *update, uint32_t pin_num, uint32_t flags) 629 { 630 chipc_gpio_pin_mode mode; 631 int error; 632 633 if (!CC_GPIO_VALID_PIN(pin_num)) 634 return (EINVAL); 635 636 /* Verify flag compatibility and determine the pin mode */ 637 if ((error = chipc_gpio_check_flags(sc, pin_num, flags, &mode))) 638 return (error); 639 640 /* Apply the mode-specific changes */ 641 switch (mode) { 642 case CC_GPIO_PIN_INPUT: 643 CC_GPIO_UPDATE(update, pin_num, pullup, false); 644 CC_GPIO_UPDATE(update, pin_num, pulldown, false); 645 CC_GPIO_UPDATE(update, pin_num, out, false); 646 CC_GPIO_UPDATE(update, pin_num, outen, false); 647 CC_GPIO_UPDATE(update, pin_num, timeroutmask, false); 648 CC_GPIO_UPDATE(update, pin_num, ctrl, false); 649 650 if (flags & GPIO_PIN_PULLUP) { 651 CC_GPIO_UPDATE(update, pin_num, pullup, true); 652 } else if (flags & GPIO_PIN_PULLDOWN) { 653 CC_GPIO_UPDATE(update, pin_num, pulldown, true); 654 } 655 656 return (0); 657 658 case CC_GPIO_PIN_OUTPUT: 659 CC_GPIO_UPDATE(update, pin_num, pullup, false); 660 CC_GPIO_UPDATE(update, pin_num, pulldown, false); 661 CC_GPIO_UPDATE(update, pin_num, outen, true); 662 CC_GPIO_UPDATE(update, pin_num, timeroutmask, false); 663 CC_GPIO_UPDATE(update, pin_num, ctrl, false); 664 665 if (flags & GPIO_PIN_PRESET_HIGH) { 666 CC_GPIO_UPDATE(update, pin_num, out, true); 667 } else if (flags & GPIO_PIN_PRESET_LOW) { 668 CC_GPIO_UPDATE(update, pin_num, out, false); 669 } 670 671 if (flags & GPIO_PIN_PULSATE) 672 CC_GPIO_UPDATE(update, pin_num, timeroutmask, true); 673 674 return (0); 675 676 case CC_GPIO_PIN_TRISTATE: 677 CC_GPIO_UPDATE(update, pin_num, pullup, false); 678 CC_GPIO_UPDATE(update, pin_num, pulldown, false); 679 CC_GPIO_UPDATE(update, pin_num, out, false); 680 CC_GPIO_UPDATE(update, pin_num, outen, false); 681 CC_GPIO_UPDATE(update, pin_num, timeroutmask, false); 682 CC_GPIO_UPDATE(update, pin_num, ctrl, true); 683 684 if (flags & GPIO_PIN_OUTPUT) 685 CC_GPIO_UPDATE(update, pin_num, outen, true); 686 687 return (0); 688 } 689 690 device_printf(sc->dev, "unknown pin mode %d\n", mode); 691 return (EINVAL); 692 } 693 694 /** 695 * Verify that @p flags are valid for use with @p pin_num, and on success, 696 * return the pin mode described by @p flags in @p mode. 697 * 698 * @param sc GPIO driver instance state. 699 * @param pin_num The pin number to configure. 700 * @param flags The pin flags to be validated. 701 * @param[out] mode On success, will be populated with the GPIO pin mode 702 * defined by @p flags. 703 * 704 * @retval 0 success 705 * @retval EINVAL if @p flags are invalid. 706 */ 707 static int 708 chipc_gpio_check_flags(struct chipc_gpio_softc *sc, uint32_t pin_num, 709 uint32_t flags, chipc_gpio_pin_mode *mode) 710 { 711 uint32_t mode_flag, input_flag, output_flag; 712 713 CC_GPIO_ASSERT_VALID_PIN(sc, pin_num); 714 715 mode_flag = flags & (GPIO_PIN_OUTPUT | GPIO_PIN_INPUT | 716 GPIO_PIN_TRISTATE); 717 output_flag = flags & (GPIO_PIN_PRESET_HIGH | GPIO_PIN_PRESET_LOW 718 | GPIO_PIN_PULSATE); 719 input_flag = flags & (GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN); 720 721 switch (mode_flag) { 722 case GPIO_PIN_OUTPUT: 723 /* No input flag(s) should be set */ 724 if (input_flag != 0) 725 return (EINVAL); 726 727 /* Validate our output flag(s) */ 728 switch (output_flag) { 729 case GPIO_PIN_PRESET_HIGH: 730 case GPIO_PIN_PRESET_LOW: 731 case (GPIO_PIN_PRESET_HIGH|GPIO_PIN_PULSATE): 732 case (GPIO_PIN_PRESET_LOW|GPIO_PIN_PULSATE): 733 case 0: 734 /* Check for unhandled flags */ 735 if ((flags & ~(mode_flag | output_flag)) != 0) 736 return (EINVAL); 737 738 *mode = CC_GPIO_PIN_OUTPUT; 739 return (0); 740 741 default: 742 /* Incompatible output flags */ 743 return (EINVAL); 744 } 745 746 case GPIO_PIN_INPUT: 747 /* No output flag(s) should be set */ 748 if (output_flag != 0) 749 return (EINVAL); 750 751 /* Validate our input flag(s) */ 752 switch (input_flag) { 753 case GPIO_PIN_PULLUP: 754 case GPIO_PIN_PULLDOWN: 755 case 0: 756 /* Check for unhandled flags */ 757 if ((flags & ~(mode_flag | input_flag)) != 0) 758 return (EINVAL); 759 760 *mode = CC_GPIO_PIN_INPUT; 761 return (0); 762 763 default: 764 /* Incompatible input flags */ 765 return (EINVAL); 766 } 767 768 break; 769 770 case (GPIO_PIN_TRISTATE|GPIO_PIN_OUTPUT): 771 case GPIO_PIN_TRISTATE: 772 /* No input or output flag(s) should be set */ 773 if (input_flag != 0 || output_flag != 0) 774 return (EINVAL); 775 776 /* Check for unhandled flags */ 777 if ((flags & ~mode_flag) != 0) 778 return (EINVAL); 779 780 *mode = CC_GPIO_PIN_TRISTATE; 781 return (0); 782 783 default: 784 /* Incompatible mode flags */ 785 return (EINVAL); 786 } 787 } 788 789 /** 790 * Return the current pin mode for @p pin_num. 791 * 792 * @param sc GPIO driver instance state. 793 * @param pin_num The pin number to query. 794 */ 795 static chipc_gpio_pin_mode 796 chipc_gpio_pin_get_mode(struct chipc_gpio_softc *sc, uint32_t pin_num) 797 { 798 CC_GPIO_LOCK_ASSERT(sc, MA_OWNED); 799 CC_GPIO_ASSERT_VALID_PIN(sc, pin_num); 800 801 if (CC_GPIO_RDFLAG(sc, pin_num, GPIOCTRL)) { 802 return (CC_GPIO_PIN_TRISTATE); 803 } else if (CC_GPIO_RDFLAG(sc, pin_num, GPIOOUTEN)) { 804 return (CC_GPIO_PIN_OUTPUT); 805 } else { 806 return (CC_GPIO_PIN_INPUT); 807 } 808 } 809 810 static device_method_t chipc_gpio_methods[] = { 811 /* Device interface */ 812 DEVMETHOD(device_probe, chipc_gpio_probe), 813 DEVMETHOD(device_attach, chipc_gpio_attach), 814 DEVMETHOD(device_detach, chipc_gpio_detach), 815 816 /* GPIO interface */ 817 DEVMETHOD(gpio_get_bus, chipc_gpio_get_bus), 818 DEVMETHOD(gpio_pin_max, chipc_gpio_pin_max), 819 DEVMETHOD(gpio_pin_getname, chipc_gpio_pin_getname), 820 DEVMETHOD(gpio_pin_getflags, chipc_gpio_pin_getflags), 821 DEVMETHOD(gpio_pin_getcaps, chipc_gpio_pin_getcaps), 822 DEVMETHOD(gpio_pin_setflags, chipc_gpio_pin_setflags), 823 DEVMETHOD(gpio_pin_get, chipc_gpio_pin_get), 824 DEVMETHOD(gpio_pin_set, chipc_gpio_pin_set), 825 DEVMETHOD(gpio_pin_toggle, chipc_gpio_pin_toggle), 826 DEVMETHOD(gpio_pin_access_32, chipc_gpio_pin_access_32), 827 DEVMETHOD(gpio_pin_config_32, chipc_gpio_pin_config_32), 828 829 DEVMETHOD_END 830 }; 831 832 DEFINE_CLASS_0(gpio, chipc_gpio_driver, chipc_gpio_methods, sizeof(struct chipc_gpio_softc)); 833 EARLY_DRIVER_MODULE(chipc_gpio, bhnd_chipc, chipc_gpio_driver, NULL, NULL, 834 BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE); 835 836 MODULE_DEPEND(chipc_gpio, bhnd, 1, 1, 1); 837 MODULE_DEPEND(chipc_gpio, gpiobus, 1, 1, 1); 838 MODULE_VERSION(chipc_gpio, 1); 839