1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2017 The FreeBSD Foundation 5 * 6 * This software was developed by Landon Fuller under sponsorship from 7 * the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33 #ifndef _BHND_CORES_CHIPC_CHIPC_GPIOVAR_H_ 34 #define _BHND_CORES_CHIPC_CHIPC_GPIOVAR_H_ 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 42 #include <dev/bhnd/bhnd.h> 43 44 /** 45 * ChipCommon GPIO device quirks. 46 */ 47 enum { 48 /** 49 * No GPIO event support. 50 * 51 * The CHIPC_GPIOEVENT, CHIPC_GPIOEVENT_INTM, and 52 * CHIPC_GPIOEVENT_INTPOLARITY registers are not available. 53 */ 54 CC_GPIO_QUIRK_NO_EVENTS = (1<<0), 55 56 /** 57 * No GPIO duty-cycle timer support. 58 * 59 * The CHIPC_GPIOTIMERVAL and CHIPC_GPIOTIMEROUTMASK registers are not 60 * available. 61 */ 62 CC_GPIO_QUIRK_NO_DCTIMER = (1<<1), 63 64 /** 65 * No GPIO pull-up/pull-down configuration support. 66 * 67 * The CHIPC_GPIOPU and CHIPC_GPIOPD registers are not available. 68 */ 69 CC_GPIO_QUIRK_NO_PULLUPDOWN = (1<<2), 70 71 /** 72 * Do not attach a child gpioc(4) device. 73 * 74 * This is primarily intended for use on bridged Wi-Fi adapters, where 75 * userspace modification of GPIO pin configuration could introduce 76 * significant undesirable behavior. 77 */ 78 CC_GPIO_QUIRK_NO_GPIOC = (1<<3), 79 }; 80 81 /** ChipCommon GPIO pin modes */ 82 typedef enum { 83 CC_GPIO_PIN_INPUT, 84 CC_GPIO_PIN_OUTPUT, 85 CC_GPIO_PIN_TRISTATE 86 } chipc_gpio_pin_mode; 87 88 /** 89 * A single GPIO update register. 90 */ 91 struct chipc_gpio_reg { 92 uint32_t value; /**< register update value */ 93 uint32_t mask; /**< register update mask */ 94 }; 95 96 /** 97 * A GPIO register update descriptor. 98 */ 99 struct chipc_gpio_update { 100 struct chipc_gpio_reg pullup; /**< CHIPC_GPIOPU changes */ 101 struct chipc_gpio_reg pulldown; /**< CHIPC_GPIOPD changes */ 102 struct chipc_gpio_reg out; /**< CHIPC_GPIOOUT changes */ 103 struct chipc_gpio_reg outen; /**< CHIPC_GPIOOUTEN changes */ 104 struct chipc_gpio_reg timeroutmask; /**< CHIPC_GPIOTIMEROUTMASK changes */ 105 struct chipc_gpio_reg ctrl; /**< CHIPC_GPIOCTRL changes */ 106 }; 107 108 #define CC_GPIO_UPDATE(_upd, _pin, _reg, _val) do { \ 109 (_upd)->_reg.mask |= (1 << (_pin)); \ 110 if (_val) \ 111 (_upd)->_reg.value |= (1 << (_pin)); \ 112 else \ 113 (_upd)->_reg.value &= ~(1 << (_pin)); \ 114 } while(0) 115 116 /** 117 * ChipCommon GPIO driver instance state. 118 */ 119 struct chipc_gpio_softc { 120 device_t dev; 121 device_t gpiobus; /**< attached gpiobus child */ 122 struct bhnd_resource *mem_res; /**< chipcommon register block */ 123 int mem_rid; /**< resource ID of mem_res */ 124 uint32_t quirks; /**< device quirks (see CC_GPIO_QUIRK_*) */ 125 struct mtx mtx; /**< lock protecting RMW register access */ 126 }; 127 128 #define CC_GPIO_LOCK_INIT(sc) mtx_init(&(sc)->mtx, \ 129 device_get_nameunit((sc)->dev), NULL, MTX_DEF) 130 #define CC_GPIO_LOCK(sc) mtx_lock(&(sc)->mtx) 131 #define CC_GPIO_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 132 #define CC_GPIO_LOCK_ASSERT(sc, what) mtx_assert(&(sc)->mtx, what) 133 #define CC_GPIO_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx) 134 135 #define CC_GPIO_WR4(sc, off, val) \ 136 bhnd_bus_write_4((sc)->mem_res, (off), (val)) 137 #define CC_GPIO_WRFLAG(sc, pin_num, flag, val) \ 138 CC_GPIO_WR4(sc, CHIPC_ ## flag, \ 139 (CC_GPIO_RD4(sc, CHIPC_ ## flag) & ~(1 << pin_num)) | \ 140 (val ? (1 << pin_num) : 0)) 141 142 #define CC_GPIO_RD4(sc, off) \ 143 bhnd_bus_read_4((sc)->mem_res, (off)) 144 #define CC_GPIO_RDFLAG(sc, pin_num, flag) \ 145 ((CC_GPIO_RD4(sc, CHIPC_ ## flag) & (1 << pin_num)) != 0) 146 147 #define CC_GPIO_NPINS 32 148 #define CC_GPIO_VALID_PIN(_pin) \ 149 ((_pin) >= 0 && (_pin) < CC_GPIO_NPINS) 150 #define CC_GPIO_VALID_PINS(_first, _num) \ 151 ((_num) <= CC_GPIO_NPINS && CC_GPIO_NPINS - (_num) >= _first) 152 153 #define CC_GPIO_ASSERT_VALID_PIN(sc, pin_num) \ 154 KASSERT(CC_GPIO_VALID_PIN(pin_num), ("invalid pin# %" PRIu32, pin_num)); 155 156 #define CC_GPIO_QUIRK(_sc, _name) \ 157 ((_sc)->quirks & CC_GPIO_QUIRK_ ## _name) 158 159 #define CC_GPIO_ASSERT_QUIRK(_sc, name) \ 160 KASSERT(CC_GPIO_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set")) 161 162 #endif /* _BHND_PWRCTL_BHND_PWRCTLVAR_H_ */ 163