1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 18 * NO WARRANTY 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGES. 30 */ 31 32 /* 33 */ 34 35 #ifndef _BHND_CORES_CHIPC_CHIPC_SPI_H_ 36 #define _BHND_CORES_CHIPC_CHIPC_SPI_H_ 37 38 #define CHIPC_SPI_MAXTRIES 1000 39 40 #define CHIPC_SPI_ACTION_INPUT 1 41 #define CHIPC_SPI_ACTION_OUTPUT 2 42 43 #define CHIPC_SPI_FLASHCTL 0x00 44 #define CHIPC_SPI_FLASHCTL_OPCODE 0x000000ff 45 #define CHIPC_SPI_FLASHCTL_ACTION 0x00000700 // 46 /* 47 * We don't use action at all. Experimentaly found, that 48 * action 0 - read current MISO byte to data register (interactive mode) 49 * action 1 = read 2nd byte to data register 50 * action 2 = read 4th byte to data register (surprise! see action 6) 51 * action 3 = read 5th byte to data register 52 * action 4 = read bytes 5-8 to data register in swapped order 53 * action 5 = read bytes 9-12 to data register in swapped order 54 * action 6 = read 3rd byte to data register 55 * action 7 = read bytes 6-9 to data register in swapped order 56 * It may be wrong if CS bit is 1. 57 * If CS bit is 1, you should write cmd / data to opcode byte-to-byte. 58 */ 59 #define CHIPC_SPI_FLASHCTL_CSACTIVE 0x00001000 60 #define CHIPC_SPI_FLASHCTL_START 0x80000000 //same as BUSY 61 #define CHIPC_SPI_FLASHCTL_BUSY 0x80000000 //same as BUSY 62 #define CHIPC_SPI_FLASHADDR 0x04 63 #define CHIPC_SPI_FLASHDATA 0x08 64 65 struct chipc_spi_softc { 66 device_t sc_dev; 67 struct resource *sc_res; /**< SPI registers */ 68 int sc_rid; 69 70 struct resource *sc_flash_res; /**< flash shadow */ 71 int sc_flash_rid; 72 }; 73 74 /* register space access macros */ 75 #define SPI_BARRIER_WRITE(sc) bus_barrier((sc)->sc_res, 0, 0, \ 76 BUS_SPACE_BARRIER_WRITE) 77 #define SPI_BARRIER_READ(sc) bus_barrier((sc)->sc_res, 0, 0, \ 78 BUS_SPACE_BARRIER_READ) 79 #define SPI_BARRIER_RW(sc) bus_barrier((sc)->sc_res, 0, 0, \ 80 BUS_SPACE_BARRIER_READ | \ 81 BUS_SPACE_BARRIER_WRITE) 82 83 #define SPI_WRITE(sc, reg, val) bus_write_4(sc->sc_res, (reg), (val)); 84 85 #define SPI_READ(sc, reg) bus_read_4(sc->sc_res, (reg)) 86 87 #define SPI_SET_BITS(sc, reg, bits) \ 88 SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) | (bits)) 89 90 #define SPI_CLEAR_BITS(sc, reg, bits) \ 91 SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) & ~(bits)) 92 93 #endif /* _BHND_CORES_CHIPC_CHIPC_SPI_H_ */ 94