1 /*- 2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 3 * Copyright (c) 2017 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * Portions of this software were developed by Landon Fuller 7 * under sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 16 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 17 * redistribution must be conditioned upon including a substantially 18 * similar Disclaimer requirement for further binary redistribution. 19 * 20 * NO WARRANTY 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 24 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 25 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 26 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 29 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGES. 32 * 33 * $FreeBSD$ 34 */ 35 36 #ifndef _BHND_CORES_CHIPC_CHIPCVAR_H_ 37 #define _BHND_CORES_CHIPC_CHIPCVAR_H_ 38 39 #include <sys/types.h> 40 #include <sys/rman.h> 41 42 #include <dev/bhnd/nvram/bhnd_spromvar.h> 43 44 #include "chipc.h" 45 46 DECLARE_CLASS(bhnd_chipc_driver); 47 extern devclass_t bhnd_chipc_devclass; 48 49 struct chipc_region; 50 51 const char *chipc_flash_name(chipc_flash type); 52 const char *chipc_flash_bus_name(chipc_flash type); 53 const char *chipc_sflash_device_name(chipc_flash type); 54 55 /* 56 * ChipCommon device quirks / features 57 */ 58 enum { 59 /** No quirks */ 60 CHIPC_QUIRK_NONE = 0, 61 62 /** 63 * ChipCommon-controlled SPROM/OTP is supported, along with the 64 * CHIPC_CAP_SPROM capability flag. 65 */ 66 CHIPC_QUIRK_SUPPORTS_SPROM = (1<<1), 67 68 /** 69 * The BCM4706 NAND flash interface is supported, along with the 70 * CHIPC_CAP_4706_NFLASH capability flag. 71 */ 72 CHIPC_QUIRK_4706_NFLASH = (1<<2), 73 74 /** 75 * The SPROM is attached via muxed pins. The pins must be switched 76 * to allow reading/writing. 77 */ 78 CHIPC_QUIRK_MUX_SPROM = (1<<3), 79 80 /** 81 * Access to the SPROM uses pins shared with the 802.11a external PA. 82 * 83 * On modules using these 4331 packages, the CCTRL4331_EXTPA_EN flag 84 * must be cleared to allow SPROM access. 85 */ 86 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM = (1<<4) | 87 CHIPC_QUIRK_MUX_SPROM, 88 89 /** 90 * Access to the SPROM uses pins shared with the 802.11a external PA. 91 * 92 * On modules using these 4331 chip packages, the external PA is 93 * attached via GPIO 2, 5, and sprom_dout pins. 94 * 95 * When enabling and disabling EXTPA to allow SPROM access, the 96 * CCTRL4331_EXTPA_ON_GPIO2_5 flag must also be set or cleared, 97 * respectively. 98 */ 99 CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM = (1<<5) | 100 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM, 101 102 /** 103 * Access to the SPROM uses pins shared with two 802.11a external PAs. 104 * 105 * When enabling and disabling EXTPA, the CCTRL4331_EXTPA_EN2 must also 106 * be cleared to allow SPROM access. 107 */ 108 CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM = (1<<6) | 109 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM, 110 111 112 /** 113 * SPROM pins are muxed with the FEM control lines on this 4360-family 114 * device. The muxed pins must be switched to allow reading/writing 115 * the SPROM. 116 */ 117 CHIPC_QUIRK_4360_FEM_MUX_SPROM = (1<<5) | 118 CHIPC_QUIRK_MUX_SPROM, 119 120 /** Supports CHIPC_CAPABILITIES_EXT register */ 121 CHIPC_QUIRK_SUPPORTS_CAP_EXT = (1<<6), 122 123 /** Supports HND or IPX OTP registers (CHIPC_OTPST, CHIPC_OTPCTRL, 124 * CHIPC_OTPPROG) */ 125 CHIPC_QUIRK_SUPPORTS_OTP = (1<<7), 126 127 /** Supports HND OTP registers. */ 128 CHIPC_QUIRK_OTP_HND = (1<<8) | 129 CHIPC_QUIRK_SUPPORTS_OTP, 130 131 /** Supports IPX OTP registers. */ 132 CHIPC_QUIRK_OTP_IPX = (1<<9) | 133 CHIPC_QUIRK_SUPPORTS_OTP, 134 135 /** OTP size is defined via CHIPC_OTPLAYOUT register in later 136 * ChipCommon revisions using the 'IPX' OTP controller. */ 137 CHIPC_QUIRK_IPX_OTPL_SIZE = (1<<10) 138 }; 139 140 /** 141 * chipc child device info. 142 */ 143 struct chipc_devinfo { 144 struct resource_list resources; /**< child resources */ 145 rman_res_t irq; /**< child IRQ, if mapped */ 146 bool irq_mapped; /**< true if IRQ mapped, false otherwise */ 147 }; 148 149 /** 150 * chipc driver instance state. 151 */ 152 struct chipc_softc { 153 device_t dev; 154 155 struct bhnd_resource *core; /**< core registers. */ 156 struct chipc_region *core_region; /**< region containing core registers */ 157 158 uint32_t quirks; /**< chipc quirk flags */ 159 struct chipc_caps caps; /**< chipc capabilities */ 160 161 struct mtx mtx; /**< state mutex. */ 162 size_t sprom_refcnt; /**< SPROM pin enable refcount */ 163 struct rman mem_rman; /**< port memory manager */ 164 STAILQ_HEAD(, chipc_region) mem_regions;/**< memory allocation records */ 165 }; 166 167 #define CHIPC_LOCK_INIT(sc) \ 168 mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \ 169 "BHND chipc driver lock", MTX_DEF) 170 #define CHIPC_LOCK(sc) mtx_lock(&(sc)->mtx) 171 #define CHIPC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 172 #define CHIPC_LOCK_ASSERT(sc, what) mtx_assert(&(sc)->mtx, what) 173 #define CHIPC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx) 174 175 #endif /* _BHND_CORES_CHIPC_CHIPCVAR_H_ */ 176